Semiconductor device

Abstract

The embodiment provides a semiconductor device capable of suppressing unwanted power supply during a cutoff operation. The semiconductor device of the embodiment includes a first terminal (PVOUT), a second terminal (PGND), and a first circuit (12). The first circuit includes a first switching element (Q2), a first resistor (R5), and a second switching element (Q4). A first terminal of the first switching element is connected to a first node (N1) supplied with a first voltage (VH). A second terminal of the first switching element is connected to the first terminal. The gate of the first switching element is connected between the first node and the second terminal. The first resistor and the second switching element are connected in series between the first node and the second terminal. When the first voltage is stopped from being supplied to the first node, the semiconductor device sets the first and second switching elements from a cutoff state to a conduction state.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2021-123097 (filed on July 28, 2021). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices. Background Technology

[0004] Semiconductor devices are known for supplying power to loads. Summary of the Invention

[0005] The implementation provides a semiconductor device capable of suppressing unwanted power supply during a cutoff operation.

[0006] The semiconductor device of the embodiment includes a first terminal, a second terminal, and a first circuit. The first circuit includes a first switching element, a first resistor, and a second switching element. A first terminal of the first switching element is connected to a first node to which a first voltage is supplied. A second terminal of the first switching element is connected to the first terminal. The gate of the first switching element is connected between the first node and the second terminal. The first resistor and the second switching element are connected in series between the first node and the second terminal. When the supply of the first voltage to the first node is stopped, the semiconductor device switches the first switching element and the second switching element from a cutoff state to a conduction state. Attached Figure Description

[0007] Figure 1 This is a circuit diagram illustrating an example of the configuration of the semiconductor device of the first embodiment and the load powered by the semiconductor device.

[0008] Figure 2 This is a timing diagram illustrating an example of the operation of the semiconductor device according to the first embodiment.

[0009] Figure 3 This is a circuit diagram illustrating an example of the configuration of the semiconductor device and the load powered by the semiconductor device in the second embodiment.

[0010] Figure 4 This is a timing diagram illustrating an example of the operation of the semiconductor device according to the second embodiment.

[0011] Figure 5 This is a timing diagram illustrating other operational examples of the semiconductor device in the second embodiment.

[0012] Figure 6 This is a circuit diagram illustrating an example of the configuration of a modified semiconductor device and a load powered by the semiconductor device. Detailed Implementation

[0013] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the description, constituent elements having substantially the same function and structure will be labeled with the same reference numerals. Furthermore, the embodiments shown below are for illustrative purposes. The embodiments are not limited to the material, shape, structure, or arrangement of the constituent parts. Various modifications can be made to the embodiments.

[0014] [1] First implementation method

[0015] The semiconductor device of the first embodiment will be described.

[0016] [1-1] Composition

[0017] [1-1-1] Overall Structure of Semiconductor Device 1

[0018] Figure 1 This is a circuit diagram illustrating an example of the configuration of the semiconductor device and the load powered by the semiconductor device according to the first embodiment. The semiconductor device 1 is a load switch that powers the load 2. The semiconductor device 1 is, for example, an IC (Integrated Circuit) chip. The load 2 is a circuit that uses the power supplied from the semiconductor device 1 to perform various operations. The load 2 is, for example, an IC chip.

[0019] Semiconductor device 1 includes terminals PVIN, PVOUT, PEN and PGND, switching element Q1, control circuit 10, voltage generation circuit 11, and switching circuit 12.

[0020] Terminal PVIN is the power supply terminal of semiconductor device 1. A voltage VIN is applied to terminal PVIN from outside semiconductor device 1.

[0021] Terminal PVOUT is the output terminal of semiconductor device 1. Power is supplied to the outside of semiconductor device 1 from terminal PVOUT.

[0022] Terminal PEN is the control terminal of semiconductor device 1. Command CMD is input to terminal PEN from outside semiconductor device 1. Command CMD includes commands to cause semiconductor device 1 to drive load 2 and commands to cause semiconductor device 1 to stop driving load 2. Furthermore, in the following description, the operation of causing semiconductor device 1 to drive load 2 is also referred to as a conduction operation. Furthermore, the operation of causing semiconductor device 1 to stop driving load 2 is also referred to as a cutoff operation. Furthermore, the command to cause semiconductor device 1 to drive load 2 is also referred to as the conduction operation command CMD. Furthermore, the command to cause semiconductor device 1 to stop driving load 2 is also referred to as the cutoff operation command CMD.

[0023] Terminal PGND is the ground terminal of semiconductor device 1. Terminal PGND is grounded.

[0024] Switching element Q1 is an N-channel MOSFET. A voltage VIN is applied to the drain of switching element Q1 via terminal PVIN. The source of switching element Q1 is connected to terminal PVOUT. The gate of switching element Q1 is connected to node N1. When switching element Q1 is in the on-state, it outputs voltage VIN to load 2 via terminal PVOUT. Here, the voltage Ron(Q1)×IOUT, which is the product of the on-resistance Ron(Q1) and the current IOUT flowing through the on-state switching element Q1, is set to a negligible level. When switching element Q1 is in the off-state, it does not output voltage VIN to load 2 via terminal PVOUT.

[0025] Control circuit 10 controls the overall operation of semiconductor device 1. Control circuit 10 receives command CMD from outside semiconductor device 1 via terminal PEN. Based on the received command CMD, control circuit 10 controls the operation of voltage generation circuit 11 and switching circuit 12. Control circuit 10 outputs signals EN1 and EN2 to switching circuit 12.

[0026] The voltage generation circuit 11 is, for example, a charge pump. A voltage VIN is input to the voltage generation circuit 11 via terminal PVIN. Based on the control of the control circuit 10, the voltage generation circuit 11 generates a voltage higher than VIN. The voltage generated by the voltage generation circuit 11 is supplied to node N1.

[0027] Switching circuit 12 controls the switching element Q1 to turn on and off. Based on signals EN1 and EN2 received from control circuit 10, switching circuit 12 sets switching element Q1 to the off state.

[0028] Load 2 includes a capacitive load CL and a resistive load RL. The capacitive load CL stores the supplied power. The resistive load RL consumes the supplied power. The capacitive load CL is located between the terminal PVOUT and the ground voltage. The resistive load RL is located between the terminal PVOUT and the ground voltage, and is connected in parallel with the capacitive load CL.

[0029] [1-1-2] Configuration of switch circuit 12

[0030] The switching circuit 12 is described in detail below. The switching circuit 12 includes resistive elements R1 to R4 and switching elements Q2 to Q4. Switching element Q2 is a P-channel MOSFET. Switching elements Q3 and Q4 are N-channel MOSFETs.

[0031] Resistors R1 through R3 are connected in series between node N1 and terminal PGND in the order R1, R2, R3. Specifically, one end of resistor R1 is connected to node N1, and the other end is connected to node N2. One end of resistor R2 is connected to node N2, and the other end is connected to node N3. One end of resistor R3 is connected to node N3, and the other end is connected to terminal PGND.

[0032] One end of the resistor R4 is connected to the terminal PVOUT.

[0033] The source of switching element Q2 is connected to node N1. The gate of switching element Q2 is connected to node N2. The drain of switching element Q2 is connected to the other end of resistor R4. In other words, the drain of switching element Q2 is connected to terminal PVOUT via resistor R4.

[0034] The source of switching element Q3 is connected to terminal PGND. The drain of switching element Q3 is connected to node N3. A signal EN1 is supplied to the gate of switching element Q3. Switching element Q3 is in the on state and the off state based on the H-level signal EN1 and the L-level signal EN1, respectively.

[0035] The source of switching element Q4 is connected to terminal PGND. The drain of switching element Q4 is connected to node N1. A signal EN2 is supplied to the gate of switching element Q4. Switching element Q4 is in the on state and the off state based on the H-level signal EN2 and the L-level signal EN2, respectively.

[0036] Additionally, although not shown, switching elements Q1 to Q4 each include a body diode. Specifically, switching elements Q1, Q3, and Q4, which are N-channel MOSFETs, each include a body diode with the anode connected to the source and the cathode connected to the drain. Switching element Q2, which is a P-channel MOSFET, includes a body diode with the anode connected to the drain and the cathode connected to the source.

[0037] The resistance values ​​of resistors R1 to R3 are each greater than the resistance value of resistor R4. Specifically, for example, the resistance values ​​of resistors R1 to R3 are hundreds of kilohms to several megahms, while the resistance value of resistor R4 is several thousand ohms.

[0038] The resistance values ​​of resistors R1 to R3 are referred to as resistance values ​​r1 to r3. The threshold voltage of switch Q2 is referred to as Vth(Q2). The voltage output by voltage generation circuit 11 to node N1 is referred to as voltage VH. Resistance values ​​r1 to r3 are determined to satisfy the following equations (1) and (2).

[0039] |VH×(r1) / (r1+r2+r3)|<|Vth(Q2)| (1)

[0040] |VH×(r1) / (r1+r2)|>|Vth(Q2)| (2)

[0041] [1-2] Actions

[0042] The operation of semiconductor device 1 will be explained. The voltage at node N1 will be referred to as VN1. The voltage at terminal PVOUT will be referred to as VOUT. The ground voltage GND is 0V.

[0043] Figure 2 This is a timing diagram illustrating an example of the operation of the semiconductor device according to the first embodiment. Figure 2 The image shows a scenario where semiconductor device 1, performing a turn-on operation, receives a cut-off command (CMD) and executes the cut-off operation. Figure 2 The diagram shows voltage VN1, voltage VOUT, signal EN1, and signal EN2. Voltage VN1 is represented by a solid line, and voltage VOUT is represented by a dashed line. Signals EN1 and EN2 are represented by solid lines.

[0044] At time t10, semiconductor device 1 is performing a conduction operation. During the conduction operation, control circuit 10 outputs voltage VH to voltage generation circuit 11. Thus, voltage VN1 becomes voltage VH. Voltage VH is a voltage higher than the sum of the threshold voltage of switching element Q1 and voltage VIN. Based on voltage VH, switching element Q1 becomes the conducting state. The conducting switching element Q1 supplies voltage VIN to load 2 via terminal PVOUT. Thus, voltage VOUT becomes voltage VIN.

[0045] Furthermore, the control circuit 10 outputs L-level signals EN1 and EN2 to the switching circuit 12. As a result, switching elements Q3 and Q4 are in the off state.

[0046] Since the switching element Q3 is in the off state, the voltage at node N2 is the value obtained by dividing the voltage VH by the series-connected resistors R1 to R3. The magnitude of the gate-source voltage VGS(Q2) of the switching element Q2 can be expressed by the following equation (3).

[0047] |VGS(Q2)|=|VH×(r1) / (r1+r2+r3)| (3)

[0048] The resistance values ​​r1 to r3 of the resistors R1 to R3 are determined to satisfy equation (1) above. Therefore, the magnitude of the gate-source voltage VGS(Q2) is smaller than the threshold voltage Vth(Q2) of the switching element Q2. As a result, the switching element Q2 is in the off state.

[0049] Thus, in the semiconductor device 1 that is performing the conduction operation, switching element Q1 is in the on state, while switching elements Q2 to Q4 are in the off state. Switching element Q1, in the on state, supplies power to load 2.

[0050] At time t11, semiconductor device 1 receives a cutoff command CMD and executes the cutoff operation. Specifically, if control circuit 10 receives the cutoff command CMD, it stops outputting voltage VH to voltage generation circuit 11. Furthermore, control circuit 10 outputs a signal EN1 at level H and a signal EN2 at level H to switching circuit 12.

[0051] In the switching circuit 12, the switching element Q3 becomes in the on state based on the H-level signal EN1.

[0052] As a result, the switching element Q3, which is in the on state, short-circuits the resistor element R3. Therefore, the voltage at node N2 becomes the value after the voltage VH is divided by the resistor elements R1 and R2. The magnitude of the gate-source voltage VGS(Q2) of the switching element Q2 can be expressed by the following equation (4).

[0053] |VGS(Q2)|=|VH×(r1) / (r1+r2)| (4)

[0054] The resistance values ​​r1 and r2 of resistors R1 and R2 are determined to satisfy equation (2) above. Therefore, the magnitude of the gate-source voltage VGS(Q2) becomes larger than the threshold voltage Vth(Q2) of the switching element Q2. As a result, the switching element Q2 becomes in the on state.

[0055] As a result, node N1 and terminal PVOUT are connected via switching element Q2, which is in the on state, and resistor element R4. Thus, voltage VN1 is discharged via switching element Q2 and resistor element R4, in such a way that the magnitude of the gate-source voltage VGS(Q1) of switching element Q1 decreases.

[0056] Furthermore, in the switching circuit 12, the switching element Q4 becomes conductive based on the H-level signal EN2. As a result, node N1 and terminal PGND are short-circuited due to the conductive state of the switching element Q4. Consequently, voltage VN1 is discharged via the conductive state of the switching element Q4.

[0057] Thus, at time t11, voltage VN1 begins to discharge, and voltage VN1 gradually decreases from voltage VH.

[0058] At time t12, as the voltage VN1 decreases, the gate-source voltage VGS(Q1) of the switching element Q1 becomes smaller than the threshold voltage Vth(Q1) of the switching element Q1, and the switching element Q1 becomes off. The off-state switching element Q1 does not supply power to load 2.

[0059] In load 2, where the power supply has been cut off, the charge accumulated in the capacitive load CL is consumed by the resistive load RL. As a result, after time t12, the voltage VOUT gradually decreases to 0V.

[0060] If voltage VN1 gradually decreases, the gate-source voltage VGS(Q2) of switching element Q2 becomes less than the threshold voltage Vth(Q2) of switching element Q2, and switching element Q2 becomes off. Conversely, even if voltage VN1 decreases, switching element Q4 remains on. Thus, voltage VN1 gradually decreases to 0V.

[0061] At time t13, voltage VN1 becomes 0V. Figure 2 In the example shown, since voltage VN1 drops to 0V before voltage VOUT, the gate-source voltage VGS(Q1) of switching element Q1 is below 0V at time t13.

[0062] At time t14, the voltage VOUT becomes 0V. At time t14, the gate-source voltage VGS(Q1) of the switching element Q1 is 0V.

[0063] Thus, upon receiving the cut-off instruction CMD, semiconductor device 1 performs the cut-off operation, switching elements Q2 to Q4 become on and reduce voltage VN1, thereby causing switching element Q1 to switch off. Switching element Q1, now in the off state, stops supplying power to load 2. Furthermore, voltage VN1 drops to 0V due to the on-state switching element Q4, and the gate-source voltage VGS(Q1) of switching element Q1 becomes below 0V or 0V.

[0064] [1-3] Effects

[0065] The semiconductor device 1 according to the first embodiment described above can suppress unwanted power supply during the cutoff operation. Hereinafter, the effects of the semiconductor device 1 according to the first embodiment will be described in detail.

[0066] The semiconductor device 1 of the first embodiment includes switching elements Q2 and Q4. The source of switching element Q2 is connected to node N1, which is supplied with voltage VH. The drain of switching element Q2 is connected to terminal PVOUT via resistor R4. The gate of switching element Q2 is connected to node N2, which is the connection node between resistors R1 to R3 connected in series between node N1 and terminal PGND; in other words, it is connected between node N1 and terminal PGND. The source of switching element Q4 is connected to terminal PGND. The drain of switching element Q4 is connected to node N1. When the voltage VH is stopped from being supplied to node N1, switching elements Q2 and Q4 change from the off state to the on state.

[0067] With the above configuration, the semiconductor device 1 of the first embodiment can reduce the voltage VN1 of node N1 to 0V in a short time when switching from a conduction operation to a cutoff operation. Specifically, when the cutoff operation begins, switching elements Q2 and Q4 become conduction states, thereby discharging the voltage VN1. If the voltage VN1 decreases, switching element Q2 changes to a cutoff state, but switching element Q4 remains conduction state, and the voltage VN1 is discharged to 0V. Therefore, the semiconductor device 1 of the first embodiment does not cause the voltage VN1 to stagnate at a specific voltage when switching from a conduction operation to a cutoff operation, but can discharge it to 0V. Thus, the semiconductor device 1 of the first embodiment can reduce the gate-source voltage VGS(Q1) of switching element Q1 to below 0V or 0V in a short time when switching from a conduction operation to a cutoff operation. Thus, the semiconductor device 1 of the first embodiment can suppress the switching element Q1 from a cutoff operation to an undesirable conduction state, and can suppress undesirable power supply.

[0068] [2] Second implementation method

[0069] The semiconductor device of the second embodiment differs from that of the semiconductor device of the first embodiment in the configuration of the switching circuit and the operation of the control circuit. Hereinafter, the differences between the semiconductor device 1a of the second embodiment and the first embodiment will be explained.

[0070] [2-1] Composition

[0071] [2-1-1] Configuration of semiconductor device 1a

[0072] Figure 3 This is a circuit diagram illustrating an example of the configuration of the semiconductor device and the load powered by the semiconductor device according to the second embodiment. The semiconductor device 1a has a configuration in which the switching circuit 12 of the semiconductor device 1 described in the first embodiment is replaced with a switching circuit 12a.

[0073] In addition to the configuration of switch circuit 12, switch circuit 12a also includes resistor element R5. Resistor element R5 is located between node N1 and the drain of switch element Q4. Specifically, one end of resistor element R5 is connected to node N1, and the other end of resistor element R5 is connected to the drain of switch element Q4. In other words, resistor element R5 and switch element Q4 are connected in series between node N1 and terminal PGND. The resistance value of resistor element R5 is smaller than the individual resistance values ​​of resistors R1 to R3. Specifically, for example, the resistance value of resistor element R5 is several thousand ohms. Other configurations are the same as switch circuit 12.

[0074] In semiconductor device 1a, the configuration other than the switching circuit 12a is the same as that of semiconductor device 1.

[0075] [2-1-2] Composition of load 2a

[0076] Next refer to Figure 3 The load 2a will be described. In the second embodiment, the case in which the load 2a is connected to the terminal PVOUT, which is the output terminal of the semiconductor device 1a, will be described as an example. The load 2a has a configuration in which the resistive load RL of the load 2 described in the first embodiment is replaced by a power supply PS.

[0077] Power supply PS is a constant voltage source with an output voltage VA. Voltage VA is, for example, the same voltage as voltage VIN. Power supply PS outputs voltage VA to terminal PVOUT. Other configurations are the same as load 2.

[0078] Furthermore, since load 2a includes a power supply PS, if the voltage of a node electrically connected to load 2a becomes lower than voltage VA, current can flow from the power supply PS to that node. For example, if semiconductor device 1a performs a cut-off operation, current can flow from the power supply PS into the switching circuit 12a. In this embodiment, the current that flows from the power supply PS through terminal PVOUT into semiconductor device 1a and through the switching circuit 12a to terminal PGND when semiconductor device 1a is performing a cut-off operation is called current IL. Since current IL becomes a load on the power supply PS, it is preferable to suppress it.

[0079] Furthermore, if the gate-source voltage VGS(Q1) of switching element Q1 becomes larger than the withstand voltage VMAX(Q1), then switching element Q1 may break. The on-resistance Ron(Q2) of switching element Q2, the on-resistance Ron(Q4) of switching element Q4, the resistance value r4 of resistor R4, the resistance value r5 of resistor R5, and the voltage VA are determined to satisfy the following relationship (5).

[0080] VMAX(Q1)>((r4+Ron(Q2) / (r4+Ron(Q2)+r5+Ron(Q4))×VA (5)

[0081] [2-2] Actions

[0082] The operation of semiconductor device 1a will be explained.

[0083] Figure 4 This is a timing diagram illustrating an example of the operation of the semiconductor device according to the second embodiment. Figure 4 The image shows a scenario where a semiconductor device 1a, performing a turn-on operation, receives a cut-off command CMD and executes the cut-off operation. Figure 4 The diagram shows the voltage VN1 at node N1, the voltage VOUT at terminal PVOUT, the current IL flowing from terminal PVOUT into semiconductor device 1a, signal EN1, and signal EN2.

[0084] The conduction operation of semiconductor device 1a is the same as that of semiconductor device 1 described in the first embodiment. That is, upon receiving the conduction operation command CMD, semiconductor device 1a performs the conduction operation, switching element Q1 becomes in the on state, and switching elements Q2 to Q4 become in the off state. Moreover, the on-state switching element Q1 supplies power to load 2a.

[0085] At time t20, semiconductor device 1a is conducting. During the period from time t20 to time t21, voltage VN1 is equal to voltage VH. During the period from time t20 to time t21, voltage VN1 is greater than voltage VA, therefore the current IL flowing into semiconductor device 1a is 0A. During the period from time t20 to time t21, signals EN1 and EN2 maintain a low level.

[0086] At time t21, semiconductor device 1a receives a cutoff command CMD and executes the cutoff operation. Specifically, if control circuit 10 receives the cutoff command CMD, it stops outputting voltage VH to voltage generation circuit 11. Moreover, control circuit 10 outputs H-level signals EN1 and EN2 to switching circuit 12a.

[0087] In the switching circuit 12a, the switching element Q3 becomes on based on the signal EN1 at level H. As a result, the switching element Q2 becomes on. Consequently, the voltage VN1 is discharged via the on-state switching element Q2 and the resistor element R4, in such a way that the magnitude of the gate-source voltage VGS(Q1) of the switching element Q1 decreases.

[0088] Furthermore, in the switching circuit 12a, the switching element Q4 becomes conductive based on the H-level signal EN2. As a result, node N1 and terminal PGND are electrically connected to the conductive switching element Q4 via the resistive element R5. Consequently, voltage VN1 is discharged via the resistive element R5 and the conductive switching element Q4.

[0089] If voltage VN1 is discharged, the gate-source voltage VGS(Q1) of switching element Q1 becomes smaller than the threshold voltage Vth(Q1) of switching element Q1, and then switching element Q1 becomes off. In the off state, switching element Q1 does not supply power to load 2a.

[0090] Since load 2a contains power supply PS, even if the power supply from semiconductor device 1a is cut off, the voltage VOUT at terminal PVOUT remains at voltage VA.

[0091] If voltage VN1 is further discharged, and becomes lower than voltage VA, current flows from terminal PVOUT through resistor R4 and the on-state switch Q2 into node N1. The current path from node N1 to ground voltage GND includes a current path through resistor R5 and the on-state switch Q4 to terminal PGND, a current path through resistors R1 and R2 and the on-state switch Q3 to terminal PGND, and a current path through resistors R1 to R3 to terminal PGND. The resistance values ​​of resistors R1 to R3 are greater than the resistance value of resistor R5. Therefore, the main current path from node N1 to ground voltage GND is the current path through resistor R5 and the on-state switch Q4.

[0092] Thus, current flows into node N1 through resistor R4 and the on-state switch Q2, and node N1 is discharged through resistor R5 and the on-state switch Q4. Therefore, the voltage VN1 of node N1 stabilizes at a voltage V1 that can be expressed by the following equation (6).

[0093] V1=((r5+Ron(Q4)) / (r4+Ron(Q2)+r5+Ron(Q4))×VA (6)

[0094] Thus, if voltage VN1 starts discharging at time t21, voltage VN1 will decrease to voltage V1 and stabilize at voltage V1.

[0095] When the voltage VN1 is the same as the voltage V1, the magnitude of the gate-source voltage VGS(Q1) of the switching element Q1 is determined as shown in the following equation (7).

[0096] |VGS(Q1)|=VA-V1=((r4+Ron(Q2) / (r4+Ron(Q2)+r5+Ron(Q4))×VA (7)

[0097] According to equations (5) and (7) above, when the voltage VN1 is the same as the voltage V1, the magnitude of the gate-source voltage VGS(Q1) of the switching element Q1 is smaller than the withstand voltage VMAX(Q1).

[0098] Furthermore, when the voltage VN1 is the voltage V1, the current IL flowing from the terminal PVOUT into the semiconductor device 1a can be expressed as the current I1 in the following equation (8), taking into account the main current path.

[0099] I1=VA / (r4+Ron(Q2)+r5+Ron(Q4)) (8)

[0100] Thus, if voltage VN1 starts discharging at time t21, the current IL increases to current I1 and stabilizes at current I1.

[0101] At time t22, the control circuit 10 switches the signal EN2 to the L level. Time t22 corresponds to the time t21 from which the control circuit 10 outputs the H-level signal EN1 and the H-level signal EN2 to the switching circuit 12a, after the first period W1 has elapsed.

[0102] In the switching circuit 12a, the switching element Q4 becomes the off state based on the L-level signal EN2.

[0103] When switching element Q4 is in the off state, the main current path from node N1 to ground becomes the current path via resistors R1 and R2, and the on-state switching element Q3. That is, the current IL flowing into semiconductor device 1a flows to terminal PGND via resistor R4, the on-state switching element Q4, resistors R1 and R2, and the on-state switching element Q3.

[0104] The change in the current path at time t22 results in an increase in voltage VN1 and a decrease in current IL. The changes in voltage VN1 and current IL are explained.

[0105] The resistance values ​​of resistors R1 and R2 are greater than the resistance value of resistor R4, the on-resistance of switch Q4, and the on-resistance of switch Q3. Therefore, voltage VN1 rises to voltage V2 as can be expressed by the following equation (9) and stabilizes at voltage V2.

[0106] V2 = VA (9)

[0107] Furthermore, the current IL is reduced to a current I2 that can be expressed as in equation (10) below, and stabilizes at current I2.

[0108] I2=VA / (r1+r2) (10)

[0109] The denominator r1+r2 of equation (10) representing current I2 is the sum of higher resistance values. The denominator r4+Ron(Q2)+r5+Ron(Q4) of equation (8) representing current I1 is smaller than the denominator r1+r2 of equation (10). Thus, current I2 is smaller than current I1.

[0110] At time t23, the control circuit 10 switches the signal EN1 to the L level. Time t23 corresponds to the time t21 when the control circuit 10 outputs the H-level signal EN1 and the H-level signal EN2 to the switching circuit 12a, after a longer second period W2 than the first period W1.

[0111] In the switching circuit 12a, the switching element Q3 becomes off based on the L-level signal EN1. As a result, the switching element Q2 also becomes off.

[0112] When switching element Q3 becomes off, the main current path from node N1 to ground voltage GND becomes a current path via series-connected resistors R1 to R3. Voltage VN1 is reduced by the discharge of the series-connected resistors R1 to R3.

[0113] If voltage VN1 discharges, the difference between voltage VN1 and voltage VA becomes greater than the forward voltage VF(Q2) of the body diode of switching element Q2, and the body diode of switching element Q2 becomes conductive. As a result, the current IL flowing into semiconductor device 1a flows to terminal PGND via resistor R4, the body diode of switching element Q2, resistor R1, resistor R2, and resistor R3.

[0114] Thus, the change in the current path at time t23 results in a decrease in voltage VN1 and a reduction in current IL. The changes in voltage VN1 and current IL will be explained separately.

[0115] The resistance values ​​of resistors R1 to R3 are greater than either the resistance value of resistor R4 or the parasitic resistance of the body diode of switching element Q2. Therefore, voltage VN1 drops to voltage V3 as can be expressed by the following equation (11) and stabilizes at voltage V3.

[0116] V3=VA-VF(Q2) (11)

[0117] Furthermore, the current IL is reduced to a current I3 that can be expressed as in equation (12) below, and stabilizes at current I3.

[0118] I3=((VA-VF(Q2)) / (r1+r2+r3)) (12)

[0119] Compared to equation (10) which represents current I2, equation (12) representing current I3 has a smaller numerator (VF(Q2)) and a larger denominator (r3). Thus, current I3 is smaller than current I2.

[0120] Thus, the semiconductor device 1a, upon receiving the cutoff operation instruction CMD, performs the cutoff operation, setting signals EN1 and EN2 to H level, and turning on switching elements Q2 to Q4, thereby turning off switching element Q1. Furthermore, if the setting of signals EN1 and EN2 to H level is followed by a first period W1, then signal EN2 is set to L level. Moreover, if the setting of signals EN1 and EN2 to H level is followed by a longer second period W2 than the first period W1, then signal EN1 is set to L level.

[0121] As a result, as explained above, when the semiconductor device 1a is connected to a load 2a containing a power supply PS, the magnitude of the gate-source voltage VGS (Q1) of the switching element Q1 is maintained below the withstand voltage VMAX (Q1). Furthermore, the magnitude of the current IL flowing from the terminal PVOUT is smaller after passing through the first period W1 and the second period W2 compared to the magnitude flowing in during the first period and the second period.

[0122] Furthermore, when the semiconductor device 1a is connected to the load 2 described in the first embodiment, if the semiconductor device 1a receives a cutoff operation command CMD, the voltage VN1 and the voltage VOUT are discharged to 0V within the first period W1. That is, when the load connected to the terminal PVOUT is the load 2, the semiconductor device 1a of the second embodiment operates in the same way as the semiconductor device 1 of the first embodiment, by setting the voltage VN1 to 0V and setting the gate-source voltage VGS(Q1) of the switching element Q1 to 0V or less or 0V.

[0123] [2-3] Effects

[0124] The semiconductor device 1a according to the second embodiment described above can suppress damage to the switching element Q1 during the cut-off operation and can suppress the current flowing into the terminal PVOUT. The effects of the semiconductor device 1a according to the second embodiment will be described in detail below.

[0125] The semiconductor device 1a of the second embodiment includes a resistive element R5. The resistive element R5 and the switching element Q4 are connected in series between node N1 and terminal PGND.

[0126] According to this configuration, the semiconductor device 1a of the second embodiment can suppress the damage of the switching element Q1 during the cutoff operation. Specifically, when the cutoff operation is performed with a load including the power supply PS connected to the terminal PVOUT, the current flowing into node N1 is discharged through the resistor element R5 and the on-state switching element Q4. Since the current flowing into node N1 is discharged through the resistor element R5, a voltage difference is generated across the resistor element R5. As a result, the situation where the difference between voltage VN1 and voltage VA increases is suppressed, thereby preventing the magnitude of the gate-source voltage VGS(Q1) of the switching element Q1 from becoming a withstand voltage VMAX(Q1) or higher. Therefore, the semiconductor device 1a of the second embodiment can suppress the damage of the switching element Q1 and improve the reliability of operation.

[0127] Furthermore, in the second embodiment, the control circuit 10 of the semiconductor device 1a sets the switching element Q4 from the on state to the off state after a first period W1 has elapsed since the switching elements Q3 and Q4 were set from the off state to the on state. Moreover, the control circuit 10 sets the switching element Q4 from the on state to the off state after a longer second period W2, which is longer than the first period W1, elapsed since the switching elements Q3 and Q4 were set from the off state to the on state.

[0128] Therefore, the semiconductor device 1a of the second embodiment can suppress the damage of the switching element Q1 during the cut-off operation and can suppress the current flowing into the semiconductor device 1a from the terminal PVOUT.

[0129] When a load including a power supply PS is connected to terminal PVOUT, if switching elements Q3 and Q4 are in the ON state, the current IL increases compared to when switching elements Q3 and Q4 are in the OFF state. During the OFF operation, semiconductor device 1a sets switching elements Q3 and Q4 to the OFF state after the second period W2, thus suppressing the current IL after the second period W2. Therefore, semiconductor device 1a of the second embodiment can suppress the load of a power supply when the connected load includes a power supply.

[0130] Furthermore, the semiconductor device 1a defines the second period W2 until the switching element Q4 is set to the off state as a length longer than or equal to the first period W1 until the switching element Q3 is set to the off state. Thus, during the period when the switching element Q4 is in the on state, the switching element Q3 is kept in the on state.

[0131] With a load including power supply PS connected to terminal PVOUT, and switching elements Q4 in the ON state and Q2 and Q3 in the OFF state, voltage VN1 is 0V, voltage VOUT becomes voltage VA, and the magnitude of the gate-source voltage VGS(Q1) of switching element Q1 may increase. The semiconductor device 1a of the second embodiment keeps switching element Q3 in the ON state while switching element Q4 is in the ON state, thus suppressing the increase of the gate-source voltage VGS(Q1) of switching element Q1 through resistor element R5. Therefore, the semiconductor device 1a of the second embodiment can suppress the current flowing into the semiconductor device 1a from terminal PVOUT and can suppress damage to switching element Q1.

[0132] [2-4] Examples of other actions

[0133] exist Figure 4 In the example shown, the second period W2 is longer than the first period W1. In the second embodiment, since the second period W2 only needs to be longer than or equal to the first period W1, the second period W2 can also be equal to the first period W1. Hereinafter, refer to... Figure 5 The case where W2 in the second period is equal to W1 in the first period is explained.

[0134] Figure 5 This is a timing diagram illustrating other operational examples of the semiconductor device according to the second embodiment. Figure 5 The image shows a semiconductor device 1a, which is performing a turn-on operation, receiving a cut-off command CMD and executing the cut-off operation. Figure 5 The diagram shows the voltage VN1 at node N1, the voltage VOUT at terminal PVOUT, the current IL flowing from terminal PVOUT into semiconductor device 1a, signal EN1, and signal EN2.

[0135] Figure 5 The action example shown is relative to Figure 4 The action example shown differs in the length of the second period W2. Figure 5 The times t30, t31, and t32 correspond to respectively Figure 4 The times t20, t21, and t22. Figure 5 The actions from time t30 to time t32 and Figure 4 The actions from time t20 to time t22 are the same. Figure 5 Actions after time t32 and Figure 4 The actions after time t22 are different.

[0136] During the period from time t30 to time t31, semiconductor device 1a is in a conducting operation. During the period from time t30 to time t31, voltage VN1 is equal to voltage VH. During the period from time t30 to time t31, voltage VN1 is greater than voltage VA, therefore the current flowing into semiconductor device 1a is 0A. During the period from time t30 to time t31, signals EN1 and EN2 maintain a low level.

[0137] At time t31, semiconductor device 1a receives the cutoff operation command CMD and executes the cutoff operation. At time t31, signals EN1 and EN2 change from L level to H level. Furthermore, after time t31, voltage VN1 decreases to voltage V1 and stabilizes at voltage V1. After time t31, the current flowing into terminal PVOUT increases to I1 and stabilizes at current I1.

[0138] At time t32, the control circuit 10 switches signals EN1 and EN2 to L level, respectively. Time t32 corresponds to the time t31 from when the control circuit 10 outputs H level signals EN1 and EN2 from the switching circuit 12a, after the timing of the first period W1 and the second period W2 which is equal to the first period W1.

[0139] In switching circuit 12a, switching element Q3 is turned off based on the low-level signal EN1. As a result, switching element Q2 is also turned off. Furthermore, switching element Q4 is turned off based on the low-level signal EN2.

[0140] Therefore, the current IL flowing into semiconductor device 1a flows to terminal PGND via resistor R4, the body diode of switching element Q2, resistor R1, resistor R2, and resistor R3. After time t32, voltage VN1 rises to voltage V3 and stabilizes at voltage V3. After time t32, current IL decreases to current I3 and stabilizes at current I3.

[0141] Thus, when the second period W2 is set to be equal to the first period W1, the semiconductor device of the second embodiment can also suppress the damage of the switching element Q1 during the cut-off operation and suppress the current flowing in from the terminal PVOUT.

[0142] [3] Variations, etc.

[0143] In the above embodiment, the example described is that the semiconductor device serving as a load switch is configured within an IC chip. However, a load switch can also be configured by combining multiple components, such as an IC chip with a gate driver and a package of switching elements. Figure 6This is a circuit diagram illustrating an example of the configuration of a modified semiconductor device and a load powered by the semiconductor device. Semiconductor device 1b is a load switch that powers load 2. Semiconductor device 1b includes semiconductor device 100 and switching element Q1a.

[0144] Semiconductor device 100 is a gate driver that drives the gate of switching element Q1a. Semiconductor device 100 is, for example, an IC chip. Compared to semiconductor device 1 described in the first embodiment, semiconductor device 100 has a configuration that does not include switching element Q1 but further includes terminal PVGATE. Terminal PVGATE is an output terminal of semiconductor device 100. Terminal PVGATE is connected to node N1. Other configurations of semiconductor device 100 are the same as those of semiconductor device 1 described in the first embodiment.

[0145] Switching element Q1a is an N-channel MOSFET. Switching element Q1a is, for example, a semiconductor device packaged independently of semiconductor device 100. The drain of switching element Q1a is connected to terminal PVIN. The source of switching element Q1a is connected to terminal PVOUT. The gate of switching element Q1a is connected to terminal PVGATE.

[0146] Thus, even when multiple components are combined to form a load switch, the same effect as the implementation method can be obtained.

[0147] In the above embodiments, examples of loads powered by semiconductor devices were described, including capacitive and resistive loads, and loads including capacitive loads and power supplies. However, the configuration of a load powered by a semiconductor device is not limited to the examples shown in the above embodiments. A load powered by a semiconductor device can be, for example, an information processing terminal such as a personal computer or a smartphone, or a battery charging device.

[0148] In this specification, "the first terminal of the switching element" corresponds to the source or drain of the MOSFET. "The second terminal of the switching element" corresponds to the drain or source of the MOSFET.

[0149] In this specification, "approximately equal voltages" means that even if there is a small voltage difference due to the influence of transistor on-resistance, leakage current, resistive components of wiring, etc., they are considered to be approximately equal.

[0150] In this specification, "connection" refers to an electrical connection, which may include other components. Furthermore, regarding "electrical connection," an insulator may be present as long as the same operation as the electrical connection structure is possible. Additionally, in this specification, "on state" means applying a voltage greater than or equal to the threshold voltage of the corresponding transistor to its gate. "Off state" means applying a voltage less than the threshold voltage of the corresponding transistor to its gate, which may include, for example, a small current flow such as leakage current.

[0151] While several embodiments of the invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, as well as within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device, characterized by comprising: have: First terminal; Second terminal; First circuit; and Second circuit; The first circuit includes: The first switching element includes a first terminal connected to a first node supplied with a first voltage, a second terminal connected to the first terminal, and a gate connected between the first node and the second terminal. The first resistor and the second switching element are connected in series between the first node and the second terminal; The second resistor has one end connected to the first node; The third resistor has one end connected to the other end of the second resistor and the gate of the first switching element; The fourth resistor has one end connected to the second terminal; as well as The third switching element includes a first end connected to the second terminal and a second end connected to the other end of the third resistor and the other end of the fourth resistor; When the supply of the first voltage to the first node is stopped, the first switching element and the second switching element are switched from the off state to the on state. When the supply of the first voltage to the first node is stopped, the second circuit sets the second switching element and the third switching element from the off state to the on state.

2. The semiconductor device of claim 1, wherein, After a first period has elapsed since the second circuit switched the second and third switching elements from the off state to the on state, it switches the second switching element from the on state to the off state. After a second period longer than the first period has elapsed since the second switching element and the third switching element were changed from the off state to the on state, the second circuit changes the third switching element from the on state to the off state.

3. The semiconductor device as claimed in claim 2, wherein, The second circuit sets the gate voltages of the second and third switching elements from a cutoff state to a conducting state by changing the gate voltages of the second and third switching elements from a first logic level to a second logic level. After the first period has elapsed since the second circuit switched the second and third switching elements from the off state to the on state, it switches the gate voltage of the second switching element from the second logic level to the first logic level. After the second circuit has passed the second period from setting the second switching element and the third switching element from the off state to the on state, it sets the voltage of the gate of the third switching element from the second logic level to the first logic level.

4. The semiconductor device of claim 1, wherein, The first switching element is a P-channel MOSFET. The second and third switching elements are N-channel MOSFETs.

5. The semiconductor device of claim 1, wherein, It also includes a third circuit that generates the first voltage and outputs the generated first voltage to the first node. The second circuit instructs the third circuit to stop the output of the first voltage.

6. The semiconductor device according to any one of Claims 1 to 5, wherein It also has: The third terminal is supplied with a second voltage from outside the semiconductor device; and The fourth switching element includes a first end connected to the first terminal, a second end connected to the third terminal, and a gate connected to the first node.

7. The semiconductor device of claim 6, wherein, The first voltage is higher than the second voltage. The fourth switching element is an N-channel MOSFET.

8. The semiconductor device according to any one of claims 1 to 5, wherein, It also has a fourth terminal connected to the first node.

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