Level conversion circuits, chips and electronic devices

Abstract

This invention discloses a level conversion circuit, a chip, and an electronic device. The level conversion circuit includes a level input module, a level output module, a first switch module, a second switch module, an isolation module, a first pull-up transistor, and a second pull-up module. Through the circuit connection of the level conversion circuit of this application, when the level input module is connected to a ground signal, the level output module can be controlled to output a ground signal; when the level input module is connected to a low-voltage level signal, the level output module can be controlled to output a high-voltage level signal. This application achieves the conversion of high-voltage level signals with a small number of transistors, effectively improving the level conversion efficiency while protecting the working stability of the level conversion circuit and reducing the chip production cost.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a level conversion circuit, chip, and electronic device. Background Technology

[0002] Different operating voltage levels often exist within the same chip, necessitating the transmission of signals between these levels. High-voltage level conversion circuits convert low-voltage input control signals into high-voltage output control signals. However, during high-voltage level conversion, if the difference between the low-voltage input signal and the high-voltage output signal is too large, more high-breakdown-voltage transistors are needed to step down the voltage. Adding too many high-breakdown-voltage transistors can significantly reduce the driving capability of the driver transistors, even preventing the low-voltage control signal from being transmitted correctly, thus causing the entire level conversion circuit to malfunction. Summary of the Invention

[0003] To address the aforementioned technical problems, this application provides a level conversion circuit, a chip, and an electronic device, with the specific solutions as follows:

[0004] In a first aspect, embodiments of this application provide a level conversion circuit, including: a level input module, a first switch module, a second switch module, an isolation module, and a level output module;

[0005] The level input module includes a level input interface and a first inverter, wherein the input terminal of the first inverter is connected to the level input interface;

[0006] One end of the first switch module MN2 is connected to the level input interface, and one end of the second switch module MN3 is connected to the output terminal of the first inverter;

[0007] The first switch module and the second switch module are connected to the level output module through the isolation module;

[0008] The level output module includes a level output interface, a second inverter, a first pull-up transistor, and a second pull-up module.

[0009] One end of the first pull-up transistor and one end of the second pull-up module are connected to the level output interface, the input of the second inverter is connected to the level output interface, and the output of the second inverter outputs a feedback signal to control the on / off state of the first pull-up transistor.

[0010] When the level input interface is connected to a ground signal, the first switch module is turned off, the second switch module is turned on, and the level output interface outputs a ground signal; when the level input interface is connected to a low-voltage level signal, the first switch module is turned on, the second switch module is turned off, and the level output interface outputs a high-voltage level signal.

[0011] According to a specific embodiment of the present application, the first inverter includes a first P-type transistor and a first N-type transistor;

[0012] The control terminals of the first P-type transistor and the first N-type transistor are connected to the level input interface. The source of the first P-type transistor is used to receive the low-voltage level signal. The source of the first N-type transistor is grounded. The drains of the first P-type transistor and the first N-type transistor serve as the output terminals of the first inverter and are connected to the control terminal of the second switching submodule.

[0013] According to a specific embodiment of the present application, the first switch module is a first switch transistor, and the second switch submodule is a second switch transistor;

[0014] The first switching transistor, the second switching transistor, the first P-type transistor, and the first N-type transistor are all low breakdown voltage transistors.

[0015] According to a specific embodiment of the present application, the second inverter includes a second P-type transistor and a second N-type transistor;

[0016] The second pull-up module includes a second pull-up transistor and a third pull-up transistor. The sources of both the second and third pull-up transistors are used to connect to the high-voltage level signal. The drain of the second pull-up transistor is connected to the level output interface. The control terminals of the second and third pull-up transistors and the drain of the third pull-up transistor are all connected to the isolation module.

[0017] The isolation module includes a first isolation tube, a second isolation tube, a third isolation tube, and a fourth isolation tube. The control terminals of the first and second isolation tubes are used to receive low-voltage level signals. The control terminal of the third isolation tube is connected to the output terminal of the first inverter. The control terminal of the fourth isolation tube is used to receive high-voltage level signals. The first switching transistor is connected to the drain of the third pull-up transistor through the first and third isolation tubes. The second switching transistor is connected to the level output interface through the second and fourth isolation tubes.

[0018] The control terminals of the second P-type transistor and the second N-type transistor are connected to the level output interface as the input terminals of the second inverter. The source of the second P-type transistor is used to connect to the high-voltage level signal, and the source of the second N-type transistor is grounded. The drains of the second P-type transistor and the second N-type transistor are connected to the control terminals of the third isolation transistor and the third pull-up transistor as the output terminals of the second inverter.

[0019] According to a specific embodiment of this application, the first isolation transistor, the second isolation transistor, the third isolation transistor, the fourth isolation transistor, the first pull-up transistor, the second pull-up transistor, the third pull-up transistor, the second P-type transistor, and the second N-type transistor are all high breakdown voltage transistors.

[0020] According to a specific embodiment of the present application, the first pull-up transistor is a weak pull-up transistor, and the second pull-up transistor and the third pull-up transistor are both strong pull-up transistors.

[0021] According to a specific embodiment of this application, when the level input interface is connected to a ground signal, the first inverter outputs a low-voltage level signal, the first switch is turned off, the second switch is turned on, the first pull-up transistor and the second pull-up transistor are turned off, the input terminal of the second inverter receives the ground signal, the output terminal of the second inverter outputs a high-voltage level signal, the state of the third pull-up transistor changes from the on state to the off state, the third isolation transistor is turned on, and the level output interface is used to output a ground signal.

[0022] According to a specific embodiment of this application, when a low-voltage level signal is connected to the level input interface, the first inverter outputs a ground signal, the first switch is turned on, the second switch is turned off, the first pull-up transistor and the second pull-up transistor are turned off, and the states of the first pull-up transistor and the second pull-up transistor change from the on state to the off state. The input terminal of the second inverter receives a high-voltage level signal, the output terminal of the second inverter outputs a ground signal, the third isolation transistor is turned off, the third pull-up transistor is turned on, and the level output interface is used to output a high-voltage level signal.

[0023] Secondly, embodiments of this application provide a chip, the chip including the level conversion circuit described in the first aspect and any embodiment of the first aspect.

[0024] Thirdly, embodiments of this application provide an electronic device, which includes the chip described in the second aspect above.

[0025] This application provides a level conversion circuit, a chip, and an electronic device. The level conversion circuit includes: a level input module, a level output module, a first switch module, a second switch module, an isolation module, a first pull-up transistor, and a second pull-up module. Through the circuit connection of this application's level conversion circuit, when the level input module is connected to a ground signal, the level output module can be controlled to output a ground signal; when the level input module is connected to a low-voltage level signal, the level output module can be controlled to output a high-voltage level signal. This application achieves high-voltage level signal conversion with a small number of transistors, effectively improving level conversion efficiency while protecting the operational stability of the level conversion circuit and reducing chip production costs. Attached Figure Description

[0026] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope of protection of the present invention. In the various drawings, similar components are numbered similarly.

[0027] Figure 1 A schematic diagram of the circuit connection of a level conversion circuit provided in an embodiment of this application is shown. Detailed Implementation

[0028] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0029] The components of the embodiments of the invention described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0030] In the following, the terms “comprising,” “having,” and their cognates, which may be used in various embodiments of the invention, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as excluding, firstly, the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations thereof.

[0031] Furthermore, the terms "first," "second," and "third" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0032] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the invention pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of the invention.

[0033] refer to Figure 1 This is a circuit connection diagram of a level conversion circuit provided in an embodiment of this application. The level conversion circuit provided in this embodiment of the application is as follows: Figure 1 As shown, the level conversion circuit includes: a level input module, a first switch module, a second switch module, an isolation module, and a level output module;

[0034] The level input module includes a level input interface IN and a first inverter, wherein the input terminal of the first inverter is connected to the level input interface IN.

[0035] One end of the first switch module is connected to the level input interface IN, and one end of the second switch module is connected to the output terminal of the first inverter;

[0036] The first switch module and the second switch module are connected to the level output module through the isolation module;

[0037] The level output module includes a level output interface OUT, a second inverter, a first pull-up transistor MP5, and a second pull-up module MP3.

[0038] One end of the first pull-up transistor MP5 and one end of the second pull-up module MP3 are connected to the level output interface OUT. The input of the second inverter is connected to the level output interface OUT. The output of the second inverter outputs a feedback signal to control the on / off state of the first pull-up transistor MP5.

[0039] When the level input interface IN is connected to the ground signal VSS, the first switch module is turned off, the second switch module is turned on, and the level output interface OUT outputs the ground signal VSS; when the level input interface IN is connected to the low-voltage level signal VDDL, the first switch module is turned on, the second switch module is turned off, and the level output interface OUT outputs the high-voltage level signal VDDH.

[0040] Specifically, the voltage conversion circuit described in this embodiment can be applied to any chip that needs to convert low-voltage signals into high-voltage signals.

[0041] In specific embodiments, the chip circuit often has a variety of electronic components that require different power supplies to drive, or the electronic components in the chip circuit need to be connected to different driving voltages at different times. In this case, the voltage conversion circuit proposed in this embodiment can be used to drive the electronic components that require high-voltage signals through the low-voltage level signal provided by the low-voltage power supply connected to the level input interface IN.

[0042] Specifically, the level input interface IN can be used to connect a power supply capable of providing low-voltage level signals, such as a power supply providing voltage signals below 1.5V or a power supply providing voltage signals below 0.8V.

[0043] This embodiment does not specifically limit the power supply specifications of the level input interface IN. The level input interface IN can also be connected to other electronic components, and the power supply voltage of the electronic components is a low-voltage level signal.

[0044] The level output interface OUT can be used to connect an electronic component that requires a high-voltage level signal to drive it, such as an electronic component that requires a voltage signal of 2V or higher or an electronic component that requires a voltage signal of 4.95V or higher.

[0045] The electronic components connected to the level output interface OUT in this embodiment can be adaptively configured according to the needs of the actual application scenario.

[0046] Specifically, such as Figure 1 As shown, in this embodiment, the first switching module can be a first switching transistor MN2, and the second switching module can be a second switching transistor MN3. The control electrode of the first switching transistor MN2 is connected to the level input interface IN, and the control electrode of the second switching transistor MN3 is connected to the output terminal of the first inverter.

[0047] The sources of both the first switch MN2 and the second switch MN3 are grounded. When either the first switch MN2 or the second switch MN3 is turned on, the voltage of the circuit containing the switch will be pulled to ground. The first and second switch modules can also be replaced with switching devices that have the same function as the first switch MN2 and the second switch MN3, depending on the actual application scenario. No limitation is made here.

[0048] In this embodiment, the first inverter is a low-level operating voltage inverter, and the second inverter is a high-level operating voltage inverter.

[0049] When the input terminal of the first inverter is the ground signal VSS, the output terminal of the first inverter is the low voltage level signal VDDL; when the input terminal of the first inverter is the low voltage level signal VDDL, the output terminal of the first inverter is the ground signal VSS.

[0050] When the input terminal of the second inverter is the ground signal VSS, the output terminal of the second inverter is the high-voltage level signal VDDH; when the input terminal of the second inverter is the high-voltage level signal VDDH, the output terminal of the second inverter is the ground signal VSS.

[0051] More specifically, the structure of the first inverter can be as follows: Figure 1 As shown, the first inverter includes a first P-type transistor MP1 and a first N-type transistor MN1;

[0052] The control terminals of the first P-type transistor MP1 and the first N-type transistor MN1 are connected to the level input interface IN. The source of the first P-type transistor MP1 is used to connect to the low-voltage level signal VDDL. The source of the first N-type transistor MN1 is grounded. The drains of the first P-type transistor MP1 and the first N-type transistor MN1 serve as the output terminals of the first inverter and are connected to the control terminal of the second switching transistor MN3.

[0053] In a specific embodiment, when the level input interface IN receives the ground signal VSS, the first P-type transistor MP1 is turned on and the first N-type transistor MN1 is turned off. At this time, the signal output by the output terminal INB of the first inverter is the low-voltage level signal VDDL of the source of the first P-type transistor MP1.

[0054] When the level input interface IN receives a low-voltage level signal VDDL, the first P-type transistor MP1 is turned off and the first N-type transistor MN1 is turned on. At this time, the signal output by the output terminal INB of the first inverter is the ground signal VSS of the source of the first N-type transistor MN1.

[0055] In actual control, the gate of the first switch MN2 is connected to the level input interface IN, and the on / off state of the first switch MN2 is determined by the voltage signal at the level input interface IN. When the voltage at the level input interface IN is the ground signal VSS, the first switch MN2 is turned off; when the voltage at the level input interface IN is the low voltage level signal VDDL, the first switch MN2 is turned on.

[0056] The gate of the second switch MN3 is connected to the output terminal INB of the first inverter. The on / off state of the second switch MN3 is determined by the voltage signal at the output terminal INB. When the voltage at the output terminal INB is ground signal VSS, the second switch MN3 is off; when the voltage at the output terminal INB is a low voltage level signal VDDL, the second switch MN3 is on.

[0057] Furthermore, the first switch MN2, the second switch MN3, the first P-type transistor MP1, and the first N-type transistor MP2 are all low breakdown voltage transistors.

[0058] In a specific embodiment, the transistors near the level signal input terminal IN can all be low breakdown voltage transistor devices, thereby reducing the number of high breakdown voltage transistor devices in the level conversion circuit and improving the transmission stability of low voltage control signals in the level conversion circuit.

[0059] Specifically, the second inverter in this embodiment can be as follows: Figure 1 As shown, the second inverter includes a second P-type transistor MP4 and a second N-type transistor MN8;

[0060] The control terminals of the second P-type transistor MP4 and the second N-type transistor MN8 are connected to the level output interface OUT as the input terminals of the second inverter. The source of the second P-type transistor MP4 is used to connect to the high-voltage level signal VDDH. The source of the second N-type transistor MN8 is grounded. The drains of the second P-type transistor MP4 and the second N-type transistor MN8 are connected to the level signal output interface OUT as the output terminals of the second inverter.

[0061] In a specific embodiment, when the input terminal of the second inverter is ground signal VSS, the second P-type transistor MP4 is turned on, the second N-type transistor MN8 is turned off, and the voltage signal output by the output terminal OUTB of the second inverter is the high voltage level signal VDDH of the source of the second P-type transistor MP4.

[0062] When the input terminal of the second inverter is a high-voltage level signal VDDH, the second P-type transistor MP4 is turned off, the second N-type transistor MN8 is turned on, and the voltage signal output by the output terminal OUTB of the second inverter is the source ground signal VSS of the second N-type transistor MN8.

[0063] In practical applications, both the first inverter and the second inverter can be replaced by inverters that meet the voltage conversion requirements; no specific limitations are made here.

[0064] According to a specific embodiment of this application, the second pull-up module includes a second pull-up transistor MP3 and a third pull-up transistor MP2, wherein the sources of the second pull-up transistor MP3 and the third pull-up transistor MP2 are both used to connect to the high-voltage level signal VDDH, the drain of the second pull-up transistor MP3 is connected to the level output interface OUT, and the control terminals of the second pull-up transistor MP3, the third pull-up transistor MP2, and the drain of the third pull-up transistor MP2 are all connected to the isolation module;

[0065] The isolation module includes a first isolation tube MN4, a second isolation tube MN5, a third isolation tube MN6, and a fourth isolation tube MN7. The control terminals of the first isolation tube MN4 and the second isolation tube MN5 are used to receive low-voltage level signals. The control terminal of the third isolation tube MN6 is connected to the output terminal of the first inverter. The control terminal of the fourth isolation tube MN7 is used to receive a high-voltage level signal VDDH. The first switching tube MN2 is connected to the drain of the third pull-up tube MP2 through the first isolation tube MN4 and the third isolation tube MN6. The second switching tube MN3 is connected to the level output interface OUT through the second isolation tube MN5 and the fourth isolation tube MN7.

[0066] The first isolation transistor MN4, the second isolation transistor MN5, the third isolation transistor MN6, the fourth isolation transistor MN7, the third pull-up transistor MP2, the second pull-up transistor MP3, the first pull-up transistor MP5, the second P-type transistor MP4, and the second N-type transistor MN8 are all high breakdown voltage transistors.

[0067] In a specific embodiment, the first isolation tube MN4 and the second isolation tube MN5 constitute a first-level high-level step-down isolation tube, and the third isolation tube MN6 and the fourth isolation tube MN7 constitute a second-level high-level step-down isolation tube, both used to isolate the high-level signal VDDH and the low-level signal VDDL.

[0068] Furthermore, the sources of the third pull-up transistor MP2, the second pull-up transistor MP3, the first pull-up transistor MP5, and the second P-type transistor MP4 are all used to connect to the high-level signal VDDH. Therefore, all of the above transistor components need to be high-breakdown-voltage transistors to prevent the transistors in the level conversion circuit from being broken down by the high-level signal.

[0069] In addition, the third pull-up transistor MP2 and the second pull-up transistor MP3 are both strong pull-up transistors, while the first pull-up transistor MP5 is a weak pull-up transistor.

[0070] In practical applications, when the level output interface OUT outputs a high-voltage level signal, the voltage signal at OUT is continuously pulled up through the first pull-up transistor MP5. Therefore, the third pull-up transistor adopts a weak pull-up transistor to reduce the loss of the pull-up drive transistor.

[0071] According to a specific embodiment of this application, when the level input interface IN is connected to the ground signal VSS, the first inverter outputs a low-voltage level signal VDDL, the first switch MN2 is turned off, the second switch MN3 is turned on, the third pull-up transistor MP2 and the second pull-up transistor MP3 are turned off, the input terminal of the second inverter receives the ground signal VSS, the output terminal of the second inverter outputs a high-voltage level signal VDDH, the state of the first pull-up transistor MP5 changes from the on state to the off state, and the level output interface OUT is used to output the ground signal VSS.

[0072] In a specific embodiment, when the input signal at the level input interface IN is the ground signal VSS, the output signal at the output terminal INB of the first inverter is the low-level signal VDDL. At this time, the first switch MN2 is turned off, the second switch MN3 is turned on, and no current flows in the cascaded path formed by the first switch MN2, the first isolation tube MN4, the third isolation tube MN6 and the third pull-up tube MP2.

[0073] At this time, the gates of the third pull-up transistor MP2 and the second pull-up transistor MP3 are pulled to a high-level operating voltage state by the high-level signal VDDH of the source of the first pull-up transistor, and the third pull-up transistor MP2 and the second pull-up transistor MP3 are turned off.

[0074] At this time, the first pull-up transistor MP5 may be in the on state. When the cascaded path formed by the second switching transistor MN3, the second isolation transistor MN5 and the fourth isolation transistor MN7 pulls the voltage at the level signal output interface OUT to the ground signal VSS, the output signal of the output terminal OUTB of the second inverter becomes the high-level signal VDDH, controlling the first pull-up transistor MP5 to turn off and the third isolation transistor MN6 to turn on, so that the signal at the level output interface OUT is continuously the ground signal VSS.

[0075] According to a specific embodiment of this application, when the level input interface IN is connected to a low-voltage level signal VDDL, the first inverter outputs a ground signal VSS, the first switch MN2 is turned on, the second switch MN3 is turned off, the third pull-up transistor MP2 and the second pull-up transistor MP3 are turned off, and the states of the third pull-up transistor MP2 and the second pull-up transistor MP3 change from the on state to the off state. The input terminal of the second inverter receives a high-voltage level signal VDDH, the output terminal of the second inverter outputs a ground signal VSS, the first pull-up transistor MP5 is turned on, and the level output interface is used to output the high-voltage level signal VDDH.

[0076] In a specific embodiment, when the level input interface IN is connected to a low-voltage level signal VDDL, the output signal at the output terminal INB of the first inverter is a ground signal VSS. At this time, the first switch MN2 is turned on, the second switch MN3 is turned off, and current flows in the cascaded path formed by the first switch MN2, the first isolation tube MN4, the third isolation tube MN6 and the third pull-up tube MP2, causing the third pull-up tube MP3 to turn on and pull up the voltage at the level output interface OUT to the high-voltage level signal VDDH.

[0077] At this time, the voltage signal received by the second inverter is the high-voltage level signal VDDH, and the voltage signal at the output terminal OUTB of the second inverter is the ground signal VSS, thereby controlling the first pull-up transistor MP5 to turn on and the third isolation transistor MN6 to turn off.

[0078] At this time, the cascaded path consisting of the first switching transistor MN2, the first isolation transistor MN4, the third isolation transistor MN6, and the third pull-up transistor MP2 is turned off by the ground isolation transistor MN6, and the current is cut off. This causes the voltage at the gate of the third pull-up transistor MP2 and the second pull-up transistor MP3 to be pulled up to a high-level signal VDDH, thereby turning off the third pull-up transistor MP2 and the second pull-up transistor MP3.

[0079] At this time, the voltage signal at the output interface OUT is kept high by the first pull-up transistor MP5, which maintains the level signal VDDH.

[0080] The level conversion circuit proposed in this embodiment achieves the conversion of low-voltage signals to high-voltage signals based on a small number of high-breakdown-voltage transistor components. Furthermore, the primary high-voltage signal isolator formed by the first and second isolators, and the secondary high-voltage signal isolator formed by the third and fourth isolators, effectively protect the safety of the low-breakdown-voltage transistor components in the level conversion circuit, thus significantly improving the conversion stability and safety of the level conversion circuit in this embodiment.

[0081] In addition, this application also provides a chip, which includes the level conversion circuit in the foregoing embodiments.

[0082] The chip in this embodiment includes electronic components that require low-voltage level signals to drive and electronic components that require high-voltage level signals to drive.

[0083] Furthermore, the electronic components that require low-voltage level signals for driving and the electronic components that require high-voltage level signals for driving can be the same electronic component.

[0084] This application also provides an electronic device, which includes the level conversion circuit described in the foregoing embodiments.

[0085] In summary, this application provides a level conversion circuit, a chip, and an electronic device. The level conversion circuit proposed in this embodiment achieves the conversion between low-voltage and high-voltage signals using a small number of high-breakdown-voltage transistors and low-breakdown-voltage transistors. While ensuring the level conversion efficiency of the circuit, it effectively reduces the manufacturing cost of the level conversion circuit, thereby reducing the manufacturing cost of the corresponding chip and improving production efficiency. Furthermore, the specific implementation process of the chip and electronic device mentioned in the above embodiments can be found in the specific implementation process of the circuit embodiments above, and will not be repeated here.

[0086] In addition, the functional modules or units in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0087] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A level conversion circuit, characterized in that, include: Level input module, first switch module, second switch module, isolation module and level output module; The level input module includes a level input interface and a first inverter, wherein the input terminal of the first inverter is connected to the level input interface; One end of the first switch module is connected to the level input interface, and one end of the second switch module is connected to the output terminal of the first inverter; the first switch module is a first switch transistor, and the second switch module is a second switch transistor; The first switch module and the second switch module are connected to the level output module through the isolation module; The level output module includes a level output interface, a second inverter, a first pull-up transistor, and a second pull-up module. One end of the first pull-up transistor and one end of the second pull-up module are connected to the level output interface. The other end of the first pull-up transistor is used to receive a high-voltage level signal. The input of the second inverter is connected to the level output interface. The output of the second inverter outputs a feedback signal to control the on / off state of the first pull-up transistor. When the level input interface is connected to a ground signal, the first switch module is turned off, the second switch module is turned on, and the level output interface outputs a ground signal. When a low-voltage signal is received at the level input interface, the first switch module is turned on, the second switch module is turned off, and the level output interface outputs a high-voltage signal. The second pull-up module includes a second pull-up transistor and a third pull-up transistor. The sources of both the second and third pull-up transistors are used to connect to the high-voltage level signal. The drain of the second pull-up transistor is connected to the level output interface. The control terminals of the second and third pull-up transistors and the drain of the third pull-up transistor are all connected to the isolation module. The isolation module includes a first isolation tube, a second isolation tube, a third isolation tube, and a fourth isolation tube. The control terminals of the first and second isolation tubes are used to receive low-voltage level signals. The control terminal of the third isolation tube is connected to the output terminal of the second inverter. The control terminal of the fourth isolation tube is used to receive high-voltage level signals. The first switching transistor is connected to the drain of the third pull-up transistor through the first and third isolation tubes. The second switching transistor is connected to the level output interface through the second and fourth isolation tubes.

2. The level conversion circuit according to claim 1, characterized in that, The first inverter includes a first P-type transistor and a first N-type transistor; The control terminals of the first P-type transistor and the first N-type transistor are connected to the level input interface. The source of the first P-type transistor is used to receive the low-voltage level signal, and the source of the first N-type transistor is grounded. The drains of the first P-type transistor and the first N-type transistor serve as the output terminals of the first inverter and are connected to the control terminal of the second switching module.

3. The level conversion circuit according to claim 2, characterized in that, The first switching transistor, the second switching transistor, the first P-type transistor, and the first N-type transistor are all low breakdown voltage transistors.

4. The level conversion circuit according to claim 3, characterized in that, The second inverter includes a second P-type transistor and a second N-type transistor; The control terminals of the second P-type transistor and the second N-type transistor are connected to the level output interface as the input terminals of the second inverter. The source of the second P-type transistor is used to connect to the high-voltage level signal, and the source of the second N-type transistor is grounded. The drains of the second P-type transistor and the second N-type transistor are connected to the control terminals of the third isolation transistor and the third pull-up transistor as the output terminals of the second inverter.

5. The level conversion circuit according to claim 4, characterized in that, The first isolation transistor, the second isolation transistor, the third isolation transistor, the fourth isolation transistor, the first pull-up transistor, the second pull-up transistor, the third pull-up transistor, the second P-type transistor, and the second N-type transistor are all high breakdown voltage transistors.

6. The level conversion circuit according to claim 5, characterized in that, The first pull-up transistor is a weak pull-up transistor, while the second and third pull-up transistors are both strong pull-up transistors.

7. The level conversion circuit according to claim 6, characterized in that, When the level input interface is connected to a ground signal, the first inverter outputs a low-voltage level signal, the first switch is turned off, the second switch is turned on, the first pull-up transistor and the second pull-up transistor are turned off, the input terminal of the second inverter receives the ground signal, the output terminal of the second inverter outputs a high-voltage level signal, the state of the third pull-up transistor changes from the on state to the off state, the third isolation transistor is turned on, and the level output interface is used to output a ground signal.

8. The level conversion circuit according to claim 6, characterized in that, When a low-voltage signal is connected to the level input interface, the first inverter outputs a ground signal, the first switch is turned on, the second switch is turned off, the first pull-up transistor and the second pull-up transistor are turned off, and the states of the first pull-up transistor and the second pull-up transistor change from the on state to the off state. The input terminal of the second inverter receives a high-voltage signal, the output terminal of the second inverter outputs a ground signal, the third isolation transistor is turned off, the third pull-up transistor is turned on, and the level output interface is used to output a high-voltage signal.

9. A chip, characterized in that, The chip includes the level conversion circuit according to any one of claims 1-8.

10. An electronic device, characterized in that, The electronic device includes the chip of claim 9.

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