All-digital phase-locked loop and its correction method

Abstract

The present disclosure relates to an all-digital phase-locked loop and a correction method thereof. An all-digital phase-locked loop (ADPLL) includes a digitally controlled oscillator (DCO) configured to generate a clock signal according to a frequency control signal; a time-to-digital converter (TDC) coupled to the digitally controlled oscillator and configured to generate a digital output signal according to a phase difference between the clock signal and a reference signal; and a normalization circuit coupled to the time-to-digital converter and configured to convert the digital output signal into a clock phase value according to a gain parameter; wherein the normalization circuit selects one of a plurality of candidate gain parameters stored in the normalization circuit as the gain parameter according to the digital output signal.

Description

Technical Field

[0001] This invention relates to an all-digital phase-locked loop, and more particularly to an all-digital phase-locked loop and its correction method, such as a gain correction method for a time-to-digital converter within the all-digital phase-locked loop. Background Technology

[0002] In the operation of an all-digital phase-locked loop (PLL), a time-to-digital converter (TD-to-RTC) acts as a phase detector, converting the phase difference between the reference signal and the output signal of the digitally controlled oscillator into digital code, enabling subsequent processing in the digital domain. However, the TDC retains some characteristics of analog circuits; for example, its resolution may vary due to factors such as process-voltage-temperature (PVT) variations. Since the TDC's resolution affects the setpoints of certain parameters in the all-digital PLL, estimation errors in the TDC's resolution can impact the overall performance of the PLL.

[0003] Therefore, a novel architecture and related calibration method are needed to ensure that parameters related to the time-to-digital converter (e.g., the gain of the time-to-digital converter) can be properly obtained with correct or optimal values ​​under various process variations and temperatures. Summary of the Invention

[0004] One of the objectives of this invention is to provide an all-digital phase-locked loop (ADPLL) and its correction method, so as to set the parameters related to the time-to-digital converter without or with minimal side effects, so as to give the time-to-digital converter better linearity.

[0005] One embodiment of the present invention discloses an all-digital phase-locked loop (ADPLL), comprising: a digitally controlled oscillator (DCO) for generating a clock signal based on a frequency control signal; a time-to-digital converter (TDC) coupled to the DCO for generating a digital output signal based on the phase difference between the clock signal and a reference signal; and a normalization circuit coupled to the TDC for converting the digital output signal into a clock phase value based on a gain parameter; wherein the normalization circuit selects one of a plurality of stored candidate gain parameters as the gain parameter corresponding to the digital output signal.

[0006] One embodiment of the present invention discloses a correction method for an all-digital phase-locked loop (ADPLL), comprising: generating a clock signal using a digitally controlled oscillator (DCO) in the ADPLL based on a frequency control signal; generating a digital output signal using a time-to-digital converter (TDC) in the ADPLL based on the phase difference between the clock signal and a reference signal; converting the digital output signal into a clock phase value using a normalization circuit in the ADPLL based on a gain parameter; and selecting one of a plurality of candidate gain parameters stored in the normalization circuit as the gain parameter based on the digital output signal.

[0007] The all-digital phase-locked loop and its correction method provided by embodiments of the present invention can select the corresponding gain parameter according to the digital output signal, thereby increasing the linearity of the time-to-digital converter. Furthermore, the correction method of the present invention is not limited by the resolution of the time-to-digital converter, nor does it significantly increase additional costs. Therefore, the present invention can solve the problems of related technologies without or with minimal side effects. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the resolution of an estimated time-to-digital converter according to an embodiment of the present invention.

[0009] Figure 2 This is a circuit architecture for a time-to-digital converter according to an embodiment of the present invention.

[0010] Figure 3 for Figure 2 The circuit architecture shown involves certain signals.

[0011] Figure 4 This is a normalized operation for a time-to-digital converter according to an embodiment of the present invention.

[0012] Figure 5 This is a simplified schematic diagram of a fully digital phase-locked loop according to an embodiment of the present invention.

[0013] Figure 6 This refers to certain signals after locking under ideal conditions, according to one embodiment of the present invention.

[0014] Figure 7This refers to certain signals when the time-to-digital converter gain has a -20% error, according to one embodiment of the present invention.

[0015] Figure 8 This refers to certain signals when the time-to-digital converter gain has a +20% error, according to one embodiment of the present invention.

[0016] Figure 9 According to one embodiment of the present invention Figure 5 The example shown is a minimum mean square circuit.

[0017] Figure 10 This is a workflow of a correction method for a fully digital phase-locked loop according to an embodiment of the present invention.

[0018] Figure 11 This is a simplified schematic diagram of a fully digital phase-locked loop according to another embodiment of the present invention.

[0019] Figure 12 This is a schematic diagram of a storage device according to an embodiment of the present invention. Detailed Implementation

[0020] The present invention will be described below with reference to several embodiments. It should be noted that the elements in each embodiment may be implemented via hardware (e.g., a device or circuit) or firmware (e.g., at least one program written into a microprocessor). Furthermore, the terms "first," "second," and similar descriptions in the following description are used only to define different elements, parameters, data, signals, or steps, and are not intended to limit their order.

[0021] In the operation of an all-digital phase-locked loop (ADPLL), assuming the period of the clock signal CKV output by the digitally controlled oscillator (DCO) is T... V Furthermore, the time-to-digital converter (TDC) relies on the phase difference between the clock signal CKV and the reference signal FREF (e.g., the time difference Δt between the rising edge of the clock signal CKV and the rising edge of the reference signal FREF). r Generates digital output signal N r This fully digital phase-locked loop requires the digital output signal N to be processed. r Normalize to make the digital output signal N r Convert to a number between 0 and 1 (For example, the phase difference between the clock signal CKV and the reference signal FREF can be expressed as...) T times VThis normalization is performed to facilitate subsequent operations. However, the results of the above normalization will be affected by the resolution Δt of the time-to-digital converter. res (For example, the time difference corresponding to the least significant bit of the digital output signal of the time-to-digital converter, or the unit delay of the time-to-digital converter) has an impact, among which The resolution Δt of the time-to-digital converter res The normalization process will change with variations in semiconductor process-voltage-temperature (PVT), therefore the above normalization operation also needs to be corrected for changes in resolution.

[0022] Figure 1 To estimate the resolution Δt of a time-to-digital converter according to an embodiment of the present invention res A schematic diagram. (See example.) Figure 1 As shown, this time-to-digital converter can detect the time difference Δt between the rising edge of the clock signal CKV and the reference signal FREF. r Furthermore, the time difference Δt between the falling edge of the clock signal CKV and the reference signal FREF is also detected. f .like Figure 1 As shown, Δt r With Δt f The difference between them is half a cycle T of the clock signal CKV. V / 2, and the time-to-digital converter (or its subsequent processing circuitry) can utilize the time-to-digital converter based on Δt r With Δt f The resolution Δt of the time-to-digital converter can be roughly calculated from the respective digital output signals. res .

[0023] Figure 2 The circuit architecture of a time-to-digital converter 20 according to an embodiment of the present invention is as follows: Figure 3 for Figure 2 The circuit architecture shown involves certain signals. It should be noted that... Figure 2 The circuit architecture shown is merely an example of the time-to-digital converter 20 and is not intended to limit the invention. Figure 2 As shown, the time-to-digital converter 20 may include multiple inverters connected in series to form an inverter chain. Since each of these inverters causes a signal delay, the respective output signals D of these inverters will vary. <0> D <1> D <2> ... D <l-1>and D <l>Each of the clock signals CKV input to the first inverter has its own corresponding delay time, such as... Figure 3 D in <0> D <1> D <2> D <3> D <4> D <5> D <6> and D <7> As shown, the delay introduced by one of the inverters is the resolution Δt of the time-to-digital converter 20. res In this embodiment, the output signal D <0> D <1> D <2> ... D <l-1>and D <l>All inputs are fed to the input terminals (labeled "D") of the flip-flop, and the output terminal (labeled "Q") of the flip-flop is output when triggered by the rising edge of the reference signal FREF. Figure 3 As shown in Q<0:L>. In this embodiment, the output signal Q<0:L> changes from 0 to 1 (e.g., Q... <1> Q for 0 <2> The part marked as 1 represents the falling edge of the clock signal CKV, while the output signal Q<0:L> changes from 1 to 0 (e.g., Q). <5> For 1 and Q <6> The portion that is 0 represents the rising edge of the clock signal CKV. Next, the time-to-digital converter 20 can use its internal pseudo-thermometer-code edge detector 22 (e.g., a detector used to detect transitions from 0 to 1 and from 1 to 0 in a digital sequence) to detect the output signal Q<0:L> and output a binary digital output signal N accordingly. r and N f Let Δt represent the time difference between the rising edge of clock signal CKV and reference signal FREF, respectively. r and the time difference Δt between the falling edge of the clock signal CKV and the reference signal FREF f (e.g., Δt) r ≈N r ×Δt res And Δt f ≈N f ×Δt res ), for example N r =6 and N f =2. It should be noted that... Figure 2 The circuit architecture of the time-to-digital converter 20 shown is for illustrative purposes only and is not intended to limit the invention. For example, the number of bits in the output signal of the time-to-digital converter 20 can be varied according to system requirements, and L can be any positive integer.

[0024] Figure 4 This is a normalization operation for a time-to-digital converter 20 according to an embodiment of the present invention. For example... Figure 4 As shown, the time-to-digital converter 20 can convert the digital output signal N obtained from the above operation into digital output signal N. r and N f The data is transmitted to the normalization circuit 30. First, the normalization circuit 30 can utilize the first calculation unit 31 (labeled "periodic average" for ease of understanding) to perform... Figure 1 The calculations shown are used to obtain the average value of the period of the clock signal CKV. and the resolution Δt of the time-to-digital converter 20 res Then, the second calculation unit 32 (labeled as) is used (For ease of understanding) The reciprocal is output in 12-bit binary form (e.g., the signal PERINV), and then the digital output signal N is converted using multiplier 33. r Multiply by the signal PERINV to generate W F Bits (e.g., W) F The result of multiplying (=15) is then processed by the third calculation unit 34 (labeled as "2^W"). F –(x)」) converts the multiplication result into the form of an unsigned 2's complement and outputs it as a signal ε, where W F A binary signal ε of 1 bit can be represented using discrete data (e.g., the k-th data point) as follows:

[0025]

[0026] It should be noted that when the duty cycle of the clock signal CKV is not 50%, the average value of the period of the clock signal CKV obtained above should be used. and the resolution Δt of the time-to-digital converter 20 res The operation would require relatively complex hardware to implement. Furthermore, the above estimation method is also limited by the resolution Δt of the time-to-digital converter 20. res Therefore, estimation errors can lead to a decrease in the performance of the all-digital phase-locked loop (e.g., excessive output jitter / spur).

[0027] For the sake of simplicity, all the following explanations will be in decimal form. Figure 5 This is a simplified schematic diagram of an all-digital phase-locked loop 50 according to an embodiment of the present invention. The all-digital phase-locked loop 50 may include a time-to-digital converter 500, a digitally controlled oscillator 510 (illustrated as a circle containing a sine wave for ease of understanding), a normalization circuit 520, an accumulator 530 (labeled "Σ" for ease of understanding), a low-pass filter (LPF) 540 (illustrated as a square with a low-pass response waveform for ease of understanding), and an adder 550 (illustrated as a circle containing a plus sign for ease of understanding). In this embodiment, the parameter FCW_F can be set as the ratio between the target frequency of the clock signal CKV and the frequency of the reference signal FREF, and the accumulator 530 continuously accumulates the parameter FCW_F, outputting the accumulated result as a reference phase. The time-to-digital converter can be coupled to the digitally controlled oscillator and used to generate a digital output signal N based on the phase difference between the clock signal CKV and the reference signal FREF. r [k](e.g., N) r The value of the reference signal FREF in the k-th cycle. A normalization circuit can be coupled to this time-to-digital converter and can be used based on the gain parameter K. TDC Convert the digital output signal into a clock phase value (For example The value of the reference signal FREF in the k-th cycle, where the clock phase value It can be regarded as a digital output signal N r [k] is the result after normalization. Adder 550 can subtract the above reference phase from the instantaneous phase (e.g., the sum of the instantaneous ratio between the instantaneous frequency of clock signal CKV and the frequency of reference signal FREF) to obtain the phase difference value. (For example The value of the reference signal FREF in the kth cycle is used to generate a frequency control signal for the low-pass filter 540 to control the digital control oscillator 510 to generate a clock signal CKV based on the frequency control signal, so that the instantaneous frequency of the clock signal CKV gradually converges to the target frequency.

[0028] It should be noted that the digital output signal N generated by the time-to-digital converter 500 r [k] and its normalized clock phase value This is only used to represent the fractional part of the instantaneous phase, while the integer part of the instantaneous phase can be implemented using a counter. Since the operation of using a counter to generate the integer part of the instantaneous phase is a well-known technique in the art and does not affect the implementation of the correction of the time-to-digital converter 500 and the normalization circuit 520 in this invention, for the sake of simplicity, the counter is not shown in the diagram, and related details are not described here. Similarly, Figure 5 The reference phase value output by the accumulator 530 shown (For example The value of the reference signal FREF in the kth cycle is also used only to represent the fractional part of the aforementioned reference phase for the sake of simplicity.

[0029] exist Figure 5 In the illustrated embodiment, the normalization circuit 520 may include a multiplier 521 for converting the digital output signal N... r [k] multiplied by the gain parameter K TDC To generate clock phase values And the gain parameter K TDC The correct value can be calculated using the following formula:

[0030]

[0031] Where t res This can represent the resolution of a time-to-digital converter 500 (e.g., the aforementioned Δt). res ), and T DCO This can represent the period of the clock signal CKV output by the digitally controlled oscillator 510 (e.g., the T mentioned above). V or Due to the resolution t of the time-to-digital converter 500 res It is quite sensitive to PVT variation (e.g., at 25°C t) res The time is 13 picoseconds (ps), but at a temperature of 25°C, t res (10 ps), therefore the gain parameter K varies between different temperatures. TDC There will be a gain error, and the gain parameter K TDC Gain errors can cause unwanted frequency components, such as fractional purs, to appear.

[0032] For example, assuming the reference signal FREF has a frequency of 40MHz, the ratio FCW between the target frequency of the clock signal CKV and the frequency of the reference signal FREF is 125.25, and the expected resolution t... res The target frequency f of the clock signal CKV is 10ps. DCO If it is 5010MHz, then K TDC It is approximately 0.05.

[0033] Figures 6 to 8 Clock phase based on the frequencies of clock signal CKV and reference signal FREF Reference phase and phase difference Values ​​under different circumstances. For example... Figure 6 As shown, in each period of the reference signal FREF, the digital output signal N... r The reference phases are 5, 10, 15, and 0 in sequence. The values ​​are 0.25, 0.5, 0.75, and 0 in that order. (Regarding the gain parameter K...) TDC In the absence of gain error (e.g., true resolution t) res The corresponding gain parameter (i.e., t) res / T DCO ) and for the gain parameter K TDC The preset values ​​are all 0.05), clock phase The values ​​are 0.25, 0.5, 0.75, and 0 in sequence, therefore the phase difference is... All remain at 0. When the gain parameter K is preset. TDC With an error of -20% (e.g., 0.04), this will cause clock phase... The phase difference is 0.2, 0.4, 0.6 and 0 in sequence. Even in the locked state, there is still a positive phase difference (e.g., 0.05, 0.1, 0.15, and 0), such as... Figure 7 As shown. When the gain parameter K is preset. TDC With an error of +20% (e.g., 0.06), this will affect the clock phase. The phase difference is 0.3, 0.6, 0.8 and 0 in sequence. Even in the locked state, there is still a negative phase difference (e.g., -0.05, -0.1, -0.15, and 0), such as... Figure 8 As shown.

[0034] From the examples above, we can see that the gain parameter K... TDC With digital output signal N r [k] and phase difference It has a correlation. For example, the larger the value of N, the more correlated it is. r [k] will result in a larger phase difference. For example, the gain parameter K TDC A positive gain error will result in a negative phase difference. And the gain parameter K TDC A negative gain error will result in a positive phase difference.

[0035] Therefore, embodiments of the present invention provide a correction method and a corresponding architecture to correct the digital output signal N. r [k] and / or phase difference Used to correct the gain parameter K TDC .

[0036] like Figure 5 As shown, in addition to multiplier 521, normalization circuit 520 may further include multiplier 522 and least mean square (LMS) circuit 523 (denoted as "LMS" for simplicity), wherein least mean square circuit 523 is coupled between multipliers 521 and 522. In this embodiment, normalization circuit 520 can be based on clock phase value With reference phase value Phase difference value between Adjust the gain parameter K TDC Specifically, when the phase difference value Positive (e.g.) Figure 7 As shown), K represents the gain parameter. TDC There is a negative error (e.g., gain parameter K). TDC Less than t res / T DCO Therefore, the normalization circuit 520 can improve the gain parameter K. TDC ; and when the phase difference value Negative (e.g.) Figure 8 As shown), K represents the gain parameter. TDC There is a positive error (e.g., gain parameter K). TDC Greater than t res / T DCO The normalization circuit 520 can reduce the gain parameter K. TDC .

[0037] In this embodiment, the normalization circuit 520 can be based on the phase difference value. and digital output signal N r Adjust the gain parameter K TDC For example, the normalization circuit 520 can be based on the phase difference value. With digital output signal N r product Adjust the gain parameter K TDC .like Figure 5 As shown, the normalization circuit 520 can use a multiplier to calculate the phase difference value. With digital output signal N r product For the basis of the minimum mean square circuit 523 The calculation results are used to adjust the gain parameter K. TDC .

[0038] Figure 9 According to one embodiment of the present invention Figure 5 The example shown is the minimum mean square circuit 523. (See example 523 ... Figure 9 As shown, the least mean square circuit 523 may include a multiplier 524 and an accumulator 525 (denoted as "Σ" for ease of understanding). In this embodiment, the least mean square circuit 523 can be used to determine the phase difference value. With digital output signal N r product And the current gain parameter K used in the current period (e.g., the (k-1)th period of the reference signal FREF). TDC [k-1] Generates the next gain parameter K for the next cycle (e.g., the kth cycle of the reference signal FREF). TDC [k]. For example, the multiplier 522 can multiply a 19-bit... With 6-bit digital output signal N r [k] multiply to produce a 25-bit product. Multiplier 524 can multiply the above product The result is further multiplied by a predetermined value μ, and the accumulator 525 can add the result of the multiplication to the gain parameter K. TDC [k-1] is used to obtain the 16-bit gain parameter K. TDC [k], where the predetermined value μ can be any suitable constant, and the related operations can be represented as discrete data as follows:

[0039]

[0040] It should be noted that the above calculation method and Figure 9 The architecture shown is only the minimum mean square circuit 523 with gain parameter K. TDC This is one example of an adjustment, and not a limitation thereof. Anything that can be adjusted based on the phase difference value... and / or digital output signal N r [k] will change the gain parameter K TDC Gradually adjust / converge to t res / T DCO All implementation methods described herein fall within the scope of this invention.

[0041] Figure 10 This is a workflow of a calibration method for a fully digital phase-locked loop according to an embodiment of the present invention, wherein the calibration method can be applied to... Figure 5 The fully digital phase-locked loop 50 is shown. It should be noted that one or more steps can be performed without affecting the overall result. Figure 10 The process shown may be added, modified, or deleted, and these steps are not necessarily required to be followed exactly. Figure 10 Execute in the order shown.

[0042] In step 1010, the all-digital phase-locked loop 50 uses a digitally controlled oscillator 510 to generate a clock signal CKV based on a frequency control signal.

[0043] In step 1020, the all-digital phase-locked loop 50 uses the time-to-digital converter 500 to generate a digital output signal N based on the phase difference between the clock signal CKV and the reference signal FREF. r [k].

[0044] In step 1030, the all-digital phase-locked loop 50 utilizes the normalization circuit 520 based on the gain parameter K. TDC The digital output signal N r [k] is converted to clock phase value.

[0045] In step 1040, the all-digital phase-locked loop 50 utilizes the normalization circuit 50 based on the clock phase value With reference phase value Phase difference value between Adjust the gain parameter K TDC .

[0046] In summary, embodiments of the present invention provide a fully digital phase-locked loop and its correction method, which can correct based on phase difference values. and the signal N output by the time-to-digital converter r Determine the gain parameter K TDC The directionality of the error is determined, and a feedback correction mechanism is established to ensure that the gain parameter K... TDC It can gradually converge to the correct value. Furthermore, the correction mechanism proposed in this invention is not limited by the resolution of the time-to-digital converter; in particular, the accuracy during correction can be determined by the bit count design of the computational units (e.g., multipliers 521 and 522, and the least mean square circuit 523) within the normalization circuit 520. Therefore, this invention can, without or with minimal side effects, reduce the accuracy of time-to-digital converter-related parameters (e.g., the gain K of the time-to-digital converter). TDC It converges to the correct or optimal value.

[0047] In the foregoing embodiments, Figure 5 The normalization circuit 520 in the middle is used to instantly correct the gain parameter K. TDC However, due to the gain parameter K TDC It will be affected by the previous gain parameter K TDC and the current phase difference Due to the impact of this approach, the digital output signal N may be affected. r Even with the same value, the gain parameter K may vary significantly. TDC This consequently affects the linearity of the time-to-digital converter 500.

[0048] Therefore, this invention further proposes a fully digital phase-locked loop and its correction method, wherein the corresponding digital output signal Nr selects one of a plurality of candidate gain parameters from storage as the gain parameter. In one embodiment, the candidate gain parameter is generated by the normalization circuit 520 based on a plurality of previous phase difference values ​​and a plurality of previous digital output signals. For example, using the phase difference values... and digital output signal N r [n-2] Generate candidate gain parameters K TDC [n-2], and in terms of phase difference value and digital output signal N r [n-1] Generate candidate gain parameters K TDC [n-1], and in terms of phase difference value and digital output signal N r [n] Generates candidate gain parameters K TDC [n]. Candidate gain parameter K TDC [n-2]、K TDC [n-1] and K TDC [n] will be temporarily stored in the normalization circuit 520. When the value of the digital output signal Nr is N again... r When [n], then the candidate gain parameter K is selected from the multiple stored candidate gain parameters. TDC [n] is output to the multiplier 521, instead of... Figure 5 In typical implementations, the gain parameter K is generated in real time. TDC .

[0049] Figure 11 This is a simplified schematic diagram of a fully digital phase-locked loop according to another embodiment of the present invention. Figure 11 In the embodiments, except Figure 5 In addition to the components shown, the normalization circuit 1100 further includes a multiplexer 1101, a storage device 1103, a demultiplexer 1105, and a first delay circuit 1107. The multiplexer 1101 is controlled by a digital output signal Nr[k]. The demultiplexer 1105 is controlled by a delayed digital output signal Nr[kd] and is coupled to the output of the minimum mean square circuit 523. The storage device 1103 is coupled to multiple inputs of the multiplexer 1101 and multiple outputs of the demultiplexer 1105 to store candidate gain parameters. In one embodiment, the storage device 1103 includes multiple registers for storing candidate gain parameters. The first delay circuit 1107 is coupled to the multiplexer 1101 and the demultiplexer 1105 to receive the digital output signal Nr[k] to generate a delayed digital output signal Nr[kd].

[0050] exist Figure 11 In this embodiment, the multiplexer 1101 first selects the corresponding candidate gain parameter as the gain parameter K based on the digital output signal Nr[k]. TDC Then the minimum mean square circuit 523 will output the delayed digital signal Nr[kd] and the phase difference based on the time difference. The normalization circuit 1100 generates candidate gain parameters for the corresponding digital output signal Nr[kd] and updates the candidate gain parameters for the corresponding digital output signal Nr[k] stored in the storage device 1103 based on the candidate gain parameters for the corresponding digital output signal Nr[kd]. In one embodiment, the candidate gain parameters are not updated, but the same candidate gain parameters are used continuously without being changed after the corresponding candidate gain parameters are generated based on the digital output signal Nr[k].

[0051] Figure 12 This is a schematic diagram of a storage device 1103 according to an embodiment of the present invention, which will show candidate gain parameters stored in the storage device 1103. Figure 12 As shown, the storage device 1103 includes multiple registers Re1…Ren, multiple adders 1201_1…1201_n, and multiple second delay circuits 1203_1…1203_n. Registers Re1…Ren are used to store candidate gain parameters K respectively. TDC1 …K TDCn Adders 1201_1…1201_n are each coupled to one of the registers Re1…Ren, and are also coupled to the demultiplexer 1105. The second delay circuits 1203_1…1203_n are each coupled to one of the registers Re1…Ren and one of the adders 1201_1…1201_n. Figure 12 In the embodiment, the candidate gain parameter K, which was originally temporarily stored in registers Re1…Ren, TDC1 …K TDCn The signal will be first delayed by the second delay circuit 1203_1…1203_n, and then added to the gain parameter generated according to the delayed digital output signal Nr[kd] to generate a new candidate gain parameter and update it in register Re1.

[0052] For example, if Figure 11 The digital output signal Nr[1] generated by the time-to-digital converter 1100 in the middle is then Figure 11 The multiplexer 1101 shown is controlled by the digital output signal Nr[1] and the candidate gain parameter K stored in the output register Re1. TDC1 As the gain parameter K TDC The digital output signal Nr[1] will be Figure 11 The first delay circuit 1107 generates a delayed digital output signal Nr[1d] (not shown) by delaying the signal. The minimum mean square circuit 523 will generate the delayed digital output signal Nr[1d] based on the delay and the phase difference. Generate delay gain parameter K TDC1d Then adder 1201_1 will add the delay gain parameter K. TDC1d With candidate gain parameter K TDC1 Add them together and update the register Re1.

[0053] However, please note that Figure 11 as well as Figure 12 The embodiments described are merely illustrative, and any circuit architecture that can achieve the same function should be within the scope of this invention. Figure 11 as well as Figure 12 The embodiments described herein provide a correction method for an all-digital phase-locked loop (PLL), comprising the following steps: generating a clock signal using a digitally controlled oscillator in the PLL based on a frequency control signal; generating a digital output signal using a time-to-digital converter in the PLL based on the phase difference between the clock signal and a reference signal; converting the digital output signal into a clock phase value using a normalization circuit in the PLL based on a gain parameter; and selecting one of a plurality of stored candidate gain parameters as the gain parameter using the normalization circuit. Other detailed steps can be easily derived from the foregoing embodiments and will not be repeated here.

[0054] The all-digital phase-locked loop and its correction method provided by embodiments of the present invention can select the corresponding gain parameter according to the digital output signal, thereby increasing the linearity of the time-to-digital converter. Furthermore, the correction method of the present invention is not limited by the resolution of the time-to-digital converter, nor does it significantly increase additional costs. Therefore, the present invention can solve the problems of related technologies without or with minimal side effects.

[0055] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0056] Symbol Explanation

[0057] CKV: Clock signal

[0058] FREF: Reference signal

[0059] Δt r , Δt f Time difference

[0060] T V :cycle

[0061] 20: Time-to-Digital Converter

[0062] D <0> D <1> D <2> D <3> D <4> D <5> D <6> D <7> ~D <l-1> 、D <l>Output signal

[0063] Q <0> Q <1> Q <2> ~Q <l-1> 、Q <l>Output signal

[0064] N r N f Digital output signal

[0065] 30: Normalized circuit

[0066] 31: First Calculation Unit

[0067] 32: Second Calculation Unit

[0068] 33: Multiplier

[0069] 34: Third Calculation Unit

[0070] PERINV, ε: signal

[0071] 50: All-digital phase-locked loop

[0072] 500: Time-to-Digital Converter

[0073] 510: Digitally Controlled Oscillator

[0074] 520, 1100: Normalized circuit

[0075] 521, 522: Multipliers

[0076] 523: Minimum Mean Square Circuit

[0077] 524: Multiplier

[0078] 525: Accumulator

[0079] 530: Accumulator

[0080] 540: Low-pass filter

[0081] 550, 1201_1…1201_n: Adders

[0082] FCW_F: Parameters

[0083] Clock phase value

[0084] Reference phase value

[0085] Phase difference value

[0086] N r [k]: Digital output signal

[0087] K TDC Gain parameters

[0088] 1010, 1020, 1030, 1040: Steps

[0089] 1101 Multiplexer

[0090] 1103 Storage device

[0091] 1105 Demultiplexer

[0092] 1107 First Delay Circuit

[0093] 1203_1…1203_n Second Delay Circuit

[0094] Re1…Ren registers< / l> < / l-1> < / l> < / l-1> < / l> < / l>

Claims

1. A fully digital phase-locked loop, comprising: A digitally controlled oscillator is used to generate a clock signal based on a frequency control signal; A time-to-digital converter, coupled to the digitally controlled oscillator, is used to generate a digital output signal based on the phase difference between the clock signal and a reference signal; and A normalization circuit, coupled to the time-to-digital converter, is used to convert the digital output signal into a clock phase value according to the gain parameter and to store multiple candidate gain parameters, wherein the normalization circuit generates the candidate gain parameters based on the product of one of the previous multiple phase difference values ​​and one of the previous multiple multiple digital output signals. The normalization circuit selects one of the multiple candidate gain parameters stored in the digital output signal as the gain parameter.

2. The all-digital phase-locked loop as claimed in claim 1, wherein the normalization circuit includes a minimum mean square circuit for generating a next gain parameter for the next cycle based on the product of the phase difference and the digital output signal and the current gain parameter used in the current cycle.

3. The all-digital phase-locked loop as described in claim 1, wherein the normalization circuit further comprises: The multiplexer, controlled by the digital output signal, outputs one of the candidate gain parameters as the gain parameter; The demultiplexer is controlled by a delayed digital output signal to receive a delay gain parameter generated based on the delayed digital output signal, and the delay gain parameter is used to update the corresponding candidate gain parameter; A storage device, coupled to multiple inputs of the multiplexer and multiple outputs of the demultiplexer, is used to store the candidate gain parameters; A first delay circuit, coupled to the multiplexer and the demultiplexer, is used to receive the digital output signal to generate the delayed digital output signal.

4. The all-digital phase-locked loop as described in claim 3, wherein the normalization circuit further comprises: Multiple registers are used to store these candidate gain parameters; Multiple adders, each coupled to one of these registers, and coupled to the demultiplexer; and Multiple second delay circuits are respectively coupled to one of the registers and one of the adders.

5. A calibration method for a fully digital phase-locked loop, comprising: The digitally controlled oscillator in this fully digital phase-locked loop generates a clock signal based on the frequency control signal. The time-to-digital converter in this all-digital phase-locked loop generates a digital output signal based on the phase difference between the clock signal and the reference signal; The normalization circuit in the all-digital phase-locked loop generates multiple candidate gain parameters based on the product of one of the previous multiple phase difference values ​​and one of the previous multiple multiple digital output signals. The normalization circuit in this all-digital phase-locked loop converts the digital output signal into a clock phase value based on the gain parameter; and The normalization circuit is used to select one of the multiple candidate gain parameters stored in the digital output signal as the gain parameter.

6. The correction method as described in claim 5, wherein the step of converting the digital output signal into the clock phase value using the normalization circuit in the all-digital phase-locked loop according to the gain parameter includes: The normalization circuit is used to multiply the digital output signal by the gain parameter to generate the clock phase value.

7. The correction method of claim 6, wherein the step of selecting one of a plurality of candidate gain parameters stored in the digital output signal using the normalization circuit as the gain parameter comprises: Delay the digital output signal to generate a delayed digital output signal; The multiplexer is controlled by this digital output signal; The demultiplexer is controlled by a delayed digital output signal; and The multiplexer controls which of the candidate gain parameters in the storage device to be output, and the demultiplexer controls the storage device to receive the delay gain parameter generated according to the delayed digital output signal, the delay gain parameter being used to update the corresponding candidate gain parameter.

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