Control circuit and correction method for a signal converter

Abstract

The present application provides a control circuit and a correction method for a signal converter. The control circuit can be an existing control circuit, so that no additional correction circuit is needed to reduce the circuit area. Further, the control circuit is, for example, an embedded microcontroller or other types of microcontrollers, which generally have analog comparators and arithmetic units. By executing firmware program codes through the arithmetic units and using the analog comparators, the control circuit can correct the signal converter.

Description

Technical Field

[0001] This invention relates to an automatic calibration technique for a signal converter (e.g., a digital-to-analog converter, or DAC for short), and more particularly to a control circuit and calibration method for use with a signal converter, wherein the control circuit can be an existing control circuit, so there is no need to add an additional calibration circuit to reduce the circuit area. Background Technology

[0002] DACs (Digital Converters) are susceptible to aging due to factors such as ambient temperature and component usage time, leading to varying rates of internal component aging and resulting in offset during digital-to-analog conversion. Previous technologies calibrated DACs by adding an additional calibration circuit. This circuit used an analog comparator to compare a reference signal with the analog signal actually converted by the DAC, and then calibrated the DAC based on the comparison result. The need for an additional calibration circuit with an analog comparator increases the overall chip area. Furthermore, the added calibration circuit also increases power consumption.

[0003] Furthermore, existing calibration circuits cannot automatically calibrate DACs against hacker attacks. One common chip attack method involves increasing or decreasing the temperature of the DAC to cause it to output incorrect analog signals, thus achieving the attack's objective. Therefore, there is a need for a DAC calibration technology solution that can reduce circuit area, lower power consumption, and resist hacker attacks. Summary of the Invention

[0004] According to the purpose of this invention, embodiments of this invention provide a control circuit for a signal converter, comprising: a switch, the input of which is electrically connected to the output of the signal converter to receive an analog signal output by the signal converter based on a digital signal conversion, the output and input of which are turned on according to an event trigger signal, wherein the initial value of the digital signal corresponds to an analog reference signal; an analog comparator, the first input of which receives the analog reference signal, and the second input of which is electrically connected to the output of the switch; and a signal converter control unit, electrically connected to the output of the analog comparator and the input of the signal converter, which is enabled according to the event trigger signal to transmit the digital signal to the input of the signal converter; wherein if the signal converter control unit determines that the comparison signal output by the analog comparator has not changed state, it increases or decreases the value of the digital signal according to the comparison signal; if the signal converter control unit determines that the comparison signal output by the analog comparator has changed state, it records the value of the digital signal before or after the change, thereby obtaining the offset of the signal converter.

[0005] According to the purpose of this invention, embodiments of the invention further provide a signal conversion system and a method for use in a signal converter, wherein the signal conversion system uses the aforementioned control circuit, and the method for use in a signal converter is executed by the aforementioned control circuit.

[0006] In summary, the embodiments of the present invention provide a control circuit, method, and signal conversion system that can be used in a signal converter, which does not require additional correction circuitry, thus reducing circuit area and power consumption.

[0007] To further understand the technology, means, and effects of the present invention, reference can be made to the following detailed description and accompanying drawings, which will provide a thorough and concrete understanding of the purpose, features, and concepts of the present invention. However, the following detailed description and accompanying drawings are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0008] The present invention can be more fully understood through the following detailed description of the embodiments in conjunction with the accompanying drawings, in which:

[0009] Figure 1 This is a block diagram of a control circuit that can be used in a signal converter according to an embodiment of the present invention;

[0010] Figure 2 This is a block diagram of a control circuit that can be used in a signal converter according to another embodiment of the present invention;

[0011] Figure 3 This is a block diagram of a reference signal supplier that can be used in the control circuit of a signal converter according to an embodiment of the present invention;

[0012] Figure 4A This is a block diagram of the signal conversion system according to an embodiment of the present invention;

[0013] Figure 4B This is a block diagram of a signal conversion system according to another embodiment of the present invention;

[0014] Figure 5 This is a flowchart of a method applicable to a signal converter according to an embodiment of the present invention.

[0015] The symbols indicated in the diagram are explained as follows: 1, 2 control circuit; 10, 20, 43, 46 signal converter; ACMP analog comparator; SW switch; 11, 21 signal converter control unit; 12, 22 filtering and control circuit; 13, 23 event trigger; 14, 24 reference signal supplier; 15 packaging circuit; 16, 26 timing trigger; 17 bus interface; 18, 28 direct memory accessor; 19, 29 memory; SEL[1:0] select signal; Vbg bandgap voltage; Vref internal reference voltage; Vext external reference voltage; MUX1, MUX2 multiplexer; 41 digital data source; 42, 45 microcontroller; 44 playback device; S51~S58 steps. Detailed Implementation

[0016] Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Where possible, the same component reference numerals are used in the drawings and description to refer to the same or similar parts. Furthermore, the exemplary embodiments are merely one way of implementing the design concept of the invention, and the following examples are not intended to limit the invention.

[0017] This invention provides a control circuit, method, and signal conversion system for use in signal converters (e.g., DACs). The control circuit can be an existing control circuit, thus eliminating the need for additional calibration circuits to reduce circuit area. Furthermore, the control circuit can be, for example, an embedded microcontroller or other types of microcontrollers. Generally, microcontrollers have analog comparators and arithmetic units. By executing firmware code through the arithmetic unit and using the analog comparator, the control circuit can calibrate the signal converter. In other embodiments, the control circuit can also be a purely hardware circuit and is not solely used for signal converter calibration. Therefore, this invention eliminates the need for additional calibration circuits, thereby reducing circuit area, and using a control circuit for signal converter calibration does not additionally consume processor resources. Furthermore, by calibrating the signal converter only when a specific event occurs, this invention can further reduce power consumption. Moreover, the specific event can be designed as the detection of a hacker attack on the chip, thereby achieving the effect of preventing hacker attacks on the chip.

[0018] Furthermore, this invention can also be applied in situations where a calibration circuit for the signal converter is unavailable. Calibration of the signal converter can be achieved by electrically connecting it to an existing control circuit. Furthermore, it can be used when an external signal converter calibration circuit fails, allowing the control circuit to calibrate the signal converter. This invention enables automatic calibration of the signal converter at regular intervals, preventing signal converter aging and ensuring continued normal operation even after prolonged use. In one embodiment, the signal converter can be an internal signal converter within the control circuit, eliminating the need for calibration of analog circuit offsets through integrated signal exchange between analog and digital circuits. When the signal converter is a DAC, it can be an internal DAC within the control circuit or an external DAC outside the control circuit, and this invention is not limited by the location or type of the signal converter.

[0019] Incidentally, the signal converter referred to in this invention broadly refers to various circuits that take digital signals as input and output analog signals, such as, but not limited to, circuits where the input and output are linear or have a linear relationship. For example, a converter may be a DAC that linearly converts the value of a digital signal into an analog signal, or it may be a modulation circuit that generates different analog radio frequency modulation signals based on a digital signal.

[0020] First, please refer to Figure 1 , Figure 1 This is a block diagram of a control circuit that can be used in a signal converter according to an embodiment of the present invention. The control circuit 1 that can be used to correct the signal converter 10 includes an analog comparator ACMP, a switch SW, a signal converter control unit 11, a filtering and control circuit 12, an event trigger 13, a reference signal supplier 14, a wrapper control circuit 15, a timing trigger 16, a bus interface 17, a direct memory accessor 18, and a memory 19.

[0021] The first input terminal of the analog comparator ACMP is electrically connected to the output terminal of the reference signal supplier 14, the input terminal of the switch SW is electrically connected to the output terminal of the signal converter 10, and the output terminal of the switch SW is electrically connected to the second input terminal of the analog comparator ACMP. The first input terminal and the second input terminal of the analog comparator ACMP are respectively the inverting input terminal and the inverting input terminal, or the first input terminal and the second input terminal of the analog comparator ACMP are respectively the inverting input terminal and the inverting input terminal. In this embodiment, the first input terminal and the second input terminal of the analog comparator ACMP are respectively the inverting input terminal and the inverting input terminal.

[0022] The signal converter control unit 11 is electrically connected to the filter and control circuit 12, event trigger 13, packaging circuit 15, timing trigger 16, direct memory accessor 18, and the control terminal of switch SW. Event trigger 13 is electrically connected to the control terminal of switch SW and the filter and control circuit 12. The output terminal of analog comparator ACMP is electrically connected to the filter and control circuit 12. Packaging circuit 15 is electrically connected to bus interface 17 and timing trigger 16. Bus interface 17 is electrically connected to the input terminal of signal converter 10. Through the above electrical connections, it can be seen that the signal converter control unit 11 is electrically connected to the input terminal of signal converter 10 via packaging circuit 15 and bus interface 17. Additionally, direct memory accessor 18 is electrically connected to memory 19.

[0023] The control terminal of switch SW receives either an event trigger signal generated by event trigger 13 or a control signal from signal converter control unit 11, ensuring that the conduction between the input and output terminals of switch SW is controlled by signal converter control unit 11. In principle, switch SW can remain on when an event trigger signal is generated, but to reduce power consumption, it is designed to be additionally controlled by signal converter control unit 11, so that switch SW is only turned on when signal converter 10 obtains an updated digital signal. The input terminal of switch SW receives the analog signal output by signal converter 10 based on the digital signal conversion, and when conduction occurs between the input and output terminals of switch SW, it transmits the analog signal to the second input terminal of analog comparator ACMP, where the initial value of the digital signal corresponds to the analog reference signal provided by reference signal supplier 14. The first input terminal of analog comparator ACMP receives the analog reference signal, and the output terminal of analog comparator ACMP outputs the comparison signal generated by analog comparator ACMP comparing the analog reference signal and the analog signal.

[0024] In this embodiment of the invention, the reference signal supplier 14 is used to provide an analog reference signal, wherein the analog reference signal is derived from an internal reference voltage Vref (e.g., ...). Figure 3 ), external reference voltage Vext and bandgap voltage Vbg (e.g. Figure 3 The selection is performed by the internal reference voltage Vref, which is the internal reference voltage generated by the control circuit 1 itself, and the external reference voltage Vext, which is the reference voltage from outside the control circuit 1. The bandgap voltage Vbg is generated by the bandgap voltage generator. Further, the reference signal supplier 14 is selected according to the selection signal SEL[1:0]. The reference signal supplier 14 is also electrically connected to the signal converter control unit 11, and the selection signal SEL[1:0] can be generated by the signal converter control unit 11. It should be noted that the reference signal supplier 14 can be a non-essential component, and the analog reference signal can be directly taken from the internal reference voltage Vref (e.g., ...). Figure 3), external reference voltage Vext and bandgap voltage Vbg (e.g. Figure 3 One of them is used.

[0025] Event trigger 13 is used to detect whether a specific event has occurred to generate an event trigger signal, causing control circuit 1 to enter an automatic calibration mode for calibrating signal converter 10. Specific events include periodic events that are timed to a specific time, forced calibration events, and / or temperature rise / fall events. The specific time can be set by signal converter control unit 11, for example, setting automatic calibration of signal converter 10 every 10 days. Temperature rise / fall events can be determined by temperature changes obtained from a temperature sensor. Hackers may exploit temperature changes to attack the chip, causing the offset of signal converter 10 to differ from before, resulting in incorrect analog signal output by signal converter 10, thus achieving their attack objectives. Forced calibration events refer to events where a user, developer, or repair technician forcibly performs calibration using debugging tools. The types of specific events described above are merely examples, and the invention is not limited thereto.

[0026] The signal converter control unit 11 is enabled by an event trigger signal and is used to transmit a digital signal to the input of the signal converter 10. Typically, the initial value of the digital signal can be stored in memory. Thus, the signal converter 10 can receive and convert the digital signal to an analog signal when enabled by a timing trigger signal generated by the timing trigger 16. The timing trigger 16 is controlled by the signal converter control unit 11 and is used to generate a timing trigger signal that enables the signal converter 10. The reciprocal of the periodic trigger time of the timing trigger signal is the frequency at which the signal converter 10 updates the analog signal, and the periodic trigger time can be set by the signal converter control unit 11. Furthermore, the signal converter control unit 11 can be turned on in response to the timing trigger signal after being enabled by an event trigger signal, thereby saving power consumption.

[0027] When the timing trigger signal enables the signal converter 10, if the signal converter control unit 11 determines that the comparison signal output by the analog comparator ACMP has not changed state, it increases or decreases the value of the digital signal according to the comparison signal. Conversely, if the signal converter control unit 11 determines that the comparison signal output by the analog comparator ACMP has changed state, it records the value of the digital signal before or after the change, thereby obtaining the offset of the signal converter 10.

[0028] Furthermore, when the digital signal is at its initial value, the comparison signal will not change state. Based on whether the comparison signal is at a logic high or low level, it is known whether the value of the digital signal should be increased or decreased to update the digital signal. Next, when the timing trigger signal enable converter 10 is activated again, the converter 10 generates an analog signal based on the updated digital signal. The analog comparator ACMP re-compares the signals. If the generated comparison signal changes state, the value of the digital signal before or after the change is recorded. Conversely, if the generated comparison signal changes state, the value of the digital signal continues to be increased or decreased to update the digital signal, and the analog comparator ACMP re-compares the signals again when the timing trigger signal enable converter 10 is activated again.

[0029] Assuming the analog reference signal is 0mV and the initial value of the corresponding digital signal is 0, and a change in the comparison signal occurs when the accumulated digital signal value reaches 10, then the recorded digital signal value is 9 or 10. Assuming the unit of the digital signal value represents 1mV, the offset of the signal converter 10 can be calculated as 9mV or 10mV. Assuming the analog reference signal is 300mV and the initial value of the corresponding digital signal is 150, and a change in the comparison signal occurs when the accumulated digital signal value reaches 145, then the recorded digital signal value is 146 or 145. Assuming the unit of the digital signal value represents 2mV, the offset of the signal converter 10 can be calculated as -8mV or -10mV.

[0030] Generally, the comparison signal of the analog comparator ACMP may be affected by noise. Therefore, if it is directly sent to the signal converter control unit 11 for direct reading, it may be misjudged due to noise. In this embodiment, the filtering and control circuit 12 is enabled according to the event trigger signal to filter the noise of the comparison signal output by the analog comparator ACMP, so as to output the noise-filtered comparison signal to the signal converter control unit 11. However, in an environment with less noise, the filtering and control circuit 12 can be removed from the control circuit 1 to reduce hardware costs. In addition, the filtering and control circuit 12 can be turned on according to the timing trigger signal after being enabled by the event trigger signal, thereby saving power consumption. Furthermore, in this embodiment, the signal converter control unit 11 sets the event trigger 13 through the filtering and control circuit 12, but the present invention is not limited thereto.

[0031] Direct memory accessor 18 serves as a data transfer bridge for signal converter control unit 11 to access memory 19. This allows signal converter control unit 11 to access memory 19 without going through the processing unit, thus reducing the resource consumption of the processing unit. Furthermore, memory 19 can be static random access memory, flash memory, or other types of memory. Memory 19 does not necessarily have to be internal memory within control circuit 1, but can be external memory outside of control circuit 1. Direct memory accessor 18 can be, for example, a peripheral device direct memory accessor (PDMA), and the invention is not limited thereto. Note that direct memory accessor 18 and memory 19 can be optional components. Although temporarily storing the digital signal value of the current calibration in memory 19 allows for direct retrieval during the next calibration, reducing calibration time, direct memory accessor 18 and memory 19 can be removed if calibration time is not a concern and circuit cost reduction is desired.

[0032] At Figure 1 In this embodiment, the signal converter 10 can be an external DAC other than the control circuit 1, and the control circuit 1 is a single chip. Therefore, unless specifically designed, such as using the same frequency and data format, the control circuit 1 typically needs an interface to communicate with the external DAC; that is, it normally requires a packaging circuit 15 and a bus interface 17. The packaging circuit is enabled based on the timing trigger signal and is used to buffer and output digital signals, as well as to output the timing trigger signal. The bus interface 17 is used to transmit the digital signals and the timing trigger signal to the signal converter 10 outside the control circuit 1. The bus interface 17 can be, for example, an I2C interface, but the present invention is not limited thereto.

[0033] As described above, control circuit 1 can be any type of arithmetic circuit including an analog comparator ACMP, such as an embedded microcontroller. The arithmetic circuit runs firmware code to configure the switch SW, signal converter control unit 11, event trigger 13, packaging circuit 15, and timing trigger 16; or, all components of control circuit 1 may be implemented by multiple hardware circuits rather than by running firmware code.

[0034] Next, please refer to Figure 2 , Figure 2 This is a block diagram of a control circuit for a signal converter according to another embodiment of the present invention. Different from... Figure 1 Although control circuit 1 and control circuit 2 are still single chips, they also include signal converter 20, that is, signal converter 20 is the internal DAC of control circuit 2. In this embodiment, reference signal supplier 24, analog comparator ACMP, filtering and control circuit 22, signal converter control unit 21, event trigger 23, timing trigger 26, direct memory accessor 28 and memory 29 are all connected to... Figure 1 The reference signal supplier 14, analog comparator ACMP, filtering and control circuit 12, signal converter control unit 11, event trigger 13, timing trigger 16, direct memory accessor 18, and memory 19 are the same, so they will not be described in detail. Since the signal converter 20 is the internal DAC of the control circuit 2, it does not need a packaging circuit 15 and a bus interface 17. Therefore, the timing trigger 26 and the signal converter control unit 21 will be directly electrically connected to the signal converter 20.

[0035] Additionally, please refer to Figure 3 , Figure 3 This is a block diagram of a reference signal supplier that can be used in the control circuit of a signal converter according to an embodiment of the present invention. The reference signal supplier may include two multiplexers, MUX1 and MUX2. The two input terminals of multiplexer MUX1 receive the bandgap voltage Vbg and the internal reference voltage Vref, and multiplexer MUX1 determines the output terminal of multiplexer MUX1 to output either the bandgap voltage Vbg or the internal reference voltage Vref according to the first bit SEL[0] of the selection signal SEL[1:0]. The two input terminals of multiplexer MUX2 receive the output of multiplexer MUX1 and the external reference voltage Vext, and multiplexer MUX2 determines the output terminal of multiplexer MUX2 to output either the output of multiplexer MUX1 or the external reference voltage Vext according to the second bit SEL[1] of the selection signal SEL[1:0].

[0036] Furthermore, please refer to Figure 4A and Figure 4B , Figure 4A This is a block diagram of the signal conversion system according to an embodiment of the present invention, and Figure 4B This is a block diagram of a signal conversion system according to another embodiment of the present invention. In both embodiments, the signal conversion system includes a digital data source 41, a control circuit, a signal converter 43 or 46, and an analog signal processing device. The digital data source 41 is electrically connected to the signal converter 43 or 46 and the control circuit, and the analog signal processing device is electrically connected to the signal converter 43 or 46 and the control circuit. In both embodiments, the control circuit is a microcontroller 42 or 45, the signal converter 43 is an external DAC other than the microcontroller 42, the signal converter 46 is an internal DAC within the microcontroller 45, and the analog signal processing device is a playback device 44, such as an image or audio playback device. Additionally, in other embodiments, the analog signal processing device may be a signal quality enhancement device, such as a vacuum tube audio enhancement device. In short, the present invention is not limited to the type of analog signal processing device.

[0037] Finally, please refer to Figure 5 , Figure 5This is a flowchart of a method for calibrating a signal converter according to an embodiment of the present invention. The method for calibrating a signal converter is executed in an arithmetic circuit with an analog comparator. First, in step S51, the initial value of the digital signal for which the signal converter performs signal conversion is obtained. For example, the value from the previous calibration is retrieved from memory as the initial value, or the initial value is generated directly. Additionally, in this step, the periodic triggering time of the timing trigger signal is set in conjunction with the setting of a specific event. Then, in step S52, when a specific event is detected, an automatic calibration mode is entered.

[0038] Then, in step S53, in automatic calibration mode, the analog signal output by the signal converter based on the digital signal is acquired, and the analog signal is compared with the analog reference signal by an analog comparator, wherein the initial value of the digital signal corresponds to the analog reference signal. Next, in step S54, the value of the digital signal is increased or decreased according to the comparison signal to update the digital signal. Then, a timing trigger signal is generated to output the updated digital signal to the signal converter, and the signal converter then generates an analog signal based on the updated digital signal. Then, in step S55, the comparison signal corresponding to the updated digital signal is acquired to determine whether the comparison signal has changed state. If the comparison signal has not changed state, step S57 is executed to continue increasing or decreasing the value of the digital signal according to the comparison signal, thereby updating the value of the digital signal, and step S55 continues to be executed after step S57. If the comparison signal has changed state, the value of the digital signal before or after the change is stored to obtain the offset of the signal converter.

[0039] In summary, the embodiments of the present invention provide a control circuit, method, and signal conversion system that can be used in signal converters. In addition to eliminating the need for additional correction circuits, thereby reducing circuit area and power consumption, it can also reduce the use of processor resources, prevent hacker attacks on the chip, and prevent signal converter aging.

[0040] It will be understood that the above embodiments are cited by way of example only, and the invention is not limited to what has been specifically shown and described above. Instead, the scope of the invention includes combinations and sub-combinations of the various features described above, variations and modifications that would occur to those skilled in the art upon reading the foregoing description, and those not disclosed in the prior art. Documents incorporated herein by reference should be considered part of this application, and the definitions in this specification should be considered, except that the scope of any terms is defined in these incorporated documents in a manner that conflicts with the express or implied definitions in this specification.

Claims

1. A control circuit that can be used in a signal converter, characterized in that, The control circuit includes: A switch, the input of which is electrically connected to the output of the signal converter, to receive the analog signal output by the signal converter based on the digital signal conversion, the output of which is connected to the input according to an event trigger signal, wherein the initial value of the digital signal corresponds to the analog reference signal; An analog comparator, whose first input receives the analog reference signal, and whose second input is electrically connected to the output of the switch; and A signal converter control unit is electrically connected to the output of the analog comparator and the input of the signal converter. It is enabled according to the event trigger signal to transmit the digital signal to the input of the signal converter. If the signal converter control unit determines that the comparison signal output by the analog comparator has not changed state, it increases or decreases the value of the digital signal according to the comparison signal. If the signal converter control unit determines that the comparison signal output by the analog comparator has changed state, it records the value of the digital signal before or after the change state, thereby obtaining the offset of the signal converter. The control circuit further includes: A filtering and control circuit is electrically connected between the output terminal of the signal converter and the signal converter control unit. It is enabled according to the event trigger signal and is used to perform noise filtering on the comparison signal output by the analog comparator, so as to output the noise-filtered comparison signal to the signal converter control unit.

2. The control circuit as described in claim 1, characterized in that, The control circuit also includes: A direct memory accessor, electrically connected to the signal converter control unit; and The memory, electrically connected to the direct memory accessor, is used to store the value of the digital signal; The direct memory accessor serves as a data transfer bridge for the signal converter control unit to access memory.

3. The control circuit as described in claim 1, characterized in that, The control circuit also includes: An event trigger, electrically connected to the switch and the signal converter control unit, is used to detect whether a specific event has occurred to generate the event trigger signal; and A timing trigger is electrically connected to and controlled by the signal converter control unit to enable the signal converter according to a timing trigger signal.

4. The control circuit as described in claim 3, characterized in that, The signal converter is an external digital-to-analog converter, separate from the control circuit. The control circuit is a single chip and further includes: The packaging circuit is electrically connected to the signal converter control unit and the timing trigger, and is enabled according to the timing trigger signal. It is used to buffer and output the digital signal, and to output the timing trigger signal. A bus interface is provided, which electrically connects the packaging circuit to an external DAC, for transmitting the digital signal and the timing trigger signal to the external DAC.

5. The control circuit as described in claim 3, characterized in that, The control circuit is a single chip, and the control circuit also includes an internal DAC. The signal converter is the internal DAC, and the internal DAC is electrically connected to the timing trigger.

6. The control circuit as described in claim 3, characterized in that, The signal converter control unit is further configured to set the periodic triggering time of the specific event and the timing trigger signal, and the signal converter control unit is further configured to control the conduction between the input terminal and the output terminal of the switch.

7. The control circuit as described in claim 3, characterized in that, The control circuit also includes: A reference signal supplier, electrically connected to the first input of the analog comparator, is used to provide the analog reference signal, wherein the analog reference signal is selected from one of an internal reference voltage, an external reference voltage, and a bandgap voltage.

8. The control circuit as described in claim 3, characterized in that, The control circuit mentioned therein is an operational circuit including the analog comparator, which runs firmware program code to configure the switch, the signal converter control unit, the event trigger and the timing trigger; or, the switch, the signal converter control unit, the event trigger and the timing trigger are implemented by multiple hardware circuits.

9. A calibration method for use in signal converters, characterized in that, The method is executed in a control circuit, which is an arithmetic circuit including an analog comparator. The arithmetic circuit runs firmware code to execute the method, and in automatic calibration mode, the method includes: The initial value of the digital signal to be converted by the signal converter is obtained, wherein the signal converter is used to convert the digital signal to generate an analog signal; The analog signal output by the signal converter based on the digital signal is obtained, and the analog signal is compared with an analog reference signal by the analog comparator, wherein the initial value of the digital signal corresponds to the analog reference signal; Enabled according to the event trigger signal, it is used to perform noise filtering on the comparison signal output by the analog comparator, so as to output the noise-filtered comparison signal to the signal converter control unit; The digital signal is updated by increasing or decreasing the value of the digital signal according to the comparison signal; The updated digital signal is output to the signal converter; Acquire the comparison signal corresponding to the updated digital signal to determine whether the comparison signal has changed state; If the comparison signal does not change state, the value of the digital signal continues to increase or decrease based on the comparison signal; and If the comparison signal changes state, the digital signal before or after the comparison signal changes state is stored to obtain the offset of the signal converter.

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