Analog-to-digital converter, electric quantity detection circuit and battery management system

Abstract

The embodiment of the present application provides an analog-to-digital converter, an electric quantity detection circuit and a battery management system, the analog-to-digital converter comprises a modulator, an auxiliary conversion module and an output module, the modulator is used for converting an input signal in a plurality of preset conversion periods respectively, and outputting a first conversion result after each conversion, wherein the first conversion result comprises a residual signal; the auxiliary conversion module is connected to the modulator, and is used for converting the residual signal of the last conversion period in the plurality of conversion periods, and outputting a second conversion result; the output module is connected to the modulator and the auxiliary conversion module, and is used for compensating the residual signal of the last conversion period according to the second conversion result, and outputting a final conversion result. The analog-to-digital converter provided by the embodiment of the present application can improve the precision.

Description

Technical Field

[0001] This application relates to the field of analog-to-digital conversion technology, specifically to an analog-to-digital converter, a power detection circuit, and a battery management system. Background Technology

[0002] In recent years, with the improvement of VLSI manufacturing capabilities, Σ-Δ ADCs (Sigma-Delta Analog-to-Digital Converters) have been increasingly widely used due to their high resolution, good linearity, and low cost. Low-order incremental Σ-Δ ADCs offer high measurement accuracy, fast dynamic response, and low power consumption for AC signals; however, they suffer from significant quantization errors when measuring DC signals. Therefore, improving the measurement accuracy of low-order incremental Σ-Δ ADCs for signals, especially DC signals, is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0003] In view of the above problems, embodiments of this application provide an analog-to-digital converter, a power detection circuit, and a battery management system to solve the above technical problems.

[0004] The embodiments of this application are implemented using the following technical solutions:

[0005] An analog-to-digital converter (ADC) includes a modulator, an auxiliary conversion module, and an output module. The modulator converts an input signal in multiple preset conversion cycles and outputs a first conversion result after each conversion, wherein the first conversion result includes a residual signal. The auxiliary conversion module is connected to the modulator and converts the residual signal of the last conversion cycle in the multiple conversion cycles, and outputs a second conversion result. The output module is connected to the modulator and the auxiliary conversion module and compensates for the residual signal of the last conversion cycle according to the second conversion result, and outputs the final conversion result.

[0006] In some implementations, the conversion rate of the auxiliary conversion module is an integer multiple of the conversion rate of the modulator.

[0007] In some implementations, the auxiliary conversion module includes a clock generation circuit and an auxiliary quantizer. The clock generation circuit is used to output a clock signal, and the clock frequency of the clock signal is an integer multiple of the conversion frequency of the modulator. The auxiliary quantizer is connected to the clock generation circuit and the modulator and is used to quantize the residual signal of the last conversion cycle and output the second conversion result.

[0008] In some implementations, the output module includes a digital integral filter, an error compensation module, and a weighting module. The digital integral filter is connected to the modulator and is used to filter the first conversion result. The error compensation module is connected to the auxiliary quantizer and is used to convert the second conversion result into an error compensation signal. The weighting module is connected to the digital integral filter and the error compensation module and is used to perform equivalent processing on the error compensation signal and superimpose it with the first conversion result, and output the final conversion result.

[0009] In some implementations, when the modulator has 1 bit depth and the auxiliary quantizer has 2 bit depths, the weighting module performs equivalent processing on the error compensation signal using the following formula: Among them, V D For error compensation signal; V ref is the reference voltage of the digital-to-analog converter; PGA is the gain of the modulator; n is the number of cycles in the multiple conversion cycles.

[0010] In some implementations, the analog-to-digital converter also includes a reset circuit for resetting the analog-to-digital converter before the modulator converts the input signal in each conversion cycle.

[0011] In some implementations, the modulator includes an integrator, a master quantizer, and a digital-to-analog converter. The integrator integrates the difference between the input signal and the output signal of the digital-to-analog converter in each conversion cycle to output an integrated signal. The master quantizer is connected to the integrator and quantizes the integrated signal to output a first conversion result. The digital-to-analog converter is connected to the output of the master quantizer and the input of the integrator and generates an output signal based on the first conversion result, and feeds the output signal back to the integrator.

[0012] This application embodiment also provides a power detection circuit, including the analog-to-digital converter described above. The power detection circuit further includes a sampling circuit; one end of the sampling circuit is used to sample the input voltage, and the other end is connected to the analog-to-digital converter.

[0013] This application also provides a battery management system, including the above-described power detection circuit.

[0014] This application also provides an analog-to-digital conversion method applied to any of the above-mentioned analog-to-digital converters. The method includes converting the input signal in multiple preset conversion cycles and outputting a first conversion result after each conversion, wherein the first conversion result includes a residual signal; in the last conversion cycle of the multiple conversion cycles, converting the residual signal and outputting a second conversion result; and compensating the residual signal in the first conversion result of the last conversion cycle according to the second conversion result and outputting a final conversion result.

[0015] This application provides an analog-to-digital converter (ADC), a power detection circuit, a battery management system, and an ADC method. The ADC includes a modulator, an auxiliary conversion module, and an output module. The modulator converts the input signal in multiple preset conversion cycles and outputs a first conversion result after each conversion, where the first conversion result includes a residual signal. The auxiliary conversion module is connected to the modulator and converts the residual signal in the last conversion cycle of the multiple conversion cycles, outputting a second conversion result. The output module is connected to the modulator and the auxiliary conversion module and compensates for the residual signal in the last conversion cycle based on the second conversion result, outputting a final conversion result. This embodiment improves the accuracy of the ADC by having the auxiliary conversion module convert the input signal simultaneously with the modulator in the last conversion cycle and compensating for the residual signal in the last conversion cycle based on the second conversion result.

[0016] These or other aspects of this application will become more apparent from the description of the following embodiments. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A block diagram of an analog-to-digital converter provided in an embodiment of this application is shown.

[0019] Figure 2 An example diagram of one implementation of the analog-to-digital converter provided in this application is shown.

[0020] Figure 3 An example diagram of a first-order incremental Σ-Δ ADC provided in an embodiment of this application is shown.

[0021] Figure 4 A circuit diagram of a power detection circuit provided in an embodiment of this application is shown.

[0022] Figure 5 A flowchart illustrating an analog-to-digital conversion method provided in an embodiment of this application is shown. Detailed Implementation

[0023] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0024] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0025] With the widespread adoption of fast charging and 5G (5th generation mobile networks), accurate mobile phone battery monitoring is required. This monitoring is achieved through a fuel gauge, which measures and displays battery power, typically including remaining capacity, full charge capacity, percentage capacity, voltage, current, and temperature. Some fuel gauges also include discharge / charge time, maximum chemical capacity, and an impedance meter. The fuel gauge obtains charge (current * time) information by performing high-precision sampling of the battery current within a specified time window. By measuring the open-circuit voltage and combining this information, it dynamically updates key parameters such as battery power and impedance meter readings.

[0026] Traditional Σ-Δ ADCs (Sigma-Delta Analog-to-Digital Converters) lack precise automatic gain control, offset elimination mechanisms, and utilize complex digital decimation filters, thus failing to meet the requirements of ADCs used in instrumentation and sensing applications. While dual-slope ADCs offer better low offset and accurate gain, they require 2N+1 quantization cycles to achieve N-bit quantization accuracy, while also demanding high-precision matching accuracy from the analog circuitry. Due to limitations in the number of quantization cycles and the matching accuracy of analog components, dual-slope ADCs cannot meet the requirements of high-precision ADCs. Incremental Σ-Δ ADCs, on the other hand, perfectly meet the application conditions in instrumentation and sensing. Therefore, incremental Σ-Δ ADCs are widely used in battery power monitoring systems because they enable accurate acquisition of battery voltage / current signals.

[0027] Low-order incremental Σ-Δ ADCs offer high measurement accuracy, fast dynamic response, and low power consumption for AC signals; however, they exhibit significant quantization errors in DC signal measurement accuracy. Mobile phone battery monitoring systems, on the other hand, have high power consumption requirements, needing to respond quickly to battery current fluctuations with load changes. These systems typically utilize low-power incremental Σ-Δ ADCs. Therefore, improving the measurement accuracy of low-order incremental Σ-Δ ADCs, particularly for DC signals, is a problem that urgently needs to be solved by those skilled in the art.

[0028] Through long-term research and verification by the inventors, this application provides an analog-to-digital converter (ADC), a power detection circuit, a battery management system, and an ADC method. The ADC includes a modulator, an auxiliary conversion module, and an output module. The modulator converts the input signal in multiple preset conversion cycles and outputs a first conversion result after each conversion, wherein the first conversion result includes a residual signal. The auxiliary conversion module is connected to the modulator and converts the residual signal in the last conversion cycle of the multiple conversion cycles, outputting a second conversion result. The output module is connected to the modulator and the auxiliary conversion module and compensates for the residual signal in the last conversion cycle based on the second conversion result, outputting a final conversion result. This embodiment improves the accuracy of the ADC by having the auxiliary conversion module convert the input signal simultaneously with the modulator in the last conversion cycle and compensating for the residual signal in the last conversion cycle based on the second conversion result.

[0029] like Figure 1 As shown, this application embodiment provides an analog-to-digital converter 100. The analog-to-digital converter 100 includes a modulator 110, an auxiliary conversion module 120, and an output module 130. The modulator 110 is used to convert the input signal in a preset plurality of conversion cycles, and outputs a first conversion result after each conversion, wherein the first conversion result includes a residual signal; the auxiliary conversion module 120 is connected to the modulator 110 and is used to convert the residual signal of the last conversion cycle in the plurality of conversion cycles and output a second conversion result; the output module 130 is connected to the modulator 110 and the auxiliary conversion module 120 and is used to compensate the residual signal of the last conversion cycle according to the second conversion result and output the final conversion result.

[0030] Modulator 110 is an incremental Σ-Δ modulator. Analog-to-digital converter 100 samples the input signal according to a sampling clock and sends the input signal to modulator 110. Modulator 110 receives the input signal and converts it. Each time analog-to-digital converter 100 samples, modulator 110 can convert the input signal at least once. In this embodiment, the input signal can be, but is not limited to, an AC signal or a DC signal. For ease of description, all conversion cycles in the preset multiple conversion cycles will be referred to as a "complete conversion cycle" below.

[0031] Furthermore, the first conversion result output by the modulator 110 in each cycle includes a residual signal, which is related to the conversion error of the modulator 110. Specifically, in each conversion cycle, the modulator converts the input signal sampled in the current conversion cycle with the accumulated conversion error of each previous conversion cycle to obtain the first conversion result. Therefore, the residual signal in the first conversion result corresponds to the superposition of the conversion errors of each conversion cycle before the current conversion cycle. Assuming that the number of preset multiple conversion cycles is n, the residual signal in the first conversion result output by the modulator 110 in the i-th cycle corresponds to the accumulated conversion error of the modulator 110 in the previous i-1 cycles, where 1 ≤ i ≤ n.

[0032] In one implementation, the first conversion result output by the modulator 110 is a code value, which can correspond to a voltage value. This voltage value is also the voltage value of the input signal deduced from the first conversion result of the modulator 110, and is called the theoretical value of the input signal. The difference between this theoretical value and the actual value of the input signal is the conversion error of the modulator 110. Further, the residual signal of the last conversion cycle corresponds to the superposition of the conversion errors of the modulator 110 within the complete conversion cycle, that is, the difference between the voltage value corresponding to the first conversion result of the last conversion cycle and the actual voltage value of the input signal. For example, assuming the actual voltage value corresponding to the input signal is 1V and the voltage value corresponding to the first conversion result is 1.1V, then the conversion error is 0.1V. For example, assuming the actual voltage value corresponding to the input signal is 1V, the voltage value corresponding to the conversion result of the first conversion cycle is 1.1V, and the conversion error is 0.1V; the voltage value corresponding to the conversion result of the second conversion cycle is 0.8V, and the conversion error is -0.2V; the conversion errors of the first two conversion cycles are added together to -0.1V, then the conversion error corresponding to the residual signal output in the third conversion cycle is -0.1V.

[0033] In this embodiment, the auxiliary conversion module 120 is activated when the modulator 110 performs the last conversion on the input signal. At this time, in the last conversion cycle of the modulator 110, the auxiliary conversion module 120 converts the residual signal and outputs the second conversion result.

[0034] Furthermore, since the residual signal in the first conversion result output by modulator 110 in the last conversion cycle (the nth cycle) corresponds to the superposition of the conversion errors in the reset cycle and the previous n-1 conversion cycles, the superposition value of this conversion error divided by n is the final conversion error of the modulator. Therefore, the residual signal in the last conversion cycle can be used to characterize the final conversion error of the modulator. The auxiliary conversion module 120 converts the residual signal during the last conversion of modulator 110. Therefore, the output module 130 compensates for the residual signal in the first conversion result of the last conversion cycle based on the second conversion result, which is equivalent to compensating for the final conversion error of modulator 110. Thus, the conversion error of the final conversion result output by output module 130 is smaller than the conversion error of the first conversion result output by modulator 110, thereby improving the conversion accuracy of analog-to-digital converter 100. Simultaneously, since the auxiliary conversion module 120 only starts in the last conversion cycle of modulator 110, it does not significantly increase the power consumption of analog-to-digital converter 100, allowing analog-to-digital converter 100 to maintain low power consumption.

[0035] Therefore, the analog-to-digital converter 100 provided in this embodiment converts the residual signal through the auxiliary conversion module 120 when the modulator 110 performs the last conversion on the input signal, and outputs a second conversion result; and is connected to the modulator 110 and the auxiliary conversion module 120 through the output module 130, and is used to compensate the residual signal in the first conversion result of the last conversion cycle according to the second conversion result, so that the final conversion result output by the output module 130 has a smaller conversion error than the first conversion result output by the modulator 110, thereby improving the conversion accuracy of the analog-to-digital converter 100 while maintaining low power consumption.

[0036] In some implementations, such as Figure 2As shown, the modulator 110 includes an integrator 111, a main quantizer 112, and a digital-to-analog converter 113. The integrator 111 is an incremental Σ-Δ modulation integrator, used to integrate the difference between the input signal and the output signal of the digital-to-analog converter 113 in each conversion cycle to output an integrated signal. The main quantizer 112 is connected to the integrator 111 and is used to quantize the integrated signal to output a first conversion result. The digital-to-analog converter 113 is connected to the output of the main quantizer 112 and the input of the integrator 111 to form a feedback path. The digital-to-analog converter 113 generates an output signal based on the first conversion result and feeds the output signal back to the integrator 111. Furthermore, the modulator 110 also includes a first gain module 114, a second gain module 115, and a third gain module 116. The first gain module 114 receives the input signal at its input terminal and its output terminal is connected to the input terminal of the integrator 111. The second gain module 115 is located between the integrator 111 and the main quantizer 112, with its input terminal connected to the output terminal of the integrator 111 and its output terminal connected to the input terminal of the main quantizer 112. The third gain module 116 is located in the feedback path, with its input terminal connected to the output terminal of the digital-to-analog converter 113 and its output terminal connected to the input terminal of the integrator 111. Since the first conversion result output by the modulator 110 is the quantization result of the main quantizer 112, the conversion error of the modulator 110 will be referred to as the "quantization error" below.

[0037] As an example, the master quantizer 112 is a first-order single-bit quantizer, meaning that the master quantizer 112 has only 1 bit depth, and its output code value is either 0 or 1. In this case, the master quantizer 112 can be implemented using a comparator. Correspondingly, the digital-to-analog converter 113 outputs a corresponding feedback voltage based on the output code value of the master quantizer 112. For example, when the output code value of the master quantizer 112 is 1, the digital-to-analog converter 113 outputs a first feedback voltage; when the output code value of the master quantizer 112 is 0, the digital-to-analog converter 113 outputs a second feedback voltage.

[0038] In this embodiment, the modulator 110 is a Σ-Δ modulator, whose sampling and conversion frequency is much higher than the frequency of the input signal. The tracking performance of the aforementioned feedback loop will cause the long-term average value of the difference between the voltage value corresponding to the first conversion result and the input signal to tend to zero, that is, the average quantization error or the superimposed quantization error will tend to zero after multiple conversions. In this way, the first conversion result gradually approaches the input value, thereby realizing analog-to-digital conversion. In the actual conversion process, although the average quantization error becomes smaller and smaller, it always exists. Therefore, this embodiment uses the auxiliary conversion module 120 to supplement the quantization error of the modulator 110, so as to improve the conversion accuracy of the analog-to-digital converter 100.

[0039] The auxiliary conversion module 120 includes a clock generation circuit 121 and an auxiliary quantizer 122. The clock generation circuit 121 outputs a clock signal, the clock frequency of which is an integer multiple of the conversion frequency of the modulator 110. The auxiliary quantizer 122 is connected to the clock generation circuit 121 and the modulator 110, and is used to quantize the residual signal of the last conversion cycle and output a second conversion result.

[0040] Specifically, the input terminal of the auxiliary quantizer 122 is connected to the input terminal of the main quantizer 112, and it starts working when the main quantizer 112 performs the last quantization of the input signal. The auxiliary quantizer 122 and the main quantizer 112 synchronously quantize the output signal of the second gain module 115. The first conversion result obtained by the main quantizer 112 after the last quantization is not the same as the input signal. The difference between the first conversion result and the input signal is the residual signal. At this time, when the auxiliary quantizer 122 starts quantization synchronously when the main quantizer 112 performs the last quantization, the auxiliary quantizer 122 quantizes the residual signal. In this embodiment, the conversion rate of the auxiliary conversion module 120 is an integer multiple of the conversion rate of the modulator 110. That is, the auxiliary quantizer 122 uses the aforementioned clock signal as a high-frequency reference clock, and the quantization rate of the auxiliary quantizer 122 is an integer multiple of the quantization rate of the main quantizer 112. During the final quantization period of the main quantizer 112, the auxiliary quantizer 122 quantizes the residual signal at a quantization rate that is an integer multiple of the quantization rate of the main quantizer 112. The number of quantizations by the auxiliary quantizer 122 is also an integer multiple of the number of quantizations by the main quantizer 112. At this time, the auxiliary quantizer 122 and the main quantizer 112 output quantized information synchronously, and the number of code values ​​output by the auxiliary quantizer 122 during the final quantization period is an integer multiple of the number of code values ​​output by the main quantizer 112. For example, if the quantization rate of the auxiliary quantizer 122 is twice the quantization rate of the main quantizer 112, then during the final quantization period, the main quantizer 112 outputs one code value, and the auxiliary quantizer 122 outputs two code values. It can be understood that the quantized information output by the auxiliary quantizer 122 is also the second conversion result output by the auxiliary conversion module 120.

[0041] Furthermore, the output module 130 includes a digital integrating filter 131, an error compensation module 132, and a weighting module 133. The digital integrating filter 131 is connected to the modulator 110 and is used to filter the first conversion result; the error compensation module 132 is connected to the auxiliary quantizer 122 and is used to convert the second conversion result into an error compensation signal; the weighting module 133 is connected to the digital integrating filter 131 and the error compensation module 132, and is used to perform equivalent processing on the error compensation signal, superimpose it with the first conversion result, and output the final conversion result.

[0042] Specifically, in this embodiment, the digital integrating filter 131 is connected to the output of the main quantizer 112 to digitally filter the quantized information output by the main quantizer 112. The digital integrating filter 131 can be a low-order or high-order digital integrating filter; this embodiment does not limit the order of the digital integrating filter 131. As an example, the digital integrating filter 131 can be used to calculate the average value of multiple first conversion results output by the main quantizer within a complete conversion cycle; this average value represents the final quantization result of the main quantizer 112. Optionally, the digital integrating filter 131 can be implemented by digital circuitry or software.

[0043] The error compensation module 132 converts the second conversion result output by the auxiliary quantizer 122 into an error compensation signal. Specifically, the error compensation module 132 converts the code value output by the auxiliary quantizer 122 into an analog signal to facilitate subsequent processing of the second conversion result. For example, assuming the auxiliary quantizer 122 outputs a code value D[0:1] = 11, the error compensation module 132 converts this code value into an analog signal and outputs V. D[0：1] =3. It is understandable that the converted analog signal is also the error compensation signal.

[0044] The weighting module 133 performs further equivalent processing on the error compensation signal output by the error compensation module 132, and then weights the processed error compensation signal onto the digital integrating filter 131. Specifically, since the quantization rate of the auxiliary quantizer 122 is an integer multiple of the quantization rate of the main quantizer 112, during the last quantization period, the number of code values ​​(i.e., the number of bits) output by the auxiliary quantizer 122 is a multiple of the number of code values ​​output by the main quantizer 112. At this time, the weighting module 133 performs equivalent processing on the code values ​​output by the auxiliary quantizer 122 according to the number of bits of the main quantizer 112, so that the second conversion result output by the auxiliary quantizer 122 can be weighted with the first conversion result output by the main quantizer 112. For example, suppose the auxiliary quantizer 122 outputs a code value D[0:1] = 11, which includes two code values; the main quantizer 112 outputs a code value for the last quantization. At this time, after the error compensation module 132 converts the code value D[0:1] into an analog signal, the weighting module 133 processes the digital-to-analog conversion D[0:1] into an equivalent code value and outputs a digital signal. The equivalent digital signal is then accumulated to the digital integration filter 131 to compensate for the first conversion result output by the main quantizer 112.

[0045] In this embodiment, when the modulator has 1 bit and the auxiliary quantizer has 2 bits, the weighting module 133 can perform equivalent processing on the error compensation signal using the following formula. Among them, V q-comp For equivalent error compensation signal; VD For error compensation signal; V ref is the reference voltage of digital-to-analog converter 113; PGA is the gain of modulator 110; n is the number of cycles in multiple conversion cycles.

[0046] Furthermore, the weighting module 133 converts the equivalent error compensation signal into a digital signal and accumulates it to the digital integrating filter 131, thereby weighting the first conversion result output by the main quantizer 112 and outputting the final conversion result. Due to the compensation effect of the equivalent error compensation signal, the quantization error of this final conversion result is smaller than that of the first conversion result output by the main quantizer 112. At the same time, since the auxiliary quantizer 122 is only activated during the last quantization of the main quantizer 112, the sampling accuracy and linearity of the analog-to-digital converter 100 are effectively improved, the impact of quantization error is reduced, and accuracy is improved while maintaining fast dynamic response capability without increasing power consumption.

[0047] like Figure 3 As shown, the principle of the analog-to-digital converter 100 provided in this application embodiment will be described in detail below, taking a first-order incremental Σ-Δ ADC as an example.

[0048] The analog-to-digital converter 100 also includes a reset circuit (not shown). The reset circuit resets the analog-to-digital converter 100 at each conversion cycle of the modulator 110, before converting the input signal, to eliminate the previous quantization information of the analog-to-digital converter 100. Specifically, the reset circuit can reset the main quantizer 112, the auxiliary quantizer 122, and the digital integrator filter 131.

[0049] When the analog-to-digital converter 100 converts the input signal, during the reset phase: V1[0]=0(1);

[0050] V1[0] is the output signal of the second gain module 115 during the reset phase. The reset phase will be referred to as the 0th conversion below.

[0051] First conversion cycle: V1[1]=(V1[0]+a1*Vin[0]-b1*Vref*D[0])*a2 (2);

[0052] From equation (2), we get: V1[1]=(a1*Vin[0]-b1*Vref*D[0])*a2 (3);

[0053] Wherein, V1[1] is the output signal of the second gain module 115 in the first conversion cycle (i.e., the first conversion); a1 is the gain of the first gain module 114; Vin[0] is the input signal in the reset phase; b1 is the gain of the third gain module 116; Vref is the reference signal of the digital-to-analog converter 113; and D[0] is the code value output by the main quantizer 112 in the reset phase.

[0054] Second conversion cycle: V1[2]=(V1[1]+a1*Vin[1]-b1*Vref*D[1])*a2 (4);

[0055] From equation (4), we get: V1[2]=[a1*(Vin[1]+Vin[0])-b1*Vref*(D[1]+D[0])]*a2 (5);

[0056] Wherein, V1[2] is the output signal of the second gain module 115 in the second conversion cycle (i.e., during the second conversion); Vin[1] is the input signal sampled by the analog-to-digital converter 100 in the first conversion cycle; and D[1] is the code value output by the main quantizer 112 during the first conversion.

[0057] Therefore, it can be deduced that in the nth transformation:

[0058] Where V1[n] is the output signal of the second gain module 115 during the nth conversion; Vin[k] is the input signal; and D[k] is the digital integral filter.

[0059] Since the analog-to-digital converter 100 is a first-order incremental Σ-Δ ADC, the input signal Vin satisfies the following equation:

[0060]

[0061] Wherein, PGA is the gain of analog-to-digital converter 100, PGA = a1 / b1; D[k] is the code value output by the main quantizer 112 in the kth conversion cycle, that is, the first conversion result in the kth conversion cycle.

[0062] In equation (7), Vq=[V1[n]| / (b1*a2)] / (n*PGA).

[0063] Where -Vref / (n*PGA)≤Vq≤Vref / (n*PGA); -Vref*b1*a2≤V1[n]≤Vref*b1*a2. Vin' is the input voltage corresponding to the final conversion result of the master quantizer 112, and the theoretical value of the input voltage; Vq is the residual error of the first conversion result, that is, the difference between the theoretical value and the actual input voltage.

[0064] In this embodiment, during the last conversion of the main quantizer 112, the auxiliary quantizer 122 starts to synchronously quantize the output signal of the second gain module 115 with the main quantizer 112. The conversion rate of the auxiliary quantizer 122 is M times the conversion rate Fs of the main quantizer 112. In this embodiment, M = 2. That is, the second conversion result output by the auxiliary quantizer 122 is D[0:1].

[0065] Furthermore, the output range of the main quantizer 112 is -Vref to +Vref, defining the quantization level as four intervals.

[0066] When -Vref≤V1[n] / (b1*a2)≤-Vref / 2, D[0:1]=00, and at this time the error compensation signal V output by the error compensation module 132 is... D[0：1] =0, the equivalent error compensation signal output by weighting module 133

[0067] When -Vref / 2 < V1[n] / (b1*a2) ≤ 0, D[0:1] = 01, and the error compensation signal V output by the error compensation module 132 is... D[0：1] =1, the equivalent error compensation signal output by weighting module 133

[0068] When 0 < V1[n]| / (b1*a2)≤Vref / 2, D[0:1]=10, and at this time the error compensation signal V output by the error compensation module 132 is... D[0：1] =2, the equivalent error compensation signal output by weighting module 133

[0069] When Vref / 2 < V1[n] / (b1*a2) ≤ Vref, D[0:1] = 11, and the error compensation signal V output by the error compensation module 132 is... D[0：1] =3, the equivalent error compensation signal output by weighting module 133

[0070] Assume a1 = 40 / 15, b1 = 4 / 15, a2 = 21 / 24, PGA = 10, input signal Vin = 5.4uV, Vref = 1.2V, Fs = 65536Hz, n = 65536.

[0071] At this time, the quantization error of the main quantizer 112 is Vq = [V1[n] / (b1*a2)] / (n*PGA) = 1.74μV; the first conversion result Vin' = Vin - Vq = 3.66μV, that is, the measurement error of the second conversion result output by the main quantizer 112 is 1.74μV.

[0072] Furthermore, assuming the second conversion result D[0:1] = 11 output by the auxiliary quantizer 122, then the equivalent error compensation signal output by the weighting module 133 at this time...

[0073] After the weighting module 133 superimposes the equivalent error compensation signal with the first conversion result output by the main quantizer 112, the final conversion result Vin” is output as 3.66μV + 1.83μV = 5.49μV. At this point, the measurement error of the final conversion result Vin” is 0.09μV. Therefore, the measurement error of the analog-to-digital converter 100 is reduced from 1.74μV to 0.09μV, and the accuracy of the analog-to-digital converter 100 is improved. It can be seen that the analog-to-digital converter 100 has a small quantization error, maintains low power consumption while achieving high measurement accuracy, and has good dynamic response capability.

[0074] The analog-to-digital converter (ADC) provided in this embodiment includes a modulator, an auxiliary conversion module, and an output module. The modulator converts the input signal in multiple preset conversion cycles and outputs a first conversion result after each conversion, wherein the first conversion result includes a residual signal. The auxiliary conversion module is connected to the modulator and converts the residual signal in the last conversion cycle of the multiple conversion cycles, and outputs a second conversion result. The output module is connected to the modulator and the auxiliary conversion module and compensates for the residual signal in the last conversion cycle based on the second conversion result, and outputs a final conversion result. This embodiment improves the accuracy of the ADC by having the auxiliary conversion module convert the input signal simultaneously with the modulator in the last conversion cycle and compensating for the residual signal in the last conversion cycle based on the second conversion result.

[0075] like Figure 4 As shown in the figure, this application embodiment also provides a power detection circuit 200. The power detection circuit 200 includes a sampling circuit 210 and the analog-to-digital converter 100 described above. One end of the sampling circuit 210 is used to sample the input signal, and the other end is connected to the analog-to-digital converter 100.

[0076] The sampling circuit 210 includes a first resistor R1, a second resistor R2, a third resistor R3, and a capacitor C1. The first terminal of the first resistor R1 is connected to the first terminal of the second resistor R2, and the second terminal is connected to the first terminal of the third resistor R3. The two terminals of the first resistor R1 are also connected to the two terminals of the battery BAT. The first terminal of the capacitor C1 is connected to the second terminal of the second resistor R2, and the second terminal is connected to the second terminal of the third resistor R3. The second terminals of the second resistor R2 and the second terminals of the third resistor R3 are connected to the analog-to-digital converter.

[0077] The sampling circuit 210 can sample the voltage of the battery BAT and convert the sampled signal into a differential signal, which is then input to the analog-to-digital converter for high-precision measurement.

[0078] The power detection circuit provided in this embodiment includes a modulator, an auxiliary conversion module, and an output module. The modulator converts the input signal in multiple preset conversion cycles and outputs a first conversion result after each conversion, wherein the first conversion result includes a residual signal. The auxiliary conversion module is connected to the modulator and converts the residual signal in the last conversion cycle of the multiple conversion cycles, and outputs a second conversion result. The output module is connected to the modulator and the auxiliary conversion module and compensates for the residual signal in the last conversion cycle according to the second conversion result, and outputs the final conversion result. This embodiment improves the accuracy of the analog-to-digital converter by having the auxiliary conversion module convert the input signal simultaneously with the modulator in the last conversion cycle and compensating for the residual signal in the last conversion cycle according to the second conversion result.

[0079] This application also provides a battery management system, which includes the above-described power detection circuit.

[0080] like Figure 5 As shown, this application embodiment also provides an analog-to-digital conversion method 300, which can be applied to incremental Σ-Δ ADC. The analog-to-digital conversion method 300 includes the following steps S310 to S330.

[0081] Step S310: The input signal is converted in multiple preset conversion cycles, and a first conversion result is output after each conversion, wherein the first conversion result includes the residual signal.

[0082] In this embodiment, the analog-to-digital converter samples the input signal according to the sampling clock and converts the input signal. The analog-to-digital converter can convert the input signal at least once for each sample.

[0083] Each first conversion result includes a residual signal, which is related to the conversion error. Specifically, in each conversion cycle, the input signal sampled in the current conversion cycle is converted with the accumulated conversion error of each previous conversion cycle to obtain the first conversion result. Therefore, the residual signal in the first conversion result corresponds to the superposition of the conversion errors of each conversion cycle before the current conversion cycle. Assuming that the number of preset multiple conversion cycles is n, the residual signal in the first conversion result output by the modulator 110 in the i-th cycle corresponds to the accumulated conversion error of the modulator 110 in the previous i-1 cycles, where 1 ≤ i ≤ n.

[0084] Step S320: In the last conversion cycle of multiple conversion cycles, perform auxiliary conversion on the residual signal and output the second conversion result.

[0085] In this embodiment, the residual signal can be simultaneously converted during the last conversion cycle of the analog-to-digital converter. Specifically, an additional auxiliary conversion module can be started in the last cycle of the analog-to-digital converter to perform auxiliary quantization of the residual signal synchronously with the converter, thereby obtaining the second conversion result.

[0086] Step S330: Compensate the residual signal in the first conversion result of the last conversion cycle according to the second conversion result, and output the final conversion result.

[0087] In this embodiment, since the residual signal in the first conversion result output in the last conversion cycle (the nth cycle) corresponds to the superposition of the conversion errors in the reset cycle and the previous n-1 conversion cycles, the superposition value of this conversion error divided by n is the final conversion error. Therefore, the residual signal in the last conversion cycle can be used to characterize the final conversion error. By performing auxiliary conversion on the residual signal during the last conversion, the residual signal in the first conversion result of the last conversion cycle can be compensated based on the second conversion result, which is equivalent to compensating for the final conversion error. Therefore, the conversion error of the final conversion result is smaller than the conversion error of the first conversion result, thereby improving the conversion accuracy of the analog-to-digital converter.

[0088] The analog-to-digital conversion method provided in this application converts the input signal in multiple preset conversion cycles and outputs a first conversion result after each conversion, wherein the first conversion result includes a residual signal; in the last conversion cycle of the multiple conversion cycles, the residual signal is converted by auxiliary conversion and a second conversion result is output; then, the residual signal in the first conversion result of the last conversion cycle is compensated according to the second conversion result, and the final conversion result is output, thereby improving the accuracy of the analog-to-digital converter.

[0089] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An analog-to-digital converter, characterized in that, include: A modulator is used to convert an input signal in multiple preset conversion cycles and output a first conversion result after each conversion, wherein the first conversion result includes a residual signal; An auxiliary conversion module, connected to the modulator, is used to initiate the conversion in the last conversion cycle of the modulator, convert the residual signal of the last conversion cycle among the plurality of conversion cycles, and output a second conversion result; wherein the residual signal in the first conversion result output in the last conversion cycle corresponds to the superposition of conversion errors of the modulator in the remaining conversion cycles among the plurality of conversion cycles excluding the last conversion cycle; and An output module is connected to the modulator and the auxiliary conversion module, and is used to compensate the residual signal of the last conversion cycle according to the second conversion result, and output the final conversion result; Wherein, the conversion rate of the auxiliary conversion module is an integer multiple of the conversion rate of the modulator; The auxiliary conversion module includes: A clock generation circuit for outputting a clock signal, the clock frequency of which is an integer multiple of the switching frequency of the modulator; and An auxiliary quantizer, connected to the clock generation circuit and the modulator, is used to quantize the residual signal of the last conversion cycle and output the second conversion result.

2. The analog-to-digital converter as described in claim 1, characterized in that, The output module includes: A digital integrator filter, connected to the modulator, is used to filter the first conversion result; and An error compensation module, connected to the auxiliary quantizer, is used to convert the second conversion result into an error compensation signal; and The weighting module, connected to the digital integral filter and the error compensation module, is used to perform equivalent processing on the error compensation signal and superimpose it with the first conversion result, and output the final conversion result.

3. The analog-to-digital converter as described in claim 2, characterized in that, The modulator includes an integrator, a master quantizer, and a digital-to-analog converter; The integrator is used to integrate the difference between the input signal and the output signal of the digital-to-analog converter in each conversion cycle to output an integrated signal; The main quantizer is connected to the integrator and is used to quantize the integrated signal to output the first conversion result; as well as The digital-to-analog converter is connected to the output of the main quantizer and the input of the integrator, and is used to generate an output signal based on the first conversion result and feed the output signal back to the integrator.

4. The analog-to-digital converter as described in claim 3, characterized in that, When the modulator has 1 bit depth and the auxiliary quantizer has 2 bit depth, the weighting module performs equivalent processing on the error compensation signal using the following formula: ;in, This is the error compensation signal; is the reference voltage of the digital-to-analog converter; PGA is the gain of the modulator; n is the number of cycles of the plurality of conversion cycles.

5. The analog-to-digital converter as described in claim 1, characterized in that, The analog-to-digital converter further includes a reset circuit for resetting the analog-to-digital converter before the modulator converts the input signal in each conversion cycle.

6. A power detection circuit, characterized in that, The analog-to-digital converter includes any one of claims 1 to 5, and the power detection circuit further includes a sampling circuit; one end of the sampling circuit is used to sample the input voltage, and the other end is connected to the analog-to-digital converter.

7. A battery management system, characterized in that, Includes the power detection circuit as described in claim 6.

8. An analog-to-digital conversion method, applied to the analog-to-digital converter according to any one of claims 1 to 5, characterized in that, The method includes: The input signal is converted in multiple preset conversion cycles, and a first conversion result is output after each conversion, wherein the first conversion result includes a residual signal; In the last conversion cycle of the plurality of conversion cycles, the residual signal is converted and a second conversion result is output; and the residual signal in the first conversion result of the last conversion cycle is compensated according to the second conversion result and a final conversion result is output.

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