Printed circuit board

Abstract

A printed circuit board is provided. The printed circuit board includes a first insulating layer having a recess in one surface thereof, a first circuit pattern embedded in the first insulating layer and exposed from a lower surface of the recess, a second insulating layer disposed on the one surface of the first insulating layer to be disposed in at least a portion of the recess, and a via hole penetrating at least a portion of the second insulating layer, disposed in the recess, and connected to the first circuit pattern.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2021-0099711, filed on July 29, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a printed circuit board, and more particularly, to a printed circuit board including vias without pads or solder pads. Background Technology

[0003] As electronic devices (including mobile phones) in the information technology (IT) field have become lighter, thinner, shorter, and smaller, circuit density has increased, and the number of input / output integrated circuits has also increased. Consequently, the circuit patterns used in printed circuit boards (PCBs) are becoming increasingly thinner in width. Implementing microcircuits can require long development cycles and large investments in infrastructure, making them difficult to implement easily.

[0004] As a key technology for microcircuit routing, it is necessary to reduce the linewidth of circuit patterns and the distance between them. However, the wide pads or solder pads of vias used for interlayer connections are a major factor making it difficult to lay out a large number of circuit traces. Therefore, there is a need to develop technologies for interlayer connections that are unaffected by pads or solder pads, and there is a demand for methods that increase circuit density through structural changes without any additional facility investment or material alterations. Summary of the Invention

[0005] One aspect of this disclosure is to provide a printed circuit board capable of implementing microcircuits.

[0006] Another aspect of this disclosure provides a printed circuit board that can reduce processing costs and processing time.

[0007] Another aspect of this disclosure provides a printed circuit board that is advantageous for increasing circuit density.

[0008] Another aspect of this disclosure provides a printed circuit board capable of preventing defects caused by via plating or delamination.

[0009] According to one aspect of this disclosure, a printed circuit board may include: a first insulating layer having a recess in one surface of the first insulating layer; a first circuit pattern embedded in the first insulating layer and exposed from a lower surface of the recess; a second insulating layer disposed on the one surface of the first insulating layer to be disposed in at least a portion of the recess; and a via penetrating at least a portion of the second insulating layer, disposed in the recess, and connected to the first circuit pattern.

[0010] According to another aspect of this disclosure, a printed circuit board may include: a first insulating layer having a recess in one surface of the first insulating layer; a first circuit pattern embedded in the first insulating layer and exposed from a lower surface of the recess; a second circuit pattern disposed on the one surface of the first insulating layer; and a plurality of vias spaced apart from each other in the recess and each of the first circuit pattern and the second circuit pattern connecting to each other.

[0011] According to another aspect of this disclosure, a printed circuit board may include: a first insulating layer having a recess in one surface of the first insulating layer; a second insulating layer disposed on the one surface of the first insulating layer and including a portion disposed in the recess; a plurality of first circuit patterns spaced apart from each other in the first insulating layer and exposed from the recess; a plurality of second circuit patterns embedded in the second insulating layer; and a plurality of vias spaced apart from each other in the recess and extending from the plurality of first circuit patterns to the plurality of second circuit patterns, respectively. Attached Figure Description

[0012] The above and other aspects, features, and advantages of this disclosure will be more clearly understood through the following specific embodiments in conjunction with the accompanying drawings, in which:

[0013] Figure 1 It is a block diagram that schematically illustrates an example of an electronic device system;

[0014] Figure 2 This is a perspective view schematically illustrating an exemplary embodiment of the electronic device;

[0015] Figure 3 This is a cross-sectional view schematically illustrating an exemplary embodiment of a printed circuit board;

[0016] Figures 4 to 10 It is a schematic illustration of the materials used in manufacturing. Figure 3 A flowchart of an exemplary embodiment of the method for making a printed circuit board;

[0017] Figure 11 It is shown Figure 3 Enlarged views of the circuit pattern and vias of the printed circuit board; and

[0018] Figure 12 It is shown schematically. Figure 3 A cross-sectional view of a modified exemplary embodiment of a printed circuit board. Detailed Implementation

[0019] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0020] Figure 1This is a block diagram that schematically illustrates an example of an electronic device system.

[0021] Reference Figure 1 Electronic device 1000 may house motherboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 may be physically and / or electrically connected to motherboard 1010. These components may be connected to other electronic components described below via various signal lines 1090.

[0022] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), or flash memory; application processor chips, such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, or microcontrollers; and logic chips, such as analog-to-digital converters (ADCs) or application-specific integrated circuits (ASICs). Chip-related components 1020 are not limited to these, but may also include other types of chip-related components. Furthermore, these chip-related components 1020 may be combined with each other. Chip-related components 1020 may be in the form of a package including the aforementioned chips.

[0023] Network-related components 1030 may include components compatible with or operating according to protocols such as: Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE, EV-DO (evolution-data only, an evolution of CDMA2000 1x), HSPA+, HSDPA+, HSUPA+, GSM, EDGE, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, and 5G protocols, as well as any other wireless and wired protocols specified after the protocols listed above. However, network-related component 1030 is not limited to this, but may also include components compatible with or operating according to various other wireless or wired standards or protocols. Additionally, network-related component 1030 may be combined with chip-related component 1020 to form a package.

[0024] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), etc. However, other components 1040 are not limited to these, but also include passive components of various other chip assembly types for various other purposes. Furthermore, other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030 to form a package.

[0025] Depending on the type of electronic device 1000, it may include other electronic components that are physically and / or electrically connected to the motherboard 1010 or not physically and / or electrically connected to the motherboard 1010. Examples of other electronic components may include a camera 1050, an antenna 1060, a display 1070, a battery 1080, etc. Other electronic components are not limited to these, but may include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage units (e.g., hard disk drives), optical discs (CDs), digital versatile discs (DVDs), etc. Depending on the type of electronic device 1000, it may also include other electronic components for various purposes.

[0026] Electronic device 1000 can be a smartphone, personal digital assistant (PDA), digital video camera, digital camera, network system, computer, monitor, tablet PC, laptop PC, netbook PC, television, video game console, smartwatch, automotive component, etc. However, electronic device 1000 is not limited to these, and can be any other electronic device capable of processing data.

[0027] Figure 2 This is a perspective view schematically illustrating an exemplary embodiment of the electronic device.

[0028] Reference Figure 2 For example, the electronic device could be a smartphone 1100. A motherboard 1110 can be housed in the smartphone 1100, and various electronic components 1120 can be physically and / or electrically connected to the motherboard 1110. Additionally, a camera module 1130, a speaker 1140, etc., can also be housed in the smartphone 1100. Some of the electronic components in the electronic components 1120 can be the aforementioned chip-related components, for example, a printed circuit board 1121 on the surface of which multiple electronic components are mounted, but are not limited thereto. Furthermore, the electronic device is not limited to the smartphone 1100, but can be any other electronic device as described above.

[0029] Figure 3 This is a cross-sectional view schematically illustrating an exemplary embodiment of a printed circuit board.

[0030] Reference Figure 3 According to an exemplary embodiment, a printed circuit board 100 may include: a substrate B; a first circuit pattern 210 disposed on the substrate B; a first insulating layer 110 disposed on the substrate B to embed the first circuit pattern 210, and a recess R formed in the first insulating layer 110; a second circuit pattern 220 disposed on the first insulating layer 110; a via 300 disposed in the recess R of the first insulating layer 110 to electrically connect the first circuit pattern 210 and the second circuit pattern 220 to each other; and a second insulating layer 120 disposed on the first insulating layer 110 to at least partially fill the recess R and at least partially cover the second circuit pattern 220 and the via 300. Furthermore, this disclosure is not limited thereto; the printed circuit board may not include a substrate, a second circuit pattern, and / or a second insulating layer.

[0031] The recess R can be formed in a surface of the first insulating layer 110 of the printed circuit board 100 according to an exemplary embodiment by a skiving process. The recess R can be formed using conventional insulating material processing methods (such as laser processes described later), and at least a portion of the first circuit pattern 210 can be exposed from the lower surface of the recess R. Unlike the process for forming corresponding vias for interlayer connections on the first circuit pattern 210, the process for forming the recess R in one step as described above ensures that space for vias 300 will be provided therein, allowing the printed circuit board to be manufactured by a simpler process.

[0032] Furthermore, the recess R of the printed circuit board 100 according to the exemplary embodiment may have a tapered shape, and the recess R is formed in one surface of the first insulating layer 110 by a laser process. That is, the recess R may be tapered to have a smaller width or cross-sectional area as it gets closer to the other surface of the first insulating layer 110. In addition, compared to a structure where one surface of the first insulating layer 110 is flat, the stepped structure produced on one surface of the first insulating layer 110 by the formation of the recess R also improves the adhesion between the first insulating layer 110 and the second insulating layer 120.

[0033] Furthermore, the vias 300 of the printed circuit board 100 according to the exemplary embodiment may have a shape different from that of conventional vias formed by laser processing, and the vias 300 are formed by a dry film D (dry film resist) in the manufacturing process described later. That is, unlike cylindrical or truncated tapered vias formed by laser processing, the vias 300 of this disclosure may have a polygonal shape with angles in a cross section (i.e., a horizontal cross section) perpendicular to the direction in which the vias 300 and the first circuit pattern 210 are stacked.

[0034] Furthermore, since the vias 300 of the printed circuit board 100 according to the exemplary embodiment are not formed by a laser process, the vias 300 can have a shape with substantially equal widths on their upper and lower surfaces, rather than a tapered shape. Tapered vias based on laser processes have a difference in cross-sectional area between their upper and lower surfaces, which can lead to cracks in the plating due to delamination in the region with the smaller cross-sectional area. In contrast, according to this disclosure, since the vias 300 are formed using a dry film D plating process, the aforementioned plating defects can be prevented.

[0035] Furthermore, the first circuit pattern 210 disposed on the underside of the via 300 of the printed circuit board 100 according to the exemplary embodiment may not require a land. Similarly, since the upper and lower surfaces of the via 300 have substantially equal cross-sectional areas, the second circuit pattern 220 disposed on the upper side of the via 300 may also not require a pad. Typically, pads and solder pads are formed with a cross-sectional area or volume larger than that of the wiring layer for effective connection with the via, which occupies a considerable amount of space. According to this disclosure, as described above, a pad-free or solder pad-free structure is proposed to form a wiring layer more densely, and the pad-free or solder pad-free structure can effectively realize microcircuit structures.

[0036] In the following description, the components of a printed circuit board 100 according to an exemplary embodiment will be described with reference to the accompanying drawings.

[0037] Reference Figure 3 The printed circuit board 100 may include: a substrate B; a first circuit pattern 210 disposed on the substrate B; a first insulating layer 110 disposed on the substrate B to cover the first circuit pattern 210, and a recess R is formed in one surface of the first insulating layer 100; a second circuit pattern 220 disposed on one surface of the first insulating layer 110; a second insulating layer 120 disposed on one surface of the first insulating layer 110 to fill at least a portion of the recess R and cover the second circuit pattern 220; and a via 300 penetrating at least a portion of the second insulating layer 120 to electrically connect the first circuit pattern 210 and the second circuit pattern 220 to each other.

[0038] The first insulating layer 110 and the second insulating layer 120 may be sequentially stacked on the substrate B. The substrate B may be a typical printed circuit board (including wiring layers, via layers and multiple interlayer insulating layers).

[0039] A recess R may be formed in one surface of the first insulating layer 110, and a first circuit pattern 210 may be embedded in the other surface of the first insulating layer 110. The printed circuit board 100 may be in the form of a coreless, padless, and solderless board. As described above, this disclosure is characterized in that, as a construction for interlayer connection, the recess R is formed in one step by a scraping process, rather than performing a laser process to form vias on each region of the first insulating layer 110 where the first circuit pattern 210 will be exposed. The recess R may be formed by a laser process (so-called scraping process) described below, and by doing so, the first circuit pattern 210 may be partially exposed to the lower surface of the recess R. The portion of the first circuit pattern 210 for interlayer connection may be exposed to the lower surface of the recess R, so that a plurality of first circuit patterns 210 may be exposed to the lower surface of the recess R and spaced apart from each other. In addition, there is no limitation on the linewidth of the region of the first circuit pattern 210 embedded in the first insulating layer 110 and the linewidth of the region of the first circuit pattern 210 exposed to the lower surface of the recess R, but they may be substantially equal. That is, in the printed circuit board 100 of this disclosure, no individual solder pads or pads are formed in the area where the first circuit pattern 210 connects between layers (e.g., the area where the first circuit pattern 210 is connected to the via 300 and / or the via 300 is connected to the second circuit pattern 220). Additionally, one surface of the first insulating layer 110 may have a step between the portion having the recess R and another portion of the first insulating layer 110.

[0040] Additionally, multiple first circuit patterns 210 may be exposed on the lower surface of the aforementioned recess R. (Refer to...) Figure 3 Four exposed surfaces of the first circuit pattern 210 may exist on the lower surface of the recess R. In conventional processes for forming vias, the vias expose corresponding circuit patterns disposed on the underside of the vias in a one-to-one correspondence. In contrast, according to this disclosure, the process can be further simplified since the recess R is formed in one step by a scraping process. In one example, the first circuit pattern 210 may include a pattern having an upper surface covered by a first insulating layer 110, spaced apart from the recess R.

[0041] Additionally, a scraping process can be performed until the lower surface of the recess R exposes the first circuit pattern 210, such that the upper surface of the first circuit pattern 210 exposed to the lower surface of the recess R is coplanar with the lower surface of the recess R. In this disclosure, the term "coplanar" may mean that a shared surface is formed, and a shared surface may be interpreted not only as a physically perfectly flat surface, but also as including tolerances that may occur during the process.

[0042] The second insulating layer 120 may be disposed on one surface of the first insulating layer 110 to fill at least a portion of the recess R. In this case, the step formed on one surface of the first insulating layer 110 due to the recess R can result in an anchoring effect, thereby improving the adhesion between the first insulating layer 110 and the second insulating layer 120 compared to the case where one surface of the first insulating layer 110 is flat. The second insulating layer 120 may partially cover the second circuit pattern 220 and the via 300 disposed on one surface of the first insulating layer 110.

[0043] The insulating material may be used as the material for each of the first insulating layer 110 and the second insulating layer 120. Examples of insulating materials for each of the first insulating layer 110 and the second insulating layer 120 may include thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimide resins), or materials prepared by impregnating inorganic fillers (such as silica) and / or reinforcing materials (such as glass fibers) in a thermosetting or thermoplastic resin (e.g., prepreg or Ajinomoto laminate (ABF)). The number of the first insulating layer 110 and the second insulating layer 120 may be greater than or less than [the number of layers]. Figure 3 The quantities shown are as indicated. If necessary, the first insulating layer 110 and the second insulating layer 120 may include photosensitive insulating material.

[0044] The first circuit pattern 210 can be deposited on the substrate B by a plating process and embedded in another surface of the first insulating layer 110. The first circuit pattern 210 can extend in the first insulating layer 110 and can extend in a direction perpendicular to the direction of extension of the recess R. One surface of the first circuit pattern 210 can be exposed from the lower surface of the recess R, and a via 300 can be disposed on the exposed surface of the first circuit pattern 210 and contact and connect to the exposed surface of the first circuit pattern 210. In addition, the interface between the first circuit pattern 210 and the via 300 can be coplanar with the interface between the first insulating layer 110 and the second insulating layer 120 on the lower surface of the recess R.

[0045] The second circuit pattern 220 may be disposed on one surface of the first insulating layer 110 and covered by the second insulating layer 120. Furthermore, the second circuit pattern 220 may be integrally formed with the via 300. That is, the second circuit pattern 220 may be integrally formed with the via 300 by a plating process described below, and there may be no plating interface between the second circuit pattern 220 and the via 300. The second circuit pattern 220 may be electrically connected to the first circuit pattern 210 through the via 300. Additionally, since the second circuit pattern 220 and the via 300 are integrally formed, the side surfaces of the second circuit pattern 220 and the side surfaces of the via 300 may be coplanar. The second circuit pattern 220 may be disposed on at least one of the surfaces of the via 300 and the first insulating layer 110.

[0046] Metallic materials can be used as the material for each circuit pattern in the first circuit pattern 210 and the second circuit pattern 220, and the metallic material can be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first circuit pattern 210 and the second circuit pattern 220 can perform various functions according to the design. For example, the first circuit pattern 210 and the second circuit pattern 220 may include grounding patterns, power patterns, signal patterns, etc. Each of these patterns can be in the form of a line, a plane, or a pad. The first circuit pattern 210 can be formed by plating processes (such as additive process (AP), semi-additive process (SAP), modified semi-additive process (MSAP), or via sealing (TT)), therefore, the first circuit pattern 210 may include a seed layer as an electroless plating layer and an electrolytic plating layer formed based on the seed layer. If necessary, the first circuit pattern 210 may also include a primer copper foil. The number of first circuit patterns 210 and second circuit patterns 220 may be greater than or less than [the number of circuit patterns]. Figure 3 The quantities shown in the figure.

[0047] Vias 300 can be provided on the first circuit pattern 210 exposed in the recess R using a plating process of the dry film D described below. Therefore, multiple vias 300 can be provided when multiple exposed surfaces of the first circuit pattern 210 exist in the recess R. The multiple vias 300 can be spaced apart from each other in the recess R and can extend from the multiple first circuit patterns 210 to the multiple second circuit patterns 220, respectively. That is, vias 300 can be provided on the multiple first circuit patterns 210, which are spaced apart from each other on the lower surface of the recess R. Furthermore, the multiple first circuit patterns 210 can be arranged in one direction, and the recess R can extend in that direction.

[0048] Furthermore, since the via 300 is formed using a plating process with a dry film D, the via 300 of this disclosure can have a shape with substantially equal cross-sectional areas on its upper and lower surfaces. In this disclosure, the term "substantially equal" can mean not only physically identical, but also includes tolerances that may occur considering the environment in the actual process. Because the via 300 of this disclosure does not have a tapered shape based on a laser process, but rather a shape with substantially equal cross-sectional areas on its upper and lower surfaces, defective plating can be prevented. For example, in a tapered via structure, insulating material may penetrate into the interface between plating layers in areas with smaller cross-sectional areas, and the plating layers may separate from each other, leading to cracking and delamination. However, according to this disclosure, sufficient interface area between the plating layers of the first circuit pattern 210 and the via 300 can be ensured, thereby preventing cracking and delamination.

[0049] Furthermore, since the vias 300 of the printed circuit board 100 according to the exemplary embodiment are formed by performing a plating process after a resist layer is created by exposing and developing a dry film D, rather than by a laser process, it is possible to achieve the following: Figure 3 The printed circuit board 100 exhibits a pad-less and solder pad-less structure. Pads and solder pads refer to metal layers formed by plating over a large area to ensure sufficient thickness and area of ​​the metal layer in the area to be contacted by the laser or sandblasting material, and the functionality of the metal layer for electrical connection to other components (such as vias) in the circuit pattern, considering damage to the copper (Cu) layer during laser or sandblasting processes used to form vias. Therefore, larger metal layers are typically provided in pad and solder pad areas, which reduces space utilization. However, according to this disclosure, pads and solder pads can be omitted, allowing the first circuit pattern 210 to be formed more densely within the same space.

[0050] Furthermore, the absence of solder pads and solder joints facilitates the implementation of the first circuit pattern 210 as a high-density microcircuit pattern. As an example of a high-density circuit, the first circuit pattern 210 of the printed circuit board 100 may have a relatively fine average pitch compared to the average pitch of the wiring layers (not shown) in the substrate B. Here, pitch may refer to the distance from the center of one conductor pattern to the center of another adjacent conductor pattern in each wiring layer.

[0051] Furthermore, the via 300 of the printed circuit board 100 according to the exemplary embodiment (the via 300 is provided using a dry film D) may have a shape different from that of a typical via provided by a laser process. That is, unlike cylindrical or truncated conical vias provided by a laser process (whose cross-section is circular due to the effect of the laser), the via 300 of this disclosure may have a polygonal shape with angles in a horizontal cross-section, and may have the same shape as the circuit pattern according to the design. Therefore, according to this disclosure, in the area where the via 300 and the first circuit pattern 210 are in contact with each other, the side surface of the first circuit pattern 210 and the side surface of the via 300 may be coplanar with each other.

[0052] Metallic materials can also be used as the material for each via in via 300, and the metallic material can be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Via 300 may include signal connection vias, ground connection vias, power connection vias, etc., depending on the design. Via 300 may have substantially equal cross-sectional areas from its upper surface to its lower surface. Via 300 may be formed by plating processes (e.g., AP, SAP, MSAP, or TT), and therefore may include a seed layer as an electroless plating layer and an electrolytic plating layer formed based on the seed layer. The number of vias 300 may be greater than or less than [the specified number]. Figure 3 The quantities shown in the figure.

[0053] In addition, although Figure 3 The via 300 is shown to have a substantially equal cross-sectional area from its upper surface to its lower surface. However, the shape of the via 300 can be adjusted according to various designs in the following manner: if necessary, the shape of the dry film D is adjusted in the exposure and development process of the dry film D, which will be described below. Therefore, the shape of the via 300 is not necessarily limited to having a substantially equal cross-sectional area from its upper surface to its lower surface.

[0054] The same applies to other repeating components, so their descriptions will not be repeated.

[0055] Figures 4 to 10 It is a schematic illustration of the materials used in manufacturing. Figure 3 A flowchart of an exemplary embodiment of a method for manufacturing a printed circuit board.

[0056] Reference Figure 4 A first circuit pattern 210 may be formed on a substrate B. Although not shown, the substrate B may be an insulating layer supporting the first circuit pattern 210, a printed circuit board in which multiple insulating layers, wiring layers and vias are formed, or an intermediary for connecting boards to each other.

[0057] When the substrate B is a printed circuit board or an intermediary, the first circuit pattern 210 can be electrically connected to the conductor layer in the substrate B.

[0058] Reference Figure 5 A first insulating layer 110 can be formed on the substrate B to embed the first circuit pattern 210. To fill the space between the first circuit patterns 210, the first insulating layer 110 may include ABF, which is a material that is fluid before being cured.

[0059] Reference Figure 6 and Figure 7 A recess R can be formed in one surface of the first insulating layer 110 by using a laser scraping process. The scraping process refers to a method of machining an object by continuously irradiating it with a laser while moving the laser-irradiated area in one direction. For example, such as... Figure 7 ( Figure 7 As shown in the conceptual plan view (which illustrates a recess R formed in the first insulating layer 110 to expose some portions of the first circuit pattern 210), the recess R may extend in a direction perpendicular to the direction in which the first circuit pattern 210 extends.

[0060] The upper surface of the first circuit pattern 210 may be exposed to the lower surface of the recess R, and the exposed upper surface of the first circuit pattern 210 may form a shared surface with the lower surface of the recess R. Optionally, in the case of a long laser process time, the upper surface of the first circuit pattern 210 may protrude from the lower surface of the recess R by a predetermined distance.

[0061] Reference Figure 7 The remaining area of ​​the first circuit pattern 210, except for the area exposed to the recess R, can be embedded in the first insulating layer 110.

[0062] Reference Figure 8 A photoresist (such as a dry film D) may be disposed on one surface of the first insulating layer 110 and in the recess R. In this disclosure, the photoresist is referred to as a dry film D, but is not limited thereto, and the photoresist may be another photosensitive material that is easy to expose and develop.

[0063] Subsequently, a portion of the dry film D can be removed using an exposure / development process. For example... Figure 8 As shown, by developing and removing the dry film D, the upper surface of the first circuit pattern 210 exposed to the recess R can be exposed, and the area of ​​the first insulating layer 110 on which the second circuit pattern 220 is disposed can be exposed.

[0064] Reference Figure 9The second circuit pattern 220 and via 300 can be formed in the area where the dry film D is developed by a plating process. In this case, since the second circuit pattern 220 and via 300 are formed by a single plating process, the boundary between the second circuit pattern 220 and via 300 may be unclear. Furthermore, since the via 300 is formed on the first circuit pattern 210 by performing a separate plating process, an interface may exist between the corresponding plating layers of the first circuit pattern 210 and the via 300.

[0065] Reference Figure 10 The remaining dry film D can also be exposed and removed. After removing the dry film D as described above, the second circuit pattern 220 and the via 300 can be retained. This is advantageous for ensuring design freedom compared to performing plating after forming vias in the insulating material using a laser process. That is, according to this disclosure, since the area for setting the second circuit pattern 220 and the via 300 is secured by a process of exposing and developing the photosensitive material (which is relatively easier to control compared to a laser process), the shape of the second circuit pattern 220 and the via 300 can be controlled according to the design. Figure 10 In this case, the second circuit pattern 220 and the via 300 may share a surface with the exposed surface and side surface of the first circuit pattern 210, and may have a relatively straight shape rather than a tapered shape. That is, the upper and lower surfaces of the via 300 may have substantially equal cross-sectional areas, and the second circuit pattern 220 disposed on the upper side of the via 300 may also have a linewidth substantially equal to the linewidth of the via 300.

[0066] Figure 11 It is shown Figure 3 Enlarged view of the circuit pattern and vias of the printed circuit board.

[0067] Figure 11 The shapes of the first circuit pattern 210, the second circuit pattern 220, and the via 300 according to this disclosure are schematically shown. Because this disclosure employs a plating process performed after the exposure and development of the photosensitive material, rather than a laser process, the via 300 can have a polygonal shape with non-rounded corners in a horizontal cross-section. As an example, such as... Figure 11As shown, the via 300 may have a rectangular shape in its horizontal cross-section. Furthermore, at least a portion of the side surface of the first circuit pattern 210 may be coplanar with at least a portion of the side surface of the via 300, and at least a portion of the side surface of the first circuit pattern 210 may also be coplanar with at least a portion of the side surface of the second circuit pattern 220. Additionally, because the first circuit pattern 210 and the via 300 are formed by separate plating processes, an interface may exist between the corresponding plating layers of the first circuit pattern 210 and the via 300. However, because the second circuit pattern 220 and the via 300 are integrally formed, no interface may exist between the second circuit pattern 220 and the via 300.

[0068] When vias are formed using conventional laser processes, they typically take the shape of a tapered cylinder or a truncated cone. When the cross-sectional area of ​​the vias is inconsistent, defective plating is likely to occur in areas where the via has a smaller cross-sectional area (e.g., in the area where the via contacts a pad located on the underside of the via). When cracks appear in the area where the via contacts a pad located on the underside of the via, insulating material may seep into the cracks between the plating layers, leading to plating delamination or signal failure.

[0069] According to this disclosure, since the via 300 is formed using a photoresist rather than a laser process, the via 300 can be formed to have a consistent cross-sectional area, thereby ensuring sufficient contact area between the via 300 and the first circuit pattern 210 and preventing the aforementioned defects (including cracks and delamination) in advance.

[0070] Furthermore, when vias are formed using conventional laser processes, pads and solder pads need to be formed over a large area to prevent the laser from damaging the underlying pattern. In contrast, according to this disclosure, since lasers are not used to form vias, pads and solder pads can be omitted. As a result, more wiring layers can be placed in the same area, thereby enabling microcircuit patterns.

[0071] Figure 12 It is shown schematically. Figure 3 A cross-sectional view of a modified exemplary embodiment of a printed circuit board.

[0072] Figure 12 A printed circuit board 200 according to a modified exemplary embodiment is shown. According to the modified exemplary embodiment, one surface of the second insulating layer 120 can also be processed by a scraping process to form a second recess R2, thereby exposing at least a portion of the upper surface of the second circuit pattern 220. The first recess R1 and the first via 310 can respectively resemble... Figure 3 The recessed portion R is formed in the same way as the through hole 300.

[0073] A second via 320 and a third circuit pattern 230 may be provided on the upper surface of the second circuit pattern 220 exposed to the second recess R2. The second via 320 and the third circuit pattern 230 may be provided using a photoresist, and then a third insulating layer 130 may fill the second recess R2 while simultaneously covering the second via 320 and the third circuit pattern 230. Subsequently, an opening O for connecting to another external component may be formed in a surface of the third insulating layer 130 to expose at least a portion of the third circuit pattern 230 to the outside. Electrically connecting metals (such as solder or bumps) may be provided on the exposed third circuit pattern 230 for electrical connection to another component (such as an external electronic component).

[0074] Regarding the third circuit pattern 230, the descriptions of the first circuit pattern 210 and the second circuit pattern 220 provided above also apply, and the third insulating layer 130 in which the opening O is formed can be a solder resist layer comprising a photosensitive insulating material. Furthermore, in Figure 3 In the printed circuit board 100, an opening similar to the opening O described above may also be formed in the second insulating layer 120 to expose at least one second circuit pattern 220 to the outside for electrical connection to external electronic components.

[0075] As described above, as an effect of this disclosure, a printed circuit board capable of implementing microcircuits can be provided.

[0076] As another effect of this disclosure, it is possible to provide a printed circuit board that can reduce processing costs and processing time.

[0077] As another effect of this disclosure, it is possible to provide a printed circuit board that is beneficial for increasing circuit density.

[0078] As another effect of this disclosure, a printed circuit board is provided that can prevent defects caused by via plating or delamination.

[0079] While exemplary embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: The first insulating layer has a recess in one surface; Multiple first circuit patterns are embedded in the first insulating layer and are respectively exposed from the lower surface of the recess; A second insulating layer is disposed on said one surface of the first insulating layer to be disposed in at least a portion of the recess; as well as Multiple vias, penetrating at least a portion of the second insulating layer, are spaced apart from each other in the recess and are respectively connected to the multiple first circuit patterns, and The first insulating layer includes a first portion located below the recess and two second portions located on opposite sides of the recess, wherein the thickness of the first portion is less than the thickness of each of the two second portions.

2. The printed circuit board of claim 1, wherein, The first insulating layer has a step between the portion having the recess and another portion of the surface.

3. The printed circuit board according to claim 1, wherein, The upper surface of the first circuit pattern is exposed to the lower surface of the recess and is coplanar with the lower surface of the recess.

4. The printed circuit board of claim 1, further comprising a second circuit pattern disposed on at least one of the vias and the first insulating layer.

5. The printed circuit board according to claim 1, wherein, The via contacts the upper surface of the first circuit pattern, and the upper surface of the first circuit pattern is exposed from the lower surface of the recess.

6. The printed circuit board according to claim 1, wherein, The via is disposed on each of the plurality of first circuit patterns, which are spaced apart from each other on the lower surface of the recess.

7. The printed circuit board according to claim 4, wherein, The side surface of the via is coplanar with the side surface of the second circuit pattern connected to the via.

8. The printed circuit board according to claim 7, wherein, The side surface of the via is coplanar with the side surface of the first circuit pattern connected to the via.

9. The printed circuit board according to claim 1, wherein, The via has a polygonal shape with angles in a cross section perpendicular to the direction in which the via and the first circuit pattern are stacked.

10. The printed circuit board according to claim 1, wherein, The via has a substantially equal cross-sectional area from its upper surface to its lower surface.

11. The printed circuit board according to claim 1, wherein, The first circuit pattern extends in the first insulating layer and in a direction perpendicular to the direction in which the recess extends.

12. The printed circuit board according to claim 1, wherein, The recess is tapered so that it has a smaller cross-sectional area as it gets closer to the other surface of the first insulating layer.

13. A printed circuit board, comprising: The first insulating layer has a recess in one surface; Multiple first circuit patterns are embedded in the first insulating layer and are respectively exposed from the lower surface of the recess; Multiple second circuit patterns are disposed on one surface of the first insulating layer; as well as Multiple vias are spaced apart from each other in the recess, and each via connects a corresponding first circuit pattern in the plurality of first circuit patterns and a corresponding second circuit pattern in the plurality of second circuit patterns to each other. The first insulating layer includes a first portion located below the recess and two second portions located on opposite sides of the recess, wherein the thickness of the first portion is less than the thickness of each of the two second portions.

14. The printed circuit board according to claim 13, further comprising: A second insulating layer is disposed on said one surface of the first insulating layer to be disposed in at least a portion of the recess. Wherein, the interface between the first insulating layer and the second insulating layer on the lower surface of the recess is coplanar with the interface between the first circuit pattern and each of the plurality of vias.

15. The printed circuit board according to claim 13, wherein, The upper surface of each of the plurality of vias contacts the second circuit pattern. The lower surface of each of the plurality of vias contacts the first circuit pattern, and The upper and lower surfaces of each of the plurality of vias have substantially equal cross-sectional areas.

16. The printed circuit board according to claim 14, wherein, The plurality of vias penetrate at least a portion of the second insulating layer in the recess.

17. A printed circuit board, comprising: A first insulating layer having a first recess in one surface; A second insulating layer is disposed on the one surface of the first insulating layer and includes a portion disposed in the first recess; Multiple first circuit patterns are spaced apart from each other in the first insulating layer and exposed from the first recess; Multiple second circuit patterns are embedded in the second insulating layer; as well as Multiple first vias are spaced apart from each other in the first recess and extend from the multiple first circuit patterns to the multiple second circuit patterns, respectively. The first insulating layer includes a first portion located below the first recess and two second portions located on opposite sides of the first recess, wherein the thickness of the first portion is less than the thickness of each of the two second portions.

18. The printed circuit board according to claim 17, wherein, The plurality of first circuit patterns are arranged in one direction, and the first recess extends in the same direction.

19. The printed circuit board according to claim 17, wherein, The interface between one of the plurality of first circuit patterns and one of the plurality of first vias is coplanar with the interface between the first insulating layer and the second insulating layer on the lower surface of the first recess.

20. The printed circuit board according to claim 17, wherein, The side surface of one of the plurality of first vias is coplanar with the side surface of one of the plurality of second circuit patterns.

21. The printed circuit board according to claim 17, wherein, A second recess is provided in one surface of the second insulating layer, and the plurality of second circuit patterns are exposed from the second recess, wherein the printed circuit board further includes: A plurality of second vias and a plurality of third circuit patterns, the plurality of second vias being spaced apart from each other in the second recess and respectively connecting the plurality of second circuit patterns to the plurality of third circuit patterns; and A third insulating layer fills the second recess and covers the plurality of second vias and the plurality of third circuit patterns.

22. The printed circuit board according to claim 21, wherein, An opening is formed in the third insulating layer to expose at least one of the plurality of third circuit patterns to the outside.

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