Memory elements having vertical field effect transistors and methods of making the same

Abstract

The present disclosure provides a memory element having a vertical field effect transistor and a method of fabricating the memory element. The memory element has a capacitor contact disposed in a first semiconductor substrate and a channel structure disposed on an upper surface of the first semiconductor substrate. The memory element also has a first gate structure disposed on a first sidewall of the channel structure and a second gate structure disposed on a second sidewall of the channel structure. The second sidewall of the channel structure is disposed opposite the first sidewall of the channel structure. The memory element further has a bit line contact disposed on the channel structure. The channel structure is electrically connected to a capacitor and a bit line via the capacitor contact and the bit line contact.

Description

[0001] Cross-references

[0002] This application claims priority and benefits from U.S. Official Application No. 17 / 390,405, filed July 30, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a memory element and a method for fabricating the same. In particular, it relates to a memory element having a vertical field-effect transistor and a method for fabricating the same. Background Technology

[0004] Due to their simplified structure, Dynamic Random Access Memory (DRAM) offers more memory cells per chip area compared to other types of memory, such as Static Random Access Memory (SRAM). A DRAM consists of multiple DRAM cells, each including a capacitor and a transistor. The capacitor stores information, and the transistor is coupled to the capacitor to regulate its charge or discharge. During a read operation, a signal on a word line (WL) is active, turning on the transistor. The activated transistor allows voltage to pass through the capacitor, which is then read by a sense amplifier via a word line (BL). During a write operation, when the WL signal is active, the data to be written is provided on the BL.

[0005] To meet the demands of larger memory storage, the size of DRAM memory cells has been continuously reduced, resulting in a significant increase in the packaging density of these DRAMs. However, the manufacturing and integration of these memory elements involves many complex steps and operations. Integration within these memory elements has become increasingly complex. This increased complexity in the manufacturing and integration of these memory elements can lead to several defects. Therefore, there is a need for continuous improvement in the manufacturing processes and structures of these memory elements to address these defects and enhance their performance.

[0006] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0007] One embodiment of this disclosure provides a memory element. The memory element includes a capacitor contact disposed in a first semiconductor substrate; and a channel structure disposed on an upper surface of the first semiconductor substrate. The memory element also includes a first gate structure disposed on a first sidewall of the channel structure; and a second gate structure disposed on a second sidewall of the channel structure. The second sidewall of the channel structure is disposed opposite to the first sidewall of the channel structure. The memory element further includes a bit line contact disposed on the channel structure. The channel structure is electrically connected to a capacitor and a bit line via the capacitor contact and the bit line contact.

[0008] In one embodiment, the capacitor contact directly contacts a lower surface of the channel structure, and the bit line contact directly contacts an upper surface of the channel structure. In one embodiment, the channel structure is disposed between the bit line and the capacitor. In one embodiment, the memory element further includes a second semiconductor substrate bonded to a lower surface of the first semiconductor substrate, wherein the capacitor is disposed in the second semiconductor substrate. In one embodiment, the first gate structure includes a first gate electrode and a first gate dielectric, the gate dielectric being sandwiched between the first gate electrode and the channel structure, wherein the second gate structure includes a second gate electrode and a second gate dielectric, the second gate dielectric being sandwiched between the second gate electrode and the channel structure.

[0009] In one embodiment, the memory element further includes a first dielectric portion disposed on the upper surface of the first semiconductor substrate and on a third sidewall of the channel structure; and a second dielectric portion disposed on the upper surface of the first semiconductor substrate and on a fourth sidewall of the channel structure, wherein the third sidewall and the fourth sidewall of the channel structure are disposed opposite to each other. In one embodiment, the first gate structure and the second gate structure extend to cover each of the opposing sidewalls of the first dielectric portion and the second dielectric portion.

[0010] Another embodiment of this disclosure provides a memory element. The memory element includes a first capacitor contact and a second capacitor contact disposed in a semiconductor substrate; a first channel structure and a second channel structure disposed on the semiconductor substrate and spaced apart from each other. The first channel structure is electrically connected to a first capacitor via the first capacitor contact, and the second channel structure is electrically connected to a second capacitor via the second capacitor contact. The memory element also includes a first gate structure disposed on a first sidewall of the first channel structure and a first sidewall of the second channel structure; and a second gate structure disposed on a second sidewall of the first channel structure and a second sidewall of the second channel structure. The first sidewall and the second sidewall of the first channel structure are disposed opposite to each other. The memory element also includes a first bit line contact and a second bit line contact disposed on the first channel structure and the second channel structure, respectively. The first channel structure is electrically connected to a first bit line via the first bit line contact point, and the second channel structure is electrically connected to a second bit line via the second bit line contact point.

[0011] In one embodiment, the first capacitor contact is disposed between the first channel structure and the first capacitor, and the second capacitor is disposed between the second channel structure and the second capacitor. In one embodiment, the first channel structure directly contacts the first capacitor contact and the first bit line contact, and the second channel structure directly contacts the second capacitor contact and the second bit line contact. In one embodiment, the memory element further includes a first dielectric portion disposed between the first channel structure and the second channel structure, and directly contacts the first channel structure and the second channel structure.

[0012] In one embodiment, the first dielectric portion is disposed between the first gate structure and the second gate structure, and directly contacts the first gate structure and the second gate structure. In another embodiment, the first dielectric portion is separated from the semiconductor substrate. In yet another embodiment, the memory element further includes a second dielectric portion disposed between the first gate structure and the second gate structure, wherein the first channel structure is disposed between the first dielectric portion and the second dielectric portion, and directly contacts the first dielectric portion and the second dielectric portion.

[0013] Another embodiment of this disclosure provides a method for fabricating a memory element. The method includes forming a capacitor contact in a first semiconductor substrate; and forming a first sacrificial structure and a second sacrificial structure on an upper surface of the first semiconductor substrate and on opposite sides of the capacitor contact. The method also includes forming a first gate structure on a sidewall of the first sacrificial structure and forming a second gate structure on a sidewall of the second sacrificial structure facing the sidewall of the first sacrificial structure; and forming a dielectric strip between the first gate structure and the second gate structure. The method further includes replacing a first portion of the dielectric strip with a channel structure; forming a bit line contact on the channel structure; and forming a bit line on the bit line contact.

[0014] In one embodiment, the fabrication method further includes bonding a second semiconductor substrate to a lower surface of the first semiconductor substrate, wherein a capacitor in the second semiconductor substrate passes through the channel structure at the capacitor contact point. In one embodiment, the fabrication method further includes removing the first sacrificial structure and the second sacrificial structure after the channel structure is formed. In one embodiment, a second portion of the dielectric strip is adjacent to the channel structure.

[0015] In one embodiment, the steps of forming the first gate structure and the second gate structure further include forming a first gate electrode on the sidewall of the first sacrificial structure and forming a second gate electrode on the sidewall of the second sacrificial structure; and forming a first gate dielectric on one sidewall of the first gate electrode and forming a second gate dielectric on one sidewall of the second gate electrode, wherein the first gate dielectric and the second gate dielectric are physically connected by a connection covering the capacitor contact point. In one embodiment, prior to the formation of the channel structure, the connection is partially etched to expose the capacitor contact point.

[0016] This disclosure provides some embodiments of a memory element structure and its fabrication method. In some embodiments, the memory element structure includes a channel structure disposed on a semiconductor substrate and covering a capacitor contact point within the semiconductor substrate; and a bit line contact point disposed on the channel structure. In some embodiments, the memory element also includes a first gate structure disposed on a first sidewall of the channel structure; and a second gate structure disposed on a second sidewall of the channel structure, wherein the second sidewall of the channel structure is opposite to the first sidewall of the channel structure. The channel structure is electrically connected to a capacitor and a bit line via the capacitor contact point and the bit line contact point. Because the channel structure provides a vertical electrical connection between the capacitor and the bit line, the integration density of the memory element can be increased.

[0017] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, thereby enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0018] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0019] Figure 1 This is a top view schematic diagram illustrating memory elements of different embodiments of the present disclosure.

[0020] Figure 2 This is a cross-sectional schematic diagram illustrating different embodiments of the present disclosure along... Figure 1 The memory element with section A-A' in the diagram.

[0021] Figure 3 This is a cross-sectional schematic diagram illustrating different embodiments of the present disclosure along... Figure 1 The memory element with section B-B' in the middle.

[0022] Figure 4 This is a cross-sectional schematic diagram illustrating different embodiments of the present disclosure along... Figure 1 The memory element with section B-B' in the middle.

[0023] Figure 5 This is a flowchart illustrating a method for fabricating memory elements according to some embodiments of this disclosure.

[0024] Figure 6 This is a top view schematic diagram illustrating an intermediate stage in the formation of multiple sacrificial structures on a semiconductor substrate during the formation of memory elements, according to some embodiments of the present disclosure.

[0025] Figure 7 This is a cross-sectional schematic diagram illustrating different embodiments of the present disclosure in the formation along... Figure 6 The intermediate stage in the memory element with section A-A'.

[0026] Figure 8 This is a cross-sectional schematic diagram illustrating the intermediate stage in the formation of multiple gate electrode portions on such sacrificial structures during the formation of memory elements in different embodiments of the present disclosure.

[0027] Figure 9This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a gate dielectric layer on the gate electrode portions during the formation of memory elements according to different embodiments of the present disclosure.

[0028] Figure 10 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a dielectric layer on the gate dielectric layer during the formation of a memory element, according to different embodiments of the present disclosure.

[0029] Figure 11 This is a top view schematic diagram illustrating an intermediate stage in the formation of a planarization process—the formation of multiple gate electrodes, multiple gate dielectrics, and multiple dielectric strips—during memory element formation in different embodiments of this disclosure.

[0030] Figure 12 This is a cross-sectional schematic diagram illustrating different embodiments of the present disclosure in the formation along... Figure 11 The intermediate stage in the memory element with section A-A'.

[0031] Figure 13 This is a top view schematic diagram illustrating an intermediate stage in the formation of a patterned mask during the formation of memory elements in different embodiments of the present disclosure.

[0032] Figure 14 This is a cross-sectional schematic diagram illustrating different embodiments of the present disclosure in the formation along... Figure 13 The intermediate stage in the memory element with section A-A'.

[0033] Figure 15 This is a cross-sectional schematic diagram illustrating different embodiments of the present disclosure in the formation along... Figure 13 The intermediate stage in the memory element with section B-B'.

[0034] Figure 16 This is a top view schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure where a patterned mask is used as a mask during the formation of memory elements to etch dielectric strips to form a plurality of openings.

[0035] Figure 17 This is a cross-sectional schematic diagram illustrating different embodiments of the present disclosure in the formation along... Figure 16 The intermediate stage in the memory element with section A-A'.

[0036] Figure 18 This is a cross-sectional schematic diagram illustrating different embodiments of the present disclosure in the formation along... Figure 16 The intermediate stage in the memory element with section B-B'.

[0037] Figure 19This is a top view schematic diagram illustrating how, in different embodiments of the present disclosure, a patterned mask is used as a mask during memory element formation to etch the gate dielectric to deepen the intermediate stages of the openings.

[0038] Figure 20 This is a cross-sectional schematic diagram illustrating different embodiments of the present disclosure in the formation along... Figure 19 The intermediate stage in the memory element with section A-A'.

[0039] Figure 21 This is a cross-sectional schematic diagram illustrating different embodiments of the present disclosure in the formation along... Figure 19 The intermediate stage in the memory element with section B-B'.

[0040] Figure 22 This is a top view schematic diagram illustrating an intermediate stage in the formation of memory elements in different embodiments of the present disclosure, during which the vias are filled with a plurality of channel structures.

[0041] Figure 23 This is a cross-sectional schematic diagram illustrating different embodiments of the present disclosure in the formation along... Figure 22 The intermediate stage in the memory element with section A-A'.

[0042] Figure 24 This is a cross-sectional schematic diagram illustrating different embodiments of the present disclosure in the formation along... Figure 22 The intermediate stage in the memory element with section B-B'.

[0043] Figure 25 This is a top view schematic diagram illustrating an intermediate stage during the formation of memory elements in different embodiments of the present disclosure, in which the sacrificial structures are removed.

[0044] Figure 26 This is a cross-sectional schematic diagram illustrating different embodiments of the present disclosure in the formation along... Figure 25 The intermediate stage in the memory element with section A-A'.

[0045] Figure 27 This is a cross-sectional schematic diagram illustrating different embodiments of the present disclosure in the formation along... Figure 25 The intermediate stage in the memory element with section B-B'.

[0046] Figure 28 This is a top view schematic diagram illustrating an intermediate stage in the formation of multiple bit contact points on such channel structures during the formation of memory elements in different embodiments of the present disclosure.

[0047] Figure 29 This is a cross-sectional schematic diagram illustrating different embodiments of the present disclosure in the formation along... Figure 28 The intermediate stage in the memory element with section A-A'.

[0048] Figure 30 This is a cross-sectional schematic diagram illustrating different embodiments of the present disclosure in the formation along... Figure 28 The intermediate stage in the memory element with section B-B'.

[0049] Figure 31 This is a cross-sectional schematic diagram illustrating different embodiments of this disclosure. Figure 9 The steps shown represent the intermediate stage of partially removing the gate dielectric layer.

[0050] Explanation of reference numerals in the attached figures:

[0051] 10: Preparation method

[0052] 100a: Memory element

[0053] 100b: Memory element

[0054] 101: Semiconductor substrate

[0055] 101B: Lower surface

[0056] 101T: Upper surface

[0057] 103: Capacitor contact point

[0058] 105: Sacrifice Structure

[0059] 110: Opening

[0060] 110': Opening

[0061] 113: Gate electrode section

[0062] 113a: Gate electrode

[0063] 113b: Gate electrode

[0064] 115: Gate dielectric layer

[0065] 115a: Gate dielectric

[0066] 115b: Gate dielectric

[0067] 115c: Connecting part

[0068] 117: Dielectric layer

[0069] 117': Dielectric strip

[0070] 117P: Dielectric section

[0071] 119: Patterned Mask

[0072] 120: Opening

[0073] 130: Opening

[0074] 130': Opening

[0075] 133: Channel Structure

[0076] 133B: Lower surface

[0077] 143: Dielectric layer

[0078] 145: Bit line contact point

[0079] 151: Dielectric layer

[0080] 153: Bitline

[0081] 201: Semiconductor substrate

[0082] 203: Conductive layer

[0083] 205: Dielectric layer

[0084] 207: Conductive layer

[0085] 209: Capacitor

[0086] G1: Gate structure

[0087] G2: Gate structure

[0088] S11: Steps

[0089] S13: Steps

[0090] S15: Steps

[0091] S17: Steps

[0092] S19: Steps

[0093] S21: Steps

[0094] S23: Steps

[0095] S25: Steps

[0096] SW1: Sidewall

[0097] SW2: Sidewall

[0098] SW3: Sidewall

[0099] SW4: Sidewall

[0100] SW5: Sidewall

[0101] SW6: Sidewall Detailed Implementation

[0102] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0103] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0104] Figure 1 This is a top view schematic diagram illustrating a memory element 100a in different embodiments of the present disclosure. Figure 2 This is a cross-sectional schematic diagram illustrating different embodiments of the present disclosure along... Figure 1 The memory element 100a is shown in section A-A'. Figure 3 This is a cross-sectional schematic diagram illustrating different embodiments of the present disclosure along... Figure 1 The memory element 100a is the section line B-B' in the middle.

[0105] like Figures 1 to 3 As shown, memory element 100a includes a semiconductor substrate 101 (also representing a first semiconductor substrate); a dielectric layer 143 disposed on the semiconductor substrate 101; and a dielectric layer 151 disposed on the dielectric layer 143. In some embodiments, in other words, the dielectric layer 143 is disposed on an upper surface 101T of the semiconductor substrate 101, and the semiconductor substrate 201 is bonded to a lower surface 101B of the semiconductor substrate 101.

[0106] In some embodiments, the memory element 100a includes a plurality of capacitors 209 disposed on a semiconductor substrate 201; and a plurality of capacitor contacts 103 disposed in the semiconductor substrate 101. In some embodiments, each capacitor 209 includes conductive layers 203, 207 and a dielectric layer 205, the dielectric layer 205 being sandwiched between conductive layers 203, 207. In some embodiments, the memory element 100a also includes a plurality of gate structures G1 (also represented as a plurality of first gate structures) disposed on each sidewall SW1 of a plurality of channel structures 133; and a plurality of gate structures G2 (also represented as a plurality of second gate structures) disposed on each sidewall SW2 of the channel structures 133.

[0107] In some embodiments, each gate structure G1 includes a gate electrode 113a and a gate dielectric 115a, with the gate dielectric 115a sandwiched between the gate electrode 113a and a corresponding channel structure 133. In some embodiments, each gate structure G2 includes a gate electrode 113b and a gate dielectric 115b, with the gate dielectric 115b sandwiched between the gate electrode 113b and a corresponding channel structure 113. Furthermore, according to some embodiments, the memory element 100a includes a plurality of bit line contacts 145 disposed in the dielectric layer 143 and on the channel structures 133; and a plurality of bit lines 153 disposed in the dielectric layer 151 and on the bit line contacts 145.

[0108] In some embodiments, the channel structures 133 are electrically connected to a plurality of capacitors 209 and a plurality of bit lines 153 via capacitor contacts 103 and bit line contacts 145. In some embodiments, the capacitor contacts 103 directly contact each lower surface 133B of the channel structures 133, and the bit line contacts 145 directly contact each upper surface 133T of the channel structures 133.

[0109] In addition, such as Figure 1 and Figure 3 As shown, according to some embodiments, the memory element 100a further includes a plurality of dielectric portions 117P, which are interleaved with the channel structures 133. In some embodiments, each channel structure 133 has four sidewalls, sidewalls SW1 and SW2 directly contacting gate structures G1 and G2, and sidewalls SW3 and SW4 directly contacting adjacent dielectric portions 117P. In some embodiments, gate structures G1 and G2 extend to cover the opposite sidewalls of the dielectric portions 117P.

[0110] Furthermore, such as Figure 3As shown, according to some embodiments, memory element 100a includes a plurality of connection portions 115c disposed between the dielectric portions 117P and the semiconductor substrate 101. In some embodiments, each gate dielectric 115a of the gate structures G1 and each gate dielectric 115b of the gate structures G2 are physically connected through the connection portions 115c. It should be understood that the gate dielectrics 115a, the gate dielectrics 115b, and the connection portions 115c may contain the same material and be formed from the same layer. In some embodiments, memory element 100a is a dynamic random access memory (DRAM) having a vertical field-effect transistor (VFET).

[0111] Figure 4 This is a cross-sectional schematic diagram illustrating different embodiments of the present disclosure along... Figure 1 The memory element 100b is shown in section B-B'. Please note. Figure 1 The top view is also a top view of a memory element 100b, and Figure 2 The cross-sectional view is also a cross-sectional view along section line A-A' of memory element 100b. The structure of memory element 100b may be similar to or the same as that of memory element 100a, and its detailed description will not be repeated herein. One difference between memory elements 100a and 100b is that the dielectric portions 117P of memory element 100b directly contact the semiconductor substrate 101 of memory element 100b. Note that memory element 100b does not include any connection portions (e.g., the connection portions 115c of memory element 100a) connecting the gate dielectrics 115a and 115b. In some embodiments, memory element 100b is a DRAM having a VFET.

[0112] Figure 5 This is a flowchart illustrating a method 10 for fabricating memory elements (including memory elements 100a and 100b) according to some embodiments of the present disclosure. The fabrication method 10 includes steps S11, S13, S15, S17, S19, S21, S23 and S25. Figure 5 Steps S11 to S25 are described in detail with reference to the following figures.

[0113] Figure 6 , Figure 11 , Figure 13 , Figure 16 , Figure 19 , Figure 22 , Figure 25 and Figure 28 This is a top view illustrating various intermediate stages in forming memory element 100a according to some embodiments of the present disclosure, while Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 12 , Figure 14 , Figure 15 , Figure 17 , Figure 18 , Figure 20 , Figure 21 , Figure 23 , Figure 24 , Figure 26 , Figure 27 , Figure 29 and Figure 30 This is a cross-sectional view illustrating various intermediate stages in the formation of memory element 100a according to some embodiments of this disclosure. It should be understood that... Figure 7 , Figure 12 , Figure 14 , Figure 17 , Figure 20 , Figure 23 , Figure 26 as well as Figure 29 To respectively along Figure 6 , Figure 11 , Figure 13 , Figure 16 , Figure 19 , Figure 22 , Figure 25 as well as Figure 28 The sectional view along section line A-A', and Figure 15 , Figure 18 , Figure 21 , Figure 24 , Figure 27 as well as Figure 30 To respectively along Figure 13 , Figure 16 , Figure 19 , Figure 22 , Figure 25 as well as Figure 28 A sectional view with section line B-B'.

[0114] like Figure 6 and Figure 7As shown, a semiconductor substrate 101 is provided. The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer. Additionally, the semiconductor substrate 101 may comprise elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and gallium arsenide phosphide (GaInAsP).

[0115] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator (SOI) substrate, which may include a substrate, a buried oxide layer, and a semiconductor layer, wherein the buried oxide layer is located on the substrate, the semiconductor layer is located on the buried oxide layer, and the SOI substrate is, for example, a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The SOI substrate can be fabricated using separation by implanted oxygen (SIMOX), wafer bonding, and / or other applicable methods.

[0116] Please refer to the following: Figure 6 and Figure 7Multiple capacitor contacts 103 are formed in the semiconductor substrate 101, and multiple sacrificial structures 105 are formed on the upper surface 101T of the semiconductor substrate 101. The corresponding steps are described in... Figure 5 Steps S11 and S13 in the fabrication method 10 shown. In some embodiments, the sacrificial structures 105 are arranged in a parallel configuration and separated from each other by a plurality of openings 110, which expose the capacitor contacts 103 and portions of the upper surface 101T of the semiconductor substrate 101.

[0117] In some embodiments, the capacitor contacts 103 comprise a conductive material, such as copper, tungsten, aluminum, titanium, tantalum, gold, or silver. A method for fabricating the capacitor contacts 103 may include forming a patterned mask (not shown) on the upper surface 101T of a semiconductor substrate 101; using the patterned mask as a mask to etch the semiconductor substrate 101 to form a plurality of capacitor contact openings (not shown); depositing a conductive material in the capacitor contact openings and on the upper surface 101T of the semiconductor substrate 101; and planarizing the conductive material until the upper surface 101T of the semiconductor substrate 101 is exposed.

[0118] Furthermore, according to some embodiments, the sacrificial structures 105 comprise a metallic material for forming a plurality of gate electrode portions in subsequent processes. In some embodiments, the sacrificial structures 105 comprise copper, tungsten, aluminum, titanium, tantalum, gold, silver, nickel, iridium, ruthenium, or combinations thereof. The fabrication technique for the sacrificial structures 105 may include a deposition process and a subsequent etching process. The deposition process may include chemical vapor deposition (CVD), atomic layer deposition (ALD), high-density plasma CVD (HDCVD), metal-organic CVD (MOCVD), other suitable methods, or combinations thereof. The deposition process is performed using a patterned mask (not shown), and the deposition process may include a dry etching process, a wet etching process, or a combination thereof. The patterned mask may be removed after the openings 110 are formed by the etching process.

[0119] Next, as Figure 8 As shown, a plurality of gate electrode portions 113 are formed to cover each upper surface and each sidewall of the sacrificial structures 105. In some embodiments, the gate electrode portions 113 are formed to line each sidewall of the openings 110, exposing the lower surface of the openings 110. That is, some portions of the capacitor contacts 103 and the upper surface 101T of the semiconductor substrate 101 exposed through the openings 110 may remain uncovered.

[0120] In some embodiments, the gate electrode portions 113 comprise a conductive material, such as graphene. However, other suitable materials may be used to form the gate electrode portions 113, such as copper, tungsten, aluminum, titanium, tantalum, gold, silver, nickel, iridium, ruthenium, or combinations thereof. In some embodiments, the fabrication technique for the gate electrode portions 113 includes a deposition process, such as CVD, ALD, MOCVD, PECVD, PEALD, other suitable methods, or combinations thereof. Some portions of the conductive material formed on the upper surface 101T of the semiconductor substrate 101, if any, may be removed by an etching process.

[0121] Next, as Figure 9 As shown, according to some embodiments, a gate dielectric layer 115 is conformally formed on... Figure 8 Structurally. In some embodiments, a gate dielectric layer 115 is formed to cover the upper surface of each opening 110 and extends over each sacrificial structure 105. In some embodiments, the gate dielectric layer 115 is formed to cover the upper surfaces and sidewalls of the gate electrode portions 113, and to cover the portions of the capacitor contacts 103 and the upper surface 101T of the semiconductor substrate 101 exposed through the openings 110.

[0122] The gate dielectric layer 115 may be a single layer or multiple layers. In some embodiments, the gate dielectric layer 115 comprises silicon oxide, silicon nitride, silicon oxynitride, a dielectric material having a high dielectric constant, or a combination thereof. The material with a high dielectric constant may be HfO2, ZrO2, La2O3, Y2O3, Al2O3, TiO2, or other suitable materials. The fabrication technique of the gate dielectric layer 115 may include a deposition process, such as CVD, physical vapor deposition (PVD), ALD, PECVD, PEALD, other suitable methods, or a combination thereof.

[0123] Then, as Figure 10 As shown, according to some embodiments, a dielectric layer 117 is formed on the gate dielectric layer 115 and fills the remaining portions of the openings 110. For example... Figures 8 to 10 The corresponding steps are explained in the following: Figure 5 Step S15 of the fabrication method 10 shown. In some embodiments, the dielectric layer 117 comprises silicon oxide, silicon nitride, silicon oxynitride, a dielectric material with a low dielectric constant, or other suitable materials. The fabrication technique of the dielectric layer 117 may include a deposition process, such as CVD, PVD, ALD, spin coating, or other suitable methods.

[0124] like Figure 11 and Figure 12As shown, according to some embodiments, after the dielectric layer 117 is formed, a planarization process is performed on the gate electrode portions 113, the gate dielectric layer 115, and the dielectric layer 117 to remove excess material on the sacrificial structures 105, in order to obtain the gate electrodes 113a and 113b, the gate dielectrics 115a and 115b, the connection portions 115c, and the plurality of dielectric strips 117'. The corresponding steps are described in... Figure 5 Step S17 in the fabrication method 10 shown. In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process. It should be understood that the gate electrodes 113a and 113b are the remaining gate electrode portions 113, and the remaining gate dielectric layer 115 includes the gate dielectrics 115a and 115b and the connection portions 115c.

[0125] In some embodiments, each sacrificial structure 105 has a sidewall SW5 and an opposing sidewall SW6, with each sidewall SW5 facing the sidewall SW6 of its adjacent sacrificial structure 105. In some embodiments, each gate electrode 113a and its adjacent gate dielectric 115a together form a gate structure G1 (also represented as a first gate structure) on the sidewall SW5 of the sacrificial structures 105, and each gate electrode 113b and its adjacent gate dielectric 115b together form a gate structure G2 (also represented as a second gate structure) on the sidewall SW6 of the sacrificial structures 105.

[0126] Furthermore, in some embodiments, each gate dielectric 115a of the gate structures G1 is physically connected to each gate dielectric 115b of the gate structures G2 via the connecting portions 115c. In some embodiments, the capacitor contacts 103 are covered by the connecting portions 115c. In some embodiments, the connecting portions 115c are disposed between and directly contact the dielectric strips 117' (e.g., the remaining dielectric layer 117) and the capacitor contacts 103. It should be understood that the dashed lines indicating the location of the connecting portions 115c are for clarity of this disclosure. There is no obvious interface between the connecting portions 115c and the gate dielectrics 115a, 115b.

[0127] Next, as Figures 13 to 15 As shown, according to some embodiments, a patterned mask 119 having a plurality of openings 120 is formed on Figure 11 and Figure 12 In terms of structure. In some embodiments, the openings 120 of the patterned mask 119 expose portions of the dielectric portions 117', which are clearly visible. Figure 14In other words, according to some embodiments, the dielectric strips 117', gate dielectrics 115a and 115b, gate electrodes 113a and 113b, and the sacrificial structures 105 can be covered by a patterned mask 119, which clearly shows Figure 15 .

[0128] Next, please refer to Figures 16 to 24 According to some embodiments, the portions of the dielectric strips 117' exposed by the patterned mask 1 are replaced by a plurality of channel structures 133. The corresponding steps are described in... Figure 5 Step S19 of preparation method 10 is shown. (As...) Figures 16 to 18 As shown, according to some embodiments, a patterned mask 119 is used as a mask to perform an etching process on the dielectric strips 117'. The etching process may be a wet etching process, a dry etching process, or a combination thereof.

[0129] In some embodiments, portions of the dielectric strips 117' exposed through the openings 120 of the patterned mask 119 are removed to form a plurality of openings 130, while portions of the dielectric strips 117' covered by the patterned mask 119 remain substantially unetched. In this disclosure, the term "substantially" means preferably at least 90%, more preferably 95%, even more preferably 98%, and most preferably 99%. Figure 18 As shown, according to some embodiments, the remaining dielectric strips 117' are also referred to as dielectric portions 117P. In some embodiments, the sidewalls of the dielectric portions 117P that are not covered by the gate structures G1, G2 are exposed through the openings 130.

[0130] Then, as Figures 19 to 21 As shown, according to some embodiments, an etching process is performed on the connections 115c to extend (e.g., deepen) the openings 130. The etching process may be a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the portions of the connections 115c exposed through the openings 130 are removed, while the portions of the connections 115c covered by the dielectric portions 117P remain substantially unetched.

[0131] Following the etching process, a plurality of openings 130' are obtained that expose the capacitor contacts 103. In some embodiments, portions of the upper surface 101T of the semiconductor substrate 101 and portions of the gate structures G1, G2 are exposed through the openings 130'. In some embodiments, the sidewalls of the remaining connection portions 115c are exposed through the openings 130'. After the capacitor contacts 103 are exposed through the openings 130', the patterned mask 119 can be removed.

[0132] like Figures 22 to 24 As shown, according to some embodiments, after the capacitor contacts 103 are exposed, the openings 130' are filled with a plurality of channel structures 133. In some embodiments, the channel structures 133 are staggered between the dielectric portions 117P, and the sidewalls of the channel structures 133 not covered by the gate structures G1, G2 directly contact the dielectric portions 117P. In some embodiments, the lower surfaces 133B of the channel structures 133 directly contact the capacitor contacts 103.

[0133] In some embodiments, the channel structures 133 comprise silicon, ITO, IZO, IGZO, other suitable materials, or combinations thereof. The fabrication technique for the channel structures 133 may include a deposition process followed by a planarization process. The deposition process may include CVD, PVD, ALD, PECVD, PEALD, spin coating, other suitable methods, or combinations thereof. The planarization process may include CMP.

[0134] Next, as Figures 25 to 27 As shown, according to some embodiments, the sacrificial structures 105 are removed. In some embodiments, the sacrificial structures 105 are removed by an etching process. The etching process may include a dry etching process, a wet etching process, or a combination thereof.

[0135] like Figures 28 to 30 As shown, according to some embodiments, after the sacrificial structures 105 are removed, a dielectric layer 143 is formed on the semiconductor substrate 101 and covers the gate structures G1, G2 and the channel structures 133, and a plurality of bit line contacts 145 are formed in the dielectric layer 143 and on the channel structures 133. The corresponding steps are described in... Figure 5 Step S21 in the preparation method 10 shown. Some materials and processes used to form dielectric layer 143 are similar to or the same as those used to form dielectric layer 117, and their detailed description will not be repeated here.

[0136] Furthermore, in some embodiments, the equibit line contact points 145 are formed to directly contact the upper surface 133T of the channel structure 133. In some embodiments, the equibit line contact points 145 comprise a conductive material, such as copper, tungsten, aluminum, titanium, tantalum, gold, or silver. A method for fabricating the equibit line contact points 145 may include forming a patterned mask (not shown) on the dielectric layer 143; using the patterned mask as a mask to etch the dielectric layer 143 to form a plurality of equibit line contact point openings (not shown); depositing a conductive material in the equibit line contact point openings and on the dielectric layer 143; and planarizing the conductive material until the upper surface of the dielectric layer 143 is exposed.

[0137] Then, as Figures 1 to 3 As shown, according to some embodiments, a dielectric layer 151 is formed on a dielectric layer 143, and a plurality of bit lines 153 are formed in the dielectric layer 143 and cover the bit line contact points 145. The corresponding steps are described in the following... Figure 5 Step S23 in the preparation method 10 shown. Some materials and processes used to form dielectric layer 151 are similar to or the same as those used to form dielectric layer 117, and their detailed descriptions will not be repeated herein.

[0138] In some embodiments, the equibit line 153 is electrically connected to the channel structure 133 via the equibit line contact point 145. The equibit line 153 may be a single layer or multiple layers. For example, each equibit line 153 includes a lower equibit line layer (not shown) and an upper equibit line layer (not shown). In some embodiments, the lower equibit line layer comprises doped polysilicon, metal, metal silicide, or metal compound, and the upper equibit line layer comprises one or more metals or metal compounds. The fabrication technique of the equibit line 153 may include a deposition process and a subsequent etching process. The deposition process may include CVD, ALD, PECVD, PEALD, other suitable methods, or combinations thereof. The etching process may include a dry etching process, a wet etching process, or a combination thereof.

[0139] Furthermore, according to some embodiments, a semiconductor substrate 201 including a plurality of capacitors 209 is bonded to the lower surface 101B of a semiconductor substrate 101, such that each capacitor 209 is electrically connected to a corresponding capacitor contact 103. The corresponding steps are described in... Figure 5 Step S25 of the fabrication method 10 shown. In some embodiments, the capacitors 209 are electrically connected to the channel structures 133 via the capacitor contacts 103.

[0140] In some embodiments, the capacitors 209 are metal-insulator-metal (MIM) capacitors. In some embodiments, each capacitor 209 includes two conductive layers 203 and 207 and a dielectric layer 205, with the dielectric layer 205 sandwiched between the conductive layers 203 and 207. In some embodiments, the conductive layers 207 comprise titanium nitride (TiN), the dielectric layers 206 comprise a dielectric material, such as SiO2, HfO2, Al2O3, ZrO2, or combinations thereof, and the conductive layers 203 comprise TiN, low-stress SiGe, or combinations thereof.

[0141] The fabrication techniques for the conductive layers 203, 207 and the dielectric layer 205 may include multiple deposition processes and multiple planarization processes. Deposition processes may include CVD, PVD, ALD, PECVD, PEALD, spin coating, other suitable methods, or combinations thereof. Planarization processes may include CMP. After the semiconductor substrate 201, including the capacitors 209, is bonded to the semiconductor substrate 101, a memory element 100a is obtained. In some embodiments, the memory element 100a is a portion of DRAM.

[0142] In memory element 100a, the channel structure 133 is vertically disposed between the capacitor contact 103 and the bit line contact 145 to electrically connect the capacitor 209 and the bit line 153, forming a plurality of vertical field-effect transistors (VFETs) in memory element 100a. By doing so, the surface area of ​​the semiconductor substrate 101 occupied by the elements of memory element 100a can be reduced. Therefore, the integration density of memory element 100a can be increased.

[0143] Figure 31 This is a cross-sectional schematic diagram illustrating different embodiments of this disclosure. Figure 9 The steps shown involve the partial removal of an intermediate stage of the gate dielectric layer 115. In these examples, an etching process is performed on the gate dielectric layer 115 to extend (e.g., deepen) the openings 110. The etching process may be a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the gate dielectric layer 115 is removed from portions covering the capacitor contacts 103.

[0144] Following the etching process, a plurality of openings 110' are obtained that expose the capacitor contacts 103. The manufacturing process for forming the memory element 100b can then proceed as follows: Figure 10 The following steps for forming memory element 100b may be similar to or identical to those for forming memory element 100a. It should be understood that since the capacitor contacts 103 are exposed before the dielectric layer 117 is formed, the gate dielectric layer 115 does not need to be etched after etching the dielectric portions 117P formed by etching the dielectric strips 117'. Therefore, compared to... Figure 3 The connection portions 115c of the memory element 100a shown have no gate dielectric layer sandwiched in place, such as Figure 4 The dielectric portions 117P in memory element 100b are between the semiconductor substrate 101 and the substrate. Furthermore, the top view and cross-sectional view of memory element 100b along section line A-A' are the same as those of memory element 100a (e.g., Figure 1 and Figure 2 ).

[0145] This disclosure provides some embodiments of a memory element and a method for fabricating the same. In some embodiments, the memory element (e.g., memory elements 100a and 100b) includes a channel structure (e.g., channel structure 133) disposed on a semiconductor substrate (e.g., a first semiconductor substrate 101) and covering a capacitor contact (e.g., capacitor contact 103) in the semiconductor substrate; and a bit line contact (e.g., bit line contact 145) disposed on the channel structure. In some embodiments, the memory element includes a first gate structure (e.g., gate structure G1) disposed on a first sidewall (e.g., sidewall SW1) of the channel structure; and a second gate structure (e.g., gate structure G2) disposed on a second sidewall (e.g., sidewall SW2) of the channel structure opposite to the first sidewall of the channel structure. The channel structure is electrically connected to a capacitor (e.g., capacitor 209) and a bit line (e.g., bit line 153) via the capacitor contact and the bit line contact. Because the channel structure provides a vertical electrical connection between the capacitor and the bit line, forming a vertical field-effect transistor (VFET) in the memory element, the surface area of ​​the semiconductor substrate occupied by the elements in the memory element can be reduced. Therefore, the integration density of the memory element can be increased.

[0146] One embodiment of this disclosure provides a memory element. The memory element includes a capacitor contact disposed in a first semiconductor substrate; and a channel structure disposed on an upper surface of the first semiconductor substrate. The memory element also includes a first gate structure disposed on a first sidewall of the channel structure; and a second gate structure disposed on a second sidewall of the channel structure. The second sidewall of the channel structure is disposed opposite to the first sidewall of the channel structure. The memory element further includes a bit line contact disposed on the channel structure. The channel structure is electrically connected to a capacitor and a bit line via the capacitor contact and the bit line contact.

[0147] Another embodiment of this disclosure provides a memory element. The memory element includes a first capacitor contact and a second capacitor contact disposed in a semiconductor substrate; a first channel structure and a second channel structure disposed on the semiconductor substrate and spaced apart from each other. The first channel structure is electrically connected to a first capacitor via the first capacitor contact, and the second channel structure is electrically connected to a second capacitor via the second capacitor contact. The memory element also includes a first gate structure disposed on a first sidewall of the first channel structure and a first sidewall of the second channel structure; and a second gate structure disposed on a second sidewall of the first channel structure and a second sidewall of the second channel structure. The first sidewall and the second sidewall of the first channel structure are disposed opposite to each other. The memory element also includes a first bit line contact and a second bit line contact disposed on the first channel structure and the second channel structure, respectively. The first channel structure is electrically connected to a first bit line via the first bit line contact point, and the second channel structure is electrically connected to a second bit line via the second bit line contact point.

[0148] Another embodiment of this disclosure provides a method for fabricating a memory element. The method includes forming a capacitor contact in a first semiconductor substrate; and forming a first sacrificial structure and a second sacrificial structure on an upper surface of the first semiconductor substrate and on opposite sides of the capacitor contact. The method also includes forming a first gate structure on a sidewall of the first sacrificial structure and forming a second gate structure on a sidewall of the second sacrificial structure facing the sidewall of the first sacrificial structure; and forming a dielectric strip between the first gate structure and the second gate structure. The method further includes replacing a first portion of the dielectric strip with a channel structure; forming a bit line contact on the channel structure; and forming a bit line on the bit line contact.

[0149] The embodiments disclosed herein have several advantageous features. By forming a vertical field-effect transistor (VFET) in the memory element, for example, forming a vertical electrical connection between a capacitor and a bit line, the surface area of ​​the semiconductor substrate occupied by the elements in the memory element can be reduced. Therefore, the integration density of the memory element can be increased.

[0150] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0151] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A memory element, comprising: A capacitor contact point is disposed in a first semiconductor substrate; A channel structure is disposed on an upper surface of the first semiconductor substrate; A first gate structure is disposed on a first sidewall of the channel structure; A second gate structure is disposed on a second sidewall of the channel structure, wherein the second sidewall of the channel structure is disposed opposite to the first sidewall of the channel structure; A bit line contact point is provided on the channel structure, wherein the channel structure is electrically connected to a capacitor and a bit line via the capacitor contact point and the bit line contact point. A first dielectric portion is disposed on the upper surface of the first semiconductor substrate and on a third sidewall of the channel structure; and A second dielectric portion is disposed on the upper surface of the first semiconductor substrate and on a fourth sidewall of the channel structure, wherein the third sidewall of the channel structure and the fourth sidewall of the channel structure are disposed opposite to each other.

2. The memory element of claim 1, wherein the capacitor contact directly contacts a lower surface of the channel structure, and the bit line contact directly contacts an upper surface of the channel structure.

3. The memory element of claim 1, wherein the channel structure is disposed between the bit line and the capacitor.

4. The memory element of claim 1, further comprising a second semiconductor substrate bonded to a lower surface of the first semiconductor substrate, wherein the capacitor is disposed in the second semiconductor substrate.

5. The memory element of claim 1, wherein the first gate structure includes a first gate electrode and a first gate dielectric, the gate dielectric being sandwiched between the first gate electrode and the channel structure, wherein the second gate structure includes a second gate electrode and a second gate dielectric, the second gate dielectric being sandwiched between the second gate electrode and the channel structure.

6. The memory element of claim 1, wherein the first gate structure and the second gate structure extend to cover each of the opposing sidewalls of the first dielectric portion and the second dielectric portion.

7. A memory element, comprising: A first capacitor contact and a second capacitor contact are disposed in a semiconductor substrate; A first channel structure and a second channel structure are disposed on the semiconductor substrate and separated from each other, wherein the first channel structure is electrically connected to a first capacitor via the first capacitor contact point, and the second channel structure is electrically connected to a second capacitor via the second capacitor contact point. A first gate structure is disposed on a first sidewall of the first channel structure and on a first sidewall of the second channel structure; A second gate structure is disposed on a second sidewall of the first channel structure and on a second sidewall of the second channel structure, wherein the first sidewall of the first channel structure and the second sidewall of the first channel structure are disposed opposite to each other, and the first sidewall of the second channel structure and the second sidewall of the second channel structure are disposed opposite to each other. A first bit line contact point and a second bit line contact point are respectively disposed on the first channel structure and the second channel structure, wherein the first channel structure is electrically connected to a first bit line through the first bit line contact point, and the second channel structure is electrically connected to a second bit line through the second bit line contact point. A first dielectric portion is disposed between the first channel structure and the second channel structure, and directly contacts the first channel structure and the second channel structure; and A second dielectric portion is disposed between the first gate structure and the second gate structure, wherein the first channel structure is disposed between the first dielectric portion and the second dielectric portion and directly contacts the first dielectric portion and the second dielectric portion.

8. The memory element of claim 7, wherein the first capacitor contact is disposed between the first channel structure and the first capacitor, and the second capacitor is disposed between the second channel structure and the second capacitor.

9. The memory element of claim 7, wherein the first channel structure directly contacts the first capacitor contact point and the first bit line contact point, and the second channel structure directly contacts the second capacitor contact point and the second bit line contact point.

10. The memory element of claim 7, wherein the first dielectric portion is disposed between the first gate structure and the second gate structure and directly contacts the first gate structure and the second gate structure.

11. The memory element of claim 7, wherein the first dielectric portion is separated from the semiconductor substrate.

12. A method for fabricating a memory element, comprising: A capacitor contact is formed in a first semiconductor substrate; A first sacrificial structure and a second sacrificial structure are formed on an upper surface of the first semiconductor substrate and on opposite sides of the capacitor contact point; A first gate structure is formed on one sidewall of the first sacrificial structure, and a second gate structure is formed on one sidewall of the second sacrificial structure facing the sidewall of the first sacrificial structure. A dielectric strip is formed between the first gate structure and the second gate structure; A first portion of the dielectric strip is replaced with a channel structure; A single-element line contact point is formed on this channel structure; as well as A bit line is formed at the contact point of the bit line; The first gate structure is located on the first sidewall of the channel structure, and the second gate structure is located on the second sidewall of the channel structure, wherein the second sidewall of the channel structure is disposed opposite to the first sidewall of the channel structure; a second portion of the dielectric strip is adjacent to the channel structure.

13. The method of fabricating a memory element as claimed in claim 12, further comprising bonding a second semiconductor substrate to a lower surface of the first semiconductor substrate, wherein a capacitor in the second semiconductor substrate is located via the channel structure of the capacitor contact point.

14. The method for fabricating a memory element as claimed in claim 12, further comprising removing the first sacrificial structure and the second sacrificial structure after the channel structure is formed.

15. The method of fabricating a memory element as claimed in claim 12, wherein the sidewalls of the channel structure not covered by the first gate structure and the second gate structure directly contact the second portion of the dielectric strip.

16. The method for fabricating a memory element as claimed in claim 12, wherein forming the first gate structure and the second gate structure further comprises: A first gate electrode is formed on the sidewall of the first sacrificial structure and a second gate electrode is formed on the sidewall of the second sacrificial structure; as well as A first gate dielectric is formed on one sidewall of the first gate electrode and a second gate dielectric is formed on one sidewall of the second gate electrode, wherein the first gate dielectric and the second gate dielectric are physically connected by a connection portion covering the capacitor contact point.

17. The method of fabricating a memory element as claimed in claim 16, wherein prior to the formation of the channel structure, the connection portion is partially etched to expose the capacitor contact point.

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