A method of forming a semiconductor structure
By doping P-type ions into the floating gate layer of the logic region of embedded flash memory and adjusting the etching rate, the "side-cutting" problem during the etching of the floating gate layer was solved, improving the yield of embedded flash memory and simplifying the process flow.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2021-07-26
- Publication Date
- 2026-07-21
AI Technical Summary
In embedded flash memory, the "side-cutting" phenomenon is prone to occur during the etching of the floating gate layer, which leads to over-etching or residual oxide layers in the floating gate layer and floating gate dielectric layer, affecting the yield of flash memory and SRAM areas.
After the floating gate layer is formed, the logic region is doped with P-type ions, the etching rate is adjusted, and isolation trenches are formed by dry etching to avoid the "side-cutting" phenomenon.
It effectively alleviates the "side-cutting" phenomenon of the floating gate layer in the logic area during the etching process, improves the yield of flash memory and SRAM areas, simplifies the process flow and reduces manufacturing costs.
Smart Images
Figure CN115696927B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor devices and integrated circuits, and in particular to a method for forming a semiconductor structure. Background Technology
[0002] Embedded flash memory is a special type of memory that integrates flash memory into logic devices to achieve storage functionality. It is widely used due to its advantages such as low power consumption, low cost, high density, and high reliability. However, its manufacturing process is also very complex and unique, as it requires balancing the yield rates of both the Flash and SRAM areas. The yield rates of the two are not positively correlated; sometimes adjusting a certain process condition can cause one to degrade in performance while the other improves, significantly increasing the overall project difficulty.
[0003] Because the Flash region requires a floating gate (FG), a layer of gate material (poly) needs to be deposited before etching the active area (AA). During etching, the FG poly undergoes a "side-cutting" phenomenon, resulting in the FG poly being narrower than the AA. Subsequent processes will form an oxide layer (OX) at the side-cutting location, which is difficult to remove. If over-etching is performed when removing the FG poly in the SRAM region, it will damage the AA in the Flash region, reducing the Flash yield. If only a small amount of etching is performed, OX will remain, reducing the SRAM yield. Summary of the Invention
[0004] The technical problem this application aims to solve is the "side-cutting" phenomenon in the logic area of embedded flash memory.
[0005] To address the aforementioned technical problems, this application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, the semiconductor substrate including a first region and a second region, wherein the surfaces of the semiconductor substrates in the first region and the second region sequentially include a floating gate dielectric layer and a floating gate layer; doping P-type ions in the floating gate layer on the semiconductor substrate in the second region to form a doped floating gate layer; and sequentially etching the floating gate layer, the floating gate dielectric layer and a portion of the semiconductor substrate in the first region, as well as the doped floating gate layer, the floating gate dielectric layer and a portion of the semiconductor substrate in the second region to form an isolation trench.
[0006] In this embodiment of the application, the process of doping P-type ions includes: forming a doping barrier layer on the surface of the floating gate layer in the first region; using the doping barrier layer as a mask, doping the P-type ions in the floating gate layer in the second region; and removing the doping barrier layer.
[0007] In this embodiment, the doping concentration of the P-type ions is 1E14 ions / cm³. 3 ~1E16 pieces / cm3 In the embodiments of this application, the P-type ions are doped using an ion implantation process or a diffusion process, wherein the implantation energy of the ion implantation process is 1keV to 5keV, and the temperature of the diffusion process is 20℃ to 30℃.
[0008] In this embodiment of the application, the doping barrier layer includes a negative photoresist layer, and the formation process of the negative photoresist layer includes: spin-coating negative photoresist on the surface of the floating gate layer in the first region and the second region; and by exposure and development, retaining only the negative photoresist on the surface of the floating gate layer in the first region to form a negative photoresist layer.
[0009] In this embodiment, the same photomask is used for exposure and development as well as for forming the source / drain structure of the second region.
[0010] In this embodiment, the width of the opening formed by etching the doped floating gate layer is equal to or greater than the width of the top opening of the isolation trench, and the width difference is 0 to 16 nm.
[0011] In this embodiment of the application, a dry etching process is used to sequentially etch the floating gate layer, the floating gate dielectric layer and a portion of the semiconductor substrate in the first region, and the doped floating gate layer, the floating gate dielectric layer and a portion of the semiconductor substrate in the second region, and the etching rate ratio of the doped floating gate layer to the semiconductor substrate in the dry etching process is 1:(4-6).
[0012] In this embodiment, the dry etching process includes: sequentially forming an etching auxiliary layer and a mask layer on the surfaces of the floating gate layer and the doped floating gate layer, wherein the mask layer includes a pattern for defining isolation trenches for the first region and the second region; sequentially etching the etching auxiliary layer, the floating gate layer, the doped floating gate layer, the floating gate dielectric layer and the semiconductor substrate, respectively forming isolation trenches in the semiconductor substrates of the first region and the second region; and removing the etching auxiliary layer and the mask layer.
[0013] In this embodiment, the etching auxiliary layer sequentially includes a stress adjustment layer and an etching barrier layer.
[0014] In this embodiment, the stress-adjusting layer is made of TEOS, and the etching barrier layer comprises a silicon nitride layer and / or an amorphous carbon layer.
[0015] In this embodiment, the mask layer includes a photoresist layer, and the etching aid layer further includes an anti-reflection layer located on the surface of the etching barrier layer.
[0016] In this embodiment of the application, the first region is a flash memory region, and the second region is a logical region.
[0017] In this embodiment, the thickness of the floating gate layer and the doped floating gate layer is 500 angstroms to 600 angstroms.
[0018] The technical solution of this application can effectively alleviate the "side-cutting" phenomenon of the floating gate layer in the second region when etching to form isolation trenches by adding a P-type ion doping process to the floating gate layer in the second region after the floating gate layer in the first region and the second region are formed. Attached Figure Description
[0019] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:
[0020] Figure 1 and Figure 2 This is a schematic diagram of a method for forming embedded flash memory;
[0021] Figure 3 This is a schematic flowchart illustrating the method for forming the semiconductor structure according to the technical solution of this application.
[0022] Figures 4 to 8 This is a schematic diagram of each step in the method for forming a semiconductor structure according to an embodiment of this application. Detailed Implementation
[0023] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.
[0024] refer to Figure 1 A method for forming embedded flash memory involves forming a floating gate dielectric layer 20 and a floating gate layer 30 on the surface of a semiconductor substrate 10 for the flash memory region and the logic region. Figure 1Only the semiconductor substrate 10 of the logic region is shown. Next, isolation trenches 40 need to be formed in the semiconductor substrate. The floating gate layer 30, the floating gate dielectric layer 20 and the semiconductor substrate 10 are etched sequentially. Since the etching rate of the floating gate layer 30 and the floating gate dielectric layer 20 is greater than the etching rate of the semiconductor substrate 10, a "side-cutting" phenomenon occurs at position A, that is, the floating gate layer 30 and the floating gate dielectric layer 20 are over-etched, exposing part of the surface of the semiconductor substrate 10.
[0025] refer to Figure 2 After the isolation trench 40 is formed, insulating material 41 is filled into the isolation trench 40. At the same time, insulating material is also deposited at the "side cut" position, which is not easy to remove. When removing the floating gate layer 30 and floating gate dielectric layer 20 of the logic area, if over-etching is performed, the semiconductor substrate of the flash memory area will be damaged, reducing the yield of the flash memory area; if the etching is insufficient, insulating material will remain at position B, reducing the yield of the logic area.
[0026] Based on the above problems, the technical solution of this application adds a P-type ion doping process to the floating gate layer of the logic region after the floating gate layer is formed, thereby reducing the etching rate of the floating gate layer of the logic region, while the etching rate of the semiconductor substrate remains unchanged. Therefore, when etching to form isolation trenches of the same size, the "side-cutting" phenomenon of the floating gate layer of the logic region will be significantly improved.
[0027] refer to Figure 3 This application provides a method for forming a semiconductor structure, comprising:
[0028] Step S1: Provide a semiconductor substrate, the semiconductor substrate including a first region and a second region, and the surfaces of the semiconductor substrate in the first region and the second region sequentially include a floating gate dielectric layer and a floating gate layer;
[0029] Step S2: Doping P-type ions into the floating gate layer on the semiconductor substrate in the second region to form a doped floating gate layer;
[0030] Step S3: Sequentially etch the floating gate layer, floating gate dielectric layer and part of the semiconductor substrate in the first region, and the doped floating gate layer, floating gate dielectric layer and part of the semiconductor substrate in the second region to form an isolation trench.
[0031] The method for forming the semiconductor structure of the present application will be described in detail below with reference to specific embodiments and accompanying drawings.
[0032] refer to Figure 3 and Figure 4A semiconductor substrate 100 is provided. The material of the semiconductor substrate 100 may include (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide; or (iv) a combination of the above. The semiconductor substrate 100 includes a first region 110 and a second region 120, which are used to fabricate devices with different functions. For example, the first region 110 may be a flash memory region, and the second region 120 may be a logic region (SRAM region).
[0033] The surfaces of the semiconductor substrate 100 in the first region 110 and the second region 120 sequentially include a floating gate dielectric layer 200 and a floating gate layer 310. The material of the floating gate dielectric layer 200 may include silicon dioxide, for example, and the material of the floating gate layer 310 may include polysilicon, for example. The thickness of the floating gate dielectric layer 200 may be 90 angstroms to 100 angstroms, and the thickness of the floating gate layer 310 may be 500 angstroms to 600 angstroms. The floating gate dielectric layer 200 and the floating gate layer 310 may be formed by chemical vapor deposition, atomic layer deposition, or the like.
[0034] In existing processes, after forming the floating gate dielectric layer 200 and the floating gate layer 310, an isolation trench is directly formed by etching the floating gate dielectric layer 200, the floating gate layer 310, and the semiconductor substrate. However, in this embodiment, before forming the isolation trench, the floating gate layer 310 of the second region 120 is pre-treated to change its properties, transforming it into a doped floating gate layer, thereby indirectly altering the relative etching rate between the floating gate layer and the semiconductor substrate in the second region.
[0035] refer to Figure 4 A doping barrier layer 400 is formed on the surface of the floating gate layer 310 in the first region 110. The doping barrier layer 400 can be any type of mask, as long as it can cover the floating gate layer 310 in the first region 110 and prevent accidental doping of the floating gate layer 310 in the first region during subsequent doping processes of the floating gate layer in the second region 120. The doping barrier layer 400 can be, for example, a hard mask or photoresist.
[0036] In this embodiment, the doping barrier layer 400 includes a negative photoresist layer. This is because existing processes design a photomask using a positive photoresist layer when forming the source / drain structure of the second region 120, leaving the first region 110 unmasked after exposure and development. By using a negative photoresist layer as the doping barrier layer 400, this application can utilize the same photomask as the source / drain structure of the second region 120. Using an existing photomask for exposure and development eliminates the need for photomask design, simplifies the process, and reduces manufacturing costs.
[0037] The formation process of the negative photoresist layer 400 may include: spin-coating negative photoresist onto the surfaces of the floating gate layer 310 in the first region 110 and the second region 120; and, through exposure and development, retaining only the negative photoresist on the surface of the floating gate layer 310 in the first region 110 to form the negative photoresist layer 400. The negative photoresist can be any existing negative photoresist.
[0038] refer to Figure 5 Using the doped barrier layer 400 as a mask, P-type ions are doped into the floating gate layer 310 of the second region 120. These P-type ions can be any type of P-type impurity ion, such as boron ions or indium ions. The doping concentration of the P-type ions is crucial and significantly affects the etching rate of the floating gate layer 310. Higher P-type ion concentrations result in slower etching rates, but the concentration cannot be increased indefinitely. Excessively high P-type ion concentrations will affect the etching process and increase device fabrication costs. In this embodiment, the P-type ion doping concentration is 1E14 ions / cm³. 3 ~1E16 pieces / cm 3 This allows for a balance between adjusting the etching rate and manufacturing costs.
[0039] Besides the doping concentration of P-type ions, strict control of the doping process is also required to achieve the desired doping depth. In some embodiments, ion implantation is used for P-type ion doping, with an implantation energy of 1 keV to 5 keV. In other embodiments, diffusion is used for P-type ion doping at a temperature of 20°C to 30°C.
[0040] In this embodiment, the p-type ions are doped into the floating gate layer 310 of the second region 120 to form a doped floating gate layer 320. The thickness of the doped floating gate layer 320 can be the same as that of the floating gate layer 310, or it can be slightly different. When the thickness of the doped floating gate layer 320 and the floating gate layer 310 can be the same, the effect of improving the "side-hole" phenomenon is the best. The thickness of the doped floating gate layer 320 can be 500 angstroms to 600 angstroms.
[0041] After doping with the P-type ions, the doped barrier layer 400 is removed. The removal method may include wet cleaning after ashing, ensuring that the surfaces of the floating gate layer 310 and the doped floating gate layer 320 are clean; this will not be described in detail here.
[0042] refer to Figures 6 to 8 The floating gate layer 310, the floating gate dielectric layer 200 and a portion of the semiconductor substrate 100 in the first region 110, and the doped floating gate layer 320, the floating gate dielectric layer 200 and a portion of the semiconductor substrate 100 in the second region 120 are etched sequentially to form an isolation trench 400.
[0043] Continue to refer to Figure 6An etching aid layer 400 and a mask layer 500 are sequentially formed on the surfaces of the floating gate layer 310 and the doped floating gate layer 320, wherein the mask layer 500 includes a pattern of isolation trenches 400 for defining the first region 110 and the second region 120. The etching aid layer 400 can be a single-layer structure or a stacked structure. In this embodiment, the etching aid layer 400 sequentially includes a stress adjustment layer 410 and an etching barrier layer. The material of the stress adjustment layer 410 may include TEOS, and the etching barrier layer can be a single-layer structure or a stacked structure. The etching barrier layer may include a silicon nitride layer and / or an amorphous carbon layer. In this embodiment, the etching barrier layer includes a silicon nitride layer 420 and an amorphous carbon layer 430. When etching to form isolation trenches, a relatively thick etching barrier layer is required. Therefore, if only a mask layer 500 (such as photoresist) is formed on the surface of the floating gate layer 310 and the doped floating gate layer 320 as an etching barrier layer, insufficient development and collapse may occur due to the excessive thickness of the mask layer. If an etching auxiliary layer 400 and a mask layer 500 are formed on the surface of the floating gate layer 310 and the doped floating gate layer 320, and the etching auxiliary layer 400 only includes a silicon nitride layer 420, the subsequent process needs to be readjusted due to the relatively thick thickness of the silicon nitride layer 420 (the remaining thickness of the silicon nitride layer after etching needs to meet the requirements). If the etching auxiliary layer 400 includes both a silicon nitride layer 420 and an amorphous carbon layer 430, the silicon nitride layer 420 will not be too thick, and the subsequent process does not need to be readjusted. At the same time, the growth process of the amorphous carbon layer 430 is simple and convenient, and it is easy to remove without adversely affecting the subsequent process. The process for forming the etching auxiliary layer 400 and the mask layer 500 can be chemical vapor deposition, atomic layer deposition, etc.
[0044] In this embodiment, the mask layer 500 includes a photoresist layer, and the etching aid layer 400 further includes an anti-reflection layer 440 located on the surface of the etching barrier layer. In other embodiments, the mask layer 500 may also be a hard mask layer.
[0045] refer to Figure 7 The etching auxiliary layer 400, floating gate layer 310, doped floating gate layer 320, and floating gate dielectric layer 200 are etched sequentially to expose the location of the isolation trench 400. In current processes, because the etching rates of the floating gate layer in the second region and the semiconductor substrate are similar, continuing to etch the semiconductor substrate will also damage the floating gate layer in the second region, resulting in a "side-cutting" phenomenon at position C. However, in this embodiment, the floating gate layer 310 in the second region 120 is pre-treated, which can effectively avoid the occurrence of the "side-cutting" phenomenon.
[0046] refer to Figure 8The semiconductor substrate 100 is etched further to form isolation trenches 400 in the first region 110 and the second region 120, respectively. Since the floating gate layer 310 in the second region 120 is pre-treated as a doped floating gate layer 320, further etching of the semiconductor substrate 100 will not significantly affect the doped floating gate layer 320. In contrast, the "side-cutting" phenomenon in the first region 110 is more pronounced. However, the first region 110 undergoes several subsequent processes, resulting in a lower STI height in the first region 110, thus avoiding the phenomenon seen in other regions. Figure 2 As shown, this will not affect the yield of the first region 110.
[0047] The floating gate layer 310, the floating gate dielectric layer 200 and a portion of the semiconductor substrate 100 in the first region 110, and the doped floating gate layer 320, the floating gate dielectric layer 200 and a portion of the semiconductor substrate 100 in the second region 120 are etched sequentially using a dry etching process, and the etching rate ratio of the doped floating gate layer 320 to the semiconductor substrate 100 in the dry etching process is 1:(4-6).
[0048] Finally, the etching auxiliary layer 400 and the mask layer 500 can be removed by an ashing process and wet cleaning.
[0049] The width of the opening formed by finally etching the doped floating gate layer 320 is equal to or greater than the width of the top opening of the isolation trench 400, and the width difference is 0 to 16 nm.
[0050] Therefore, the semiconductor structure formation method of this application embodiment can effectively avoid the "side-penetration" phenomenon of the logic area in embedded flash memory, and achieve simultaneous improvement in the yield of the flash memory area and the logic area. Furthermore, the semiconductor structure formation method of this application embodiment can be applied not only to the fabrication of embedded flash memory, but also to the fabrication of special memories such as NVM.
[0051] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.
[0052] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.
[0053] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," when used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.
[0054] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.
[0055] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including a first region and a second region, and the surfaces of the semiconductor substrate in the first region and the second region are sequentially including a floating gate dielectric layer and a floating gate layer; P-type ions are doped only in the floating gate layer on the semiconductor substrate in the second region to form a doped floating gate layer, wherein the doping concentration of the P-type ions is 1E14 ions / cm³. 3 ~1E16 pieces / cm 3 ; The floating gate layer, floating gate dielectric layer and part of the semiconductor substrate in the first region and the doped floating gate layer, floating gate dielectric layer and part of the semiconductor substrate in the second region are etched sequentially to form an isolation trench.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, The process of doping p-type ions includes: A doped barrier layer is formed on the surface of the floating gate layer in the first region; Using the doped barrier layer as a mask, the P-type ions are doped into the floating gate layer in the second region; Remove the doped barrier layer.
3. The method for forming a semiconductor structure according to claim 2, characterized in that, The P-type ions are doped using ion implantation or diffusion processes, wherein the implantation energy of the ion implantation process is 1 keV to 5 keV, and the temperature of the diffusion process is 20℃ to 30℃.
4. The method for forming a semiconductor structure according to claim 2, characterized in that, The doped barrier layer includes a negative photoresist layer, and the formation process of the negative photoresist layer includes: Negative photoresist is spin-coated onto the surfaces of the floating gate layers in the first and second regions; By exposure and development, only the negative photoresist on the surface of the floating gate layer in the first region is retained to form a negative photoresist layer.
5. The method for forming a semiconductor structure according to claim 4, characterized in that, The same photomask is used for exposure and development as well as for forming the source / drain structure of the second region.
6. The method for forming a semiconductor structure according to claim 1, characterized in that, The width of the opening formed by etching the doped floating gate layer is equal to or greater than the width of the top opening of the isolation trench, and the width difference is 0~16nm.
7. The method for forming a semiconductor structure according to claim 1, characterized in that, The floating gate layer, floating gate dielectric layer and part of the semiconductor substrate in the first region and the doped floating gate layer, floating gate dielectric layer and part of the semiconductor substrate in the second region are sequentially etched using a dry etching process, and the etching rate ratio of the doped floating gate layer to the semiconductor substrate in the dry etching process is 1:(4~6).
8. The method for forming a semiconductor structure according to claim 7, characterized in that, The dry etching process includes: An etching aid layer and a mask layer are sequentially formed on the surfaces of the floating gate layer and the doped floating gate layer, wherein the mask layer includes a pattern for defining isolation trenches for the first region and the second region; The etching auxiliary layer, floating gate layer, doped floating gate layer, floating gate dielectric layer and semiconductor substrate are etched sequentially to form isolation trenches in the semiconductor substrates of the first region and the second region, respectively. Remove the etching auxiliary layer and the mask layer.
9. The method for forming a semiconductor structure according to claim 8, characterized in that, The etching auxiliary layer comprises, in sequence, a stress-adjusting layer and an etching barrier layer.
10. The method for forming a semiconductor structure according to claim 9, characterized in that, The stress-adjusting layer is made of TEOS, and the etching barrier layer comprises a silicon nitride layer and / or an amorphous carbon layer.
11. The method for forming a semiconductor structure according to claim 9, characterized in that, The mask layer includes a photoresist layer, and the etching aid layer further includes an anti-reflection layer located on the surface of the etching barrier layer.
12. The method for forming a semiconductor structure according to claim 1, characterized in that, The first area is a flash memory area, and the second area is a logical area.
13. The method for forming a semiconductor structure according to claim 1, characterized in that, The thickness of the floating gate layer and the doped floating gate layer is 500 angstroms to 600 angstroms.