Display panel

Abstract

This invention provides a display panel including an active layer, a first scan line, and a variable signal line. The first scan line extends along a first direction and overlaps with a first channel portion and a second channel portion disposed opposite to each other in the active layer. The variable signal line includes interconnected trace portions and overlapping portions. The overlapping portions are located on the side of the trace portions near the first electrical connection portion, and the overlapping portions at least partially overlap with the first electrical connection portion in the active layer connecting the first channel portion and the second channel portion to form a coupling capacitor. This allows for the improvement of low-frequency flicker problems when the display panel is driven at low frequencies by utilizing the variable signal transmitted through the variable signal line and the coupling capacitor.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a display panel. Background Technology

[0002] In existing display panels, LTPO (Low Temperature Polycrystalline Oxide) backplanes and LTPS (Low Temperature Poly-silicon) backplanes are commonly used. However, the leakage current of transistors in LTPS backplanes is relatively large, which will cause changes in the driving current flowing through the light-emitting devices, resulting in flickering problems in the display panel when driven at low frequencies. On the other hand, the structure and manufacturing process of LTPO backplanes are more complex, and the manufacturing cost is also higher. Summary of the Invention

[0003] This invention provides a display panel that can improve the problem of low-frequency drive flickering in display panels.

[0004] This invention provides a display panel including an active layer, a first scan line, and a variable signal line. The active layer includes a first channel portion and a second channel portion disposed opposite to each other, and a first electrical connection portion connecting the first channel portion and the second channel portion; the first scan line extends along a first direction and overlaps with the first channel portion and the second channel portion; the variable signal line includes a trace portion and an overlapping portion connected to each other, the overlapping portion being located on the side of the trace portion closer to the first electrical connection portion, and the overlapping portion at least partially overlaps with the first electrical connection portion.

[0005] This invention provides a display panel including an active layer, a first scan line, and a variable signal line. The first scan line extends along a first direction and overlaps with a first channel portion and a second channel portion disposed opposite to each other in the active layer. The variable signal line includes interconnected trace portions and overlapping portions. The overlapping portions are located on the side of the trace portions near the first electrical connection portion, and the overlapping portions at least partially overlap with the first electrical connection portion in the active layer connecting the first channel portion and the second channel portion to form a coupling capacitor. This allows for the improvement of low-frequency flicker problems when the display panel is driven at low frequencies by utilizing the variable signal transmitted through the variable signal line and the coupling capacitor. Attached Figure Description

[0006] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0007] Figure 1AThis is a schematic diagram of a structure where a variable signal line overlaps with an active layer;

[0008] Figure 1B yes Figure 1A A sectional view cut along p-p';

[0009] Figure 1C yes Figure 1A A sectional view cut along z-z'.

[0010] Figures 2A-2B This is a schematic diagram showing the connection between the first gating driving circuit and the sub-pixel provided in an embodiment of the present invention;

[0011] Figure 3 This is a schematic diagram of the sub-pixel structure provided in an embodiment of the present invention;

[0012] Figure 4 This is a timing diagram provided in an embodiment of the present invention;

[0013] Figure 5 This is a schematic diagram of display brightness changes provided in an embodiment of the present invention;

[0014] Figure 6 This is a schematic diagram of the film structure of a sub-pixel provided in an embodiment of the present invention;

[0015] Figure 7 This is a schematic diagram of the active layer structure provided in an embodiment of the present invention;

[0016] Figure 8 This is a schematic diagram of the structure of the first conductive layer provided in an embodiment of the present invention;

[0017] Figure 9 This is a schematic diagram of the structure of the second conductive layer provided in an embodiment of the present invention;

[0018] Figure 10 This is a schematic diagram of the structure of the third conductive layer provided in an embodiment of the present invention;

[0019] Figure 11 This is a schematic diagram of the structure of the fourth conductive layer provided in an embodiment of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention. In the present invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0021] Specifically, Figure 1A This is a schematic diagram of a structure where a variable signal line overlaps with an active layer. Figure 1B yes Figure 1A A sectional view cut along p-p'. Figure 1C yes Figure 1A A cross-sectional view taken along z-z'. This application provides a display panel including a substrate 100, an active layer 101, a first scan line SL1, and a variable signal line EML1.

[0022] The substrate 100 includes a rigid substrate and a flexible substrate. Optionally, the substrate 100 includes glass, polyimide, quartz, etc. Optionally, a buffer layer 100a is also provided on the substrate 100.

[0023] The active layer 101 is located on the substrate 100. Optionally, the active layer 101 comprises a silicon semiconductor material or an oxide semiconductor material. Optionally, the silicon semiconductor material includes single-crystal silicon, polycrystalline silicon, etc.; the oxide semiconductor material may include indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), or indium gallium zinc tin oxide (IGZTO), etc. Optionally, the active layer 101 is fabricated using a low-temperature polycrystalline silicon process.

[0024] The active layer 101 includes a first channel portion CP1 and a second channel portion CP2 disposed opposite to each other, and a first electrical connection portion Cn1 connected between the first channel portion CP1 and the second channel portion CP2.

[0025] The first scan line SL1 extends along the first direction x and overlaps with the first channel portion CP1 and the second channel portion CP2.

[0026] The variable signal line EML1 includes interconnected trace portion EML11 and overlapping portion EML12. The overlapping portion EML12 is located on the side of the trace portion EML11 close to the first electrical connection portion Cn1, and the overlapping portion EML12 at least partially overlaps with the first electrical connection portion Cn1, so that the overlapping portion EML12 and the first electrical connection portion Cn1 form the two electrodes of the coupling capacitor Co, so as to improve the low-frequency flicker problem by utilizing the coupling capacitor Co and the variable signal EM1 transmitted by the variable signal line EML1.

[0027] Optionally, when the display panel adopts a high-resolution design, due to space constraints, the overlap area between the variable signal line EML1 and the first electrical connection Cn1 can be greater than 0 micrometers * micrometers and less than or equal to 100 micrometers * micrometers.

[0028] Alternatively, please continue reading Figure 1A The wiring section EML11 includes a first sub-section EML11a, a second sub-section EML11b, and a third sub-section EML11c. The first sub-section EML11a and the first electrical connection section Cn1 are spaced apart. The second sub-section EML11b and the third sub-section EML11c are respectively connected to both ends of the first sub-section EML11a. The extension line between the second sub-section EML11b and the third sub-section EML11c overlaps with the first electrical connection section Cn1. The distance between the second sub-section EML11b and the second end of the first electrical connection section Cn1 is less than the distance between the third sub-section EML11c and the second end of the first electrical connection section Cn1. The overlapping section EML12 is connected to the portion of the first sub-section EML11a closest to the second sub-section EML11b, so that when the required coupling capacitor Co is small, only the overlapping section EML12 and the first electrical connection section Cn1 overlap.

[0029] Optionally, the overlapping portion EML12 protrudes toward the first scan line SL1 relative to the second sub-portion EML11b, and the first scan line SL1 has a recess corresponding to the overlapping portion EML12, so that there is no overlap between the first scan line SL1 and the overlapping portion EML12.

[0030] Alternatively, please continue reading Figures 1B-1CThe variable signal line EML1 is located on or below the active layer 101. Optionally, the display panel further includes a first conductive layer 102 located on the active layer 101, the first conductive layer 102 including the variable signal line EML1. Optionally, the first conductive layer 102 includes at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). Optionally, the first conductive layer 102 can be a single-layer film structure, or a stacked structure such as Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Cu / Mo, Cu / Ti, Cu / MoTi, or Cu / MoNb.

[0031] Optionally, the display panel further includes an insulating layer located between the first conductive layer 102 and the active layer 101. Optionally, the insulating layer includes a first insulating layer 1001 and a second insulating layer 1002. Optionally, the first insulating layer 1001 and the second insulating layer 1002 may respectively include silicon compounds, metal oxides, etc. Further, the first insulating layer 1001 and the second insulating layer 1002 may respectively include silicon oxide, silicon nitride, silicon nitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.

[0032] Figures 1B-1C 100b in the text refers to a multilayer composite insulating layer (i.e., including an interlayer dielectric layer, a first planarization layer, a second planarization layer, and a pixel definition layer, etc.).

[0033] like Figures 2A-2B This is a schematic diagram showing the connection between the first gating driving circuit and the sub-pixel provided in an embodiment of the present invention. The display panel also includes multiple signal lines and multiple sub-pixels.

[0034] Optionally, the multiple signal lines include multiple scan lines, multiple data lines DL, multiple light emission control lines EML, multiple reset lines, and multiple variable signal lines EML1.

[0035] Multiple scan lines are used to transmit multiple scan signals. These scan lines include multiple first scan lines SL1, multiple second scan lines SL22, multiple third scan lines SL21, and multiple fourth scan lines SL23. The first scan line SL1 transmits the first scan signal S1, while the second scan lines SL22, third scan lines SL21, and fourth scan lines SL23 all transmit the second scan signal S2. Among the third scan lines SL21, second scan lines SL22, and fourth scan lines SL23, which are electrically connected to the same pixel driving circuit, the second scan signal transmitted by the second scan line SL22 is valid before the second scan signal transmitted by the third scan line SL21. The second scan signal transmitted by the fourth scan line SL23 is the same as the second scan signal transmitted by the second scan line SL22 or the second scan signal transmitted by the third scan line SL21.

[0036] The data line DL is used to transmit data signals; the light control line EML is used to transmit the light control signal EM; the reset lines include a first reset line VL1 and a second reset line VL2. The first reset line VL1 is used to transmit a first reset signal, and the second reset line VL2 is used to transmit a second reset signal. The first reset signal and the second reset signal may be equal or unequal. The variable signal line EML1 is used to transmit the variable signal EM1.

[0037] Optionally, the frequency of the first scan signal S1 is lower than the frequency of the second scan signal S2. Optionally, the effective pulse of the first scan signal S1 is located within the write frame WF of a display cycle, and the effective pulse of the second scan signal S2 is located within the write frame WF and the hold frame HF of a display cycle. Wherein, when a display cycle includes the hold frame HF, the display panel employs a low refresh rate driving method.

[0038] Optionally, multiple sub-pixels located in the same row are electrically connected to the same variable signal line EML1, so that all sub-pixels located in the same row are under the action of the same variable signal EM1, thereby improving the flicker problem.

[0039] Optionally, the display panel further includes multiple gating drive circuits, which include at least one first gating drive circuit EMG1, multiple cascaded second gating drive circuits, multiple cascaded third gating drive circuits, and multiple cascaded fourth gating drive circuits EMG2.

[0040] Optionally, the display panel includes a first gating drive circuit EMG1, and multiple variable signal lines EML1 are electrically connected to the first gating drive circuit EMG1. The first gating drive circuit EMG1 is configured to output variable signals EM1 to the multiple variable signal lines EM1, such as... Figure 2A As shown, this is to ensure that multiple sub-pixels arranged in the array are all under the same variable signal EM1, thereby improving the flickering problem.

[0041] Optionally, the display panel includes multiple cascaded first gating drive circuits EMG1, each first gating drive circuit EMG1 being electrically connected to two variable signal lines EML1, and each first gating drive circuit EMG1 being configured to output a variable signal EM1 to the two variable signal lines EM1, such as... Figure 2B As shown, this is to improve the flickering problem by having multiple sub-pixels located in two rows be subjected to the same variable signal EM1.

[0042] Among them, such as Figure 2A The design of the first gating drive circuit EMG1 shown outputting the variable signal EM1 to multiple variable signal lines EM1 is beneficial for achieving a narrow bezel design for the display panel; for example... Figure 2B The design of the first gating drive circuit EMG1 shown outputs the variable signal EM1 to two variable signal lines EM1. The design requirements for the drive chip are not high, and it is easy to implement control.

[0043] Optionally, the variable signal line EML1 can also be electrically connected to the driver chip to provide a variable signal through the driver chip.

[0044] Multiple cascaded second gating drive circuits are electrically connected to multiple first scan lines SL1 to provide multiple first scan signals S1 to the multiple first scan lines SL1; multiple cascaded third gating drive circuits are electrically connected to multiple second scan lines SL22, multiple third scan lines SL21 and multiple fourth scan lines SL23 to provide multiple second scan signals S2 to the multiple second scan lines SL22, multiple third scan lines SL21 and multiple fourth scan lines SL23; multiple cascaded fourth gating drive circuits EMG2 are electrically connected to multiple light emission control lines EML to provide multiple light emission control signals to the multiple light emission control lines EML.

[0045] Optionally, the topology of the fourth gating drive circuit EMG2 is the same as that of the first gating drive circuit EMG1, so as to use the existing design and thus save design costs.

[0046] Optionally, the positions of multiple cascaded fourth gating drive circuits EMG2 and multiple cascaded first gating drive circuits EMG1 are symmetrical about the central axis of the display area of ​​the display panel, so as to facilitate wiring and reduce the bezel of the display panel.

[0047] like Figure 3 This is a schematic diagram of the sub-pixel structure provided in an embodiment of the present invention. Figure 4This is a timing diagram provided in an embodiment of the present invention. Each sub-pixel includes a light-emitting device D and a pixel driving circuit. Each sub-pixel is electrically connected to a corresponding scan line, a corresponding data line DL, and a corresponding light-emitting control line EML, so that the pixel driving circuit controls the corresponding light-emitting device D to emit light according to the corresponding scan signal, data signal, and light-emitting control signal EM. Optionally, the light-emitting device D includes an organic light-emitting diode, a sub-millimeter light-emitting diode, a micro light-emitting diode, etc.

[0048] At least one pixel driving circuit includes a driving transistor T1, a compensation transistor, and a coupling capacitor Co.

[0049] The source and drain of the driving transistor T1 are connected in series with the corresponding light-emitting device D between the first power line VDD and the second power line VSS. The driving transistor T1 is used to generate a driving current to drive the light-emitting device D to emit light according to the data signal transmitted to the gate of the driving transistor T1.

[0050] The compensation transistor includes a first sub-transistor TL1 and a second sub-transistor TL2 connected in series, with a connection node A between them. One of the source and drain of the first sub-transistor TL1 is electrically connected to the gate of the driving transistor T1. The other of the source and drain of the first sub-transistor TL1 is electrically connected to one of the source and drain of the second sub-transistor TL2 via connection node A. The other of the source and drain of the second sub-transistor TL2 is electrically connected to one of the source and drain of the driving transistor T1. The gates of both the first sub-transistor TL1 and the second sub-transistor TL2 are electrically connected to a first scan line SL1.

[0051] The coupling capacitor Co is connected in series between the variable signal line EML1 and the connection node A. It is used to couple the potential of the connection node A according to the variable signal EM1 transmitted by the variable signal line EML1, so as to change the difference between the gate potential of the connection node A and the driving transistor T1.

[0052] Please continue reading. Figure 3 At least one of the pixel driving circuits further includes a data transistor T2, the source and drain of which are electrically connected between the other of the source and drain of the driving transistor T1 and the data line DL, and the gate of the data transistor T2 is electrically connected to the third scan line SL21. The data transistor T2 is used to transmit a data signal to the gate of the driving transistor T1 according to the second scan signal S2 transmitted by the corresponding third scan line SL21, so that the gate of the driving transistor T1 has a first potential.

[0053] During the light-emitting phase in which the driving transistor T1 drives the light-emitting device D to emit light, the variable signal EM1 has at least one level transition, so that the potential of the connection node A changes accordingly due to coupling during the light-emitting phase, thereby changing the gate potential of the driving transistor T1 accordingly to improve the flickering problem.

[0054] Optionally, when the display panel includes multiple cascaded first gating drive circuits EMG1, and each first gating drive circuit EMG1 is configured to output a variable signal EM1 to two variable signal lines EM1, the timing of the level transitions of the multiple variable signals EM1 is different, such as... Figure 4 As shown in EM1(n) and EM1(n+1), multiple sub-pixels can adjust the gate potential of their respective driving transistors T1 at different times, so that the average gate potential of the driving transistors T1 of the multiple sub-pixels is basically stable at the first potential during the light emission phase. When the display panel includes a first gating driving circuit EMG1, and the first gating driving circuit EMG1 is configured to output a variable signal EM1 to multiple variable signal lines EM1, the timing of the variable signal EM1 can be as follows: Figure 4 As shown in EM1.

[0055] Optionally, during the light-emitting phase in which the driving transistor T1 drives the light-emitting device D to emit light, the variable signal EM1 has at least one jump from the second potential V2 to the third potential V3, with the first potential being between the second potential V2 and the third potential V3, so that the average value of the gate potential of the driving transistor T1 is substantially stable at the first potential during the light-emitting phase.

[0056] Optionally, in order to make the first potential between the second potential V2 and the third potential V3, the capacitance value of the coupling capacitor Co can be greater than 0 FL and less than or equal to 10 FL.

[0057] Please continue reading. Figure 3 The at least one pixel driving circuit also includes a compensation transistor T3, a first switching transistor T4, a second switching transistor T5, an initial transistor T6, a reset transistor, and a storage capacitor Cst.

[0058] The source and drain of compensation transistor T3 are electrically connected between one of the source and drain of driving transistor T1 and the other of the source and drain of second sub-transistor TL2, and the gate of compensation transistor T3 is electrically connected to the third scan line SL21. Compensation transistor T3, in conjunction with data transistor T2, transmits the data signal to the gate of driving transistor T1 based on the second scan signal S2 transmitted via the third scan line SL21.

[0059] The source and drain of the first switching transistor T4 are electrically connected between the other of the source and drain of the driving transistor T1 and the first power supply line. The source and drain of the second switching transistor T5 are electrically connected between one of the source and drain of the driving transistor T1 and the first node B. The gates of both the first switching transistor T4 and the second switching transistor T5 are electrically connected to the light-emitting control line EML. The first switching transistor T4 and the second switching transistor T5 are used to drive the driving transistor T1 to drive the light-emitting device D to emit light according to the light-emitting control signal EM transmitted by the light-emitting control line EML.

[0060] The source and drain of the initial transistor T6 are electrically connected between the second reset line VL2 and the first node B, and the gate of the initial transistor T6 is electrically connected to the fourth scan line SL23. The initial transistor T6 is used to transmit the second reset signal transmitted through the second reset line VL2 to the first node B according to the second scan signal transmitted through the fourth scan line SL23. The light-emitting device D is electrically connected between the first node B and the second power supply line VSS.

[0061] The source and drain of the reset transistor are electrically connected between the first reset line VL1 and the other of the source and drain of the second sub-transistor TL2, and the gate of the reset transistor is electrically connected to the second scan line SL22. Optionally, the reset transistor includes a third sub-transistor TL3 and a fourth sub-transistor TL4 connected in series. One of the source and drain of the third sub-transistor TL3 is electrically connected to the first reset line VL1, one of the source and drain of the fourth sub-transistor TL4 is electrically connected to the other of the source and drain of the second sub-transistor TL2, and the other of the source and drain of the fourth sub-transistor TL4 is electrically connected to the other of the source and drain of the third sub-transistor TL3. The gates of both the third sub-transistor TL3 and the fourth sub-transistor TL4 are electrically connected to the second scan line SL22.

[0062] The storage capacitor Cst is connected in series between the first power supply line and the gate of the driving transistor T1 to maintain the gate potential of the driving transistor T1.

[0063] Optionally, the transistors included in the pixel driving circuit are made of silicon semiconductor materials or oxide semiconductor materials. The silicon semiconductor materials include polycrystalline silicon, monocrystalline silicon, etc.; the oxide semiconductor materials include indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), or indium gallium zinc tin oxide (IGZTO), etc.

[0064] Please continue reading. Figures 3-4Taking a pixel driving circuit as an example where each transistor is a P-type transistor, the first scan line SL1, electrically connected to the gate of the first sub-transistor TL1 and the gate of the second sub-transistor TL2, transmits the first scan signal S1(n) of the nth level; the second scan line SL22, electrically connected to the gate of the third sub-transistor TL3 and the gate of the fourth sub-transistor TL4, transmits the second scan signal S2(n-1) of the n-1th level; the light emission control line EML, electrically connected to the gate of the first switching transistor T4 and the gate of the second switching transistor T5, transmits the light emission control signal EM(n) of the nth level; and the third scan line SL21, electrically connected to the gate of the data transistor T2 and the gate of the compensation transistor T3, and the fourth scan line SL23, electrically connected to the gate of the initial transistor T6, all transmit the second scan signal S2(n) of the nth level, the working principle of the pixel driving circuit is explained. Where n ≥ 1.

[0065] During the reset phase t1, the first scan signal S1(n) transmitted by the first scan line SL1 and the second scan signal S2(n-1) transmitted by the second scan line SL22 are valid. The first sub-transistor TL1, the second sub-transistor TL2, the third sub-transistor TL3 and the fourth sub-transistor TL4 are turned on. The first reset signal transmitted by the first reset line VL1 is transmitted to the gate of the driving transistor T1 through the third sub-transistor TL3, the fourth sub-transistor TL4, the second sub-transistor TL2 and the first sub-transistor TL1 to reset the gate potential of the driving transistor T1.

[0066] During the data writing phase t2, the first scan signal S1(n) transmitted by the first scan line SL1 and the second scan signal S2(n) transmitted by the third scan line SL21 and the fourth scan line SL23 are valid. The first sub-transistor TL1, the second sub-transistor TL2, the data transistor T2, the compensation transistor T3, and the initial transistor T6 are turned on in response to the second scan signal S2(n). The data signal transmitted by the data line DL is transmitted to the gate of the driving transistor T1 via the data transistor T2, the compensation transistor T3, the second sub-transistor TL2, and the first sub-transistor TL1, so that the gate of the driving transistor T1 has a first potential. The second reset signal transmitted by the second reset line VL2 is transmitted to the first node B via the initial transistor T6 to reset the anode potential of the light-emitting device D.

[0067] During the light-emitting stage t3, the light-emitting control signal EM(n) transmitted by the light-emitting control line EML is valid. The first switching transistor T4 and the second switching transistor T5 turn on in response to the light-emitting control signal EM(n), driving transistor T1 to generate the driving current that drives the light-emitting device D to emit light. Optionally, the frequency of the light-emitting control signal EM(n) is greater than the frequency of the first scanning signal S1(n), which can improve the low-frequency flicker problem by continuously changing the bright and dark states of the light-emitting device D.

[0068] The write frame WF includes the stage where the data signal is transmitted to the gate of the driving transistor T1, while the hold frame HF does not include the stage where the data signal is transmitted to the gate of the driving transistor T1. When driving the display using a low frequency, a display cycle includes at least one hold frame HF, and the data displayed in the hold frame HF is consistent with the data displayed in the write frame WF. Therefore, it can be understood that the light-emitting stage t3 extends from the write frame WF to the hold frame HF. The second scan signal S2 still has a valid pulse within the hold frame, which can correct the gate potential of the driving transistor T1 and compensate for the brightness changes of the light-emitting device D.

[0069] The transition time of the variable signal EM1(n) is after the data signal is transmitted to the gate of the driving transistor T1. The variable signal EM1(n) can transition during the light-emitting phase t3 of the write frame or during the hold frame HF. To avoid the brightness change of the light-emitting device D being perceptible to the human eye due to the transition of the variable signal EM1(n), the transition time of the variable signal EM1(n) is located within the invalid pulse duration of the light-emitting control signal EM(n), or the transition time of the variable signal EM1(n) is the same as the transition time of the light-emitting control signal EM(n). For example, during the light-emitting phase t3 of the write frame WF, the time when the variable signal EM1(n) transitions from the second potential V2 to the third potential V3 is the same as the time when the light-emitting control signal EM(n) transitions from a high level to a low level; or, the time when the variable signal EM1(n) transitions from the third potential V3 to the second potential V2 is the same as the time when the light-emitting control signal EM(n) transitions from a high level to a low level. Optionally, the first potential is greater than the third potential V3 and less than the second potential V2.

[0070] The duration for which the variable signal EM1(n) maintains the second potential V2 is the first time period t11, and the duration for which the variable signal EM1(n) maintains the third potential V3 is the second time period t12. During the first time period t11 of writing frame WF, the gate of driving transistor T1 is mainly affected by the first reset signal and the data signal. Whether the variable signal EM1(n) is at the third potential V3 or the second potential V2 does not affect the gate potential of driving transistor T1. After the variable signal EM1(n) jumps during the light-emitting stage t3, the potential of connection node A changes accordingly due to coupling, thereby causing the gate potential of driving transistor T1 to change accordingly. Taking the example that each transistor in the pixel driving circuit is still a P-type transistor, when the variable signal EM1(n) jumps from the third potential V3 to the second potential V2, the potential of connection node A is coupled up to a level greater than the gate potential of driving transistor T1 through the coupling capacitor Co. Connection node A leaks current to the gate of driving transistor T1, causing the gate potential of driving transistor T1 to increase accordingly, thereby reducing the driving current and causing a decrease in the brightness of light-emitting device D. When the variable signal EM1(n) transitions from the second potential V2 to the third potential V3, the potential of the connection node A is coupled down to a level lower than the gate potential of the driving transistor T1 through the coupling capacitor Co. This causes leakage current from the gate of the driving transistor T1 to the connection node A, resulting in a corresponding decrease in the gate potential of the driving transistor T1. Consequently, the driving current increases, leading to an increase in the brightness of the light-emitting device D. Therefore, the transition of the variable signal EM1(n) can cause a change in the brightness of the light-emitting device D. By continuously transitioning the variable signal EM1(n) between the second potential V2 and the third potential V3, the average value of the gate potential of the driving transistor T1 can be kept essentially stable at the first potential.

[0071] Optionally, the duration of the first time period t11 can be equal to or unequal to the duration of the second time period t12. Understandably, the durations of the first time period t11 and the second time period t12 can be set according to actual needs. The duration for which the variable signal EM1(n) maintains the second potential V2 each time can be all equal or all unequal, and the duration for which the variable signal EM1(n) maintains the third potential V3 each time can also be all equal or all unequal. The shorter the durations of the first time period t11 and the second time period t12, the more times the variable signal EM1(n) transitions, and the higher the frequency of the variable signal EM1(n).

[0072] Theoretically, the potential of connection node A and the gate potential of driving transistor T1 are always equal, resulting in minimal brightness variation in light-emitting device D. However, since the gate potential of driving transistor T1 differs across different gray levels, while the potential of connection node A remains relatively constant, only a few gray levels can achieve good display performance without altering the potential of connection node A. The improvement in display performance for most other gray levels is poor due to the difference between the potential of connection node A and the gate potential of driving transistor T1. Therefore, this application utilizes the relatively long light-emitting phase t3 inherent in low-frequency driving to allow the potential of connection node A to become variable within the light-emitting phase t3 via coupling capacitor Co. This integrates the influence of the second potential V2 and the third potential V3 on the gate potential of driving transistor T1, stabilizing the average gate potential of driving transistor T1 at the first potential. Consequently, the brightness of light-emitting device D is maintained at approximately the initial brightness, mitigating the flickering problem inherent in low-frequency driving and thus improving display quality.

[0073] Understandably, when the display panel includes multiple cascaded first gating drive circuits EMG1, and each first gating drive circuit EMG1 is configured to output a variable signal EM1 to two variable signal lines EM1, the second potential V2 of the multiple variable signals EM1 may be the same or different, the third potential V3 of the multiple variable signals EM1 may also be the same or different, the duration for which the multiple variable signals EM1 maintain the second potential V2 each time may also be the same or different, and the duration for which the multiple variable signals EM1 maintain the third potential V3 each time may also be the same or different.

[0074] like Figure 5 This is a schematic diagram of display brightness variation provided by an embodiment of the present invention; wherein, L1 represents the display brightness variation curve obtained by driving the light-emitting device using the pixel driving circuit of the present application, which varies with the gate potential of the driving transistor T1, and L2 represents the display brightness variation curve obtained by driving the light-emitting device using a pixel driving circuit in the prior art (the pixel driving circuit in the prior art has no coupling capacitor Co), which varies with the gate potential of the driving transistor. A comparison shows that within one display cycle (1 Display), the brightness of the light-emitting device D driven by the pixel driving circuit of the present application changes multiple times, but the amplitude of the brightness variation of the light-emitting device D is significantly smaller than the brightness variation amplitude of the light-emitting device driven by the pixel driving circuit in the prior art.

[0075] Furthermore, since the duration of one display cycle (1 Display) is greater than the duration of each brightness change, even if the number of times the second potential V2 is greater than the gate potential of the driving transistor T1 is not equal to the number of times the third potential V3 is less than the gate potential of the driving transistor T1, it only manifests as a difference in the number of brightness change switching in L1. From the perspective of the duration of one display cycle (1 Display), the difference in the number of brightness change switching has little impact on the overall brightness change. It is understandable that one display cycle (1 Display) may include only one write frame WF, or it may include one write frame WF and at least one hold frame HF.

[0076] like Figure 6 This is a schematic diagram of the film structure of a sub-pixel provided in an embodiment of the present invention, as shown below. Figure 7 This is a schematic diagram of the active layer structure provided in an embodiment of the present invention. Please continue reading. Figures 6-7 The active layer 101 includes a first sub-active pattern of a first sub-transistor TL1, a second sub-active pattern of a second sub-transistor TL2, a first active pattern of a driving transistor T1, a second active pattern of a data transistor T2, a third active pattern of a compensation transistor T3, a fourth active pattern of a first switching transistor T4, a fifth active pattern of a second switching transistor T5, a sixth active pattern of an initial transistor T6, and a first electrical connection portion Cn1.

[0077] Optionally, the first sub-active pattern includes a first channel portion CP1, the second sub-active pattern includes a second channel portion CP2, and a first electrical connection portion Cn1 is connected between the first sub-active pattern and the second sub-active pattern to serve as a connection node A. Optionally, the first electrical connection portion Cn1 extends along a first direction x, and the first sub-active pattern and the second sub-active pattern extend along a second direction y, with the first direction x and the second direction y intersecting. The first sub-active pattern and the second sub-active pattern are located on the same side of the first electrical connection portion Cn1. The first end of the first electrical connection portion Cn1 is connected to the first end STL1 of the first sub-active pattern, and the second end of the first electrical connection portion Cn1 is connected to the second end DTL2 of the second sub-active pattern.

[0078] Optionally, the overlapping portion EML12 overlaps with the junction of the second end of the first electrical connection portion Cn1 and the second end of the second sub-active pattern DTL2, so that the junction of the overlapping portion EML12 with the second end of the first electrical connection portion Cn1 and the second end of the second sub-active pattern DTL2 forms the two electrodes of the coupling capacitor Co.

[0079] Optionally, the ion doping concentration of the first electrical connection portion Cn1 is greater than that of the first channel portion CP1 and the second channel portion CP2, so that the conductivity of the first electrical connection portion Cn1 is higher than that of the first channel portion CP1 and the second channel portion CP2, thereby using the first electrical connection portion Cn1 to electrically connect the first sub-active pattern and the second sub-active pattern.

[0080] The first end ST1 of the first active pattern is connected to the second end DT2 of the second active pattern and the second end DT4 of the fourth active pattern; the second end DT1 of the first active pattern is connected to the first end ST3 of the third active pattern and the first end ST5 of the fifth active pattern, and the second end DT5 of the fifth active pattern is connected to the first end ST6 of the sixth active pattern. The second, third, fourth, and fifth active patterns all extend along the second direction y, and the second and third active patterns are spaced apart, as are the fourth and fifth active patterns. The second end DT3 of the third active pattern is connected to the first end ST2 of the second sub-active pattern.

[0081] Optionally, the active layer 101 further includes a third sub-active pattern of a third sub-transistor TL3, a fourth sub-active pattern of a fourth sub-transistor TL4, and a second electrical connection Cn2 connecting the third sub-active pattern and the fourth sub-active pattern. The third sub-active pattern includes a third channel portion CP3, and the fourth sub-active pattern includes a fourth channel portion CP4. The second scan line SL22 overlaps with the third channel portion CP3 and the fourth channel portion CP4, so that the display panel can still be manufactured using existing manufacturing processes, thereby achieving a lower manufacturing cost than LTPO backplanes.

[0082] Optionally, the first terminal STL3 of the third sub-active pattern and the second terminal DTL4 of the fourth sub-active pattern are connected through a second electrical connection Cn2. The second electrical connection Cn2 extends along the first direction x and overlaps with the first reset line VL1, so that the overlapping portion of the second electrical connection Cn2 and the first reset line VL1 forms the two electrodes of another coupling capacitor, thereby maintaining the intermediate node (i.e., the middle node of the third sub-transistor TL3 and the fourth sub-transistor TL4) Figure 3 The potential of point C in the middle reduces the influence of the intermediate node potential of the third sub-transistor TL3 and the fourth sub-transistor TL4 on the gate potential of the driving transistor T1.

[0083] Optionally, the third sub-active pattern and the fourth sub-active pattern are both located between the variable signal line EML1 and the first reset line VL1, and the third sub-active pattern and the fourth sub-active pattern are spaced apart from the variable signal line EML1, so as to avoid the variable signal line EML1 and the first scan line SL1 forming unnecessary transistors when connecting the second sub-active pattern and the fourth sub-active pattern, thereby affecting the normal display of the sub-pixel.

[0084] Optionally, the second sub-active pattern and the fourth sub-active pattern are electrically connected to the bridging section F3, which is in a different layer from the variable signal line EML1 and the first scan line SL1.

[0085] Optionally, the variable signal line EML1 and the first reset line VL1 are in the same layer and made of the same material. For example... Figure 8 This is a schematic diagram of the structure of the first conductive layer provided in an embodiment of the present invention. The first conductive layer 102 further includes a first reset line VL1, a second reset line VL2, and a first electrode portion E1. The first reset line VL1 is located on the side of the variable signal line EML1 away from the second reset line VL2; the first electrode portion E1 is located between the second reset line VL2 and the variable signal line EML1, and the first electrode portion E1 overlaps with the first active pattern.

[0086] Optionally, the first power line VDD includes an electrically connected first sub-power line VDD1 and a second sub-power line VDD2. The first sub-power line VDD1 extends along a second direction y; the second sub-power line VDD2 extends along a first direction x, and the first sub-power line VDD1 and the second sub-power line VDD2 are on different layers. Optionally, the first conductive layer 102 further includes the second sub-power line VDD2, which is located between the first electrode portion E1 and the variable signal line EML1, and is connected to the first electrode portion E1.

[0087] Optionally, the variable signal line EML1 is on a different layer from the first scan line SL1 and the second scan line SL22, such as... Figure 9 This is a schematic diagram of the structure of the second conductive layer provided in an embodiment of the present invention; the display panel further includes a second conductive layer, which is located between the first conductive layer 102 and the active layer 101. Further, the second conductive layer is located between the first insulating layer 1001 and the second insulating layer 1002. Optionally, the second conductive layer includes a first scan line SL1, a third scan line SL21, a second scan line SL22, a fourth scan line SL23, a light emission control line EML, and a second electrode portion E2.

[0088] Among them, the variable signal line EML1 is located between the first scan line SL1 and the second scan line SL22, the first reset line VL1 is located on the side of the second scan line SL22 away from the variable signal line EML1, the third scan line SL21 is located between the first scan line SL1 and the second sub-power line VDD2, the light emission control line EML is located between the second sub-power line VDD2 and the second reset line VL2, and the fourth scan line SL23 is located on the side of the second reset line VL2 away from the light emission control line EML.

[0089] The portion of the first scan line SL1 that overlaps with the first channel portion CP1 serves as the gate of the first sub-transistor TL1, and the portion of the first scan line SL1 that overlaps with the second channel portion CP2 serves as the gate of the second sub-transistor TL2. The portion of the second scan line SL22 that overlaps with the third channel portion CP3 serves as the gate of the third sub-transistor TL3, and the portion of the second scan line SL22 that overlaps with the fourth channel portion CP4 serves as the gate of the fourth sub-transistor TL4. The third scan line SL21 partially overlaps with the second and third active patterns; the portion of the third scan line SL21 that overlaps with the second active pattern serves as the gate of the data transistor T2, and the portion of the third scan line SL21 that overlaps with the third active pattern serves as the gate of the compensation transistor T3. The light-emitting control line EML partially overlaps with the fourth and fifth active patterns; the portion of the light-emitting control line EML that overlaps with the fourth active pattern serves as the gate of the first switching transistor T4, and the portion of the light-emitting control line EML that overlaps with the fifth active pattern serves as the gate of the second switching transistor T5. The fourth scan line SL23 partially overlaps with the sixth active pattern, and the overlapping portion of the fourth scan line SL23 and the sixth active pattern serves as the gate of the initial transistor T6. The second electrode portion E2 overlaps with the first active pattern to serve as the gate of the driving transistor T1; the first electrode portion E1 and the second electrode portion E2 overlap to form the two electrodes of the storage capacitor Cst.

[0090] Optionally, the first terminal ST2 of the second active pattern, the second terminal DTL1 of the first sub-active pattern, the first terminal STL2 of the second sub-active pattern, and the second terminal DT3 of the third active pattern are all located between the third scan line SL21 and the first scan line SL1. The second terminal DTL3 of the third sub-active pattern and the first terminal STL4 of the fourth sub-active pattern are located between the variable signal line EML1 and the second scan line SL22. The first terminal ST4 of the fourth active pattern and the second terminal DT5 of the fifth active pattern are both located between the light emission control line EML and the second reset line VL2. The second terminal DT6 of the sixth active pattern is located on the side of the fourth scan line SL23 away from the second reset line VL2. Optionally, the first active pattern is U-shaped.

[0091] like Figure 10 This is a schematic diagram of the structure of the third conductive layer provided in an embodiment of the present invention. The display panel also includes an interlayer dielectric layer and a third conductive layer located on the first conductive layer. The third conductive layer includes a first conductive portion F1, a second conductive portion F2, a bridging portion F3, a fourth conductive portion F4, a fifth conductive portion F5, a sixth conductive portion F6, and a seventh conductive portion F7.

[0092] The first conductive portion F1 extends along the second direction y and is electrically connected between the second electrode portion E2 and the second end DTL1 of the first sub-active pattern, thereby realizing the electrical connection between the gate of the driving transistor T1 and the first sub-transistor TL1. Specifically, the first electrode portion E1 includes a first opening that exposes the second electrode portion E2, and the first conductive portion F1 is electrically connected to the second electrode portion E2 through the first opening and a via penetrating the interlayer dielectric layer and the second insulating layer 1002 (e.g., Figure 10 At CNT1 in the diagram, it is electrically connected to the second end DTL1 of the first sub-active pattern through a via penetrating the interlayer dielectric layer, the second insulating layer 1002, and the first insulating layer 1001 (e.g., at CNT1 in the diagram). Figure 10 (CNT2 in the middle).

[0093] The second conductive portion F2 overlaps with and is electrically connected to the first end ST2 of the second active pattern, serving as the source of the data transistor T2. Specifically, the second conductive portion F2 is electrically connected to the first end ST2 of the second active pattern through a via penetrating the interlayer dielectric layer, the second insulating layer 1002, and the first insulating layer 1001 (e.g., ...). Figure 10 (at CNT3 in the transistor) to be used as the source of data transistor T2.

[0094] The bridging portion F3 extends along the second direction y and is electrically connected between the first end STL2 of the second sub-active pattern and the first end STL4 of the fourth sub-active pattern, thereby realizing the electrical connection between the second sub-transistor TL2 and the fourth sub-transistor TL4. Specifically, the bridging portion F3 is electrically connected to the first end STL2 of the second sub-active pattern through a via penetrating the interlayer dielectric layer, the second insulating layer 1002, and the first insulating layer 1001 (e.g., ...). Figure 10 At CNT4, it is electrically connected to the first end STL4 of the fourth sub-active pattern through a via penetrating the interlayer dielectric layer, the second insulating layer 1002, and the first insulating layer 1001 (e.g., at CNT4). Figure 10 (CNT5 in the middle).

[0095] The fourth conductive portion F4 extends along the second direction y and is electrically connected between the first electrode portion E1 and the first end ST4 of the fourth active pattern, realizing the electrical connection between the first switching transistor T4 and the second sub-power line VDD2. Specifically, the fourth conductive portion F4 is electrically connected to the first electrode portion E1 through a via penetrating the interlayer dielectric layer (e.g., ...). Figure 10 At CNT6 in the diagram, it is electrically connected to the first end ST4 of the fourth active pattern via a via penetrating the interlayer dielectric layer, the second insulating layer 1002, and the first insulating layer 1001 (e.g., at CNT6 in the diagram). Figure 10 (CNT7 in the middle).

[0096] The fifth conductive part F5 is electrically connected between the second terminal DTL3 of the third sub-active pattern and the first reset line VL1 to realize the electrical connection between the third sub-transistor TL3 and the first reset line VL1. Specifically, the fifth conductive part F5 is electrically connected to the second terminal DTL3 of the third sub-active pattern through a via penetrating the interlayer dielectric layer, the second insulating layer 1002, and the first insulating layer 1001 (e.g., Figure 10 At CNT8 in the middle, it is electrically connected to the first reset line VL1 through a via penetrating the interlayer dielectric layer (e.g., at CNT8). Figure 10 (CNT9 in the middle).

[0097] The sixth conductive portion F6 extends along the second direction y and overlaps with the second electrode portion E2, the light-emitting control line EML, and the fifth active pattern portion, and is electrically connected to the second end DT5 of the fifth active pattern to serve as the first node B. Specifically, the sixth conductive portion F6 is electrically connected to the second end DT5 of the fifth active pattern through a via penetrating the interlayer dielectric layer, the second insulating layer 1002, and the first insulating layer 1001 (e.g., ...). Figure 10 (CNT10 in the middle).

[0098] The seventh conductive portion F7 is electrically connected between the second terminal DT6 of the sixth active pattern and the second reset line VL2 to achieve an electrical connection between the initial transistor T6 and the second reset line VL2. Specifically, the seventh conductive portion F7 is electrically connected to the second terminal DT6 of the sixth active pattern through a via penetrating the interlayer dielectric layer, the second insulating layer 1002, and the first insulating layer 1001 (e.g., ...). Figure 10 At CNT11 in the middle), it is electrically connected through the second reset line VL2 via the via penetrating the interlayer dielectric layer (such as...). Figure 10 (CNT12 in the middle).

[0099] Figure 11 This is a schematic diagram of the structure of the fourth conductive layer provided in an embodiment of the present invention; the display panel also includes a first planarization layer and a fourth conductive layer located on the third conductive layer, the fourth conductive layer including a data line DL and a first sub-power line VDD1.

[0100] The data cable DL includes a first main body DL1 and an extension DL2. The first main body DL1 extends along a second direction y. The extension DL2 is located on the side of the first main body DL1 near the first active pattern. The extension DL2 overlaps with the first end ST2 of the second active pattern and the second conductive part F2. The extension DL2 is electrically connected to the second conductive part F2, and the extension DL2 is electrically connected to the first end ST2 of the second active pattern through the second conductive part F2. Specifically, the extension DL2 is electrically connected to the second conductive part F2 through a via penetrating the first planarization layer (e.g., ...). Figure 11 (at PLN1 in the middle).

[0101] The first sub-power line VDD1 is spaced apart from the data line DL. The first sub-power line VDD1 includes a second main body VD1, a third main body VD2, and a clearance portion VD3 located between the second main body VD1 and the third main body VD2 and corresponding to the extension portion DL2. Both the second main body VD1 and the third main body VD2 extend along the second direction y. The clearance portion VD3 overlaps with the junction of the first sub-part EML11a and the third sub-part EML11c, and is spaced apart from the overlapping portion EML12, thereby eliminating the overlap between the clearance portion VD3 and the overlapping portion EML12 and thus eliminating parasitic capacitance between the clearance portion VD3 and the overlapping portion EML12.

[0102] Optionally, the second sub-power line VDD2 is electrically connected to the first sub-power line VDD1 through the fourth conductive portion F4. Specifically, a portion of the third main body VD2 overlaps with and is electrically connected to the fourth conductive portion F4. Furthermore, the fourth conductive portion F4 is electrically connected between the first electrode portion E1 and the first end ST4 of the fourth active pattern. The first electrode portion E1 is also electrically connected to the second sub-power line VDD2. Therefore, the fourth conductive portion F4 can realize the electrical connection between the second sub-power line VDD2 and the first sub-power line VDD1, and can also electrically connect one of the source and drain terminals of the first switching transistor T4 to the second sub-power line VDD2 and the first sub-power line VDD1. The third main body VD2 is electrically connected to the fourth conductive portion F4 through a via penetrating the first planarization layer (e.g., ...). Figure 11 (at PLN2 in the middle).

[0103] Optionally, the fourth conductive layer further includes a node connection portion B1, which is located on the side of the first sub-power line VDD1 away from the data line DL, and overlaps with and is electrically connected to the sixth conductive portion F6. Specifically, the node connection portion B1 is electrically connected to the sixth conductive portion F6 through a via penetrating the first planarization layer (e.g., Figure 11 (at PLN3 in the middle).

[0104] It is understandable that the dimensions of the corresponding vias in each conductive layer and active layer can be larger than the dimensions of the non-corresponding vias in each conductive layer and active layer.

[0105] Optionally, multiple light-emitting devices are electrically connected to the first node B of multiple pixel driving circuits. The source and drain of the light-emitting device and the driving transistor T1 in the corresponding pixel driving circuit are electrically connected between a first voltage terminal and a second voltage terminal. Optionally, a first power supply line is electrically connected between the first voltage terminal and one of the source and drain of the driving transistor T1, and a second power supply line is electrically connected between the cathode of the light-emitting device and the second voltage terminal.

[0106] The present invention also provides a display device, the display device comprising any of the above-described driving circuits or any of the above-described display panels.

[0107] Understandably, the display device includes portable display devices (such as laptops, mobile phones, etc.), fixed terminals (such as desktop computers, televisions, etc.), measuring devices (such as fitness trackers, thermometers, etc.), etc.

[0108] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A display panel, characterized in that, include: The active layer includes a first channel portion and a second channel portion disposed opposite to each other, and a first electrical connection portion connecting the first channel portion and the second channel portion; the first channel portion extends along a second direction; The first scan line extends along a first direction and overlaps with the first channel portion and the second channel portion; A variable signal line includes interconnected and overlapping trace portions and overlapping portions on the same layer, wherein the overlapping portions are located on the side of the trace portions closer to the first electrical connection portion, and the overlapping portions at least partially overlap the first electrical connection portion; as well as The light emission control line is located on the side of the first scan line away from the variable signal line along the second direction, and the second direction intersects the first direction.

2. The display panel according to claim 1, characterized in that, It also includes multiple sub-pixels, each of which includes a light-emitting device and a pixel driving circuit, the pixel driving circuit including: The driving transistor is connected in series with the light-emitting device between the first power line and the second power line; and The compensation transistor includes a first sub-transistor and a second sub-transistor connected in series. One of the source and drain of the first sub-transistor is electrically connected to the gate of the driving transistor. The other of the source and drain of the first sub-transistor is electrically connected to one of the source and drain of the second sub-transistor. The other of the source and drain of the second sub-transistor is electrically connected to one of the source and drain of the driving transistor. The gates of the first sub-transistor and the second sub-transistor are both electrically connected to the first scan line. The active layer further includes a first sub-active pattern of the first sub-transistor and a second sub-active pattern of the second sub-transistor, wherein the first sub-active pattern includes the first channel portion and the second sub-active pattern includes the second channel portion.

3. The display panel according to claim 2, characterized in that, The display panel includes multiple variable signal lines, and multiple sub-pixels located in the same row are electrically connected to the same variable signal line.

4. The display panel according to claim 3, characterized in that, Also includes: A first gating drive circuit, electrically connected to the plurality of said variable signal lines, is configured to output a variable signal to the plurality of said variable signal lines; During the light-emitting phase in which the driving transistor drives the light-emitting device to emit light, the variable signal has at least one level transition.

5. The display panel according to claim 3, characterized in that, Also includes: Multiple cascaded first gating drive circuits, each of the first gating drive circuits being electrically connected to the two said variable signal lines and configured to output a variable signal to the two said variable signal lines; During the light-emitting phase in which the driving transistor drives the light-emitting device to emit light, each of the variable signals has at least one level transition, and the timing of the level transitions of the multiple variable signals is different.

6. The display panel according to claim 2, characterized in that, The pixel driving circuit further includes a reset transistor, which includes a third sub-transistor and a fourth sub-transistor connected in series. One of the source and drain of the third sub-transistor is electrically connected to a first reset line. One of the source and drain of the fourth sub-transistor is electrically connected to the other of the source and drain of the second sub-transistor. The other of the source and drain of the fourth sub-transistor is electrically connected to the other of the source and drain of the third sub-transistor. The gates of both the third and fourth sub-transistors are electrically connected to a second scan line. The variable signal line is located between the first scan line and the second scan line, and the variable signal line is on a different layer than the first scan line and the second scan line.

7. The display panel according to claim 6, characterized in that, The active layer further includes a third sub-active pattern of the third sub-transistor, a fourth sub-active pattern of the fourth sub-transistor, and a second electrical connection portion connected between the third sub-active pattern and the fourth sub-active pattern; the third sub-active pattern includes a third channel portion, and the fourth sub-active pattern includes a fourth channel portion; Wherein, the second scan line overlaps with the third channel portion and the fourth channel portion, and the first reset line overlaps with the second electrical connection portion; the third sub-active pattern and the fourth sub-active pattern are both located between the variable signal line and the first reset line, and the third sub-active pattern and the fourth sub-active pattern are both spaced apart from the variable signal line.

8. The display panel according to claim 7, characterized in that, The second sub-active pattern and the fourth sub-active pattern are electrically connected through a bridging portion that is different from the variable signal line and the first scan line.

9. The display panel according to claim 6, characterized in that, The variable signal line is in the same layer as the first reset line and is made of the same material.

10. The display panel according to claim 1, characterized in that, The ion doping concentration of the first electrical connection portion is greater than that of the first channel portion and the second channel portion.

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