Apparatus and method for handling memory access requests

Abstract

A technique for processing memory access requests is described. An apparatus has an interconnecter to couple a plurality of requester elements with a plurality of slave elements. The plurality of requester elements are arranged to issue memory access requests for processing by the plurality of slave elements. An intermediate element within the interconnecter acts as a serialization point for ordering memory access requests issued by the plurality of requester elements via the intermediate element. The intermediate element has tracking circuitry to track processing of memory access requests accepted by the intermediate element. In addition, request acceptance management circuitry is provided that, in response to the intermediate element receiving a given memory access request, is arranged to identify a target slave element of the plurality of slave elements for the given memory access request and determine whether the given memory access request is to be accepted by the intermediate element in dependence on a bandwidth capability indication of the target slave element. This approach can improve overall system bandwidth utilization.

Description

Background Technology

[0001] This technology relates to an apparatus and method for processing memory access requests, and more particularly to a technique for processing such memory access requests within an interconnect provided by the apparatus.

[0002] Interconnectors can be used to couple multiple requester elements to multiple slave elements. Requester elements can be arranged to issue memory access requests, and the memory access requests can cause the slave element to which the memory access request is directed to to be accessed (e.g., writing data to or from the slave element or a memory device associated with the slave element, or reading data from or from the slave element or a memory device associated with the slave element).

[0003] Intermediate elements can be placed within the interconnect to coordinate the processing of various memory access requests issued by requester elements. These intermediate elements can be configured to track pending memory access requests they are coordinating, but there is typically a limited number of pending memory access requests that an intermediate element can track at any given time. Once this limit is reached, the intermediate element may have to reject any additional memory access requests issued by multiple requester elements until some of the pending requests already tracked have been completed.

[0004] It has been found that this approach can limit system performance, for example, when one slave element can process memory access requests faster than another, for instance, due to the different bandwidth capabilities of their associated memory devices. A technique is desired to improve system performance in such cases. Summary of the Invention

[0005] In one exemplary arrangement, an apparatus is provided, comprising: an interconnect for coupling a plurality of requester elements to a plurality of slave elements, the plurality of requester elements being arranged to issue memory access requests for processing by the plurality of slave elements; and an intermediate element disposed within the interconnect to act as a serialization point for sequencing the memory access requests issued by the plurality of requester elements via the intermediate element; the intermediate element including tracking circuitry to track the processing of the memory access requests accepted by the intermediate element; the intermediate element further including request acceptance management circuitry, the request acceptance management circuitry being arranged to identify a target slave element among the plurality of slave elements for the given memory access request in response to the intermediate element receiving a given memory access request, and to determine whether the given memory access request will be accepted by the intermediate element based on a bandwidth capability indication of the target slave element.

[0006] In another exemplary configuration, a method for processing memory access requests is provided, the method comprising: providing an interconnect to couple a plurality of requester elements to a plurality of slave elements, the plurality of requester elements being arranged to issue the memory access requests for processing by the plurality of slave elements; employing an intermediate element disposed within the interconnect to act as a serialization point for sequencing the memory access requests issued by the plurality of requester elements via the intermediate element; tracking the processing of the memory access requests accepted by the intermediate element within tracking circuitry of the intermediate element; and, in response to the intermediate element receiving a given memory access request, identifying a target slave element among the plurality of slave elements for the given memory access request, and determining whether the given memory access request will be accepted by the intermediate element based on a bandwidth capability indication of the target slave element.

[0007] In yet another exemplary arrangement, an apparatus is provided comprising: an interconnect component for coupling a plurality of requester elements to a plurality of slave elements, the plurality of requester elements being arranged to issue memory access requests for processing by the plurality of slave elements; and an intermediate element component disposed within the interconnect component for acting as a serialization point for ordering the memory access requests issued by the plurality of requester elements via the intermediate element component; the intermediate element component includes a tracking component for tracking the processing of the memory access requests accepted by the intermediate element component; the intermediate element component further includes a request acceptance management component for identifying a target slave element among the plurality of slave elements for the given memory access request in response to the intermediate element component receiving the given memory access request, and for determining whether the given memory access request will be accepted by the intermediate element component based on a bandwidth capability indication of the target slave element. Attached Figure Description

[0008] The present technology will be further described by way of illustration only, with reference to examples of the present technology shown in the accompanying drawings, wherein: Figure 1 It is a block diagram of a system based on an exemplary arrangement; Figure 2 This schematically illustrates how, according to an exemplary arrangement, the memory address space can be divided into different regions associated with different types of memory. Figure 3 This is an illustration based on an exemplary arrangement. Figure 1 A flowchart of the operation of intermediate components; Figure 4A and Figure 4B This is a flowchart illustrating how an intermediate element uses busy signals provided from various subordinate elements when deciding whether to accept a newly received memory access request, according to an exemplary configuration. Figure 5A The form of a system address mapping that can be associated with each requester element in an exemplary arrangement is shown; Figure 5B This is a flowchart illustrating, according to an exemplary arrangement, how an intermediate element uses the quality of service information provided in association with a memory access request to determine whether to accept the memory access request; Figure 6A This illustrates the form in which a system address mapping can be provided in association with an intermediate element in an exemplary arrangement; Figure 6B This illustrates, according to an exemplary arrangement, how an intermediate element uses data from sources such as memory access sources when deciding whether to accept a memory access request. Figure 6A The flowchart shown illustrates the static bandwidth information obtained through system address mapping. Figure 7 The operation of an intermediate element according to an exemplary arrangement is illustrated schematically; Figure 8A Specific examples illustrate how a shared tracking structure within an intermediate element can limit overall system bandwidth when the techniques described herein are not used; and Figure 8B Specific examples illustrate how the use of the techniques described in this article can allow for improvements in overall system bandwidth management. Detailed Implementation

[0009] According to one exemplary embodiment, an apparatus is provided having an interconnect for coupling a plurality of requester elements to a plurality of slave elements. The plurality of requester elements are arranged to issue memory access requests for processing by the plurality of slave elements. An intermediate element is disposed within the interconnect to act as a serialization point for ordering these memory access requests issued by the plurality of requester elements via the intermediate element. Thus, the intermediate element can act as a point within the interconnect at which the ordering of memory access requests from different requester elements is determined. In some instances, these memory access requests (also referred to herein simply as access requests) may specify addresses within a cacheable region of memory, and one or more of the requester elements may have local caches. In this case, the intermediate element may also act as a consistency point, applying a cache consistency protocol to ensure that each requester element sees the latest version of the data accessed in response to its access request.

[0010] The intermediate element includes tracking circuitry to monitor the processing of memory access requests accepted by it. Thus, the intermediate element can track each accepted memory access request while it remains in a waiting state within the system. Once a slave element has performed a read or write operation specified by the memory access request (or at least confirmed that the write operation will be performed), or the intermediate element has processed the access request directly without needing to contact the slave element, the intermediate element can be configured to stop tracking the associated memory access request, freeing up space to track another memory access request. In some implementations, it may be necessary to return any necessary confirmations (along with the read data of the read memory access request) to the requester element before the intermediate element stops tracking the memory access request.

[0011] The tracking circuitry within this intermediate element will have a limited size, thus limiting the total number of pending memory access requests that the intermediate element can track at any given time. Therefore, it is possible that when the intermediate element receives a new memory access request, it may not have the resources available to track that new memory access request, and in such a case, it may be necessary to signal the requesting element that issued the memory access request that the memory access request cannot be accepted at the current time. For example, this could allow the requesting element to retry the memory access request at an appropriate time.

[0012] However, this approach can lead to underutilization of certain available system bandwidth in some situations. For example, various slave elements may have different capabilities; in particular, some slave elements may be able to process memory access requests faster than others, for example, due to the bandwidth capabilities of the associated memory device. Therefore, in such cases, a memory access request that might target one of the faster slave elements may be rejected by that intermediate element, even if that faster slave element has the capability to receive and process the new memory access request. According to the techniques described herein, a mechanism is employed to seek to reduce the likelihood of this occurring.

[0013] Specifically, according to the technology described herein, the intermediate element further includes a request acceptance management circuit, which, in response to the intermediate element receiving a given memory access request, is arranged to identify a target slave element among the plurality of slave elements for the given memory access request. Furthermore, the request acceptance management circuit then determines whether the given memory access request will be accepted by the intermediate element based on a bandwidth capability indication of the target slave element.

[0014] This method allows for modification of the criteria used to decide whether to accept a memory access request, based on the target slave element of the newly received memory access request and, in particular, information that can be used to indicate the bandwidth capabilities of that target slave element. For example, this method can be used to limit the amount of tracking circuit resources available for tracking memory access requests targeting slower slave elements, in order to reserve available space within the tracking circuit for memory access requests targeting faster slave elements. With this method, it is possible that if a newly received memory access request targets a single slave element, the memory access request can be accepted by an intermediate element, while if the memory access request targets a different slave element, the memory access request may be rejected. It has been found that this method can lead to more efficient utilization of the overall system bandwidth.

[0015] There are several ways to handle a situation where a given memory access request is determined not to be accepted by the intermediate element. In one exemplary embodiment, the device further includes a retry management circuit arranged to communicate with the requester element that issued the given memory access request when the request acceptance management circuit indicates that the given memory access request will not be accepted, in order to implement a retry mechanism for the given memory access request. The retry mechanism can take various forms. For example, when the retry management circuit notifies that the given memory access request is not accepted, the relevant requester element can be arranged to periodically retry the memory access request, or to perform some kind of polling operation to seek to determine when the intermediate element will have the capability to receive the memory access request in its tracking circuitry. As another exemplary method, the requester element can wait until the intermediate element provides a static grant signal at an appropriate time, which effectively guarantees that the requester element will make room for the given memory access request in the tracking circuitry resources of the intermediate element, at which point the requester element will subsequently reissue the memory access request.

[0016] In one exemplary implementation, a similar retry mechanism may also be employed between the intermediate element and various slave elements, and thus if a slave element cannot accept a memory access request propagated to it by the intermediate element, a retry signal may be issued from the slave element to the intermediate element so that the intermediate element may retry propagating the memory access request to the slave element when appropriate.

[0017] The bandwidth capability of each target slave element can be identified in various ways. In one exemplary implementation, each slave element has an associated memory device, and the bandwidth capability of the target slave element may depend on the associated memory device. For example, the bandwidth capability of the target slave element may depend on the memory type of the associated memory device. Specifically, different types of memory may have different access speeds, and this will affect the speed at which the associated target slave element can handle memory access requests.

[0018] There are several ways in which the request acceptance management circuitry can be arranged to determine the bandwidth capability indication of the target slave element. However, in one exemplary implementation, the request acceptance management circuitry derives the bandwidth capability indication of the target slave element by referring to at least one information source.

[0019] The information source can take many forms, and in fact, when seeking to derive the bandwidth capability indication of the target slave element, the request acceptance management circuit can refer to multiple different information sources.

[0020] In one exemplary embodiment, the at least one information source includes information signals received by the intermediate element from the plurality of slave elements, and the request acceptance management circuit is arranged to use the information signals to derive the bandwidth capability indication of each of the slave elements. Therefore, according to this method, information continuously provided by the slave elements can be used to maintain the bandwidth capability indication of each slave element, thus enabling dynamic adjustment of the bandwidth capability indication based on information received by the slave elements during use.

[0021] The information signals can take various forms, but in one exemplary embodiment, a busy signal is included by each slave element to identify its busy level. Therefore, according to this embodiment, the actual busy level of a slave element can be used to influence whether an additional memory access request targeting that slave element will be accepted by the intermediate element. For example, this allows new memory access requests targeting that slave element to be accepted when the slave element is not too busy, but prevents new memory access requests targeting that slave element from being accepted when it is known that the slave element's busy level is above a certain threshold.

[0022] In one exemplary implementation, the tracking circuit may have multiple entries for tracking memory access requests, and the request acceptance management circuit may be arranged to determine that a given memory access request will be accepted by the intermediate element when there is a free entry among the multiple entries, and the bandwidth capability indicator of the target slave element instructs the target slave element to operate below a given busy threshold level.

[0023] While a single threshold level can be used for each target slave element, in alternative implementations, multiple thresholds can be used if desired to allow for a more hierarchical approach between the point at which all memory access requests for a particular target slave element are accepted and the point at which all memory access requests for that target slave element are temporarily denied.

[0024] There are several ways in which the request acceptance management circuit can track information signals received by the slave elements. In one exemplary embodiment, the device has a storage device for maintaining a bandwidth capability indication for each slave element, and the request acceptance management circuit is arranged to maintain the bandwidth capability indication for each slave element in the storage device based on the received information signals. Therefore, the request acceptance management circuit can update the contents of the storage device based on the information signals received from each slave element.

[0025] While in one exemplary embodiment the request acceptance management circuitry may be arranged to utilize only the most recent information signal received from each slave element, in another embodiment, the request acceptance management circuitry may be arranged to maintain a bandwidth capability indication of the slave element based on information signals received from each slave element within a previously selected time period. In this way, the busy level of each slave element can be averaged based on the information signals received over a period of time.

[0026] As an alternative to or supplement to using information signals received from subordinate elements, the at least one information source may include a quality of service (QoS) indication received by the intermediate element in association with a given memory access request. According to this method, each requester element may append QoS indication information to each issued memory access request, the QoS indication influencing the decision made by the request acceptance management circuitry regarding whether any particular memory access request should be accepted.

[0027] As previously described, the tracking circuit may have multiple entries for tracking memory access requests. For each quality of service indicator, an association threshold may be defined, which identifies the number of entries within the tracking circuit that can be used simultaneously to track memory access requests with that quality of service indicator. The request acceptance management circuit is then arranged to determine that a given memory access request will be rejected if, taking into account the association threshold for the quality of service indicator of a given memory access request, no entries are available within the tracking circuit. Thus, purely as an illustrative example, if for a particular received memory access request that has an associated quality of service indicator, and for that quality of service indicator, it is determined that up to 50% of the entries are available to track memory access requests with that quality of service indicator, then if 50% of the entries have been used to track memory access requests with that quality of service indicator, the memory access request can be rejected even if there are still available free entries in the tracking circuit. This approach can be used, for example, to ensure that space is reserved within the tracking circuit to track subsequently received memory access requests that may have higher quality of service requirements.

[0028] There are several ways to determine a quality of service (QoS) indication. For example, address mapping circuitry can be provided associated with each requester element to translate the memory address specified by a memory access request issued by that requester element into a target identifier for routing the memory access request through an interconnect. For example, when the memory access request specifies a memory address within a memory address space allocated to one of the aforementioned dependent elements, the target identifier can identify the intermediate element to which the memory access request will be routed. The address mapping circuitry can be arranged to provide memory type information for different memory address ranges, for example, to identify the type of memory device used for these different memory address ranges, which in turn can provide an access speed indication. The QoS indication can then be determined based on the memory type information for the memory address range (including the memory address specified by the memory access request). The QoS indication information can be encoded directly within the address mapping circuitry, or alternatively, it can be derived based on the memory type information extracted from the address mapping circuitry.

[0029] As an alternative to or supplement to the aforementioned information signals and quality of service indications, the at least one information source may include at least one dependent element attribute determined by the intermediate element. Such dependent element attributes can be determined in various ways. For example, the address mapping circuit may be associated with the intermediate element, which determines a target dependent element for each received memory access request. The address mapping circuit may also provide at least one dependent element attribute for each dependent element, so that the intermediate element can retrieve such dependent element attributes from the address mapping circuit when determining a target dependent element for a received memory access request.

[0030] The at least one dependent element attribute can take various forms, but in one exemplary embodiment, it includes a bandwidth indicator value for the dependent element. In a particular exemplary embodiment, the bandwidth indicator value can be a static value, and thus can be predetermined and then referenced during use of the device. The bandwidth indicator value can take various forms, but in one example, it depends on the memory type of the memory device associated with the dependent element. Therefore, the bandwidth indicator value can, for example, take into account information such as the access speed of the memory device, which can depend on the specific type of memory used.

[0031] When using such bandwidth indication values, an association threshold can be defined for each such bandwidth indication value. This association threshold identifies the number of entries within the tracking circuit that can be simultaneously used to track memory access requests with that bandwidth indication value targeting a slave element. The request acceptance management circuit can then be arranged to determine that a given memory access request will be rejected if, taking into account the association threshold for the bandwidth indication value of the target slave element of a given memory access request, there are no available entries within the tracking circuit. Therefore, by way of example, the association threshold can be set higher for memory access requests targeting relatively fast slave elements and lower for memory access requests targeting relatively slow slave elements. This allows control over the extent to which the tracking circuit resources of the intermediate element can be used to track relatively slow memory access requests, in order to seek to reserve available space to receive new memory access requests targeting faster memory. This approach improves overall system bandwidth utilization.

[0032] A specific example will now be described with reference to the accompanying drawings.

[0033] Figure 1This is a block diagram of a system according to an exemplary specific implementation. The device includes multiple requester elements 10, 15, 55 coupled to multiple slave elements 75, 85, 95 via interconnect 30. While slave elements can take many forms, for the purposes of this discussion, slave elements for accessing different memory devices are considered. Thus, slave element 75 may be connected to memory device 80, which in this example may be in the form of double data rate (DDR) memory, while slave element 85 is connected to another memory device 90, which may, for example, be in the form of high bandwidth memory (HBM). As another example, slave element 95 may be arranged to provide a link to off-chip memory 97 (e.g., using a CCIX link, which is a high-performance, low-latency chip-to-chip interface), and the off-chip memory may be implemented by yet another type of memory device. When using a CCIX link, slave element 95 may be referred to as a CXSA element.

[0034] Within interconnect 30, multiple intermediate elements can be provided, which can serve as serialization points for ordering access requests issued by the requester elements. Figure 1 In the example shown, intermediate element 65 is provided as a serialization point for access requests originating from any requester elements 10, 15, 55 targeting subordinate elements 75, 85, 95. In this document, intermediate elements such as intermediate element 65 may also be referred to as home nodes.

[0035] Interconnector 30 provides communication channels for supporting communication between each requester element and each home node, as well as for supporting communication between the home node and associated slave elements.

[0036] exist Figure 1 The example shown illustrates two types of requester elements, referred to herein as fully consistent requesters 10 and 15 and an input / output (I / O) consistent requester 55. Such as Figure 1 The full conformance requester of element 10 or element 15 shown may have an associated local hardware conformance cache and may be arranged to be connected to the interconnect via associated interfaces 35, 45.

[0037] Access requests issued by any requester elements 10, 15, and 55 involving cacheable memory addresses will be routed via the fully consistent home node, and... Figure 1In the example, assume that intermediate element 65 is actually a fully consistent home node. The fully consistent home node will not only act as a serialization point for access requests but also as a consistency point, and therefore can implement a cache coherence protocol to ensure that the requester issuing an access request associated with a cacheable memory address sees the latest version of the data. Typically, such a consistent home node will include listener control circuitry to track which local caches have cached data within a specific address region, thereby identifying which local caches need to be listened to in order to implement the cache coherence protocol.

[0038] In contrast to the fully consistent requester elements 10 and 15, I / O consistent requester elements such as element 55 do not include a hardware consistent cache and do not require associated listening functionality to respond to listening requests.

[0039] Although not in Figure 1 As shown, however, interconnector 30 may include non-consistent home nodes that do not provide a consistency point and cannot handle listener requests. These may be used, for example, when accessing non-cacheable regions of memory or peripheral devices or device memory.

[0040] The system can also include two different types of slave elements: slave elements that can be coupled to a fully consistent home node and slave elements that can be coupled to a non-consistent home node. In the example shown herein, home node 65 is a fully consistent home node, therefore slave elements 75, 85, and 95 are of the type used to connect to a fully consistent home node. However, the techniques described herein can also be applied relative to non-consistent home nodes, in which case the slave elements would be of the type used to connect to a non-consistent home node. Regardless of whether the home node is fully consistent, the techniques described herein improve overall system bandwidth utilization when multiple slave elements used to access different types of memory are connected to the same home node.

[0041] While the techniques described herein can be used with various types of interconnects, for the purposes of the following discussion, it will be assumed that interconnect 30 uses the Advanced Microcontroller Bus Architecture (AMBA) developed by Arm Limited (Cambridge, United Kingdom), and specifically the AMBA 5 CHI (Consistent Hub Interface) architecture specification. According to this specification, fully consistent requester elements are referred to as RN-F (Fully Consistent Requesting Nodes), and fully consistent home nodes are referred to as HN-F (Fully Consistent Home Nodes). According to the aforementioned specification, I / O consistent requester elements are referred to as RN-I (I / O Consistent Requesting Nodes), and such requesting nodes are arranged to generate only a subset of transactions defined by the interconnect protocol and do not require listening functionality. Similarly, non-consistent home nodes are referred to as HN-I in the AMBA 5 CHI architecture specification. Such home nodes can be arranged to process a finite subset of transactions defined by the protocol and, when acting as serialization points, do not provide a consistent point and cannot handle listenable requests. Similarly, slave elements connected to consistent home nodes (also called slave nodes) are referred to as SN-F, while slave elements connected to non-consistent home nodes are referred to as SN-I.

[0042] exist Figure 1 In the example shown, I / O conformance requester 55 can be shown as part of an interconnect and connected to an upstream master device, such as I / O master 20, via an external link. While interconnector 30 can operate according to the CHI architecture specification described above, and any connected full conformance requesters 10, 15 can be used... Figure 1 The CHI link shown is used for connection, but master devices such as I / O master device 20 can typically use a different communication protocol and will connect to I / O consistency requester 55 via a link using that other protocol. Figure 1 In the example shown, it is assumed that I / O master element 20 uses the AMBA AXI protocol specification developed by Armlimited (Cambridge, United Kingdom) and is connected to interconnector 30 via an AXI link.

[0043] The routing of access requests through the interconnector is controlled by the System Address Mapping (SAM) component, and the SAM can be provided in association with each requester element. For example... Figure 1 As shown, for a fully consistent requester such as requester 10, 15, associated SAM 40, 50 may be located within the interface 35, 45 provided by interconnect 30 for the requester element, while for an I / O consistent requester such as requester element 55, associated SAM 60 may be provided as part of the requester element in an exemplary embodiment.

[0044] For each requester element, the associated SAM is used to translate the memory address specified by the access request issued by that requester element into a target identifier, which indicates the completer element to which the access request will be routed via the communication channel. Figure 1 In the example shown, an access request destined for one of the subordinate elements 75, 85, or 95 will be routed via intermediate element 65, and therefore, for such addresses, the SAM associated with the requester element will identify intermediate element 65 as a completer element. This intermediate element (the home node) will then process the received access request and, if necessary, propagate it to the desired subordinate element. For this auxiliary communication, the home node can be considered the requester, and the subordinate element can be considered the completer, and so on. Figure 1 As shown, the home node 65 may include its own SAM 74 for determining the appropriate subordinate element to which the access request should be propagated.

[0045] When using such Figure 1 When using the method shown, it should be understood that access requests targeting any of the dependent elements 75, 85, or 95 will be propagated through the home node 65. The home node 65 has a tracking circuit 69 for tracking the processing of all pending memory access requests accepted by the home node. The tracking circuit may need to follow these memory access requests until they have been completed, for example, until an acknowledgment has been returned to the requesting element to confirm that the memory access has been performed. This may also involve returning read data to the requesting element for a read access request.

[0046] The tracking circuit 69 will only be able to track a limited number of memory access requests. Therefore, if a new memory access request is received from one of the requester elements 10, 15, 55, but the tracking circuit resources are already fully utilized to track existing pending memory access requests, the new memory access request may need to be rejected. The retry management circuit 70 can then be used to invoke the retry mechanism for the newly received memory access request. Specifically, the newly received memory access request will be effectively rejected, and the requester element will be notified accordingly. However, the retry mechanism will be used to enable the memory access request to be retried at a later time. The retry mechanism can take various forms, but for example, it may involve the requester element periodically retrying the memory access request, or performing some polling operation to determine when the home node 65 is available to receive memory access requests. Alternatively, the requester element may be arranged to simply wait until it subsequently receives a static clearance signal from the home node 65 that identifies that there is available space in the tracking circuit resources 69 to receive the retried memory access request.

[0047] However, a potential issue is that this approach may result in unutilized available bandwidth within the system. For example, various memory devices 80, 90, and 97 can operate at different speeds and therefore have varying bandwidth capabilities for handling memory access requests. This, in turn, will affect the bandwidth that slave elements 75, 85, and 95 associated with these memory devices can handle for memory access requests received from the home node 65. In this document, such slave elements connected to associated memory devices will be referred to as memory controllers, and it should be understood that the speed at which each memory controller can handle memory access requests can vary when associated with different memory devices. Specifically, a memory controller connected to a relatively high-speed memory device is typically able to handle more access requests within a given timeframe compared to a memory controller connected to a slower memory device.

[0048] Without using the techniques described herein, it is easy for the tracking circuit 69 to be fully utilized and thus unable to accept new memory access requests for a period of time, regardless of which memory device these requests target. Therefore, it is possible that, for example, a newly received memory access request targets a relatively high-speed memory device, whose associated memory controller may be capable of processing the request; however, because the tracking circuit 69 is fully utilized to process existing memory access requests, this request may be subject to a retry mechanism. Thus, it is possible that memory access requests targeting relatively slow memory can consume a disproportionately large amount of tracking circuit resources, effectively preventing the efficient processing of other memory access requests targeting faster memory devices. This leads to inefficient use of overall available bandwidth, reducing system performance and memory efficiency.

[0049] According to the technology described in this article, such as Figure 1 As shown, this problem is mitigated by using a request acceptance management circuit 67 provided as part of the home node 65. Specifically, the request acceptance management circuit 67 is arranged such that, in response to the home node 65 receiving a new memory access request, the request acceptance management circuit identifies a target slave element among a plurality of slave elements 75, 85, and 95 for the memory access request, and then determines whether to accept the memory access request based on the bandwidth capability indication of the target slave element. In this way, it is possible to ensure that a certain proportion of tracking circuit resource maintenance is available to process access requests targeting faster memory devices in order to seek more efficient use of overall memory bandwidth.

[0050] There are various ways to arrange the request acceptance management circuit 67 to obtain bandwidth capability indications for various slave elements, which will be discussed in detail later. However, in general, the slave elements themselves can continuously provide information signals indicating the available bandwidth they have for processing memory access requests. Such information signals can, for example, take a busy signal (in...). Figure 1 The busy signal (referred to as the CBUSY signal in the original text) provides an indication of the busy level of each slave element. Storage device 72 can be used by request acceptance management circuitry 67 to track busy signals received from each slave element over a period of time, for example, by maintaining the average busy level of each slave element over a selected previous time period. This allows for the dynamic allocation of available resources in tracking circuitry 69 among different slave elements, taking into account the relative busy levels of the slave elements. Thus, by way of example, if the busy level of a particular slave element exceeds a given threshold, the request acceptance management circuitry can be configured to reject subsequent access requests targeting that slave element until the busy level of that slave element drops below the threshold.

[0051] As another example of information that can be used by the request acceptance management circuit 67 to obtain bandwidth capability indication, a Quality of Service (QoS) signal can be received by the home node 65 in association with each new memory access request. For each possible QoS level, the request acceptance management circuit can have a defined association threshold that identifies the number of entries within the tracking circuit 69 that can be simultaneously used to track memory access requests with that QoS level. Thus, by way of example, a memory access request with a relatively high QoS level can use a larger proportion of the tracking circuit resources compared to the proportion of tracking circuit resources available to a memory access request with a lower QoS level. Furthermore, the QoS level can be selected by considering the memory type of the memory devices associated with various dependent elements, such that, for example, a higher QoS level is associated with a faster memory device.

[0052] As another exemplary method for providing a bandwidth capability indication of a target slave element to the request acceptance management circuitry 67, the SAM 74 within the home node 65 can be supplemented to provide one or more slave element attributes for each slave element. Therefore, when referring to the SAM 74 to determine the target slave element for a newly received memory access request, such slave element attributes can also be retrieved and then used to decide whether to accept the memory access request. As an example of slave element attributes that can be maintained within the SAM, a static bandwidth indication value can be provided for each slave element, indicating the bandwidth capability of that slave element. Different thresholds can then be defined for each static bandwidth indication value to identify the number of entries within the tracking circuitry 69 that can be used simultaneously to track memory access requests with that static bandwidth indication value for the target slave element. Similar to the aforementioned QoS-based mechanisms, this allows the proportion of entries available for memory access requests targeting relatively fast memory to be higher than the proportion of entries available for memory access requests targeting slower memory within the tracking circuit. Therefore, by delaying the processing of memory access requests targeting faster memory devices, the likelihood that tracking circuit resources will be fully utilized in processing access requests to slower memory devices is reduced, thereby mitigating the impact on performance.

[0053] Figure 2 The diagram illustrates how memory address space 100 can be viewed as comprising multiple regions 105, 110, 115. These regions can be assigned to different memory devices within the system, and thus, for example, region 105 can be associated with DDR memory 80, region 110 with HBM memory 90, region 115 with off-chip memory 97, and so on.

[0054] It should be understood that multiple regions can be allocated to a specific memory device, and these regions do not necessarily need to occupy adjacent addresses within the memory address space. Therefore, purely by way of example, a first region of memory and one or more other regions of memory not adjacent to that first region can be jointly allocated as the memory address space of DDR memory 80. Using the aforementioned SAM mechanism, when a memory address is specified by a requester element associated with a memory access request, it can be determined which region of the memory address space the address falls into, and thus which memory device the address maps to. This can be used to determine which home node 65 will receive the request, and, where appropriate, which slave element (e.g., a cache copy of reference data) will be contacted to handle the memory access request if the home node cannot directly handle it.

[0055] Figure 3 This illustrates, according to an exemplary implementation, when a new memory access request is received. Figure 1The flowchart describes the operation of the home node 65 (specifically, the request acceptance management circuitry 67 disposed therein). In step 120, it is determined whether a new memory access request has been received from one of the requester elements 10, 15, 55, and if so, the process proceeds to step 125, where the target slave element for the memory access request is identified. As described above, this process typically involves referencing the SAM 74 within the home node 65.

[0056] Additionally, the bandwidth capability indication of the target slave element is subsequently determined in step 130, and as mentioned above, there may be many mechanisms for making this determination, such as referencing the CBUSY signal received from the slave element, referencing the QoS signal provided in association with the memory access request, or referencing the static bandwidth indication value obtained from SAM 74 when the target slave element is identified in step 125.

[0057] Then, in step 135, given the bandwidth capability indication of the target slave element, it is determined whether to accept the memory access request. If not, in step 145, the retry management circuit 70 activates the retry mechanism, at which point the request is effectively rejected and needs to be retried later by the requester element. However, if it is determined in step 135 that the memory access request should be accepted, then in step 140 the memory access request is added to the available entry of the tracker circuit 69, and thereafter processed normally. In one exemplary implementation, Figure 3 The above steps can be performed by the request acceptance management circuit 67 of the home node 65, wherein the request acceptance management circuit either communicates with the tracking circuit 69 in step 140 to allocate an entry in the tracker circuit for a memory access request, or communicates with the retry management circuit 70 in step 145 to activate the retry mechanism.

[0058] Figure 4A This illustrates how the CBUSY signals provided by slave elements 75, 85, and 95 can be used by the home node 65 in one exemplary embodiment. In step 150, the CBUSY signals are monitored from the different slave elements, and in step 155, a bandwidth capability indication for each slave element is calculated based on the received CBUSY signals, and this indication is maintained in memory 72 by the request acceptance management circuitry for later reference when considering new memory access requests. While in one exemplary arrangement the storage device could be used only to maintain the latest CBUSY indication from each slave element, in one exemplary embodiment, the CBUSY signals received over a period of time are averaged to provide an indication of the busy level of each memory device within a previous time window of a selected width.

[0059] Figure 4B This shows when using... Figure 4AWhen maintaining CBUSY information using this method, how should it be implemented? Figure 3 The flowchart shows the decision made in step 135. In step 160, it is determined whether there are any free entries in the tracker circuit 69. If not, the request is rejected in step 165 by activating a retry mechanism. However, assuming that at least one free entry exists in the tracker circuit, the process proceeds to step 170, where it is determined whether the bandwidth capability indicator of the target slave element obtained from the storage device 72 indicates that the target slave element is operating below a busy threshold. If not, the request is rejected again in step 165; otherwise, the request is accepted in step 175, and an entry is allocated within the tracker circuit to store the details of the memory access request. When using the techniques described herein, it has been found that this can significantly reduce the chance that there are no free entries in the tracker circuit, and thus increase overall system performance by better utilizing the bandwidth capabilities of various memory devices.

[0060] By using the aforementioned CBUSY indication, it becomes possible to dynamically allocate the available resources of the tracking circuitry while taking into account the relative busy levels of various slave components. Once a slave component begins to exhibit busyness levels above a certain threshold, the request acceptance management circuitry can temporarily reject subsequent memory access requests targeting that slave component, allowing these memory access requests to be retried once the slave component's busyness has decreased. Therefore, this preserves available space for memory access requests within the tracking circuitry, identifies other slave components that may be less busy, and thus positions them in a better position to handle additional access requests.

[0061] As an alternative or supplement to using the CBUSY signal to provide bandwidth capability indication, a QoS signal associated with each new memory access request can be provided to the home node 65. Specifically, such QoS information can be added in association with the memory access request based on information retrieved from SAMs 40, 50, 60 associated with the requester elements 10, 15, 55 that issued each new memory access request.

[0062] Figure 5A This diagram schematically illustrates the information that can be provided for each requester element 10, 15, 55 in system address maps 40, 50, and 60. SAM 200 includes multiple entries 205, and each entry provides multiple fields 210, 215, and 220. Field 210 is used to identify address ranges, and the information in field 210 of the various entries 205 can be used to identify various different programmable regions within the memory address space. In one exemplary embodiment, the division of the address space is not necessarily static, and therefore different address ranges can be defined within entries 205 at different points in time.

[0063] For an address range identified within field 210 of a specific entry 205, the corresponding field 215 can be used to specify a target identifier (target ID), which indicates the completer element to be used for access within that address range. Figure 1 The addresses within the memory devices 80, 90, and 97 shown are for target accesses, assuming these accesses are routed via home node 65, and therefore the completer element identified by the target ID will be home node 65. This ensures that all such access requests are propagated from interfaces 35, 45, or requester element 55 through the interconnect's communication channel to home node 65 for subsequent processing.

[0064] like Figure 5A As shown, the third field 220 can be used to specify the memory type of the memory device associated with the address region in field 210. This memory type information can then be used to determine the appropriate QoS value for a memory access request, for example, by associating a higher QoS value with a memory type involving faster memory. While the QoS level determination can be performed based on the memory type information obtained from field 220, the actual QoS value can be populated into the memory type field 220 if needed, so that the QoS value can be obtained directly from a lookup within SAMs 40, 50, and 60.

[0065] Figure 5B The process can be performed by the request acceptance management circuit 67 to determine whether to accept a memory access request based on a specified QoS value of the newly received memory access request. In step 250, it is determined whether there are any free entries in the tracker circuit 69; if not, the request is rejected in step 255. As previously mentioned, this typically involves activating a retry mechanism using the retry management circuit 70.

[0066] Assuming at least one idle entry exists in the tracker circuitry, the process proceeds to step 260, where a QoS indication (also referred to herein as a QoS value) associated with the memory access request is identified. Furthermore, the home node 65 can be arranged to maintain such information, for example, by storing an entry threshold for each possible QoS value in storage device 72. Therefore, in step 260, in addition to identifying the QoS value associated with the memory access request, an entry threshold for that QoS value is also obtained. This identifies the maximum number of entries available within the tracking circuitry at any given time to process an access request for the selected QoS value.

[0067] Therefore, in step 265, it is determined whether the number of entries currently tracking memory access requests with the identified QoS value has reached an entry threshold. If so, the request is rejected in step 255; otherwise, the request is accepted in step 270, and information about the memory access request is added to the free entries within the tracking circuit 69. It should be understood that this method provides a static partitioning of available tracking circuit resources by associating different QoS levels with different types of memory devices and controlling the allowed occupancy level within the tracking circuit for memory access requests with different QoS levels. Through this method, it is possible to limit the number of entries within the tracking circuit available for accessing specific types of memory devices, thus, for example, avoiding disproportionate use of available tracking circuit resources for memory access to relatively slow memory, which could inhibit efficient utilization of bandwidth available for handling access to faster memory devices.

[0068] As an alternative to or supplement to the above method, when deciding whether to accept or reject a newly received memory access request, the request acceptance management circuit 67 can also use another information source. Specifically, such as... Figure 6A As shown, the SAM 74 associated with the home node 65 can be modified to provide additional information indicating the bandwidth capabilities of different slave elements. Specifically, the SAM 300 may include multiple entries 305, each providing multiple fields 310, 315, and 320. Field 310 can be used to specify a programmable address range, and for any specified address range in field 310, the corresponding field 315 provides a target identifier that indicates the slave element to be used for any access to that address range. This allows the home node 65 to determine which of these slave elements it needs to communicate with if a memory access request needs to be propagated to slave elements 75, 85, and 95 for processing. It should be noted that it is not always necessary to propagate memory access requests to slave elements, as there may be situations where the home node can directly serve the memory access request. For example, as previously described, each requester element may include a local cache structure, and the data requested by a particular memory access request may be available from one of these cache structures. In this case, the home node can directly obtain the data and return it to the requesting element without needing to access the slave element. However, when access to a dependent element is required, the information in field 315 will identify which dependent element to contact.

[0069] Furthermore, field 320 may provide one or more slave element attributes associated with the slave element identified by the target identifier in field 315. Slave element attributes may take various forms, but in one exemplary implementation, a static bandwidth indication value may be provided, which itself may be determined based on knowledge of the type of memory device associated with the slave element and thus, for example, the speed at which access can be performed within that memory device. According to this method, the bandwidth indication value is static in the sense that it is indicated by the type of memory device associated with the slave element, and therefore a higher bandwidth indication value may be provided for slave elements associated with relatively high-speed memory devices compared to slave elements associated with relatively low-speed memory devices.

[0070] Figure 6B The steps that can be performed when determining whether to accept a memory access request based on this static bandwidth indication value information are illustrated. In step 350, it is determined whether there are any free entries in the tracker circuit 69; if not, the request is rejected in step 355. However, assuming at least one free entry exists, in step 360, SAM 74, 300 are referenced to determine the target slave element and its static bandwidth indication value. Furthermore, entry threshold information for this static bandwidth indication value is obtained. In substantially the same manner as the aforementioned QoS values, the request acceptance management circuit can maintain this information, for example, by maintaining individual entry thresholds for various different possible static bandwidth indication values ​​within memory 72, and thus, once the static bandwidth indication value of the access request has been obtained from the SAM, the corresponding entry threshold can also be retrieved.

[0071] Then, in step 365, it is determined whether the number of memory access request entries with the static bandwidth indication value currently being tracked for the target slave device has reached the entry threshold level. If so, the request is rejected in step 355; otherwise, the request is accepted in step 370, and thus at this point, one of the free entries within the tracker circuitry is allocated to store information about the newly received memory access request. In almost the same manner as the aforementioned QoS mechanism, it should be understood that this mechanism allows for the static allocation of the tracking circuitry's resources based on the type of memory device being accessed, in order to seek to ensure that access to slower memory devices does not disproportionately utilize the tracking circuitry's resources, and therefore to seek to ensure that the tracking circuitry's resources remain available for access to higher-speed memory devices.

[0072] Figure 7The above-described process, which can be used within the home node 65, is illustrated schematically. When a request is received from a requester element via path 400, the bandwidth management unit (BMU) 405 (which may take the form of the aforementioned request acceptance management circuitry 67) can be used to determine whether to accept or reject the request based on certain information that can be used to derive an indication of the bandwidth capability of the target slave element associated with the request. As mentioned above, the CBUSY signal received from various slave elements can be used, and alternatively or additionally, QoS information provided with the memory access request can also be used for this purpose. Furthermore, slave element attributes obtained from SAM 74 (in Figure 7 The information referred to as MC (Memory Controller) capability information may optionally or additionally be used to provide an indication of the bandwidth capability of the target slave element.

[0073] Based on the analysis of the bandwidth management unit 405, it is determined whether an entry should be allocated for the current memory access request within the request tracker. If so, a free entry is allocated within the tracker 415 to store the latest memory access request. Figure 7 As illustrated in the diagram, at any given time, the request tracker circuitry can track requests targeting various types of memory, and when using the techniques described herein, the tracker circuitry resources can be managed to ensure that an appropriate proportion of resources are available for accessing high-speed memory, such as the aforementioned HBM memory.

[0074] If it is determined that the newly received request should not be accepted, the retry management procedure 420 is invoked, causing a retry response to be sent to the requester element via path 425.

[0075] Figure 8A An exemplary system 500 is illustrated, comprising multiple requester elements 505, 510, and 515 that issue access requests seeking access to various slave elements 530, 535, and 540 via a home node 525 within interconnect 520. In this example, it is assumed that slave element 530 is associated with DDR memory, slave element 535 with HBM memory, and slave element 540 is a CXSA slave element associated with off-chip memory 545 communicating via a CCIX link. Each of the slave elements 530, 535, and 540 may maintain its own local queues 532, 537, and 542 to track memory access requests currently being processed by those slave elements. Furthermore, within the home node 525, tracking circuitry may include a shared queue 526 that tracks all pending access requests it has accepted and processed. This may include not only pending access requests it has accepted but not yet issued to slave elements, but also pending access requests it has issued to slave elements but not yet fully processed by those slave elements.

[0076] In this example, it is assumed that the off-chip memory 545 has the slowest access speed, the DDR memory accessed by slave element 530 has a medium access speed, and the HBM memory accessed by slave element 535 has the fastest access speed. Although Figure 8A (And actually, this will be discussed later) Figure 8B The diagram illustrates access requests to each subordinate element issued by different requester elements, but this is for illustrative purposes only, and it should be noted that in one exemplary embodiment, each requester element 505, 510, 515 can target any memory device and therefore can issue access requests for routing to any of the subordinate elements 530, 535, 540.

[0077] Figure 8A This illustrates potential problems that may arise during busy periods without employing the techniques described herein, particularly when a large number of accesses target relatively slow memory devices. Specifically, a significant portion of the available space in the shared queue 526 of the tracking circuitry within home node 525 can be occupied by memory access requests targeting slower memory devices, leaving little space for access requests belonging to faster memory devices. Thus, while slave elements 530, 540 associated with slower memory devices can be utilized relatively fully, slave element 535 can be used only minimally, and this slave element has a large amount of spare capacity in its own local queue 537. Therefore, in this situation, the available bandwidth for accessing HBM memory is not fully utilized, resulting in degraded overall system performance.

[0078] Figure 8B The same exemplary system is illustrated, but in which the home node 525 includes the aforementioned bandwidth management unit 527 and is therefore able to proactively decide which memory access requests to accept, taking into account the bandwidth capabilities of the slave elements to which these memory access requests are directed. Thus, the techniques described herein prevent the shared queue 526 from being disproportionately occupied by accesses to slower memory devices, allowing for more efficient utilization of the system's overall memory access resources. Specifically, as shown, local queues 532 and 542 within slave elements 530 and 540 may no longer be fully utilized, but by employing the adaptive partitioning scheme described herein, better utilization of queue 537 associated with fast memory devices can be achieved. This approach allows for more efficient use of the available memory bandwidth within the system when the home node communicates with memory controllers associated with different types of memory devices, thereby improving overall system performance.

[0079] As can be understood from the above description, the techniques described herein mitigate the chance of traffic to slower memory controllers overwhelming shared resources in interconnects, thereby reducing the likelihood that faster memory throughput will not be fully utilized. According to the techniques described herein, shared resources at the home node can be dynamically partitioned based on the performance capabilities of the target endpoint, thereby improving overall system performance and memory efficiency.

[0080] By using the techniques described herein, these techniques can be used to maximize overall system bandwidth in the presence of memory controllers with varying bandwidth capabilities. (See reference...) Figure 8B As illustrated by an example, the bandwidth management unit can control the allocation of access requests to the shared tracker queue at the home node, ensuring that the shared tracker is mostly occupied by transactions targeting the faster memory controller (e.g., the HBM controller), while transactions targeting the slower memory controller receive less usage. This allows for more optimized utilization of resources within the HBM memory controller, thereby improving overall system performance.

[0081] In this application, the phrase "configured as..." is used to mean that the elements of the device have a configuration capable of performing the defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operation.

[0082] While exemplary embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments, and various changes, additions, and modifications can be made therein by those skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims. For example, features of the dependent claims may be combined with features of the independent claims in various ways without departing from the scope of the invention.

Claims

1. An apparatus for processing memory access requests, the apparatus comprising: An interconnect for coupling a plurality of requester elements to a plurality of slave elements, the plurality of requester elements being arranged to issue memory access requests for processing by the plurality of slave elements; as well as An intermediate element, disposed within the interconnect, serves as a serialization point for ordering memory access requests issued by the plurality of requester elements via the intermediate element. The intermediate element includes a tracking circuit shared among the plurality of subordinate elements and having multiple entries to track the processing of the memory access requests accepted by the intermediate element; The intermediate element includes an address mapping circuit configured to map a specified address range to a target identifier for a target slave element to be used for accessing the address range, and to information indicating the bandwidth capability of the target slave element. The intermediate element further includes a request acceptance management circuit, which, in response to the intermediate element receiving a given memory access request, is configured to use the address mapping circuit to identify the target slave element among the plurality of slave elements for the given memory access request, and to determine whether the given memory access request will be accepted by the intermediate element acting as a serialization point by determining whether there are free entries in the tracking circuit that are available for the given memory access request without causing an entry threshold to be exceeded. The entry threshold depends on information provided by the address mapping circuit indicating the bandwidth capability of the target slave element.

2. The apparatus according to claim 1, further comprising: A retry management circuit is configured to communicate with the requester element that issued the given memory access request when the request acceptance management circuit indicates that the given memory access request will not be accepted, so as to implement a retry mechanism for the given memory access request.

3. The apparatus according to claim 1 or claim 2, wherein: Each slave element has an associated memory device, and the information indicating the bandwidth capability of the target slave element depends on the associated memory device.

4. The apparatus of claim 3, wherein the bandwidth capability of the target slave element depends on the memory type of the associated memory device.

5. The apparatus of claim 1 or claim 2, wherein the request acceptance management circuit is arranged to determine whether a given memory access request will be accepted by the intermediate element based on a busy signal emitted by each slave element to identify the busy level of that slave element.

6. The apparatus according to claim 5, wherein: The request acceptance management circuit is configured to determine that a given memory access request will be accepted by the intermediate element when a free entry is available in the tracking circuit for the given memory access request, and the busy signal of the target slave element indicates that the target slave element operates below a given busy threshold.

7. The apparatus of claim 1, wherein the request acceptance management circuitry is arranged to maintain information indicating the bandwidth capability of each slave element based on information signals received from each slave element within a previously selected time period.

8. The apparatus according to claim 1, further comprising: A requester address mapping circuit, associated with each requester element, translates a memory address specified by a memory access request issued by the requester element into a target identifier for routing the memory access request through the interconnect. The requester address mapping circuit provides memory type information for different memory address ranges, and the information indicating bandwidth capability is determined based on the memory type information including the memory address range specified by the memory access request.

9. The apparatus of claim 1, wherein the information provided by the address mapping circuit indicating the bandwidth capability of the slave element includes a bandwidth indication value.

10. The apparatus of claim 9, wherein the bandwidth indication value depends on the memory type of the memory device associated with the slave element.

11. The apparatus according to claim 9 or claim 10, wherein: The tracking circuit has multiple entries for tracking memory access requests; For each bandwidth indication value, an entry threshold is defined, which identifies the number of entries within the tracking circuit capable of simultaneously tracking memory access requests from target dependent elements having the bandwidth indication value; and The request acceptance management circuit is configured to determine that a given memory access request will be rejected when there is no available entry in the tracking circuit, taking into account the entry threshold of the bandwidth indication value of the target slave element of the given memory access request provided by the address mapping circuit.

12. A method for processing a memory access request, the method comprising: An interconnect is provided to couple a plurality of requester elements to a plurality of slave elements, the plurality of requester elements being arranged to issue the memory access request for processing by the plurality of slave elements; An intermediate element disposed within the interconnect is used as a serialization point for sequencing the memory access requests issued by the plurality of requester elements via the intermediate element. The processing of the memory access request accepted by the intermediate element is tracked within a tracking circuit shared among the plurality of subordinate elements and having multiple entries. Within the address mapping circuit of the intermediate element, a specified address range is mapped to a target identifier for the target slave element to be used for accessing the address range, and information is mapped to indicate the bandwidth capability of the target slave element. as well as In response to the intermediate element receiving a given memory access request, the address mapping circuit identifies the target slave element among the plurality of slave elements for the given memory access request, and determines whether the given memory access request will be accepted by the intermediate element acting as a serialization point by determining whether there is a free entry in the tracking circuit that can be used for the given memory access request without causing an entry threshold to be exceeded. The entry threshold depends on information provided by the address mapping circuit indicating the bandwidth capability of the target slave element.

13. An apparatus for processing a memory access request, the apparatus comprising: An interconnect component for coupling a plurality of requester elements to a plurality of slave elements, the plurality of requester elements being arranged to issue memory access requests for processing by the plurality of slave elements; as well as An intermediate element component, disposed within the interconnect component, serves as a serialization point for ordering memory access requests issued by the plurality of requester elements via the intermediate element component. The intermediate element component includes a tracking component shared among the plurality of subordinate elements and having a plurality of entries, the tracking component being used to track the processing of the memory access requests accepted by the intermediate element component; The intermediate element component includes an address mapping component configured to map a specified address range to a target identifier for indicating a target slave element to be used for accessing the address range, and to information indicating the bandwidth capability of the target slave element. The intermediate element component further includes a request acceptance management component, which is configured to, in response to the intermediate element component receiving a given memory access request, use the address mapping component to identify the target slave element among the plurality of slave elements for the given memory access request, and to determine whether the given memory access request will be accepted by the intermediate element component acting as a serialization point by determining whether there is a free entry in the tracking component that is available for the given memory access request without causing an entry threshold to be exceeded, the entry threshold depending on information provided by the address mapping component indicating the bandwidth capability of the target slave element.

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