Learning device, inference device, tool chain for development of programmable logic device, learning method, and inference method

Abstract

The data acquisition unit (31) acquires resource usage rate data of each process of a tool chain for development of a programmable logic device and timing margin information at the time of process mapping. The inference unit (32) outputs parameters for repeated synthesis for successful placement and routing, using a learned model for inferring parameters for repeated synthesis given by the tool chain for development of the programmable logic device for successful placement and routing, from the resource usage rate data of each process and the timing margin information at the time of process mapping acquired by the data acquisition unit (31).

Description

Technical Field

[0001] This invention relates to a toolchain for developing learning devices, inference devices, and programmable logic devices. Background Technology

[0002] In recent years, with the advancement of semiconductor technology generations, the cost of developing custom ASICs (Application Specific Integrated Circuits) is increasing. Therefore, the demand for programmable logic devices such as FPGAs (Field Programmable Gate Arrays) or DRPs (Dynamic Reconfigurable Processors) is rising.

[0003] The toolchain for developing user application circuits using these programmable logic devices generally includes steps such as high-order synthesis, logic mapping, and configuration routing. Among these, configuration routing is particularly time-consuming. To complete configuration routing, it is necessary to repeatedly test and adjust constraints such as clock frequency and input / output delay settings, as well as tool options, after various changes. Especially when developing large-scale circuits using cost-controlled devices, the time required for testing can significantly impact the development process.

[0004] For example, in the EDA tool for semiconductor circuit design in Patent Document 1, to improve performance, the feature vector of the circuit is extracted, and a first configuration routing topology recommended by the feature library generation tool is referenced. Patent Document 1 also describes a method for generating another recommended configuration routing topology based on the first configuration routing topology.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: US Patent No. 10,437,954 Summary of the Invention

[0008] The problem that the invention aims to solve

[0009] Patent Document 1 derives the characteristic quantities of the circuit and recommends an appropriate topology for configuring the wiring. However, the method described in Patent Document 1 is specifically for ASIC circuit design and does not take into account its application to programmable logic devices.

[0010] The purpose of this invention is to provide a toolchain for developing learning devices, inference devices, and programmable logic devices, which enables high-speed configuration and routing when developing user application circuits using programmable logic devices.

[0011] Methods for solving problems

[0012] The learning apparatus of the present invention comprises: a data acquisition unit that acquires learning data, the learning data including resource utilization data and timing margin information for each process of a development toolchain for a programmable logic device, and the target clock frequency and iterative synthesis parameters of the development toolchain for the programmable logic device from the resource utilization data and timing margin information for each process; and a model generation unit that uses the learning data to generate a learned model, the learned model being used to infer the iterative synthesis parameters given by the development toolchain for the programmable logic device to enable successful configuration and routing based on the resource utilization data and timing margin information for each process of the development toolchain for the programmable logic device.

[0013] The inference apparatus of the present invention comprises: a data acquisition unit that acquires resource utilization data and timing margin information for process mapping of each process in a development toolchain for a programmable logic device; and an inference unit that uses a learned model to output iterative synthesis parameters for successful configuration and routing based on the resource utilization data and timing margin information for each process acquired by the data acquisition unit, wherein the learned model is used to infer iterative synthesis parameters for successful configuration and routing given by the development toolchain for a programmable logic device based on the resource utilization data and timing margin information for each process.

[0014] The learning apparatus of the present invention comprises: a data acquisition unit that acquires learning data, the learning data including a target clock frequency of a development toolchain for a programmable logic device, parameters for iterative synthesis, resource utilization data for each process of the development toolchain for the programmable logic device, and timing margin information during process mapping; and a model generation unit that uses the learning data to generate a learned model, the learned model being used to infer the success probability of routing configuration based on the target clock frequency of the development toolchain for the programmable logic device, the parameters for iterative synthesis, the resource utilization data for each process, and the timing margin information during process mapping.

[0015] The inference apparatus of the present invention comprises: a data acquisition unit that acquires the target clock frequency of a development toolchain for a programmable logic device, iterative synthesis parameters, resource utilization data of each process in the development toolchain for the programmable logic device, and timing margin information during process mapping; and an inference unit that uses a learned model to output a successful probability of configuration routing based on the target clock frequency, iterative synthesis parameters, resource utilization data of each process, and timing margin information during process mapping acquired by the data acquisition unit. The learned model is used to infer the successful probability of configuration routing based on the target clock frequency, iterative synthesis parameters, resource utilization data of each process, and timing margin information during process mapping.

[0016] Invention Effects

[0017] According to the present invention, when developing user application circuits using programmable logic devices, high-speed configuration routing can be achieved. Attached Figure Description

[0018] Figure 1 This is a structural diagram of the learning device 10 related to the toolchain for developing programmable logic devices in Embodiment 1.

[0019] Figure 2 This is a flowchart related to the learning process of the learning device 10 in Implementation 1.

[0020] Figure 3 This is a structural diagram of the inference device 30 related to the toolchain for developing the programmable logic device in Embodiment 1.

[0021] Figure 4 This is a flowchart illustrating the reasoning process of the repeated synthesis parameters performed by the reasoning device 30 in Embodiment 1.

[0022] Figure 5 This is a diagram showing the structure of the learning device 10A related to the toolchain for developing programmable logic devices in Embodiment 2.

[0023] Figure 6 This is a flowchart related to the learning process of the learning device 10A in Embodiment 2.

[0024] Figure 7 This is a diagram showing the structure of the inference device 30A related to the toolchain for developing the programmable logic device in Embodiment 2.

[0025] Figure 8 This is a flowchart illustrating the reasoning process that represents the success probability of the configuration wiring of the reasoning device 30A in Embodiment 2.

[0026] Figure 9This is a diagram showing the hardware structure of the development toolchain 40 for learning devices 10, 10A, inference devices 30, 30A, or programmable logic devices. Detailed Implementation

[0027] The embodiments are described below with reference to the accompanying drawings.

[0028] Implementation Method 1

[0029] Figure 1 This is a structural diagram of a learning device 10 related to the toolchain for developing programmable logic devices in Embodiment 1. The learning device 10 includes a data acquisition unit 12 and a model generation unit 13.

[0030] The data acquisition unit 12 acquires the target clock frequency, parameters for iterative synthesis, resource utilization data for each technology, and timing slack information during technology mapping as learning data.

[0031] The target clock frequency refers to the clock frequency that enables the programmable logic device to actually operate.

[0032] Iterative synthesis refers to performing multiple configuration routing trials to achieve the target clock frequency after configuration routing. In iterative synthesis, for example, the target clock frequency or a clock frequency higher than the target clock frequency is used as the center frequency X [MHz]. A threshold range σ [MHz] is set on both the lower and higher frequency sides, i.e., a range from (X-σ) [MHz] to (X+σ) [MHz]. Configuration routing is repeatedly tried while varying the step value Δ [MHz] within this range. The number of iterations is (2σ / Δ+1). The parameters used in iterative synthesis are X, σ, and Δ as mentioned above. The lower limit (X-σ) is set to a value greater than the target clock frequency.

[0033] Resource utilization data for each process represents the ratio of the number of used computing resources to the number of available computing resources within a programmable logic device.

[0034] Resource utilization data for each process, such as the result of process mapping for programmable logic devices, includes the utilization of ALUs (Arithmetic Logic Units) of LEs (Logic Element) or PEs (Processing Element), the utilization of multiplexers, adders, subtractors, and arithmetic shifters, etc.

[0035] The timing margin information during process mapping, as a result of static timing analysis after process mapping, includes timing redundancy. This timing redundancy is the timing redundancy of the largest signal propagation delay time (critical path) among the signal propagation delay times between FFs (Flip Flops) within the programmable logic device relative to the cycle time, given a cycle time determined by the target clock frequency. For example, with a cycle time of 10.0 ns determined by a target clock frequency of 100 MHz and a signal propagation delay time between FFs (Flip Flops) in the critical path of 7.0 ns, the timing margin is 10.0 ns - 7.0 ns = 3.0 ns.

[0036] The model generation unit 13 uses the learning data acquired by the data acquisition unit 12, which includes the target clock frequency, iterative synthesis parameters, resource utilization data for each process, and timing margin information during process mapping, to generate a learned model. This learned model is used to infer the iterative synthesis parameters given by the development toolchain for programmable logic devices to enable successful configuration and routing, based on the resource utilization data for each process and the timing margin information during process mapping of the development toolchain for programmable logic devices.

[0037] The parameters for iterative synthesis refer to the clock center frequency X [MHz] used to implement the aforementioned iterative synthesis, the threshold σ [MHz] used to determine the frequency range of the low-frequency side and the high-frequency side, and the step size Δ [MHz] used to iteratively test the configuration routing while varying within this frequency range.

[0038] "Parameters for iterative synthesis to ensure successful configuration routing" refers to the combination of the center clock frequency at which the circuit after configuration routing can achieve the target signal processing performance, and the threshold σ [MHz] and step size Δ [MHz] that satisfy the conditions of maximizing the probability of success for each configuration routing result during iterative synthesis and minimizing the number of configuration routing trials.

[0039] To meet the above conditions, for example, by selecting a smaller threshold σ to narrow the frequency range, or by selecting a larger step value Δ to reduce the number of configuration routing trials, the combination of threshold σ [MHz] and step value Δ [MHz] is determined.

[0040] It means that the maximum number of usable computing resources is not exceeded, the number of interconnect resources used does not exceed the maximum number of interconnect resources available on the programmable logic device, and the maximum value of the signal transmission delay time between FFs (Flip Flops) does not exceed the cycle time determined by the target clock frequency.

[0041] The learning algorithm used by the model generation unit 13 can employ well-known algorithms such as supervised learning, unsupervised learning, or reinforcement learning. As an example, the application of reinforcement learning will be explained. In reinforcement learning, an agent (actual agent) within an environment observes the current state (parameters of the environment) and decides on the appropriate action. The environment dynamically changes according to the agent's actions, and rewards are given to the agent based on these changes. The agent repeatedly performs this reinforcement learning, learning a course of actions that yields the highest reward. Q-learning or TD-learning (Temporal Difference Learning), representative methods of reinforcement learning, can be used. For example, in the case of Q-learning, the usual update formula for the action value function Q(s, a) is represented by equation (1).

[0042]

[0043] In equation (1), st represents the state of the environment at time t. at represents the behavior at time t. Through behavior at, the state changes to st+1. rt+1 represents the reward obtained through this change in state. γ represents the discount rate. α represents the learning coefficient. It is set to the range of 0 < γ ≤ 1 and 0 < α ≤ 1. The parameter used for iterative synthesis is behavior at. The resource utilization data of each process and the time margin information during process mapping are the state st. In Q-learning, the optimal behavior at under state st at time t is learned.

[0044] In the update formula shown in equation (1), if the behavior value Q of behavior a with the highest Q value at time t+1 is greater than the behavior value Q of behavior a performed at time t, then the behavior value Q is increased; conversely, the behavior value Q is decreased. In other words, the behavior value function Q(s, a) is updated in a way that makes the behavior value Q of behavior a at time t close to the optimal behavior value at time t+1. Thus, the optimal behavior value in a certain environment is sequentially transferred to the behavior values ​​in its previous environments.

[0045] As described above, when a learned model is generated through reinforcement learning, the model generation unit 13 has a reward calculation unit 14 and a function update unit 15.

[0046] The compensation calculation unit 14 calculates the compensation based on the target clock frequency and parameters for iterative synthesis, resource utilization data for each process, and timing margin information during process mapping. The compensation calculation unit 14 calculates the compensation r based on the configuration routing results. For example, the compensation calculation unit 14 increases the compensation r (e.g., gives a compensation of "1") when configuration routing is successful, and decreases the compensation r (e.g., gives a compensation of "-1") when configuration routing fails.

[0047] Specifically, when the routing configuration is successful, the reward calculation unit 14 increases the reward proportionally to the redundancy (%) of the utilization rate of LEs or PEs within the programmable logic device, or proportionally to the redundancy (%) of interconnect resources within the programmable logic device, or proportionally to the timing redundancy (positive slack value) of the largest signal transmission delay time (critical path) among the signal transmission delay times between FFs (Flip Flops) within the programmable logic device relative to the cycle time. The reward calculation unit 14 can either combine multiple elements of these three reward-increasing factors (redundancy of computing resources, redundancy of interconnect resources, and timing redundancy of the critical path) to increase the reward, or multiply each element by a weighting coefficient as needed to increase the reward.

[0048] In the event of a configuration routing failure, the compensation calculation unit 14 reduces the compensation proportionally to the overflow level of LEs or PEs within the programmable logic device (PLD), or proportionally to the overflow level of interconnect resources within the PLD. Alternatively, if no resources overflow, the compensation is reduced proportionally to the timing violation level (Negative Slack value) or the total negative slack value (Total Negative Slack value) relative to the cycle time of the largest signal transmission delay time (critical path) among the signal transmission delay times between FFs (Flip Flops) within the PLD. The compensation calculation unit 14 can reduce compensation by combining multiple elements from these three factors (overflow level of computing resources, overflow level of interconnect resources, and timing violation), or by multiplying each element by a weighting coefficient as needed.

[0049] The function update unit 15 updates the function used to determine the parameters for iterative synthesis according to the reward calculated by the reward calculation unit 14 and outputs it to the learned model storage unit 20. These parameters for iterative synthesis are used to ensure successful placement and routing. For example, in the case of Q-learning, the function update unit 15 uses the behavioral value function Q(st, at) represented by equation (1) as the function for calculating the parameters for iterative synthesis, which are used to ensure successful placement and routing.

[0050] The above learning process is repeated. The learned model storage unit 20 stores the behavior value function Q(st, at) updated by the function update unit 15, which is the learned model.

[0051] Next, use Figure 2 The learning process performed by the learning device 10 will be explained. Figure 2This is a flowchart related to the learning process of the learning device 10 in Implementation 1.

[0052] In step S101, the data acquisition unit 12 acquires the target clock frequency, parameters for iterative synthesis, resource utilization data for each process, and timing margin information during process mapping as learning data.

[0053] In step S102, the model generation unit 13 calculates the reward based on the target clock frequency, iterative synthesis parameters, resource utilization data for each process, and timing margin information during process mapping. Specifically, the reward calculation unit 14 obtains the target clock frequency, iterative synthesis parameters, resource utilization data for each process, and timing margin information during process mapping, and decides whether to increase or decrease the reward based on the routing configuration. If the reward calculation unit 14 determines that the reward should be increased, the process proceeds to step S103. If the reward calculation unit 14 determines that the reward should be decreased, the process proceeds to step S104.

[0054] In step S103, the reward calculation unit 14 increases the reward.

[0055] In step S104, the compensation calculation unit 14 reduces the compensation.

[0056] In step S105, the function update unit 15 updates the behavior value function Q(st, at) represented by equation (1) stored in the learned model storage unit 20 according to the reward calculated by the reward calculation unit 14.

[0057] The learning device 10 repeatedly executes the above steps S101 to S105, and stores the generated behavioral value function Q(st, at) as a learned model.

[0058] In this embodiment, the learning device 10 stores the learned model in a learned model storage unit 20 provided outside the learning device 10, but the learned model storage unit 20 may also be provided inside the learning device 10.

[0059] Figure 3 This is a structural diagram of an inference device 30 related to the toolchain for developing the programmable logic device in Embodiment 1. The inference device 30 includes a data acquisition unit 31 and an inference unit 32.

[0060] The data acquisition unit 31 acquires resource utilization data for each process and timing margin information during process mapping.

[0061] The inference unit 32 reads the learned model from the learned model storage unit 20. The learned model is used to infer the iterative synthesis parameters given by the development toolchain for programmable logic devices to enable successful configuration and routing, based on the resource utilization data of each process in the development toolchain for programmable logic devices and the timing margin information during process mapping.

[0062] The inference unit 32 uses the data acquired by the data acquisition unit 31 and the learned model to infer iterative synthesis parameters for successful configuration routing. That is, by inputting the resource utilization data of each process and the timing margin information during process mapping acquired by the data acquisition unit 31 into the learned model, the inference unit 32 can infer iterative synthesis parameters suitable for the resource utilization data and timing margin information during process mapping of each process for successful configuration routing.

[0063] For example, the inference unit 32 reads the behavior value function Q(st, at) from the learned model storage unit 20 as the learned model. Based on the behavior value function Q(s, a), the inference unit 32 obtains iterative synthesis parameters (behavior at) for each process's resource utilization data and timing margin information (state st) during process mapping. The iterative synthesis parameters contained in this behavior at are iterative synthesis parameters used to ensure successful configuration routing.

[0064] In this embodiment, it is described that the learned model is used to output the parameters for repeated synthesis to enable successful configuration and routing, based on the model generation unit 13 of the development toolchain for programmable logic devices. However, it is also possible to obtain the learned model from the development toolchain for other programmable logic devices and output the parameters for repeated synthesis to enable successful configuration and routing based on the learned model.

[0065] Next, use Figure 4 This describes the processing used to obtain parameters for iterative synthesis, which are used to ensure successful configuration routing.

[0066] Figure 4 This is a flowchart illustrating the reasoning process of the repeated synthesis parameters performed by the reasoning device 30 in Embodiment 1.

[0067] In step S201, the data acquisition unit 31 acquires the resource utilization data of each process and the timing margin information during process mapping.

[0068] In step S202, the inference unit 32 inputs the resource utilization data of each process and the timing margin information for process mapping into the learned model stored in the learned model storage unit 20.

[0069] In step S203, the inference unit 32 obtains iterative synthesis parameters for successful configuration and routing based on the learned model. The inference unit 32 outputs the obtained iterative synthesis parameters for successful configuration and routing to the development toolchain of the programmable logic device.

[0070] In step S204, the development toolchain for the programmable logic device uses the output parameters for successful configuration routing and the circuit structure information based on the process mapping to repeatedly attempt configuration routing using the actual PE (Processing Element), LE (Logic Element), SRAM (Static Random Access Memory), and interconnect resources on the programmable logic device, i.e., to perform iterative routing. At this time, the synthesis constraints for iterative routing are the parameters for successful configuration routing output in step S203. Using the center frequency X [MHz], threshold σ [MHz], and step size Δ [MHz], a frequency range from (X-σ) [MHz] to (X+σ) [MHz] is set, and the clock frequency changes by the step size Δ [MHz] each time within this range. The number of iterations for iterative routing is (2σ / Δ+1). Therefore, by performing configuration routing with the fewest possible attempts, configuration routing can be successfully performed at clock frequencies above the target signal processing performance within a short time.

[0071] In this embodiment, the application of reinforcement learning to the learning algorithm used in the inference department has been described, but it is not limited to this. Regarding the learning algorithm, in addition to reinforcement learning, supervised learning, unsupervised learning, or semi-supervised learning can also be applied.

[0072] The learning algorithm used in the model generation unit 13 can also be deep learning, which learns by extracting the feature quantities themselves. Alternatively, machine learning can be performed using other well-known methods, such as neural networks, genetic programming, functional logic programming, or support vector machines.

[0073] The learning device 10 and the inference device 30 can, for example, be devices connected to and independent of the development toolchain for the programmable logic device via a network. Alternatively, the learning device 10 and the inference device 30 can be built into the development toolchain for the programmable logic device. Furthermore, the learning device 10 and the inference device 30 can also reside on a cloud server.

[0074] The model generation unit 13 can also use learning data obtained from development toolchains of multiple programmable logic devices to learn iterative synthesis parameters for successful configuration and routing. Furthermore, the model generation unit 13 can obtain learning data from development toolchains of multiple programmable logic devices used in the same location, or from development toolchains of multiple programmable logic devices operating independently in different locations. Additionally, the development toolchain of the programmable logic device for which learning data is collected can be added to or removed from the object midway. Moreover, a learning device that has learned iterative synthesis parameters for successful configuration and routing for a specific programmable logic device's development toolchain can be applied to a development toolchain of a different programmable logic device, and the iterative synthesis parameters for successful configuration and routing can be relearned and updated for that different programmable logic device's development toolchain.

[0075] As described above, according to this embodiment, in the process of repeatedly performing configuration routing using a development toolchain for programmable logic devices to find the clock and timing constraints for successful configuration routing, the clock center frequency and frequency range obtained based on the reasoning results of artificial intelligence are used. This significantly reduces the number of trials in the configuration routing process, thus enabling a substantial reduction in the time required for the configuration routing process.

[0076] Implementation Method 2

[0077] Figure 5 This is a diagram showing the structure of the learning device 10A related to the toolchain for developing programmable logic devices in Embodiment 2.

[0078] The learning device 10A has a data acquisition unit 12A and a model generation unit 13A.

[0079] The data acquisition unit 12A acquires clock frequency, parameters for iterative synthesis, resource utilization data for each process, and timing margin information during process mapping as learning data.

[0080] The model generation unit 13A learns the success probability of configuration routing based on learning data generated from a combination of clock frequency, iterative synthesis parameters, resource utilization data for each process, and timing margin information during process mapping, as output from the data acquisition unit 12A. That is, a learned model is generated to infer the success probability of configuration routing based on the clock frequency, iterative synthesis parameters, resource utilization data for each process, and timing margin information during process mapping of the programmable logic device development toolchain. Here, the learning data is data that correlates the clock frequency, iterative synthesis parameters, resource utilization data for each process, and timing margin information during process mapping. When AI is flexibly applied to the programmable logic device development toolchain, the learned model is configured as a model for classifying (clustering) the clock frequency, iterative synthesis parameters, resource utilization data for each process, and timing margin information during process mapping when configuration routing is successful, and the clock frequency, iterative synthesis parameters, resource utilization data for each process, and timing margin information during process mapping when configuration routing fails.

[0081] The learning algorithm used in the model generation unit 13A can employ well-known algorithms such as supervised learning, unsupervised learning, and reinforcement learning. As an example, the application of K-means (clustering) as an unsupervised learning method will be explained. Unsupervised learning refers to a method of learning features from learning data by providing the learning device with learning data that does not contain results (labels).

[0082] The model generation unit 13A, for example, learns the success probability of configuration routing through so-called unsupervised learning using a grouping method based on the K-means method.

[0083] K-means is a non-hierarchical clustering algorithm that uses the average of the clusters to classify a given number of clusters into k clusters.

[0084] Specifically, the K-means method processes data as follows: First, each data point xi is randomly assigned to a cluster. Next, the center Vj of each cluster is calculated based on the assigned data. Then, the distance between each xi and each Vj is calculated, and xi is reassigned to the cluster with the nearest center. Finally, if the cluster assignments of all xi remain unchanged during the above processing, or if the change is less than a pre-set threshold, the process is considered converged and terminated.

[0085] In this application, the success probability of configuration routing is learned through so-called unsupervised learning, based on learning data generated by a combination of clock frequency, iterative synthesis parameters, resource utilization data of each process, and timing margin information during process mapping, obtained by the data acquisition unit 12A.

[0086] The model generation unit 13A generates and outputs the learned model by performing the above learning process.

[0087] The learned model storage unit 20A stores the learned model output from the model generation unit 13A.

[0088] Next, use Figure 6 The learning process of the learning device 10A will be explained. Figure 6 This is a flowchart related to the learning process of the learning device 10A in Embodiment 2.

[0089] In step S301, the data acquisition unit 12A acquires the clock frequency, iterative synthesis parameters, resource utilization data for each process, and timing margin information during process mapping. Although it is assumed that the clock frequency, iterative synthesis parameters, resource utilization data for each process, and timing margin information during process mapping are acquired simultaneously, it is sufficient to input the clock frequency, iterative synthesis parameters, resource utilization data for each process, and timing margin information during process mapping together. Alternatively, the clock frequency, iterative synthesis parameters, resource utilization data for each process, and timing margin information during process mapping can be acquired separately at different times.

[0090] In step S302, the model generation unit 13A generates a learned model by learning data generated from a combination of clock frequency, repetitive synthesis parameters, resource utilization data for each process, and timing margin information during process mapping, obtained by the data acquisition unit 12A, and learning the success probability of configuration routing through so-called unsupervised learning.

[0091] In step S303, the learned model storage unit 20A stores the learned model generated by the model generation unit 13A.

[0092] Figure 7 This diagram illustrates the structure of the inference device 30A, which is related to the toolchain for developing the programmable logic device in Embodiment 2. The inference device 30A includes a data acquisition unit 31A and an inference unit 32A.

[0093] The data acquisition unit 31A acquires clock frequency, parameters for iterative synthesis, resource utilization data for each process, and timing margin information during process mapping.

[0094] The inference unit 32A infers the success probability of configuration routing obtained from the learned model stored in the learned model storage unit 20A. Specifically, by inputting clock frequency, iterative synthesis parameters, resource utilization data for each process, and timing margin information during process mapping obtained by the data acquisition unit 31A into the learned model, the inference unit 32A can infer which cluster the clock frequency, iterative synthesis parameters, resource utilization data for each process, and timing margin information during process mapping belong to, and outputs the inference result as the success probability of configuration routing. When AI is flexibly applied to the development toolchain of programmable logic devices, the inference unit 32A determines whether the clock frequency, iterative synthesis parameters, resource utilization data for each process, and timing margin information during process mapping input to the learned model belong to a cluster indicating successful configuration routing or a cluster indicating failed configuration routing. Furthermore, if it belongs to a cluster indicating successful configuration routing, the inference unit 32A infers that the configuration routing is successful. Conversely, if it belongs to a cluster indicating failed configuration routing, the inference unit infers that the configuration routing is failed.

[0095] Alternatively, the inference unit 32A can also infer and output the probability that the clock frequency, iterative synthesis parameters, resource utilization data for each process, and timing margin information during process mapping, obtained by the data acquisition unit 31A, are part of the learned model. This probability is calculated by inputting these parameters into the learned model. For example, it can be set that the smaller the distance between the clock frequency, iterative synthesis parameters, resource utilization data for each process, and timing margin information during process mapping input to the learned model and the centroid of the cluster representing successful configuration routing, the greater the probability of belonging to that cluster.

[0096] Alternatively, the model generation unit 13A may use a soft clustering method instead of the K-means method to generate a model that generates the probability of belonging to a cluster representing successful configuration and routing. The inference unit 32A may also use a soft clustering method to infer the probability of belonging to a cluster representing successful configuration and routing based on the generated model.

[0097] In this embodiment, it is explained that the success probability of configuration routing is output using a learned model learned by the model generation unit of the development toolchain for programmable logic devices. However, it is also possible to obtain a learned model from external sources such as development toolchains for other programmable logic devices and output the success probability of configuration routing based on that learned model.

[0098] In this way, the inference unit 32A outputs the success probability of configuration routing, obtained based on clock frequency, iterative synthesis parameters, resource utilization data for each process, and timing margin information during process mapping, to the input / output unit of the development toolchain for the programmable logic device. Examples of input / output units include display devices such as displays.

[0099] Next, use Figure 8 This describes the processing used to obtain the success probability of configuration wiring using the inference device 30A.

[0100] Figure 8 This is a flowchart illustrating the inference process that represents the probability of successful configuration wiring of the inference device 30A in Embodiment 2.

[0101] In step S401, the data acquisition unit 31A acquires the clock frequency, parameters for iterative synthesis, resource utilization data for each process, and timing margin information during process mapping.

[0102] In step S402, the inference unit 32A inputs the clock frequency, repeated synthesis parameters, resource utilization data for each process, and timing margin information during process mapping into the learned model stored in the learned model storage unit 20A to obtain the success probability of configuring routing.

[0103] In step S403, the inference unit 32A outputs the success probability of configuration routing obtained through the learned model to the development toolchain of the programmable logic device.

[0104] In step S404, the toolchain for developing the programmable logic device considers the success probability of the output configuration routing and repeatedly attempts to configure the routing using the actual PE (Processing Element), LE (Logic Element), SRAM (Static Random Access Memory), and interconnect resources on the programmable logic device, i.e., iterative synthesis. As a result, the success probability of the configuration routing can be displayed on a display device such as a monitor.

[0105] Furthermore, this embodiment describes the application of unsupervised learning to the learning algorithms used in the model generation unit 13A and the inference unit 32A, but it is not limited to this. Regarding the learning algorithm, reinforcement learning, supervised learning, or semi-supervised learning can also be applied in addition to unsupervised learning.

[0106] In addition, as a learning algorithm for learning, it can also use deep learning, which can learn by extracting the feature quantity itself, or other well-known methods.

[0107] In implementing unsupervised learning in this embodiment, it is not limited to the non-hierarchical clustering based on the k-means method described above; any other well-known method capable of clustering is acceptable. For example, hierarchical clustering methods such as the shortest distance method can also be used.

[0108] In this embodiment, the learning device 10A and the inference device 30A may, for example, be devices connected to and independent of the development toolchain for the programmable logic device via a network. Alternatively, the learning device 10A and the inference device 30A may be built into the development toolchain for the programmable logic device. Furthermore, the learning device 10A and the inference device 30A may reside on a cloud server.

[0109] The model generation unit 13A can also learn the success probability of configuration routing based on learning data generated from development toolchains for multiple programmable logic devices. Furthermore, the model generation unit 13A can obtain learning data from development toolchains for multiple programmable logic devices used in the same area, or it can use learning data collected from development toolchains for multiple programmable logic devices operating independently in different areas to learn the success probability of configuration routing. Additionally, the development toolchain for the programmable logic device that collects the learning data can be added to or removed from the object midway. Moreover, the learning device that has learned the success probability of configuration routing for a particular programmable logic device's development toolchain can be applied to a development toolchain for a different programmable logic device, and the success probability of configuration routing can be relearned and updated for that different programmable logic device's development toolchain.

[0110] Figure 9 This is a diagram showing the hardware structure of the development toolchain 40 for learning devices 10, 10A, inference devices 30, 30A, or programmable logic devices.

[0111] The development toolchain 40 for learning devices 10 and 10A, inference devices 30 and 30A, and programmable logic devices can be configured to perform corresponding actions using either hardware or software of digital circuits. When the functions of the development toolchain 40 for learning devices 10 and 10A, inference devices 30 and 30A, and programmable logic devices are implemented using software, the development toolchain 40 for learning devices 10 and 10A, inference devices 30 and 30A, and programmable logic devices can be configured as follows: Figure 9 As shown, the device has a processor 51 and a memory 52 connected via a bus 53. The processor 51 is capable of executing programs stored in the memory 52.

[0112] The embodiments disclosed herein should be considered illustrative rather than restrictive in all respects. The scope of the invention is defined not by the foregoing description but by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0113] Label Explanation

[0114] 10, 10A: Learning device; 12, 12A: Data acquisition unit; 13, 13A: Model generation unit; 14: Reward calculation unit; 15: Function update unit; 20, 20A: Learned model storage unit; 31, 31A: Data acquisition unit; 32, 32A: Inference unit; 40: Toolchain for developing programmable logic devices; 51: Processor; 52: Memory; 53: Bus.

Claims

1. A learning device, the learning device having: The data acquisition unit acquires learning data, which includes resource utilization data and timing margin information for each process in the development toolchain of the programmable logic device, as well as the target clock frequency and iterative synthesis parameters of the development toolchain of the programmable logic device from the resource utilization data and timing margin information for each process; and The model generation unit uses the learning data to generate a learned model, which is used to infer the iterative synthesis parameters given by the development toolchain of the programmable logic device to enable successful configuration and routing, based on the resource utilization data of each process of the development toolchain of the programmable logic device and the timing margin information during process mapping.

2. The learning device according to claim 1, wherein, The resource utilization data for each process includes the utilization rates of arithmetic logic units, multiplexers, adders, subtractors, and arithmetic shifters of the logic elements or processing elements within the programmable logic device.

3. The learning device according to claim 1, wherein, The timing margin information during process mapping, for a period time determined by the target clock frequency, includes the redundancy of the largest signal transmission delay time among the signal transmission delay times between flip-flops within the programmable logic device relative to the period time.

4. The learning device according to claim 2, wherein, The timing margin information during process mapping, for a period time determined by the target clock frequency, includes the redundancy of the largest signal transmission delay time among the signal transmission delay times between flip-flops within the programmable logic device relative to the period time.

5. The learning device according to any one of claims 1 to 4, wherein, The parameters for repeated synthesis include: The clock frequency as the center; Thresholds, which determine the lower and upper limits of the clock frequency; and A step size value, which is used to cover the range from the lower limit value to the upper limit value of the clock frequency determined by the threshold.

6. The learning device according to claim 5, wherein, The parameters used for iterative synthesis to ensure successful wiring configuration include: The central clock frequency is used to enable the configured and routed circuit to achieve the target signal processing performance; and The combination of the threshold and the step size satisfies the condition that the probability of success of the configuration routing during iterative synthesis is maximized and the number of trials of the configuration routing is minimized.

7. The learning device according to claim 3 or 4, wherein, As a reward benchmark, if the configuration routing is successful, the model generation unit increases the reward by using the redundancy of the utilization rate of the logic elements or processing elements in the programmable logic device, or the redundancy of the utilization rate of the interconnect resources in the programmable logic device, or the redundancy of the largest signal transmission delay time among the signal transmission delay times between the flip-flops in the programmable logic device relative to the cycle time.

8. The learning device according to claim 7, wherein, As a reward benchmark, in the event of configuration routing failure, the model generation unit reduces the reward by using the degree of overflow of the utilization rate of the logic elements or processing elements in the programmable logic device, or the degree of overflow of the interconnection resources in the programmable logic device, or the degree of timing violation of the largest signal transmission delay time among the signal transmission delay times between the flip-flops in the programmable logic device relative to the cycle time.

9. A reasoning device, the reasoning device comprising: The data acquisition department acquires resource utilization data for each process in the toolchain used for programmable logic device development, as well as timing margin information during process mapping; and The inference unit uses a learned model to output iterative synthesis parameters for successful configuration routing based on the resource utilization data of each process and the timing margin information during process mapping obtained by the data acquisition unit. The learned model is used to infer iterative synthesis parameters given by the development toolchain for the programmable logic device for successful configuration routing based on the resource utilization data of each process and the timing margin information during process mapping.

10. The reasoning device according to claim 9, wherein, The resource utilization data for each process includes the utilization rates of arithmetic logic units, multiplexers, adders, subtractors, and arithmetic shifters of the logic elements or processing elements within the programmable logic device.

11. The reasoning device according to claim 9, wherein, The timing margin information during process mapping, for a cycle time determined by the target clock frequency of the development toolchain for the programmable logic device, includes the redundancy of the largest signal transmission delay time among the signal transmission delay times between flip-flops within the programmable logic device relative to the cycle time.

12. The reasoning device according to claim 10, wherein, The timing margin information during process mapping, for a cycle time determined by the target clock frequency of the development toolchain for the programmable logic device, includes the redundancy of the largest signal transmission delay time among the signal transmission delay times between flip-flops within the programmable logic device relative to the cycle time.

13. The reasoning apparatus according to any one of claims 9 to 12, wherein, The parameters used for iterative synthesis to ensure successful wiring configuration include: The central clock frequency is used to enable the configured and routed circuit to achieve the target signal processing performance; and A combination of a threshold and a step size, wherein the threshold is used to determine a lower and upper limit of a clock frequency that satisfies the condition of maximizing the probability of success of the configuration routing when performing iterative synthesis and minimizing the number of trials of the configuration routing, and the step size is used to cover a range from the lower limit to the upper limit.

14. A learning device, the learning device having: The data acquisition unit acquires learning data, which includes the target clock frequency of the development toolchain for the programmable logic device, iterative synthesis parameters, resource utilization data for each process in the development toolchain for the programmable logic device, and timing margin information during process mapping; and The model generation unit uses the learning data to generate a learned model, which is used to infer the success probability of configuration routing based on the target clock frequency of the development toolchain of the programmable logic device, the iterative synthesis parameters, the resource utilization data of each process, and the timing margin information during process mapping.

15. A reasoning device, the reasoning device comprising: The data acquisition unit acquires the target clock frequency, iterative synthesis parameters, resource utilization data for each process in the programmable logic device development toolchain, and timing margin information during process mapping for the programmable logic device development toolchain; and The inference unit uses a learned model to output the success probability of configuration routing based on the target clock frequency, the iterative synthesis parameters, the resource utilization data of each process, and the timing margin information during process mapping obtained by the data acquisition unit. The learned model is used to infer the success probability of configuration routing based on the target clock frequency, the iterative synthesis parameters, the resource utilization data of each process, and the timing margin information during process mapping.

16. A toolchain for developing programmable logic devices, wherein, The development toolchain for the programmable logic device uses the inference device according to any one of claims 9 to 13, 15 to infer iterative synthesis parameters for enabling the configuration wiring to succeed.

17. A learning method comprising the following steps: Acquire learning data, which includes resource utilization data and timing margin information for each process in the development toolchain of the programmable logic device, as well as the target clock frequency and iterative synthesis parameters of the development toolchain for the programmable logic device from the resource utilization data and timing margin information for each process; and The learned model is generated using the learning data. This learned model is used to infer iterative synthesis parameters given by the development toolchain of the programmable logic device to enable successful configuration and routing, based on resource utilization data for each process of the development toolchain of the programmable logic device and timing margin information during process mapping.

18. A reasoning method comprising the following steps: Obtain resource utilization data and timing margin information for each process in the toolchain used for programmable logic device development; and Using a learned model, based on the obtained resource utilization data for each process and the timing margin information during process mapping, output iterative synthesis parameters for successful configuration routing. This learned model is used to infer iterative synthesis parameters given by the development toolchain for the programmable logic device for successful configuration routing based on the resource utilization data for each process and the timing margin information during process mapping.

19. A learning method comprising the following steps: Acquire learning data, which includes the target clock frequency of the development toolchain for the programmable logic device, iterative synthesis parameters, resource utilization data for each process in the development toolchain for the programmable logic device, and timing margin information during process mapping; and The learned model is generated using the learning data. This learned model is used to infer the success probability of configuration routing based on the target clock frequency of the development toolchain for the programmable logic device, the iterative synthesis parameters, the resource utilization data of each process, and the timing margin information during process mapping.

20. A reasoning method comprising the following steps: Obtain the target clock frequency, iterative synthesis parameters, resource utilization data for each process in the programmable logic device development toolchain, and timing margin information during process mapping of the programmable logic device development toolchain; and Using a learned model, based on the obtained target clock frequency, the iterative synthesis parameters, the resource utilization data of each process, and the timing margin information during process mapping, the success probability of configuration routing is output. This learned model is used to infer the success probability of configuration routing based on the target clock frequency, the iterative synthesis parameters, the resource utilization data of each process, and the timing margin information during process mapping.

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