Inhibition of undesired programming at half-selected devices in cross-point arrays of resistive memory

Abstract

Aspects of the invention include performing a stochastic update of a crossbar array by generating a stochastic set of pulses for the crossbar array, the crossbar array including a plurality of row wires including a first row wire and a plurality of column wires including a first column wire, wherein a three-terminal device is coupled to the first row wire and the first column wire at an intersection of the first row wire and the first column wire, and wherein a resistivity of the three-terminal device is modified in response to a coincidence of a pulse from the stochastic set of pulses at the intersection of the first row and the first column, and wherein at least one terminal in the three-terminal device is floating.

Description

Technical Field

[0001] The present invention relates generally to resistor processing units, and more specifically, to suppressing unwanted programming at half-selected devices in a cross-point array of resistive memory devices. Background Technology

[0002] "Machine learning" is used broadly to describe the main functions of electronic systems that learn from data. In machine learning and cognitive science, artificial neural networks (ANNs) are a family of statistical learning models inspired by the biological neural networks of animals (especially the brain). ANNs can be used to estimate or approximate systems and functions that depend on a large number of inputs and are often unknown. Crossbar arrays are high-density, low-cost circuit architectures used to form various electronic circuits and devices, including ANN architectures, neuromorphic microchips, and ultra-high-density non-volatile memories. A basic crossbar array configuration includes a set of conductive row wires and a set of conductive column wires, the latter being formed to intersect with the former. The intersection points between these two sets of wires are separated by so-called crossbar devices, which can be formed from thin-film materials. Summary of the Invention

[0003] Embodiments of the present invention relate to a computer-implemented method for suppressing unwanted programming at half-select devices in a cross-point array. A non-limiting example of the computer-implemented method includes operating a random converter to generate a set of random pulses for a cross-point array comprising a plurality of row wirings and a plurality of column wirings, the plurality of row wirings including a first row wirings and the plurality of column wirings including a first column wirings, wherein a three-terminal device is coupled to the first row wirings and the first column wirings at the intersections of the first row wirings and the first column wirings, and wherein the resistivity of the three-terminal device is modified in response to the overlap of pulses from the set of random pulses at the intersections of the first row and the first column.

[0004] Embodiments of the present invention relate to a system for suppressing unwanted programming at half-select devices in a cross-point array. Non-limiting examples of the system include: a memory having computer-readable instructions; one or more processors for executing the computer-readable instructions, the computer-readable instructions controlling the one or more processors to perform operations including: operating a random converter to generate a random pulse set of a cross-point array comprising a plurality of row wirings and a plurality of column wirings, the plurality of row wirings comprising a first row wiring and the plurality of column wirings comprising a first column wiring, wherein a three-terminal device is coupled to the first row wirings and the first column wirings at the intersection of the first row wirings and the first column wirings, and wherein the resistivity of the three-terminal device is modified in response to the overlap of pulses from the random pulse set at the intersection of the first row and the first column.

[0005] Embodiments of the present invention relate to computer program products for suppressing unwanted programming at half-select devices in a cross-point array. A non-limiting example of such computer program product includes operating a random converter to generate a set of random pulses for a cross-point array comprising a plurality of row wirings and a plurality of column wirings, the plurality of row wirings including a first row wirings and the plurality of column wirings including a first column wirings, wherein a three-terminal device is coupled to the first row wirings and the first column wirings at the intersections of the first row wirings and the first column wirings, and wherein the resistivity of the three-terminal device is modified in response to the overlap of pulses from the set of random pulses at the intersections of the first row and the first column.

[0006] Additional technical features and advantages are achieved through the technology of this invention. Embodiments and aspects of the invention are described in detail herein and are considered part of the claimed subject matter. For a better understanding, refer to the detailed description and accompanying drawings. Attached Figure Description

[0007] The details of the exclusive rights described herein are specifically pointed out and explicitly claimed in the claims at the end of the specification. The foregoing and other features and advantages of embodiments of the invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 A simplified diagram illustrating the input and output connections of a biological neuron that can be modeled according to various aspects of the present invention is provided.

[0009] Figure 2 The invention can be utilized in combination with various aspects of the present invention. Figure 1 The known simplified model of a biological neuron is shown;

[0010] Figure 3 Depicting the combination Figure 2 The biological neuron model shown is a known simplified model of the ANN;

[0011] Figure 4 A simplified block diagram depicts a random computation method that can be used in one or more embodiments of the present invention;

[0012] Figure 5 Known equations are shown for managing the operation of a passive, two-terminal memristor that can be used in conjunction with aspects of the present invention;

[0013] Figure 6 The diagram depicts two terminals, a crossbar array of a nonlinear RPU device, and a voltage sequence illustrating the operation of the RPU, according to one or more embodiments of the present invention.

[0014] Figure 7 A crossbar array of a three-terminal device according to one or more embodiments of the present invention is shown.

[0015] The figures depicted herein are illustrative. Many variations of the figures or operations described herein are possible without departing from the spirit of the invention. For example, actions may be performed in a different order, or actions may be added, deleted, or modified. Furthermore, the term "coupled" and its variations describe a communication path between two elements and do not imply a direct connection between the elements, with no intervening elements / connections between them. All such variations are considered part of the specification. Detailed Implementation

[0016] Various aspects of the present invention include novel configurations of programmable resistive cross-connect devices and methods for programming these devices, referred herein as Resistor Processing Units (RPUs). A basic cross-connect array (sometimes referred to herein as a "cross-point array") configuration includes a set of conductive row wires and a set of conductive column wires, the set of column wires being formed to intersect the set of conductive row wires. The crossings between these two sets of wires are separated by so-called cross-connect devices (i.e., RPUs). A typical RPU includes a two-terminal device with non-linear switching characteristics. Various aspects of the present invention provide RPUs in a cross-connect array with three terminals, the three terminals allowing gate control at additional terminals to control the characteristics of the RPU. The other two terminals in the three-terminal RPU are source and drain terminals. The update cycle of these RPUs is controlled by a gate-channel voltage. This allows the RPU update cycle connection to be connected to the gate terminal connected to the cross-connect row wiring and the source terminal connected to the cross-connect column wiring, and the drain terminal is also connected to a separate row wiring in the cross-connect array. In this configuration, for each column line in the cross, there are two row lines. Alternatively, the gate terminal can be connected to the cross-column wiring and the drain terminal can be connected to the cross-column wiring.

[0017] In one or more embodiments of the invention, unused terminals of a three-terminal device can be floated during a refresh cycle because the potential difference across the gate and channel can be controlled using either end of the gate or channel. In an array embodiment, the float can be maintained by a single pass-gate transistor at each row and column, configured to activate in the presence of a pulse and disconnect when no pulse is present. When floated, the device is connected via its gate or source because neither the drain nor the source terminals are always floated during the refresh cycle. Device programming occurs when there is a sufficient voltage drop across the gate to the channel for current to flow to tune the device's conductivity value. Conversely, current flowing across the channel does not modify the voltage level because current cannot flow across the channel when all drains are floated during refresh. When source-drain or gate-drain (depending on the cross-array configuration) floated, the device cannot perform a sneak-path because current passes through both gates to unintentionally program both gates. A latent path refers to an undesired path of current that is typically parallel to the expected path. Channel capacitance creates an exponential correlation between this current (Ig) and voltage (Vg), and therefore it is practically impossible to create a sufficient voltage drop using a floating gate. Therefore, instead of grounding the line as performed in conventional random update schemes, in some embodiments of the invention, the line can be kept floating. By floating the connection to the line termination, this method improves the update quality of the device. Floating the terminal means not forcing the voltage on the terminal to ground during random updates. In a typical two-terminal RPU scenario, the row receives a HIGH or GND signal during random updates, and the column receives a LOW or GND signal (i.e., HIGH = +1V, GND = 0, LOW = -1V). In the three-terminal RPU cross-array described herein, the drain is floating, and the gate is HIGH or FLT and the source is LOW or FLT. For example, the update quality of the device is improved when the device is modified with a single pulse from the gate or source. Even though such updates are much smaller than those performed across the full voltage range, smaller updates are seen for half-bias conditions due to non-ideal thresholding. Floating terminals remove these cases, and devices that do not receive overlapping updates remain unaffected. Furthermore, in this configuration, half-bias pulses (e.g., a single pulse on a column or row) will not cause unwanted programming at the RPU.

[0018] The aforementioned cross-shaped array can be used in Artificial Neural Networks (ANNs). ANNs are a family of statistical learning models inspired by the biological neural networks of animals, particularly the brain. ANNs can be used to estimate or approximate systems and functions that depend on a large number of inputs and are often unknown. ANNs are typically embodied as so-called "neuronal morphology" systems of interconnected processor elements that act as simulated "neurons" and exchange "messages" with each other in the form of electronic signals. Similar to the so-called "plasticity" of synaptic neurotransmitter connections that transmit messages between biological neurons, the connections in an ANN that transmit electronic messages between simulated neurons are provided with numerical weights corresponding to the strength or weakness of a given connection. These weights can be adjusted and tuned empirically, allowing the ANN to adapt to inputs and learn. For example, an ANN for handwriting recognition is defined by a set of input neurons that can be activated by pixels of an input image. After being weighted and transformed by a function determined by the network's designer, the activation of these input neurons is then passed to other downstream neurons, often referred to as "hidden" neurons. This process is repeated until an output neuron is activated. The activated output neuron determines which character was read.

[0019] Cross-point arrays (also known as cross-point arrays or cross-line arrays) are high-density, low-cost circuit architectures used to form a variety of electronic circuits and devices, including ANN architectures, neuromorphic microchips, and ultra-high-density non-volatile memories. In practice, cross-point devices act as weighted connections between neurons in an ANN. Nanoscale two-terminal devices, such as memristors with “ideal” on-state switching characteristics, are frequently used as cross-point devices to simulate synaptic plasticity with high energy efficiency. The term “memristor” broadly refers to a passive two-terminal circuit element portion whose resistance can be changed under sufficient electrical bias. The on-state (e.g., resistance) of a memristor material can be changed by controlling the voltage applied between the individual lines in the rows and columns. Digital data can be stored by changing the conduction state of the memristor material at the cross-point to achieve a high-conductivity state or a low-conductivity state. Memristor materials can also be programmed to maintain two or more different conduction states by selectively setting the material's conduction state. The on-state of a memristor material can be read by applying a voltage to the material and measuring the current through the target cross-point device.

[0020] ANN, also known as neuromorphic systems or synaptic systems, is a computational system that can estimate or approximate other functions or systems, including, for example, biological nervous systems, the human brain, and brain-like functions such as image recognition and speech recognition. ANN combines knowledge from various disciplines, including neurophysiology, cognitive science / psychology, physics (statistical mechanics), control theory, computer science, artificial intelligence, statistics / mathematics, pattern recognition, computer vision, parallel processing, and hardware (e.g., digital / analog / VLSI / optics).

[0021] Instead of using traditional digital models that manipulate 0s and 1s, ANNs create connections between processing elements, which are essentially functional equivalents of the core system functions being estimated or approximated. For example, IBM's Systems of Neuroform Adaptive Plastic Scalable Electronics (SyNapse) computer chip is the central component of an electronic neuromorphic machine that attempts to provide a similar form, function, and architecture to the mammalian brain. While the IBM SyNapse computer chip uses the same basic transistor components as conventional computer chips, its transistors are configured to mimic the behavior of neurons and their synaptic connections. The IBM SyNapse computer chip uses a network of over one million simulated "neurons" to process information, communicating with each other using electrical spikes similar to the synaptic communication between biological neurons. The IBM SyNapse architecture includes a configuration that reads memory (i.e., simulated "synapses") and processors (i.e., simulated "neurons") that perform simple operations. Communication between these processors, typically located in different cores, is handled by an on-chip network router.

[0022] As background, now refer to Figure 1 , Figure 2 and Figure 3 This provides a general description of how a typical ANN operates. As mentioned earlier, a typical ANN models the human brain, which consists of approximately one hundred billion interconnected cells called neurons. Figure 1 A simplified diagram of a biological neuron 102 is depicted, having pathways 104, 106, 108, and 110 connecting it to upstream inputs 112 and 114, downstream outputs 116, and downstream "other" neurons 118, which are configured and arranged as shown. Each biological neuron 102 sends and receives electrical impulses via pathways 104, 106, 108, and 110. The nature of these electrical impulses and how they are processed within the biological neuron 102 are primarily responsible for overall brain function. The pathway connections between biological neurons can be strong or weak. When a given neuron receives an input impulse, the neuron processes the input according to its function and sends the result of that function to the downstream output and / or downstream "other" neurons.

[0023] Biological neuron 102 in Figure 2 The middle is modeled as having a composition of Figure 2The equation shown depicts node 202 of the mathematical function f(x). Node 202 takes electrical signals from inputs 212 and 214, multiplies each input 212 and 214 by the strength of its respective connection paths 204 and 206, obtains the sum of the inputs, passes this sum through the function f(x), and generates a result 216, which can be the final output or an input to another node, or both. In this detailed description, an asterisk (*) is used to indicate multiplication. Weak input signals are multiplied by a very small number of connection strengths, so weak input signals have a very low effect on the function. Similarly, strong input signals are multiplied by a higher number of connection strengths, so strong input signals have a greater effect on the function. The function f(x) is a design choice, and various functions can be used. A typical design choice for f(x) is the hyperbolic tangent function, which takes the sum of previous inputs and outputs a number between negative and positive one.

[0024] Figure 3 A simplified ANN model 300, organized as a weighted directed graph, is depicted, where artificial neurons are nodes (e.g., 302, 308, 316), and weighted directed edges (e.g., m1 to m20) connect the nodes. The ANN model 300 is organized such that nodes 302, 304, and 306 are input layer nodes, nodes 308, 310, 312, and 314 are hidden layer nodes, and nodes 316 and 318 are output layer nodes. Each node is connected to every node in the adjacent layers via a connection path. Figure 3 The diagram is described as having directional arrows with connection strengths m1 to m20. Although only one input layer, one hidden layer, and one output layer are shown, multiple input layers, hidden layers, and output layers can actually be provided.

[0025] Similar to the function of the human brain, each input layer node 302, 304, 306 of the ANN300 receives inputs x1, x2, x3 directly from the source (not shown) without connection strength adjustment and without node sums. Therefore, y1 = f(x1), y2 = f(x2), and y3 = f(x3), as shown in... Figure 3 The equations listed at the bottom are shown. Each hidden layer node 308, 310, 312, 314 receives its input from all input layer nodes 302, 304, 306 according to the connection strength associated with the relevant connection path. Therefore, in hidden layer node 308, y4 = f(m1*y1 + m5*y2 + m9*y3), where * denotes multiplication. Similar connection strength multiplication and node summation are performed for hidden layer nodes 310, 312, 314 and output layer nodes 316, 318, as defined in [the table / concept]. Figure 3 The equations for functions y5 to y9 are depicted at the bottom.

[0026] The ANN model 300 processes data records one at a time and "learns" by comparing the initial arbitrary classification of a record with its known actual classification. Using a training method called "backpropagation" (i.e., "error backpropagation"), the error from the initial classification of the first record is fed back into the network and used to modify the network's weighted connections approximately a second time, and this feedback process continues for many iterations. During the ANN's training phase, the correct classification of each record is known, and therefore a "correct" value can be assigned to the output nodes. For example, the node value corresponding to the correct class is "1" (or 0.9), and the node value for other nodes is "0" (or 0.1). The network's computed values ​​for each node can then be compared to these "correct" values, and an error term (i.e., the "delta" rule) is computed for each node. These error terms are then used to adjust the weights in the hidden layers so that in the next iteration, the output value will be closer to the "correct" value.

[0027] There are many types of neural networks, but two of the most widespread categories are feedforward and recurrent networks. ANN Model 300 is a non-recurrent feedforward network with input, output, and hidden layers. These signals can only propagate in one direction. Input data is passed to layers of processing elements that perform computations. Each processing element performs its computation based on a weighted sum of its inputs. The newly computed value then becomes the new input value fed to the next layer. This process continues until it has passed through all layers and determined the output. Thresholding transfer functions are sometimes used to quantify the output of neurons in the output layer.

[0028] Feedback / recursive networks include feedback paths, meaning signals can propagate in both directions using loops. This allows for all possible connections between nodes. Because loops exist in this type of network, it can become a nonlinear dynamic system in certain operations, continuously changing until it reaches an equilibrium state. Feedback networks are frequently used in associative memory and optimization problems, where the network seeks the optimal arrangement of interconnecting factors.

[0029] The speed and efficiency of machine learning in feedforward and recursive ANN architectures depend on how effectively the cross-point devices of the ANN cross array perform the core operations of typical machine learning algorithms. While a precise definition of machine learning is difficult to formulate, the learning process in the context of an ANN can be viewed as the problem of updating the connection weights of the cross-point devices so that the network can effectively perform a specific task. The cross-point devices typically learn the necessary connection weights from available training patterns. Performance improves over time by iteratively updating the weights in the network. Instead of following a set of rules specified by human experts, ANNs “learn” underlying rules (such as input-output relationships) from a given set of representative examples. Therefore, the learning algorithm can generally be defined as the process of learning rules used to update and / or adjust relevant weights.

[0030] These three main paradigms of learning algorithms are supervised, unsupervised, and hybrid. In supervised learning, or learning with a “teacher,” the network is provided with the correct answer (output) for each input pattern. Weights are determined to allow the network to produce answers as close as possible to the known correct answer. Reinforcement learning is a variant of supervised learning where the network is only provided with criticisms about the correctness of the network’s output, not the correct answer itself. Conversely, unsupervised learning, or learning without a teacher, does not require the correct answer associated with every input pattern in the training dataset. It explores the underlying structure in the data, or the correlations between patterns in the data, and organizes the patterns from these correlations into categories. Hybrid learning combines supervised and unsupervised learning. Part of the weights is typically determined through supervised learning, while other parts are obtained through unsupervised learning.

[0031] The two-terminal programmable resistive cross-point assembly, referred to in this paper as the Resistor Processing Unit (RPU), provides local data storage and local data processing capabilities. In other words, when data processing is performed, the values ​​stored at each RPU are updated in parallel and locally, eliminating the need to move related data in and out of the processor and separate storage elements. Furthermore, the local data storage and local data processing provided by the two-terminal RPU accelerates ANN learning and the ability to implement algorithms such as backpropagation for online neural network training, matrix inversion, and matrix factorization. Therefore, implementing a machine learning ANN architecture with an RPU enables online machine learning capabilities that optimize learning speed, efficiency, and power consumption. The RPU and the resulting ANN architecture improve overall ANN performance and enable a wider range of practical ANN applications.

[0032] Before providing a more detailed description of the RPU, an overview of shrink arrays, random computation, and linear and nonlinear memristor devices related to this invention will now be given. Shrink arrays consist of parallel processing elements (PEs) designed to accelerate the learning of certain highly used algorithms. Shrink arrays are typically hardwired for specific operations, such as "multiplication and accumulation," to perform massively parallel integration, convolution, correlation, matrix multiplication, or data classification tasks.

[0033] Random computation is a collection of techniques for representing continuous values ​​through random bit streams, where complex computations can be performed by simple bit-by-bit operations on the streams. Specifically, if there exist two random and independent bit streams S1 and S2 (i.e., Bernoulli processes), called random numbers, where the probability of "one" in the first stream is p and the probability of "one" in the second stream is q, then a logical AND operation on the two streams can be performed, such as... Figure 4 As shown. The probability of a "1" in the output stream is pq. By observing enough output bits and measuring the frequency of "1", pq can be estimated with arbitrary accuracy. Due to the simplicity of these so-called "multiplication and accumulation" operations (which can be implemented with a few logic gates / transistors), random computation is frequently used in the hardware design of neural networks.

[0034] However, in some stochastic techniques, the necessary weights for computation are provided to the shrinking array from an external location, and the updates to the weights are not performed by the array itself. This only addresses the speedup of vector-matrix multiplication or matrix-matrix multiplication operations that are heavily used during neural network training. However, a shrinking array without local storage cannot perform weight updates in parallel because these weights are stored at external memory locations. Accelerating weight updates is necessary to speed up the overall learning algorithm.

[0035] The term "memristor" is used to describe a passive two-terminal electronic component where the resistance value depends on the history of voltages previously applied to the device. The operation of a memristor is determined by... Figure 5 Equations [1] and [2] shown in the diagram control the current flowing through the device, the voltage applied to the device, the conductivity of the device (which is the reciprocal of the resistance), the internal state variable of the device controlling the conductivity, and the function f showing the time evolution of the internal state variable s. Memristors can be used to operate resistive memory devices such as resistive random access memory (RRAM), phase-change memory (PCM), and conductive bridged random access memory (CBRAM). This is because memristor devices remember their history (i.e., the so-called "non-volatile characteristic").

[0036] Several existing techniques are used to apply memristors to backpropagation neural network training hardware. However, this assumes ideal memristor operation, where the resistance changes linearly with respect to the voltage applied to the device. These techniques and design assumptions... Figure 5 The function f(s, v) in equation [2] is a simple function given by the relation f(s, v) = v. Consider an architecture similar to the 2D shrinking array described above, where each crossover is implemented using an ideal memristor and a pair of transistors. The memristor is actually used to store the weight values, and the pair of transistors is used to perform the local multiplication operations required to compute the weight updates, where the result of the weight updates modifies the on-state of the memristor. In practice, the four-terminal device consists of a memristor and two transistors, which are used to create a 2D array of four-terminal devices to enable backpropagation training of the neural network hardware.

[0037] When implementing an RPU device as a memristor system, it is important to note that memristors are non-ideal when they exhibit non-linear switching characteristics. In an ideal memristor, the change in resistance is linearly proportional to the voltage applied to the ideal memristor device. Therefore, once an ideal memristor device experiences any voltage, its impedance state changes. However, for the RPU device described as being implemented as a non-ideal non-linear memristor system, there exists a well-defined "setup" voltage V. SET (This is a characteristic of the device), and the memristor RPU device will need to experience a voltage V>V. SET In order to change its internal resistance state. However, when the voltage equals V SET At that time, there is a possibility of undesirable programming effects in these RPUs.

[0038] Figure 6 This diagram illustrates a two-dimensional (2D) cross array 800 performing forward matrix multiplication, backward matrix multiplication, and weight updates. The cross array 800 is formed by a set of conductive row wirings 802, 804, 806 and a set of conductive column wirings 808, 810, 812, 814 intersecting with these row wirings. The intersections between the row and column wiring groups are separated by an RPU (Radio Processing Unit). Figure 6 The diagram shows resistive elements, each with its own adjustable / updateable resistance weight, described as σ. 11 σ 21 σ 31 σ 41 σ 12 σ 22 σ 32 σ 42 σ 13 σ 23 σ 33 and σ 43 For ease of explanation, in Figure 6 An RPU 820 is labeled only with a reference number. In forward matrix multiplication, the RPU's on-state (i.e., the stored weights) can be read by applying a voltage across the RPU and measuring the current through the RPU.

[0039] Input voltages V1, V2, and V3 are applied to row wirings 802, 804, and 806, respectively. Each column wiring 808, 810, 812, and 814 sums the currents I1, I2, I3, and I4 generated by each RPU along a specific column wiring. For example, as... Figure 6 As shown, the current I4 generated by the column wiring 814 is based on the equation I4=V1σ 41 +V2σ 42 +V3σ 43 Therefore, array 800 calculates forward matrix multiplication by multiplying the values ​​stored in the RPU by the row routing inputs, which are defined by voltages V1, V2, and V3. Backward matrix multiplication is very similar. In backward matrix multiplication, voltages are applied at column routes 808, 810, 812, and 814, and then the voltages are read from row routes 802, 804, and 806. For the weight update described in more detail below, voltages are applied to both the column and row routes simultaneously, and the conductance values ​​stored in the relevant RPU devices are all updated in parallel. Thus, the multiplication and addition operations required to perform the weight update are performed locally at each RPU 820 of array 800 using the RPU devices themselves plus the relevant row or column routes of array 800. Therefore, according to an embodiment of the invention, no read-update-write cycle is required in array 800.

[0040] continue Figure 6 The diagram will now provide the methodology for positive weight updates for the RPU820 and its corresponding weight σ at the intersection of the guided row routing 806 and the guided column routing 812. 43 The nonlinear characteristics of the RPU820 are used to perform multiplication locally on the RPU820 using random computation as described below. More specifically, the described method uses the nonlinear switching characteristics of the RPU820 and random bit streams 830, 832 to perform multiplication and perform the necessary weight updates locally on the RPU820 without additional circuitry. An update generator circuit (not shown) is located around the periphery of the cross array 800 and acts as a periphery “converter” to generate the necessary voltage pulses in the form of random bit streams (e.g., 830, 832), which can be applied in parallel to all RPUs of the 2D cross array 800.

[0041] The row voltage sequence or bit stream 830 applied to row wiring 806 is shown as representing zero voltage or +0.5V. SETThe voltage pulse sequence is updated with voltage weights. The column voltage sequence or bit stream 832 applied to column wiring 814 is shown as also representing zero voltage or -0.5V. SET The voltage pulse sequence is updated with voltage weights. Figure 6 In the example, 4 / 8 is encoded by row voltage sequence 830, and 6 / 8 is encoded by column voltage sequence 832. Example voltage sequences 830 and 832 represent the positive resistance change phase of the weight update. After performing a positive weight update, a separate set of sequences with the reversed polarity of the corresponding voltages can be used to update the weights of those weights requiring this correction in the negative direction.

[0042] Voltage sequence 834 is the voltage applied to RPU 820 caused by the difference between row voltage sequence 830 and column voltage sequence 832. Voltage sequence 834 will have voltages at 0V and 0.5V. SET and V SET Three voltage steps. When the column wiring sends 0.5V. SET The voltage at that point and the line sending -0.5V. SET When the voltage is applied to the relevant RPU, the resulting V SET The pulse will cause an incremental change in the resistance of the device. Therefore, the voltage pulse applied to the RPU 820 utilizes the non-linear switching characteristics of the RPU 820 to locally perform a bit-by-bit random AND operation at the RPU 820 (e.g., as shown in the image). Figure 4 (As shown). Therefore, the resulting change in the RPU's stored weights (e.g., σ43) is proportional to the product of the two numbers (4 / 8 * 6 / 8 = 3 / 8) "converted" by the update generator circuit located on the periphery of the cross array 800.

[0043] The aforementioned cross array may have drawbacks, including the possibility that some undesirable programming of the RPU can occur when it is half-selected. Half-selection refers to the situation where V is applied during a row voltage pulse. SET The pulse, but there is no consistent -V in the column voltage pulse. SET When the pulse (and vice versa).

[0044] Various aspects of the present invention provide methods for suppressing unwanted programming at half-selected devices in a crosspoint array by utilizing three-terminal resistive memory devices. A method is provided capable of suppressing unwanted programming at half-selected devices in a crosspoint array having three-terminal resistive memory devices. In the three-terminal device, additional terminals for control characteristics are provided using additional gate control. The update cycle of the three-terminal device is controlled by the gate-channel voltage, and therefore, it is possible to utilize... Figure 7 The gate (row) and source (column) or gate (column) and drain (row) connections shown enable the update cycle connection. An example of a three-terminal cross array can be found in... Figure 7The exemplary cross-array 900 includes a set of row wirings 904 and a set of column wirings 906. At each intersection of the column wirings 906 and the row wirings 904 is a three-terminal device 902. The three-terminal device 902 includes a gate terminal 910, a source terminal 912, and a drain terminal 914. In the illustrated example, the row wirings 904 include two wirings per row, which are attached to the gate terminal 910 and the drain terminal 914 of each three-terminal device 902. A single wire is included in the cross-array 900 for each column wiring 906, and this column wiring is connected to the source terminal 912 for each three-terminal device 902. In this configuration, the update cycle occurs by utilizing a similar random update cycle technique described above. A random bit stream can be generated using an update generator circuit (not shown), which can be attached to the periphery of the cross-array 900. These random bit streams can be input to a so-called "random converter" to generate (or convert) the random bit streams into corresponding voltage pulses (e.g., V) that simulate the random bit streams. SET -V SET These voltages are then applied to all three-terminal devices 902 of the cross array 900. In one or more embodiments of the invention, the source and drain are named herein for ease of description. That is, the terms source and drain are interchangeable in the cross array 900.

[0045] In one or more embodiments of the invention, when the resistive memory device 902 is half-selected, the configuration of the cross array 900 and the utilization of the three-terminal device 902 can reduce unwanted programming effects. In the current configuration of the cross array 900, a voltage pulse must occur at the gate terminal 910 and source terminal 912 (coincidentally) of the three-terminal device 902 to cause an update of the device 902. This can be achieved by the three-terminal device 902 being a single-transfer gate transistor that is activated in the presence of a voltage pulse and blocks the connection when no voltage pulse is present. Unused terminals (drain terminal 914 in the current configuration) can remain floating during the update cycle because the potential difference across the gate channel can be controlled using either the gate terminal 910 or either end of the transistor channel. As described above, for a two-terminal device during a random update scheme, one side of the two-terminal device is connected to the cross row, and the other side of the two-terminal device is connected to the cross column. Then, "high" or "GND" is sent from the row, and "low" or "GND" is sent from the column (e.g., "high" = +1V, "GND" = 0, "low" = -1V). In this cross-array 900, each of the three-terminal devices 902 has a gate terminal 910 and a drain terminal 914 connected to row 904 of the cross-array 900, and a source terminal 912 connected to column 906. During the update cycle, the drain terminal 914 is always floating ("FLT"), the gate terminal 910 is "high" or "FLT", and the source terminal 912 is "low" or "FLT". For the conductance of device 902 to change, current needs to flow through the gate. Because the drain is always "FLT", no current can flow through device 902 when the source 912 or the gate 910 is also "FLT". Therefore, unintended modulation in "half-select" devices (as mentioned herein, "half-select" refers to the "high-GND" or "GND-low" configuration in conventional random update schemes) is avoided. In one or more embodiments of the invention, the gate stack of device 902 has high impedance. Because of this high impedance, "floating" can still be at a sufficiently low voltage to draw current through the low impedance. This is where high gate impedance occurs, where oxide or more is typically included in the gate stack, thus ensuring this property. In conventional two-terminal devices, current needs to pass through the channel (because there is no gate), which can typically have lower impedance. Therefore, in these cases, it is necessary to ground the non-"high" or "low" terminal to avoid latent paths. Because the drain terminal is always floating during the update cycle, three-terminal device 902 is connected via the gate and source. Programming of device 902 occurs when there is a sufficient voltage drop across the gate to the channel to allow current to flow to tune the conductance of device 902.

[0046] The technical benefits of this configuration include floating the drain terminal, preventing device 902 from performing a latent path, as current would need to pass through both gates to unintentionally program both devices. The channel capacitance creates this current (Id). g ) and voltage (V g The exponential correlation between the two voltage levels makes it practically impossible to create a sufficient voltage drop using a floating gate. Therefore, instead of grounding the row wiring for the drain terminal 914 as performed in a conventional random update scheme, in some embodiments of the invention, the row wiring (lines) can be kept floating. By making the lines floating, this method improves the update quality of device 902. This can occur, for example, when device 902 is modified with a single pulse from the gate or source. Even though such an update is much smaller than an update performed across the full voltage, smaller updates are seen for half-biased (half-selected) conditions due to non-ideal thresholding. Floating the drain terminal 914 eliminates these cases, and device 902 remains uncontacted without a consistent voltage pulse.

[0047] In other embodiments of the invention, the cross array 900 may include two column lines per column and one row line per row (not shown). With this configuration, the column lines will connect to the gate and source terminals of the three-terminal device, and the row lines will connect to the drain terminal.

[0048] Various embodiments of the invention are described herein with reference to the accompanying drawings. Alternative embodiments of the invention may be devised without departing from the scope of the invention. In the following description and drawings, various connections and positional relationships (e.g., above, below, adjacent, etc.) are illustrated between elements. Unless otherwise specified, these connections and / or positional relationships may be direct or indirect, and the invention is limited in this respect by not illustrating the figures. Thus, coupling of entities may refer to direct or indirect coupling, and positional relationships between entities may be direct or indirect positional relationships. Furthermore, the various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process with additional steps or functions not described in detail herein.

[0049] One or more methods described herein can be implemented using any of the following techniques or combinations thereof, each of which is well known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having appropriately combined logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0050] For the sake of brevity, conventional techniques relating to the manufacture and use of the present invention may or may not be described in detail herein. Specifically, various aspects of the computing systems and specific computer programs used to implement the different technical features described herein are well known. Consequently, for the sake of brevity, many conventional implementation details are only briefly mentioned or omitted entirely herein, without providing well-known system and / or process details.

[0051] In some embodiments of the invention, various functions or actions may occur at a given location and / or occur in relation to the operation of one or more devices or systems. In some embodiments of the invention, a portion of a given function or action may be performed at a first device or location, and the remainder of the function or action may be performed at one or more additional devices or locations.

[0052] The terminology used herein is for the purpose of describing particular embodiments of the invention only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. It should also be understood that when the terms “comprises” and / or “comprising” are used in this specification, they specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0053] All means or steps in the following claims, plus corresponding structures, materials, actions, and equivalents of the functional elements, are intended to include any structure, material, or action for performing the function in conjunction with other claimed elements as specifically claimed. Embodiments of the invention have been presented for purposes of illustration and description, but are not intended to be exhaustive or limited to the forms described. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments of the invention. Embodiments of the invention were chosen and described in order to best explain the principles and practical application of the embodiments of the invention and to enable others skilled in the art to understand the embodiments of the invention.

[0054] The figures depicted herein are illustrative. Many variations may be made to the figures or steps (or operations) described herein without departing from the spirit of embodiments of the invention. For example, actions may be performed in a different order, or actions may be added, deleted, or modified. Moreover, the term "coupled" describes a signal path between two elements and does not imply a direct connection between the elements without any intermediate elements / connections. All these variations are considered part of the embodiments of the invention.

[0055] The following definitions and abbreviations will be used to interpret the claims and the description. As used herein, the terms “comprising,” “including,” “containing,” “comprising,” “having,” “having,” “with,” or “containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0056] Furthermore, the term "exemplary" is used herein to mean "serving as an example, illustration, or illustration." Any embodiment of the invention described herein as "exemplary" is not necessarily to be construed as superior to or better than other embodiments of the invention. The terms "at least one" and "one or more" should be understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "multiple" should be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connection" can include both indirect "connection" and direct "connection."

[0057] The terms “about,” “substantially,” “roughly,” and their variations are intended to include the degree of error associated with a measurement based on a specific quantity of equipment available at the time of application submission. For example, “about” could include a range of ±8%, 5%, or 2% of a given value.

[0058] This invention can be a system, method, and / or computer program product with any possible level of technical detail integration. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of the invention.

[0059] Computer-readable storage media can be tangible means for retaining and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital universal disk (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or protrusions in slots having instructions recorded thereon, and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through fiber optic cables), or electrical signals transmitted through wires.

[0060] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a suitable computing / processing device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network), or to an external computer or external storage device. The network may include copper cables, optical fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the suitable computing / processing device.

[0061] Computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as a standalone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may execute computer-readable program instructions by utilizing state information from the computer-readable program instructions to personalize the electronic circuitry in order to perform aspects of this invention.

[0062] The present invention will now be described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0063] These computer-readable program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing device, create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that causes a computer, programmable data processing device, and / or other equipment to operate in a particular manner, such that the computer-readable storage medium storing the instructions includes an article of manufacture containing instructions that implement aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0064] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing device, or other device to cause a series of operational steps to be performed on the computer, other programmable device, or other device to produce computer-implemented processing, such that the instructions executed on the computer, other programmable device, or other device perform the functions / actions specified in one or more boxes in a flowchart and / or block diagram.

[0065] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than indicated in the figures. For example, depending on the functions involved, two consecutively shown blocks may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0066] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the embodiments described herein. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements over those found in the market, or to enable those skilled in the art to understand the embodiments described herein.

Claims

1. A computer-implemented method, comprising: The processor performs random updates to a cross-shaped array by generating a set of random pulses. The cross-shaped array includes multiple row routings and multiple column routings, wherein the multiple row routings include a first row routing and the multiple column routings include a first column routing. The three-terminal device is coupled to the first row wiring and the first column wiring at the intersection of the first row wiring and the first column wiring; The resistivity of the three-terminal device is modified in response to the overlap of pulses from the random pulse set at the intersection of the first row and the first column; and In this embodiment, at least one terminal of the three-terminal device is floating.

2. The computer implementation method according to claim 1, wherein, The three-terminal device includes a gate terminal, a source terminal, and a drain terminal.

3. The computer implementation method according to claim 2, wherein, The gate terminal is connected to the first row of wiring.

4. The computer implementation method according to claim 3, wherein: The source terminal is connected to the first column of wiring; The plurality of row wirings includes the second row wiring; The drain terminal is connected to the second row of wiring; and The drain is floating.

5. The computer implementation method according to claim 2, wherein, The gate terminal is connected to the first column of wiring.

6. The computer-implemented method according to claim 5, wherein: The source terminal is connected to the first row of wiring; The plurality of column wirings includes a second column wiring; The drain terminal is connected to the second column of wiring; and The drain terminal is floating.

7. The computer implementation method according to claim 1, wherein, The three-terminal device includes a resistor processing unit.

8. A computing system, comprising: Memory, containing computer-readable instructions; as well as One or more processors for executing the computer-readable instructions, the computer-readable instructions controlling the one or more processors to perform operations, the operations including: Random updates of a cross-array are performed by generating a set of random pulses. The cross-array includes multiple row routings and multiple column routings, wherein the multiple row routings include a first row routing and the multiple column routings include a first column routing. The three-terminal device is coupled to the first row wiring and the first column wiring at the intersection of the first row wiring and the first column wiring; The resistivity of the three-terminal device is modified in response to the overlap of pulses from the random pulse set at the intersection of the first row and the first column; and In this embodiment, at least one terminal of the three-terminal device is floating.

9. The computing system according to claim 8, wherein, The three-terminal device includes a gate terminal, a source terminal, and a drain terminal.

10. The computing system according to claim 9, wherein, The gate terminal is connected to the first row of wiring.

11. The computing system according to claim 10, wherein: The source terminal is connected to the first column of wiring; The plurality of row wirings includes the second row wiring; The drain terminal is connected to the second row of wiring; and The drain terminal is floating.

12. The computing system according to claim 9, wherein, The gate terminal is connected to the first column of wiring.

13. The computing system according to claim 12, wherein: The source terminal is connected to the first row of wiring; The plurality of column wirings includes a second column wiring; The drain terminal is connected to the second column of wiring; and The drain terminal is floating.

14. The computing system according to claim 8, wherein, The three-terminal device includes a resistor processing unit.

15. A computer program product comprising program instructions executable by a processor to cause the processor to perform operations including: The processor performs random updates to a cross-array by generating a set of random pulses. The cross-array includes multiple row routings and multiple column routings, wherein the multiple row routings include a first row routing and the multiple column routings include a first column routing. in, The three-terminal device is coupled to the first row wiring and the first column wiring at the intersection of the first row wiring and the first column wiring; as well as The resistivity of the three-terminal device is modified in response to the overlap of pulses from the random pulse set at the intersection of the first row and the first column; and In this embodiment, at least one terminal of the three-terminal device is floating.

16. The computer program product according to claim 15, wherein, The three-terminal device includes a gate terminal, a source terminal, and a drain terminal.

17. The computer program product according to claim 16, wherein, The gate terminal is connected to the first row of wiring.

18. The computer program product according to claim 17, wherein: The source terminal is connected to the first column of wiring; The plurality of row wirings includes the second row wiring; The drain terminal is connected to the second row of wiring; and The drain terminal is floating.

19. The computer program product according to claim 16, wherein, The gate terminal is connected to the first column of wiring.

20. The computer program product according to claim 19, wherein: The source terminal is connected to the first row of wiring; The plurality of column wirings includes a second column wiring; The drain terminal is connected to the second column of wiring; and The drain terminal is floating.

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