Tunable quantum couplers that facilitate quantum gates between qubits

Abstract

Devices and / or computer-implemented methods are provided that use tunable coupler and capacitor devices to facilitate quantum gates between qubits. According to embodiments, a quantum coupler device can include a tunable coupler coupled between terminals of the same polarity of a first qubit and a second qubit, the tunable coupler configured to control a first coupling between the first qubit and the second qubit. The quantum coupler device can further include a capacitor device coupled to terminals of opposite polarity of the first qubit and the second qubit, the capacitor device configured to provide a second coupling that is opposite in sign relative to the first coupling.

Description

Background Technology

[0001] This disclosure relates to a quantum coupler, and more specifically to a quantum coupler that facilitates quantum gates between qubits (qubits).

[0002] In large quantum computing processors, nearest neighboring qubits are coupled together to generate the qubit-qubit interactions involved in executing quantum gates. When these interactions are always on, unintentional coherent rotations and / or coherent qubit errors occur on bystander qubits (e.g., neighboring qubits), leading to gate errors during quantum computing. These coherent rotations and / or coherent qubit errors limit qubit performance and currently hinder the development of quantum computing processors. Coupling between neighboring qubits is a major source of coherent qubit errors, particularly ZZ errors.

[0003] Some existing techniques attempt to eliminate this coherent rotation and / or coherent qubit error (e.g., ZZ error) by coupling a tunable coupler to the qubit used to perform the quantum gate. The problem with this prior art is that the tunable coupler is designed to operate at a resonant frequency higher than the qubit's resonant frequency. At resonant frequencies higher than this qubit's resonant frequency, ZZ turn-on is small, and achieving fast gates becomes more difficult over a wide range of detuning. Summary of the Invention

[0004] The following summary is presented to provide a basic understanding of one or more embodiments of the invention. This summary is not intended to identify key or essential elements, or to depict any scope of a particular embodiment or any scope of the claims. Its sole purpose is to present the concept in a simplified form as a prelude to the more detailed description that follows. In one or more embodiments described herein, systems, devices, computer-implemented methods, and / or computer program products are described that use tunable couplers and capacitor devices to facilitate quantum gates between qubits.

[0005] According to an embodiment, a quantum coupler device may include a tunable coupler coupled between terminals of the same polarity of a first qubit and a second qubit, the tunable coupler being configured to control a first coupling between the first qubit and the second qubit. The quantum coupler device may further include a capacitor device coupled to terminals of opposite polarity of the first qubit and the second qubit, the capacitor device being configured to provide a second coupling opposite to the first coupling sign. An advantage of such a quantum coupler device is that it can improve the speed of quantum gates (e.g., reduce the time spent performing operations on qubits).

[0006] In some embodiments, the tunable coupler is configured to control the first coupling and the capacitor device is configured to provide the second coupling to eliminate coherent rotations between the first qubit and the second qubit, thereby promoting at least one of the following: reduced quantum gate errors associated with at least one of the first qubit or the second qubit; increased speed of quantum gates including the first qubit and the second qubit; improved performance of quantum processors including the quantum coupler device; or improved fidelity of quantum processors including the quantum coupler device. An advantage of such a quantum coupler device is that it can shut off the coupling between the first qubit and the second qubit, thereby eliminating coherent rotations and / or coherent qubit errors on the first qubit and / or the second qubit that cause gate errors during quantum computing.

[0007] According to another embodiment, a computer-implemented method of quantum coupling may include providing tunable coupling between terminals of the same polarity of a first qubit and a second qubit via a system operatively coupled to a processor. The computer-implemented method of quantum coupling may further include providing capacitive coupling between terminals of opposite polarity of the first qubit and the second qubit by the system. The computer-implemented method of quantum coupling may further include tuning a resonant frequency associated with the tunable coupling by the system. The capacitive coupling generates coupling that cancels out the tunable coupling when the resonant frequency associated with the tunable coupling is less than the resonant frequencies of both the first qubit and the second qubit. An advantage of this computer-implemented method of quantum coupling is that it can be implemented to improve the speed of quantum gates (e.g., reduce the time spent performing operations on qubits).

[0008] In some embodiments, the computer-implemented quantum coupling method described above may further include eliminating coherent rotations on at least one of the first qubits or the second qubits by canceling the coupling of the tunable coupling through the system when the resonant frequency associated with the tunable coupling is less than the resonant frequencies of both the first qubit and the second qubit, thereby promoting at least one of the following: reduced quantum gate errors associated with at least one of the first qubits or the second qubits; increased speed of the quantum gate including the first qubit and the second qubit; improved performance of the quantum processor; or improved fidelity of the quantum processor. An advantage of this computer-implemented quantum coupling method is that it can be implemented to close the coupling between the first qubit and the second qubit, thereby eliminating coherent rotations and / or coherent qubit errors on the first qubit and / or the second qubit that cause gate errors during quantum computing.

[0009] According to another embodiment, a quantum coupler device may include a tunable coupler coupled between a first qubit and a second qubit. The quantum coupler device may further include a capacitor device coupled between the first qubit and the second qubit. The capacitor device generates a coupling with the opposite coupling sign to that from the tunable coupler based on the fact that the resonant frequency of the tunable coupler is lower than the resonant frequencies of both the first qubit and the second qubit. An advantage of this quantum coupler device is that it can improve the speed of quantum gates (e.g., reduce the time spent performing operations on qubits).

[0010] In some embodiments, the tunable coupler is configured to control the first coupling and the capacitor device is configured to provide the second coupling to eliminate coherent rotations between the first qubit and the second qubit, thereby promoting at least one of the following: reduced quantum gate errors associated with at least one of the first qubit or the second qubit; increased speed of quantum gates including the first qubit and the second qubit; improved performance of quantum processors including the quantum coupler device; or improved fidelity of quantum processors including the quantum coupler device. An advantage of such a quantum coupler device is that it can shut off the coupling between the first qubit and the second qubit, thereby eliminating coherent rotations and / or coherent qubit errors on the first qubit and / or the second qubit that cause gate errors during quantum computing.

[0011] According to another embodiment, a device may include a first tunable coupler coupled between terminals of the same polarity of a first qubit and a second qubit, the first tunable coupler being configured to control a first coupling between the first qubit and the second qubit. The device may further include a first capacitor device coupled to terminals of opposite polarity of the first qubit and the second qubit, the first capacitor device being configured to provide a second coupling opposite to the sign of the first coupling. The device may further include a second tunable coupler coupled between terminals of the same polarity of the second qubit and a third qubit, the second tunable coupler being configured to control a third coupling between the second qubit and the third qubit. The device may further include a second capacitor device coupled to terminals of opposite polarity of the second qubit and the third qubit, the second capacitor device being configured to provide a fourth coupling opposite to the sign of the third coupling. An advantage of this device is that it can improve the speed of quantum gates (e.g., reduce the time spent operating on qubits).

[0012] In some embodiments, the first tunable coupler or the second tunable coupler is configured to control the first coupling or the third coupling, and the first capacitor device or the second capacitor device is configured to provide the second coupling or the fourth coupling, respectively, to eliminate coherent rotations between the first qubit and the second qubit or between the second qubit and the third qubit, thereby promoting at least one of the following: reduced quantum gate errors associated with at least one of the first qubit, the second qubit, or the third qubit; increased speed of quantum gates including the first qubit and the second qubit or the second qubit and the third qubit; improved performance of the quantum processor including the device; or improved fidelity of the quantum processor including the device. An advantage of such a device is that it can shut off the coupling between the first qubit and the second qubit and / or the coupling between the second qubit and the third qubit, thereby eliminating coherent rotations and / or coherent qubit errors on the first qubit, the second qubit, and / or the third qubit that cause gate errors during quantum computing.

[0013] According to another embodiment, a computer-implemented method may include providing a first tunable coupling between terminals of the same polarity of a first qubit and a second qubit, and a second tunable coupling between terminals of the same polarity of the second qubit and a third qubit, via a system operatively coupled to a processor. The computer-implemented method may further include providing a first capacitive coupling between terminals of opposite polarity of the first qubit and the second qubit, and a second capacitive coupling between terminals of opposite polarity of the second qubit and the third qubit, via the system. The computer-implemented method may further include tuning a first resonant frequency associated with the first tunable coupling and a second resonant frequency associated with the second tunable coupling via the system. The first capacitive coupling includes a first coupling that cancels the first tunable coupling when the first resonant frequency is less than a third resonant frequency of both the first qubit and the second qubit, and wherein the second capacitive coupling includes a second coupling that cancels the second tunable coupling when the second resonant frequency is less than a fourth resonant frequency of both the second qubit and the third qubit. An advantage of this computer-implemented method is that it can be implemented to improve the speed of quantum gates (e.g., reduce the time spent performing operations on qubits).

[0014] In some embodiments, the computer-implemented method described above may further include eliminating coherent rotations on at least one of the first, second, or third qubits based on at least one of the first or second tunable couplings via the system, thereby promoting at least one of the following: reduced quantum gate errors associated with at least one of the first, second, or third qubits; increased speed of the quantum gate including the first and second qubits or the second and third qubits; improved performance of the quantum processor; or improved fidelity of the quantum processor. An advantage of this computer-implemented method is that it can be implemented to close the coupling between the first and second qubits and / or the coupling between the second and third qubits, thereby eliminating coherent rotations and / or coherent qubit errors on the first, second, and / or third qubits that cause gate errors during quantum computing. Attached Figure Description

[0015] Figure 1 and Figure 2 A circuit diagram of an example, non-limiting device is shown, illustrating an example of a quantum gate between qubits that can be facilitated using a tunable coupler and a capacitor device according to one or more embodiments described herein.

[0016] Figure 3 and Figure 4 Examples, non-limiting diagrams, are shown illustrating how tunable couplers and capacitor devices can be used to facilitate quantum gates between qubits according to one or more embodiments described herein.

[0017] Figure 5 , Figure 6 , Figure 7 , Figure 8 ,and Figure 9 A flowchart illustrating an example, non-limiting computer-implemented method for facilitating quantum gates between qubits using tunable couplers and capacitor devices, according to one or more embodiments described herein.

[0018] Figure 10 A block diagram of an example, non-limiting operating environment in which one or more embodiments described herein may be facilitated is shown. Detailed Implementation

[0019] The following detailed description is illustrative only and is not intended to limit the embodiments and / or their application or use. Furthermore, it is not intended to be construed as being bound by any express or implied information presented in the prior art or invention description or detailed description sections.

[0020] One or more embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals are used throughout to refer to like elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced without these specific details in various circumstances.

[0021] Quantum computing typically utilizes quantum mechanical phenomena to perform computational and information processing functions. It can be viewed as the opposite of classical computing, which typically uses transistors to manipulate binary values. That is, while classical computers can operate on bits of 0 or 1, quantum computers operate on qubits (quantum bits), which are a superposition of both 0 and 1, and can entangle multiple qubits and use interference.

[0022] In view of the aforementioned problems of the prior art, this disclosure can be implemented as a solution to these problems in the form of device and / or computer-implemented methods that use a quantum coupler device to facilitate a quantum gate (e.g., a controlled-phase (C-phase) gate) between a first qubit and a second qubit. The quantum coupler device includes: a tunable coupler coupled between the first qubit and the second qubit; and a capacitor device coupled between the first qubit and the second qubit, wherein the capacitor device generates a coupling with the opposite sign to the coupling from the tunable coupler based on the resonant frequency of the tunable coupler being lower than the resonant frequencies of both the first qubit and the second qubit. An advantage of such device and / or computer-implemented methods is that they can be implemented to improve the speed of quantum gates (e.g., reduce the time spent operating on the qubits).

[0023] In some embodiments, this disclosure can be implemented as a solution to the problems described above in the form of device and / or computer-implemented methods that can facilitate a quantum gate (e.g., a C-phase gate) between the first qubit and the second qubit using the quantum coupling devices described above, wherein the tunable coupler is configured to control the first coupling and the capacitor device is configured to provide the second coupling to eliminate coherent rotation between the first qubit and the second qubit. An advantage of such device and / or computer-implemented methods is that they can be implemented to close the coupling between the first qubit and the second qubit, thereby eliminating coherent rotation and / or coherent qubit errors on the first qubit and / or the second qubit that cause gate errors during quantum computing.

[0024] It will be understood that when a component is referred to as being "coupled" to another component, it can describe one or more different types of coupling, including but not limited to communication coupling, electrical coupling, electromagnetic coupling, operational coupling, optical coupling, physical coupling, thermal coupling, and / or another type of coupling. It will also be understood that the following terms mentioned herein are defined as follows:

[0025] Quantum gates – can represent operations performed on qubits.

[0026] Cphase can represent a controlled phase gate, where the Z-rotation of one qubit is determined by the state of another qubit.

[0027] ZZ can represent state-dependent qubit interactions that can be used to form Cphase gates.

[0028] Flux-tunable - means that its frequency depends on the magnetic flux.

[0029] Transmon-type superconducting qubits, where the charging energy Ec is much smaller than the Josephson energy Ej.

[0030] Figure 1 A circuit diagram of an example, non-limiting device 100 according to one or more embodiments described herein is shown, which may use tunable couplers and capacitor devices to facilitate quantum gates between qubits. Device 100 may include semiconductor and / or superconducting devices that can be implemented in a quantum device. For example, device 100 may include integrated semiconductor and / or superconducting circuits (e.g., quantum circuits) that can be implemented in a quantum device, such as quantum hardware, a quantum processor, a quantum computer, and / or another quantum device. Device 100 may include semiconductor and / or superconducting devices, such as quantum coupler devices and / or tunable quantum coupler devices that can be implemented in such quantum devices as defined above.

[0031] As in Figure 1 As illustrated in the example embodiments depicted, device 100 may include a tunable coupler 102 (in... Figure 1 In the middle, it is represented as a coupler qubit and in Figure 2 The tunable coupler, denoted as coupler qubit 1, can be coupled to the first qubit 106a (in... Figure 1 The second quantum bit 106b (represented as Q1) is in the middle. Figure 1 Between terminals 104a and 104b of the same polarity (e.g., positive (+) or negative (-)), denoted as Q2. Figure 1 The tunable coupler 102 shown in the example embodiment depicted may include a superconducting quantum interference device (SQUID) 118 (referred to herein as SQUID 118). Figure 1 In the example embodiment depicted, SQUID 118 may include two Josephson junctions 120a, 120b (in Figure 1 Each is represented as X) and capacitor 122a. In various embodiments, SQUID 118 can be used to control the tunability of the tunable coupler 102, as illustrated herein (e.g., by applying a magnetic flux through SQUID 118). Figure 1 The first qubit 106a and the second qubit 106b shown in the example embodiment depicted may respectively include Josephson junctions 120c and 120d (in... Figure 1 The two capacitors are denoted as X and 122b and 122c, respectively.

[0032] As in Figure 1 As illustrated in the example embodiments depicted, the tunable coupler 102 can be connected via... Figure 1 The capacitive coupling of capacitors 108a and 108b is visually represented as capacitors 108a and 108b, respectively, coupled between terminals 104a and 104b of the same polarity (e.g., positive (+) or negative (-)) of the first qubit 106a and the second qubit 106b. The tunable coupler 102 may include tunable couplers, including but not limited to flux-tunable couplers, tunable coupler qubits, flux-tunable coupler qubits, tunable qubits, tunable buses, flux-tunable qubit buses, and / or another tunable coupler. The first qubit 106a and / or the second qubit 106b may include qubits, including but not limited to: fixed-frequency qubits, tunable qubits, transmon qubits, fixed-frequency transmon qubits, tunable transmon qubits, and / or another qubit.

[0033] As in Figure 1 As shown in the example embodiments depicted, device 100 may further include capacitor device 110 (in... Figure 1 The capacitor is represented as a bypass capacitor and is in Figure 2 The capacitor device, denoted as bypass capacitor 1, can be coupled to terminals 104a and 104c of opposite polarities (e.g., positive (+) and negative (-)) of the first qubit 106a and the second qubit 106b. (See also...) Figure 1 As illustrated in the example embodiments depicted, the capacitor device 110 may include a first terminal 112a and a second terminal 112b, which may be cross-coupled between the first qubit 106a and the second qubit 106b, wherein the tunable coupler 102 may be directly coupled between the first qubit 106a and the second qubit 106b. For example, as... Figure 1As shown, the first terminal 112a of capacitor device 110 can be coupled to terminal 104a of the first qubit 106a, and the second terminal 112b of capacitor device 110 can be coupled to terminal 104c of the second qubit 106b. Capacitor device 110 may include capacitor devices, including but not limited to differential capacitors (e.g., capacitors connected to the opposite voltage paddle of the transmon qubit), bypass capacitors, and / or other capacitor devices.

[0034] The following describes the references below. Figure 2 The design rules for the capacitor device 110 and / or the second capacitor device 210 of the described device 200 can be implemented according to one or more embodiments of the present disclosure described herein. It should be understood that, in various embodiments, the following references... Figure 2 The tunable coupler 102 and / or the second tunable coupler 202 of the described device 200 can produce the following reference Figure 2 The exchange interaction (J) between the first qubit 106a and the second qubit 106b and / or between the second qubit 106b and the third qubit 206 of the described device 200 can be approximated by the following equation (1). It should be further understood that, in these embodiments, one or more design specifications of the capacitor device 110 of device 100 and / or the second capacitor device 210 of device 200 can be estimated using the equation (1) defined below.

[0035] Equation (1)

[0036]

[0037] in:

[0038] g1 and g2 represent the coupling between the first qubit 106a and the second qubit 106b and the tunable coupler 102, respectively, and / or represent the coupling between the second qubit 106b and the third qubit 206 and the following reference. Figure 2 The coupling between the second tunable coupler 202 of the described device 200;

[0039] ω1 and ω2 represent the frequencies (e.g., resonant frequencies) of the first qubit 106a and the second qubit 106b, respectively;

[0040] ω c This indicates the frequency of the tunable coupler 102;

[0041] δ1 and δ2 represent the anharmonicity of the first qubit 106a and the second qubit 106b, respectively, and / or the second qubit 106b and the following reference. Figure 2The anharmonicity of the third quantum bit 206 of the described device 200.

[0042] In some embodiments, it may be configured (e.g., via computer 1012, system memory 1014, processing unit 1014, AWG, VNA, etc.) with capacitor device 110 and / or referred to below. Figure 2 The bypass capacitor associated with the second capacitor device 210 of the described device 200 is used to generate a bypass capacitor with J. 1,1 The sign is opposite and the magnitude is greater than or equal to J. 1,1 The amplitude of the qubit-to-qubit coupling. For example, in these embodiments, the coupling may be based on device parameters (e.g., via computer 1012, system memory 1014, processing unit 1014, AWG, VNA, etc.) and capacitor device 110 and / or the following references. Figure 2 The bypass capacitor associated with the second capacitor device 210 of the described device 200:

[0043] 1) The anharmonicity of qubits δ1 and δ2 (e.g., the first qubit 106a and the second qubit 106b and / or the second qubit 106b and the following reference) Figure 2 The anharmonicity of the third quantum bit 206 of the described device 200; and

[0044] 2) Couplings g1 and g2 between qubits and tunable couplers (e.g., between the first qubit 106a and the second qubit 106b and the tunable coupler 102, respectively, and / or between the second qubit 106b and the third qubit 206 and the following reference). Figure 2 The coupling between the second tunable coupler 202 of the described device 200.

[0045] In various embodiments, the tunable coupler 102 can be configured to generate and / or control a first coupling 114 (e.g., tunable coupling) between the first qubit 106a and the second qubit 106b. Figure 1 (Not shown in the image). In various embodiments, capacitor device 110 may be configured to generate and / or provide a second coupling 116 (e.g., capacitive coupling, in...). Figure 1(Not shown in the image), this second coupling is symbolically opposite to the first coupling 114 between the first qubit 106a and the second qubit 106b, wherein the first coupling 114 can be generated and / or controlled by the tunable coupler 102 as described above. In these embodiments, the capacitor device 110 can generate and / or provide the second coupling 116 based on the resonant frequency of the tunable coupler 102 being less than the resonant frequencies of both the first qubit 106a and the second qubit 106b, as described below. For example, in these embodiments, the capacitor device 110 can generate and / or provide the second coupling 116 based on the resonant frequency of the tunable coupler 102 being less than the resonant frequency of both the first qubit 106a and the second qubit 106b, as described below, wherein such resonant frequencies of the first qubit 106a and the second qubit 106b can be the same or different.

[0046] In the example embodiment, although Figure 1 Not shown, but device 100, tunable coupler 102, and / or capacitor device 110 may be coupled to a pulse generator device that may be external to device 100. For example, in an example embodiment, device 100, tunable coupler 102, and / or capacitor device 110 may be coupled to a pulse generator device, including but not limited to an arbitrary waveform generator (AWG), a vector network analyzer (VNA), and / or another pulse generator device that can send and / or receive pulses (e.g., microwave pulses) to and / or from device 100, tunable coupler 102, and / or capacitor device 110, wherein such pulse generator device may be external to device 100. In this example embodiment, such pulse generator device (e.g., AWG, VNA, etc.) may also be coupled to a computer (e.g., hereinafter referred to as...). Figure 10 The computer 1012 described includes a memory (e.g., hereinafter referred to as memory) on which instructions (e.g., software, routines, processing threads, etc.) can be stored. Figure 10 The system memory 1016 described herein and the processor capable of executing these instructions that can be stored in the memory (e.g., the following references) Figure 10 The processing unit 1014 described herein. In this example embodiment, such a computer can be used to operate and / or control (e.g., via the processing unit 1014 executing instructions stored in system memory 1014) such a pulse generator device (e.g., AWG, VNA, etc.), thereby enabling the pulse generator device to send and / or receive pulses (e.g., microwave pulses) to and / or from the device 100, the tunable coupler 102, and / or the capacitor device 110.

[0047] Continuing with the example embodiments described above, based on receiving pulses from such a pulse generator device (e.g., via computer 1012, system memory 1014, processing unit 1014, etc.), the tunable coupler 102 can provide tunable coupling (e.g., first coupling 114) between terminals 104a and 104b of the same polarity (e.g., positive (+) or negative (-)) of the first qubit 106a and the second qubit 106b. In this example embodiment, based on receiving pulses from such a pulse generator device (e.g., via computer 1012, system memory 1014, processing unit 1014, etc.), the capacitor device 110 can provide capacitive coupling (e.g., second coupling 116) between terminals 104a and 104c of opposite polarities (e.g., positive (+) and negative (-)) of the first qubit 106a and the second qubit 106b. In this example embodiment, based on pulses received from such a pulse generator device (e.g., via computer 1012, system memory 1014, processing unit 1014, etc.), the tunable coupler 102 can further tune the resonant frequency associated with the tunable coupling (e.g., the first coupling 114), wherein the capacitive coupling (e.g., the second coupling 116) generates a coupling that cancels out the tunable coupling when the resonant frequency associated with the tunable coupling is less than the resonant frequencies of both the first qubit 106a and the second qubit 106b (e.g., less than the resonant frequency of the first qubit 106a and less than the resonant frequency of the second qubit 106b).

[0048] Continuing with the example embodiments described above, based on receiving pulses from such a pulse generator device (e.g., via computer 1012, system memory 1014, processing unit 1014, etc.), device 100 can facilitate the execution of a quantum gate between the first qubit 106a and the second qubit 106b. For example, refer to the following... Figure 3 As described, based on receiving pulses from such a pulse generator device (e.g., via computer 1012, system memory 1014, processing unit 1014, etc.), the tunable coupler 102 can tune the resonant frequency associated with the tunable coupling (e.g., the first coupling 114) so ​​that it moves closer to the resonant frequencies of the first qubit 106a and the second qubit 106b and increases ZZ.

[0049] In various embodiments, the tunable coupler 102 can be configured to control (e.g., via computer 1012, system memory 1014, processing unit 1014, AWG, VNA, etc.) a first coupling 114, and the capacitor device 110 can be configured to provide (e.g., via computer 1012, system memory 1014, processing unit 1014, AWG, VNA, etc.) a second coupling 116 to eliminate the first qubit 106a, the second qubit 106b, and / or the adjacent qubit 106c. Figure 1 Coherent rotation and / or coherent qubit error (e.g., ZZ error) on (not shown). In these embodiments, such adjacent qubits 106c may include qubits that can be formed on device 100 at positions adjacent to the first qubit 106a and / or the second qubit 106b. In these embodiments, based on receiving pulses (e.g., microwave pulses) from pulse generator devices (e.g., AWG, VNA, etc.) as described above (e.g., via computer 1012, system memory 1014, processing unit 1014, etc.), tunable coupler 102 and capacitor device 110 may decouple the first qubit 106a from the second qubit 106b and / or decouple the adjacent qubit 106c from the first qubit 106a and / or the second qubit 106b. In these embodiments, the tunable coupler 102 and the capacitor device 110 can decouple the first qubit 106a from the second qubit 106b and / or the adjacent qubit 106c from the first qubit 106a and / or the second qubit 106b based on (e.g., using) the capacitive coupling described above (e.g., the second coupling 116). When the resonant frequency associated with the tunable coupling (e.g., the resonant frequency associated with the tunable coupler 102) is less than the resonant frequencies of both the first qubit 106a and the second qubit 106b (e.g., less than the resonant frequency of the first qubit 106a and less than the resonant frequency of the second qubit 106b), the capacitive coupling can cancel the tunable coupling (e.g., the first coupling 114). In these embodiments, based on this decoupling of the first qubit 106a from the second qubit 106b and / or the decoupling of the adjacent qubit 106c from the first qubit 106a and / or the second qubit 106b, the tunable coupler 102 and the capacitor device 110 can thereby eliminate coherent rotation and / or coherent qubit errors (e.g., ZZ errors) on the first qubit 106a, the second qubit 106b and / or the adjacent qubit 106c. In these embodiments, based on this elimination of coherent rotation and / or coherent qubit errors, device 100, tunable coupler 102, and / or capacitor device 110 can thereby facilitate: reduced quantum gate errors associated with the first qubit 106a, the second qubit 106b, and / or adjacent qubit 106c; increased speed of the quantum gate including the first qubit 106a and the second qubit 106b; improved performance of the quantum processor including device 100 (e.g., which may include a quantum coupler device); and / or improved fidelity of such a quantum processor including device 100.

[0050] Figure 2A circuit diagram of an example, non-limiting device 200 is shown, illustrating an example of a tunable coupler and a capacitor device used to facilitate quantum gates between qubits according to one or more embodiments described herein. Device 200 may include example, non-limiting alternative embodiments of device 100, wherein device 200 may include additional tunable couplers and additional capacitor devices coupled to a second qubit 106b and further coupled to an additional qubit. For brevity, repeated descriptions of the same elements and / or processes employed in the corresponding embodiments are omitted.

[0051] As in Figure 2 As illustrated in the example embodiments depicted, device 200 may include a second tunable coupler 202 (in... Figure 2 The second tunable coupler, denoted as coupler qubit 2), can couple the second qubit 106b and the third qubit 206 (in... Figure 2 Between terminals 204a and 204b of the same polarity (e.g., positive (+) or negative (-)), denoted as Q3. Figure 2 The second tunable coupler 202 shown in the example embodiment depicted may include a superconducting quantum interference device (SQUID) 220 (referred to herein as SQUID 220). Figure 2 In the example embodiment depicted, SQUID 220 may include two Josephson junctions 222a, 222b (in Figure 2 Each is represented as X) and capacitor 224a. In various embodiments, SQUID 220 can be used to control the tunability of the second tunable coupler 202, as described herein (e.g., by applying a magnetic flux through SQUID 220). Figure 2 The third qubit 206 shown in the example embodiment depicted may include a Josephson junction 222c (in... Figure 2 The following is represented as X) and capacitor 224b.

[0052] As by Figure 2 As illustrated in the example embodiment depicted, the second tunable coupler 202 can be transmitted via... Figure 2The capacitive coupling of capacitors 208a and 208b, respectively, is visually represented by the capacitive coupling between terminals 204a and 204b of the same polarity (e.g., positive (+) or negative (-)) of the second qubit 106b and the third qubit 206. The second tunable coupler 202 may include, but is not limited to, a flux-tunable coupler, a tunable coupler qubit, a flux-tunable coupler qubit, a tunable qubit, a tunable bus, a flux-tunable qubit bus, and / or another tunable coupler. The third qubit 206 may include, but is not limited to, a fixed-frequency qubit, a tunable qubit, a transmon qubit, a fixed-frequency transmon qubit, a tunable transmon qubit, and / or another qubit.

[0053] As by Figure 2 As illustrated in the example embodiments depicted, device 200 may further include a second capacitor device 210 (in... Figure 2 Represented as bypass capacitor 2), this second capacitor device can be coupled to terminals 204a and 204c of opposite polarities (e.g., positive (+) and negative (-)) of the second qubit 106b and the third qubit 206. (See also...) Figure 2 As illustrated in the example embodiment depicted, the second capacitor device 210 may include a first terminal 212a and a second terminal 212b that can be cross-coupled between the second qubit 106b and the third qubit 206, wherein the second tunable coupler 202 can be directly coupled between the second qubit 106b and the third qubit 206. For example, as... Figure 2 As shown, the first terminal 212a of the second capacitor device 210 can be coupled to the terminal 204a of the second qubit 106b, and the second terminal 212b of the second capacitor device 210 can be coupled to the terminal 204c of the third qubit 206. The second capacitor device 210 may include capacitor devices, including but not limited to differential capacitors (e.g., capacitors connected to opposite voltage plates of the transmon qubit), bypass capacitors, and / or another capacitor device.

[0054] In various embodiments, the second tunable coupler 202 can be configured to generate and / or control a third coupling 214 between the second qubit 106b and the third qubit 206 (e.g., the second tunable coupling, in...). Figure 2 (Not shown in the image). In various embodiments, the second capacitor device 210 may be configured to generate and / or provide a fourth coupling 216 (e.g., a second capacitive coupling, in...). Figure 2(Not shown in the diagram), this fourth coupling is symbolically opposite to the third coupling 214 between the second qubit 106b and the third qubit 206, wherein the third coupling 214 can be generated and / or controlled by the second tunable coupler 202 as described above. In these embodiments, the second capacitor device 210 can generate and / or provide the fourth coupling 216 based on the resonant frequency of the second tunable coupler 202 being less than the resonant frequencies of both the second qubit 106b and / or the third qubit 206 (e.g., less than the resonant frequency of the second qubit 106b and less than the resonant frequency of the third qubit 206), as described below.

[0055] In the example embodiment, although Figure 2 Not depicted, but device 200, tunable coupler 102, capacitor device 110, second tunable coupler 202 and / or second capacitor device 210 can be coupled to a pulse generator device (e.g., AWG, VNA, etc.) that is external to device 200 and can send pulses (e.g., microwave pulses) to and / or receive pulses (e.g., microwave pulses) from device 200, tunable coupler 102, capacitor device 110, second tunable coupler 202 and / or second capacitor device 210. In this example embodiment, such a pulse generator device (e.g., AWG, VNA, etc.) can also be coupled to a computer (e.g., hereinafter referred to as...). Figure 10 The computer 1012 described includes a memory (e.g., hereinafter referred to as memory) on which instructions (e.g., software, routines, processing threads, etc.) can be stored. Figure 10 The system memory 1016 described herein and the processor capable of executing these instructions that can be stored in the memory (e.g., the following references) Figure 10 The processing unit 1014 described herein. In this example embodiment, such a computer can be used to operate and / or control (e.g., via the processing unit 1014 executing instructions stored in system memory 1014) such a pulse generator device (e.g., AWG, VNA, etc.), thereby enabling the pulse generator device to send pulses (e.g., microwave pulses) to and / or receive pulses (e.g., microwave pulses) from and from the device 200, tunable coupler 102, capacitor device 110, second tunable coupler 202, and / or second capacitor device 210.

[0056] Continuing with the example embodiments described above, based on receiving pulses from such a pulse generator device (e.g., via computer 1012, system memory 1014, processing unit 1014, etc.): tunable coupler 102 can provide tunable coupling (e.g., first coupling 114) between terminals 104a and 104b with the same polarity (e.g., positive (+) or negative (-)) of the first qubit 106a and the second qubit 106b; and / or second tunable coupler 202 can provide a second tunable coupling (e.g., third coupling 214) between terminals 204a and 204b with the same polarity (e.g., positive (+) or negative (-)) of the second qubit 106b and the third qubit 206. In this example embodiment, based on receiving pulses from such a pulse generator device (e.g., via computer 1012, system memory 1014, processing unit 1014, etc.): capacitor device 110 can provide capacitive coupling (e.g., second coupling 116) between terminals 104a and 104c of opposite polarities (e.g., positive (+) and negative (-)) of the first qubit 106a and the second qubit 106b; and / or second capacitor device 210 can provide a second capacitive coupling (e.g., fourth coupling 216) between terminals 204a and 204c of opposite polarities (e.g., positive (+) and negative (-)) of the second qubit 106b and the third qubit 206. In this example embodiment, based on pulses received from such a pulse generator device (e.g., via computer 1012, system memory 1014, processing unit 1014, etc.): the tunable coupler 102 can further tune the resonant frequency associated with the tunable coupling (e.g., the first coupling 114), wherein the capacitive coupling (e.g., the second coupling 116) generates a resonant frequency when the resonant frequency associated with the tunable coupling is less than the resonant frequency of both the first qubit 106a and the second qubit 106b (e.g., less than the resonant frequency of the first qubit 106a and less than the resonant frequency of the second qubit 106b). The coupling of the tunable coupling is canceled when the resonant frequency of the second tunable coupling (e.g., the resonant frequency of the second tunable coupling 106b) is less than the resonant frequencies of both the second tunable coupling 106b and the third tunable coupling 206 (e.g., less than the resonant frequency of the second tunable coupling 106b and less than the resonant frequency of the third tunable coupling 206).

[0057] In various embodiments, tunable coupler 102 or second tunable coupler 202 can be configured to control (e.g., via computer 1012, system memory 1014, processing unit 1014, AWG, VNA, etc.) first coupling 114 or third coupling 214 respectively, and capacitor device 110 or second capacitor device 210 can be configured to provide (e.g., via computer 1012, system memory 1014, processing unit 1014, AWG, VNA, etc.) second coupling 116 or fourth coupling 216 respectively to eliminate first qubit 106a, second qubit 106b, third qubit 206, and / or adjacent qubit 218 (in Figure 2 Coherent rotation and / or coherent qubit error (e.g., ZZ error) on (not shown). In these embodiments, such adjacent qubits 218 may include qubits that can be formed on device 200 at positions adjacent to the first qubit 106a, the second qubit 106b, and / or the third qubit 206.

[0058] In these embodiments, based on receiving pulses (e.g., microwave pulses) from a pulse generator device (e.g., AWG, VNA, etc.) as described above (e.g., via computer 1012, system memory 1014, processing unit 1014, etc.), the tunable coupler 102 and capacitor device 110 can: decouple the first qubit 106a from the second qubit 106b; and / or decouple adjacent qubits 218 from the first qubit 106a and / or the second qubit 106b. In these embodiments, based on receiving such pulses from such a pulse generator device as described above, the second tunable coupler 202 and the second capacitor device 210 can: decouple the second qubit 106b from the third qubit 206; and / or decouple adjacent qubits 218 from the second qubit 106b and / or the third qubit 206.

[0059] In these embodiments, based on receiving such pulses from such a pulse generator device as described above, the tunable coupler 102 and the capacitor device 110 can, based on (e.g., using) the above-described resonant frequency associated with the tunable coupling (e.g., the resonant frequency associated with the tunable coupler 102) being less than the resonant frequencies of both the first qubit 106a and the second qubit 106b (e.g., less than the resonant frequency of the first qubit 106a and less than the resonant frequency of the second qubit 106b), cancel the capacitive coupling (e.g., the second coupling 116) of the tunable coupling (e.g., the first coupling 114). In these embodiments, based on receiving such a pulse from such a pulse generator device as described above, the second tunable coupler 202 and the second capacitor device 210 can, based on (e.g., using) the above, cancel the second tunable coupling (e.g., the third coupling 214) and the second capacitive coupling (e.g., the fourth coupling 216) when the resonant frequency associated with the second tunable coupling (e.g., the resonant frequency associated with the second tunable coupler 202) is less than the resonant frequencies of both the second qubit 106b and the third qubit 206 (e.g., less than the resonant frequency of the second qubit 106b and less than the resonant frequency of the third qubit 206).

[0060] In these embodiments, based on this decoupling of the first qubit 106a from the second qubit 106b, the second qubit 106b from the third qubit 206, and / or the adjacent qubit 218 from the second qubit 106b and / or the third qubit 206, the tunable coupler 102 and capacitor device 110 and / or the second tunable coupler 202 and the second capacitor device 210 can thereby eliminate coherent rotation and / or coherent qubit errors (e.g., ZZ errors) on the first qubit 106a, the second qubit 106b, the third qubit 206, and / or the adjacent qubit 218. In these embodiments, based on this elimination of coherent rotation and / or coherent qubit errors, device 200, tunable coupler 102, capacitor device 110, second tunable coupler 202, and / or second capacitor device 210 can thereby facilitate: reduced quantum gate errors associated with the first qubit 106a, second qubit 106b, third qubit 206, and / or adjacent qubit 218; increased speed of quantum gates including the first qubit 106a and second qubit 106b or the second qubit 106b and third qubit 206; improved performance of quantum processors including device 200 (e.g., which may include quantum coupler devices); and / or improved fidelity of such quantum processors including device 200.

[0061] In an example embodiment, during operation of device 200, to execute a quantum gate between the first qubit 106a and the second qubit 106b, the tunable coupler 102 can be pulsed on while the second tunable coupler 202 remains off. Conversely, in this example embodiment, during operation of device 200, to execute a quantum gate between the second qubit 106b and the third qubit 206, the second tunable coupler 202 can be pulsed on while the tunable coupler 102 remains off. In example, non-limiting alternative embodiments in which device 200 may include qubits (e.g., four or more qubits, not shown in the figures), each pair of qubits (between which two qubit quantum gates can be executed) may have its own coupler qubit (e.g., tunable coupler 102 or the second tunable coupler 202) and a bypass capacitor (e.g., capacitor device 110 or the second capacitor device 210). In this example, non-limiting alternative embodiment of device 200, one or more embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.) may be generalized (e.g., scaled) to accommodate a number of qubits (e.g., four or more) and / or to accommodate different topologies (e.g., different superconducting circuit topologies).

[0062] Fabrication of the various embodiments of this disclosure described herein and / or illustrated in the accompanying drawings (e.g., apparatus 100, 200, etc.) may include a multi-step sequence of steps, such as photolithography and / or chemical processing steps, which facilitate the incremental creation of electronic-based systems, devices, components, and / or circuits in semiconductor and / or superconducting devices (e.g., integrated circuits). For example, the various embodiments of this disclosure described herein and / or illustrated in the accompanying drawings (e.g., devices 100, 200, etc.) can be fabricated on a substrate (e.g., a silicon (Si) substrate, etc.) using techniques including, but not limited to: photolithography, microlithography, nanolithography, nanoimprint lithography, photomask technology, patterning technology, photoresist technology (e.g., positive photoresist, negative photoresist, hybrid photoresist, etc.), etching technology (e.g., reactive ion etching (RIE), dry etching, wet etching, ion beam etching, plasma etching, laser ablation, etc.), evaporation technology, sputtering technology, plasma ashing technology, heat treatment (e.g., rapid thermal annealing, furnace annealing, thermal oxidation, etc.), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), chemical mechanical planarization (CMP), back polishing technology and / or another technology for fabricating integrated circuits.

[0063] Various materials can be used to manufacture the various embodiments of this disclosure described herein and / or illustrated in the accompanying drawings (e.g., devices 100, 200, etc.). For example, the various embodiments of this disclosure described herein and / or illustrated in the accompanying drawings (e.g., devices 100, 200, etc.) can be manufactured using one or more different material classes, including but not limited to: conductive materials, semiconductor materials, superconducting materials, dielectric materials, polymer materials, organic materials, inorganic materials, non-conductive materials, and / or another material that can be used in conjunction with one or more of the techniques described above for manufacturing integrated circuits.

[0064] Figure 3 A non-limiting figure 300 illustrates an example of how a tunable coupler and capacitor device can facilitate quantum gates between qubits according to one or more embodiments described herein. For brevity, repeated descriptions of the same elements and / or processes employed in the corresponding embodiments are omitted.

[0065] Figure 300 may include resulting data from one or more embodiments implementing the subject matter described herein. For example, Figure 300 may include data from one or more embodiments according to the present disclosure described herein (e.g., referred to below respectively). Figure 5 and Figure 6The described computer-implemented methods 500 and / or 600 implement (e.g., simulation, quantization, etc.) the resulting data generated by device 100. In this example, such as Figure 3 As shown, Figure 300 may include a three-dimensional (3D) plot of the resulting data generated from the implementation device 100, which may be plotted as: qubit detuning in megahertz (MHz) on the Y-axis (e.g., the vertical axis of Figure 300); and the frequency of the tunable coupler 102 on the X-axis (e.g., the horizontal axis of Figure 300). Figure 3 The frequency of the tunable coupler 102 is controlled by the magnetic flux through the SQUID 118 of the device 100 and is expressed in gigahertz (GHz); and the ZZ interaction frequency is represented by a gray shading varying in the Z-axis (e.g., the axis of Figure 300 extending inside and outside the page), corresponding to frequencies ranging from 1 kHz to 1 MHz, as shown in the figure. Figure 3 The ZZ diagram is shown in the figure.

[0066] In the example embodiment, to generate Figure 300, the following parameters can be used to quantize device 100:

[0067] The frequency of the first qubit 106a is 5 GHz;

[0068] The frequency of the second qubit 106b = 5GHz + detuning;

[0069] The coupling between the first qubit 106a, the second qubit 106b, and the tunable coupler 102 is 60 MHz; and

[0070] The direct coupling between the first qubit 106a and the second qubit 106b is -2MHz.

[0071] In an example embodiment, to generate FIG300, the parameters defined above can be used to quantize device 100, wherein the frequency and detuning of tunable coupler 102 can be varied. In this example embodiment, the ZZ interaction between the first qubit 106a and the second qubit 106b can be calculated based on this variation in frequency and detuning of tunable coupler 102. In this example embodiment, as... Figure 3As depicted in Figure 300, region 302 near the frequency of tunable coupler 102 at 3.5 GHz is a region where Z-Z interactions are relatively small, which can represent the operating point where tunable coupler 102 is turned off. In this example embodiment, in order to form two qubit gates between the first qubit 106a and the second qubit 106b, the frequency of tunable coupler 102 can be increased to a relatively large value (e.g., 5 GHz). For example, in this example embodiment, the frequency of tunable coupler 102 can be achieved by applying a magnetic flux through SQUID 118 (e.g., by providing pulses via computer 1012, system memory 1014, processing unit 1014, AWG, VNA, etc., as referenced above). Figure 1 (as described) to control (e.g., increase, decrease, etc.).

[0072] Example, non-limiting alternative embodiments of Figure 300 may include a two-dimensional representation of a plane extending through Figure 300, wherein such a plane may be along... Figure 3 The line 304 is defined as depicted in the diagram. For example, the following description is provided in... Figure 4 Figure 400 shown may include this example, non-limiting alternative embodiment of Figure 300, wherein Figure 400 may include an extension that can run along Figure 300. Figure 3 The two-dimensional side view of this plane is defined by line 304.

[0073] Figure 4 Examples, non-limiting information 400, illustrating the use of tunable couplers and capacitor devices to facilitate quantum gates between qubits according to one or more embodiments described herein are shown. For brevity, repeated descriptions of the same elements and / or processes employed in the corresponding embodiments are omitted.

[0074] As described above, FIG400 may include example, non-limiting alternative embodiments of FIG300, wherein FIG400 may include along Figure 3 The line 304 shown extends through the plane of Figure 300 in a two-dimensional side view. (As in...) Figure 4 As illustrated in the example embodiments depicted herein, Figure 400 shows the effect for a given set of device parameters (e.g., as shown above with reference to...). Figure 3 The ZZ interaction strength between the first qubit 106a and the second qubit 106b (defined device parameters). In this example embodiment, this ZZ interaction strength value is plotted on the Y-axis (e.g., the vertical axis) of FIG400 and corresponds to various flux pulse values ​​(denoted as F-bus (GHz)) of the tunable coupler 102 plotted along the X-axis (e.g., the horizontal axis) of FIG400. Figure 4In the example embodiment shown, FIG400 may have a corresponding time graph 402, which shows the duration of each flux pulse that can be applied to device 100 (e.g., tunable coupler 102, capacitor device 110, etc.) when the quantum gate sequence described below is implemented.

[0075] Quantum gate sequence

[0076] As referenced above Figure 3 As described, device 100 can be implemented by providing pulses (e.g., quantization, simulation, etc.) to tunable coupler 102, which can turn ZZ interaction on and off, and the resulting data obtained from this implementation can be plotted as... Figure 3 and 4 Figures 300, 400, and / or time diagram 402 are shown. Figure 4 In the example embodiment shown in Figure 400 and time diagram 402, the first step of the quantum gate sequence (e.g., between the first qubit 106a and the second qubit 106b) is represented by the number 1 in Figure 400 and time diagram 402. In this example embodiment, at step 1 of such a quantum gate sequence, the frequency (e.g., the resonant frequency) of the tunable coupler 102 (e.g., which may include a tunable bus) can be set such that the ZZ interaction is negligible (e.g., a flux pulse of 3.75 GHz corresponds to a ZZ interaction strength of approximately 10). -5 (MHz). In this example embodiment, the second step of this quantum gate sequence is represented by number 2 in Figure 400 and time diagram 402. In this example embodiment, in step 2 of this quantum gate sequence, the frequency (e.g., resonant frequency) of the tunable coupler 102 can be tuned with a flux pulse (e.g., 4.50 GHz) to enable the ZZ interaction between the first qubit 106a and the second qubit 106b. In this example embodiment, the third step of this quantum gate sequence is represented by number 3 in Figure 400 and time diagram 402. In this example embodiment, in step 3 of this quantum gate sequence, after the flux pulse ends, the frequency (e.g., resonant frequency) of the tunable coupler 102 is returned to the off position and the ZZ interaction between the first qubit 106a and the second qubit 106b is again negligible.

[0077] The various embodiments of this disclosure described herein (e.g., device 100, device 200, etc.) may be associated with different technologies. For example, the various embodiments of this disclosure described herein (e.g., device 100, device 200, etc.) may be associated with quantum computing technology, quantum gate technology, quantum coupler technology, quantum hardware and / or software technology, quantum circuit technology, superconducting circuit technology, machine learning technology, artificial intelligence technology, cloud computing technology, and / or other technologies.

[0078] The various embodiments of this disclosure described herein (e.g., device 100, device 200, etc.) can provide technical improvements to systems, devices, components, operating steps, and / or processing steps associated with the various techniques identified above. For example, the various embodiments of this disclosure described herein (e.g., device 100, device 200, etc.) can provide tunable coupling between terminals of the same polarity of a first qubit (e.g., first qubit 106a) and a second qubit (e.g., second qubit 106b); provide capacitive coupling between terminals of opposite polarity of the first qubit and the second qubit; and / or tune the resonant frequency associated with the tunable coupling, wherein the capacitive coupling generates coupling that cancels out the tunable coupling when the resonant frequency associated with the tunable coupling is less than the resonant frequencies of both the first qubit and the second qubit. In this example, based on this cancellation (e.g., zeroing, offsetting, inversion, etc.) of the tunable coupling, the various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.) can thereby eliminate coherent rotations and / or coherent qubit errors on the first qubit, the second qubit, and / or adjacent qubits (e.g., adjacent qubit 106c) that cause gate errors during quantum computing. In this example, based on this elimination of coherent rotations and / or coherent qubit errors on the first qubit, the second qubit, and / or the adjacent qubit, the various embodiments of the present disclosure described herein (e.g., device 100, device 200, etc.) can thereby facilitate: reduced quantum gate errors associated with the first qubit, the second qubit, and / or the adjacent qubit; increased speed of the quantum gate including the first qubit and the second qubit; improved performance of the quantum processor (e.g., the quantum processor including device 100 or device 200); and / or improved fidelity of the quantum processor.

[0079] The various embodiments of this disclosure described herein (e.g., device 100, device 200, etc.) can provide technical improvements to processing units (e.g., quantum processors including device 100 or device 200, processing unit 1014, etc.) associated with one or more of the various embodiments of this disclosure described herein (e.g., device 100, device 200, etc.). For example, by canceling (e.g., zeroing, offsetting, inverting, etc.) the tunable coupling and eliminating coherent rotations and / or coherent qubit errors (as described above) on the first qubit, the second qubit, and / or the adjacent qubit, one or more of the various embodiments of this disclosure described herein (e.g., device 100, device 200, etc.) can thereby facilitate: reduced quantum gate errors associated with the first qubit, the second qubit, and / or the adjacent qubit; and / or increased speed of the quantum gate including the first qubit and the second qubit. In this example, by reducing such quantum gate error and / or increasing the speed of such quantum gate, one or more of the various embodiments of this disclosure described herein (e.g., device 100, device 200, etc.) can facilitate: improved performance of the quantum processor (e.g., including device 100 or device 200 and the quantum processor executing the quantum gate); and / or improved fidelity of such quantum processor.

[0080] Based on this cancellation of tunable coupling as described above and the elimination of coherent rotations and / or coherent qubit errors on the first qubit, the second qubit, and / or the adjacent qubit, the practical application of the various embodiments of this disclosure described herein (e.g., device 100, device 200, etc.) is that they can be implemented in quantum devices (e.g., quantum processors, quantum computers, etc.) to compute one or more solutions (e.g., heuristics, etc.) of various problems (e.g., estimation problems, optimization problems, etc.) in a range of complexities across various fields (e.g., finance, chemistry, medicine, etc.) with improved fidelity, faster and more efficient. For example, based on this cancellation of tunable coupling as described above and the elimination of coherent rotation and / or coherent qubit errors on the first qubit, the second qubit, and / or the adjacent qubit, the practical application of one or more of the various embodiments of this disclosure described herein (e.g., device 100, device 200, etc.) is that they can be implemented in, for example, a quantum processor (e.g., a quantum processor including device 100 or device 200) to compute one or more solutions (e.g., heuristics, etc.) to optimization problems in the chemical, medical, and / or financial fields, where such solutions can be used to design, for example, new compounds, new drugs, and / or new option pricing systems and / or methods.

[0081] It should be understood that the various embodiments of this disclosure described herein (e.g., device 100, device 200, etc.) provide a novel approach driven by relatively new quantum computing techniques. For example, the various embodiments of this disclosure described herein (e.g., device 100, device 200, etc.) provide a novel method to eliminate unintentional coherent rotations and / or coherent qubit errors occurring on bystander qubits (e.g., first qubit 106a, second qubit 106b, and / or adjacent qubit 106c) that cause gate errors during quantum computing. In this example, this novel method for eliminating such unintentional coherent rotations and / or coherent qubit errors can be used with quantum processors including one or more of the various embodiments of this disclosure described herein (e.g., device 100, device 200, etc.) to achieve faster and more efficient quantum computing with improved fidelity.

[0082] The various embodiments of this disclosure described herein (e.g., device 100, device 200, etc.) can employ hardware or software to solve problems that are inherently highly technical, non-abstract, and cannot be performed by humans as a set of mental actions. In some embodiments, one or more of the processes described herein can be executed by one or more dedicated computers (e.g., dedicated processing units, dedicated classical computers, dedicated quantum computers, etc.) to perform the defined tasks associated with the various technologies identified above. The various embodiments of this disclosure described herein (e.g., device 100, device 200, etc.) can be employed to solve new problems arising from advancements in the aforementioned technologies, quantum computing systems, cloud computing systems, computer architectures, and / or the use of other technologies.

[0083] It should be understood that the various embodiments of this disclosure described herein (e.g., device 100, device 200, etc.) can utilize various combinations of electrical components, mechanical components, and circuits that cannot be replicated in the human mind or performed by a human, because the various operations that can be performed by the various embodiments of this disclosure described herein (e.g., device 100, device 200, etc.) are operations beyond the capabilities of the human mind. For example, the amount of data processed, the speed at which such data is processed, or the type of data processed by the various embodiments of this disclosure described herein (e.g., device 100, device 200, etc.) within a certain time period may be greater than, faster than, or different from the amount, speed, or type of data that can be processed by the human mind within the same time period.

[0084] According to several embodiments, the various embodiments of this disclosure described herein (e.g., device 100, device 200, etc.) may also operate fully toward performing one or more other functions (e.g., full power-on, full execution, etc.) while simultaneously performing the various operations described herein. It should be understood that such simultaneous multi-operation execution is beyond the capabilities of the human mind. It should also be understood that the various embodiments of this disclosure described herein (e.g., device 100, device 200, etc.) may include information that is not manually obtainable by an entity (such as a human user). For example, the type, amount, and / or kind of information included in device 100 and / or device 200 may be more complex than information manually obtainable by a human user.

[0085] Figure 5 A flowchart of an example, non-limiting computer-implemented method 500 according to one or more embodiments described herein is shown, which may use tunable couplers and capacitor devices to facilitate quantum gates between qubits. For brevity, repeated descriptions of the same elements and / or processes employed in the corresponding embodiments are omitted.

[0086] At 502, the computer-implemented method 500 may include a system operatively coupled to a processor (e.g., processing unit 1014, etc.) (e.g., a system including a computer 1012 coupled to an AWG and / or VNA, which may be further coupled to device 100, tunable coupler 102, and / or capacitor device 110) providing tunable coupling (e.g., first coupling 114) between terminals (e.g., terminals 104a and 104b) of the same polarity (e.g., positive (+) or negative (-)) of a first qubit and a second qubit (e.g., first qubit 106a and second qubit 106b).

[0087] At 504, the computer-implemented method 500 may include capacitive coupling (e.g., second coupling 116) between terminals (e.g., terminals 104a and 104c) of opposite polarities (e.g., positive (+) and negative (-)) of the first and second qubits via the system (e.g., computer 1012 coupled to AWG and / or VNA and further coupled to device 100, tunable coupler 102 and / or capacitor device 110).

[0088] At 506, the computer-implemented method 500 may include tuning the resonant frequency associated with the tunable coupling via the system (e.g., computer 1012 coupled to AWG and / or VNA and further coupled to device 100, tunable coupler 102 and / or capacitor device 110), wherein the capacitive coupling generates coupling that cancels out the tunable coupling when the resonant frequency associated with the tunable coupling is less than the resonant frequencies of both the first qubit and the second qubit (e.g., less than the resonant frequency of the first qubit 106a and less than the resonant frequency of the second qubit 106b).

[0089] Figure 6 A flowchart of an example, non-limiting computer-implemented method 600 according to one or more embodiments described herein is shown, which can use tunable couplers and capacitor devices to facilitate quantum gates between qubits. For brevity, repeated descriptions of the same elements and / or processes employed in the corresponding embodiments are omitted.

[0090] At 602, the computer-implemented method 600 may include a system operatively coupled to a processor (e.g., processing unit 1014, etc.) (e.g., a system including a computer 1012 coupled to an AWG and / or VNA, which may be further coupled to device 100, tunable coupler 102, and / or capacitor device 110) providing tunable coupling (e.g., first coupling 114) between terminals (e.g., terminals 104a and 104b) of the same polarity (e.g., positive (+) or negative (-)) of a first qubit and a second qubit (e.g., first qubit 106a and second qubit 106b).

[0091] At 604, the computer-implemented method 600 may include capacitive coupling (e.g., second coupling 116) between terminals (e.g., terminals 104a and 104c) of opposite polarities (e.g., positive (+) and negative (-)) of the first and second qubits via the system (e.g., computer 1012 coupled to AWG and / or VNA and further coupled to device 100, tunable coupler 102 and / or capacitor device 110).

[0092] At 606, the computer-implemented method 600 may include tuning a resonant frequency associated with the tunable coupling via the system (e.g., computer 1012 coupled to AWG and / or VNA and further coupled to device 100, tunable coupler 102 and / or capacitor device 110), wherein the capacitive coupling generates coupling that cancels out the tunable coupling when the resonant frequency associated with the tunable coupling is less than the resonant frequencies of both the first qubit and the second qubit (e.g., less than the resonant frequency of the first qubit 106a and less than the resonant frequency of the second qubit 106b).

[0093] At 608, the computer-implemented method 600 may include decoupling the first qubit from the second qubit by means of the system (e.g., computer 1012 coupled to AWG and / or VNA and further coupled to device 100, tunable coupler 102 and / or capacitor device 110) based on canceling the coupling of the tunable coupling when the resonant frequency associated with the tunable coupling is less than the resonant frequencies of both the first qubit and the second qubit (e.g., less than the resonant frequency of the first qubit 106a and less than the resonant frequency of the second qubit 106b).

[0094] At 610, the computer-implemented method 600 may include eliminating coherent rotations on at least one of the first or second qubits by canceling the coupling of the tunable coupling through the system (e.g., computer 1012 coupled to AWG and / or VNA and further coupled to device 100, tunable coupler 102 and / or capacitor device 110) based on canceling the coupling of the tunable coupling when the resonant frequency associated with the tunable coupling is less than the resonant frequencies of both the first qubit and the second qubit, thereby promoting at least one of the following: reduced quantum gate error associated with at least one of the first or second qubits; increased speed of the quantum gate including the first qubit and the second qubit; improved performance of the quantum processor (e.g., quantum processor including device 100, which may include a quantum coupler device); or improved fidelity of the quantum processor.

[0095] Figure 7 A flowchart of an example, non-limiting computer-implemented method 700 according to one or more embodiments described herein is shown, which may use tunable couplers and capacitor devices to facilitate quantum gates between qubits. For brevity, repeated descriptions of the same elements and / or processes employed in the corresponding embodiments are omitted.

[0096] At 702, the computer-implemented method 700 may include providing a first tunable coupling (e.g., first coupling 114) between terminals (e.g., terminals 104a and 104b) of the same polarity (e.g., positive (+) or negative (-)) of a first qubit and a second qubit (e.g., first qubit 106a and second qubit 106b), and a second tunable coupling (e.g., third coupling 214) between terminals (e.g., terminals 204a and 204b) of the same polarity (e.g., positive (+) or negative (-)) of a second qubit and a third qubit (e.g., third qubit 206).

[0097] At 704, the computer-implemented method 700 may include providing a first capacitive coupling (e.g., second coupling 116) between the first qubit and the terminals (e.g., positive (+) and negative (-)) of opposite polarity (e.g., positive (+) and negative (-)) of the second qubit, and a second capacitive coupling (e.g., fourth coupling 216) between the second qubit and the terminals (e.g., positive (+) and negative (-)) of opposite polarity (e.g., positive (+) and negative (-)) of the third qubit.

[0098] At 706, the computer-implemented method 700 may include tuning a first resonant frequency associated with the first tunable coupling and a second resonant frequency associated with the second tunable coupling via the system (e.g., a computer 1012 coupled to the AWG and / or VNA and further coupled to the device 100, the tunable coupler 102, and / or the capacitor device 110), wherein the first capacitive coupling includes a first coupling that cancels the first tunable coupling when the first resonant frequency is less than a third resonant frequency of both the first qubit and the second qubit (e.g., less than the resonant frequency of the first qubit 106a and less than the resonant frequency of the second qubit 106b), and wherein the second capacitive coupling includes a second coupling that cancels the second tunable coupling when the second resonant frequency is less than a fourth resonant frequency of both the second qubit and the third qubit (e.g., less than the resonant frequency of the second qubit 106b and less than the resonant frequency of the third qubit 206).

[0099] Figure 8A flowchart of an example, non-limiting computer-implemented method 800 according to one or more embodiments described herein is shown, which may use tunable couplers and capacitor devices to facilitate quantum gates between qubits. For brevity, repeated descriptions of the same elements and / or processes employed in the corresponding embodiments are omitted.

[0100] At 802, the computer-implemented method 800 may include providing a first tunable coupling (e.g., first coupling 114) between terminals (e.g., terminals 104a and 104b) of the same polarity (e.g., positive (+) or negative (-)) of a first qubit and a second qubit (e.g., first qubit 106a and second qubit 106b), and a second tunable coupling (e.g., third coupling 214) between terminals (e.g., terminals 204a and 204b) of the same polarity (e.g., positive (+) or negative (-)) of a second qubit and a third qubit (e.g., third qubit 206).

[0101] At 804, the computer-implemented method 800 may include providing a first capacitive coupling (e.g., second coupling 116) between the first qubit and the terminals (e.g., positive (+) and negative (-)) of opposite polarity (e.g., positive (+) and negative (-)) of the second qubit, and a second capacitive coupling (e.g., fourth coupling 216) between the second qubit and the terminals (e.g., positive (+) and negative (-)) of opposite polarity (e.g., positive (+) and negative (-)) of the third qubit.

[0102] At 806, the computer-implemented method 800 may include tuning a first resonant frequency associated with the first tunable coupling and a second resonant frequency associated with the second tunable coupling via the system (e.g., a computer 1012 coupled to the AWG and / or VNA and further coupled to the device 100, the tunable coupler 102, and / or the capacitor device 110), wherein the first capacitive coupling includes a first coupling that cancels the first tunable coupling when the first resonant frequency is less than a third resonant frequency of both the first qubit and the second qubit (e.g., less than the resonant frequency of the first qubit 106a and less than the resonant frequency of the second qubit 106b), and wherein the second capacitive coupling includes a second coupling that cancels the second tunable coupling when the second resonant frequency is less than a fourth resonant frequency of both the second qubit and the third qubit (e.g., less than the resonant frequency of the second qubit 106b and less than the resonant frequency of the third qubit 206).

[0103] At 808, the computer-implemented method 800 may include, through the system (e.g., computer 1012 coupled to AWG and / or VNA and further coupled to device 100, tunable coupler 102 and / or capacitor device 110), performing at least one of the following based on at least one of the first tunable coupling or the second tunable coupling: decoupling the first qubit from the second qubit, or decoupling the second qubit from the third qubit, wherein at least one of the first qubit, the second qubit or the third qubit includes at least one of a fixed-frequency qubit, a tunable qubit, a transmon qubit, a fixed-frequency transmon qubit or a tunable transmon qubit.

[0104] At 810, the computer-implemented method 800 may include eliminating coherent rotations on at least one of the first qubit, the second qubit, or the third qubit via the system (e.g., computer 1012 coupled to AWG and / or VNA and further coupled to device 100, tunable coupler 102, and / or capacitor device 110) based on at least one of the first tunable coupling or the second tunable coupling, thereby promoting at least one of the following: reduced quantum gate error associated with at least one of the first qubit, the second qubit, or the third qubit; increased speed of the quantum gate including the first qubit and the second qubit or the second qubit and the third qubit; improved performance of the quantum processor (e.g., quantum processor including device 200, which may include a quantum coupler device); or improved fidelity of the quantum processor.

[0105] Figure 9A flowchart of an example, non-limiting computer-implemented method 900 according to one or more embodiments described herein is shown, which may use tunable couplers and capacitor devices to facilitate quantum gates between qubits. For brevity, repeated descriptions of the same elements and / or processes employed in the corresponding embodiments are omitted.

[0106] At 902, the computer-implemented method 900 may include providing (e.g., via a system including a computer 1012 coupled to an AWG and / or a VNA, which may be further coupled to a device 100, a tunable coupler 102, and / or a capacitor device 110) a tunable coupling (e.g., a first coupling 114) between terminals (e.g., terminals 104a and 104b) of the same polarity (e.g., positive (+) or negative (-)).

[0107] At 904, the computer-implemented method 900 may include providing (e.g., via a system including a computer 1012 coupled to an AWG and / or a VNA, which may be further coupled to a device 100, a tunable coupler 102, and / or a capacitor device 110) capacitive coupling (e.g., second coupling 116) between terminals (e.g., terminals 104a and 104c) of opposite polarities (e.g., positive (+) and negative (-)) of the second qubit.

[0108] At 906, the computer-implemented method 900 may include tuning (e.g., via a system including a computer 1012 coupled to an AWG and / or VNA, which may be further coupled to device 100, a tunable coupler 102, and / or a capacitor device 110) to a resonant frequency associated with the tunable coupling (e.g., a resonant frequency associated with a first coupling 114 that may be generated and / or controlled by the tunable coupler 102). For example, referring to the above and Figure 1 , Figure 3 and Figure 4 In the example embodiment shown, magnetic flux can be provided (e.g., via a system including a computer 1012 coupled to an AWG and / or a VNA, which may be further coupled to a device 100, a tunable coupler 102, and / or a capacitor device 110) to a tunable coupler 102, such that the magnetic flux enables tuning of the resonant frequency of the tunable coupler 102 such that it is higher than, at, or lower than the resonant frequencies of both the first qubit 106a and the second qubit 106b (e.g., higher than, at, or lower than the resonant frequency of the first qubit 106a and higher than, at, or lower than the resonant frequency of the second qubit 106b).

[0109] At 908, the computer-implemented method 900 may include determining (e.g., via a system including a computer 1012 coupled to an AWG and / or a VNA, which may be further coupled to a device 100, a tunable coupler 102, and / or a capacitor device 110) whether the ZZ interaction between the first qubit and the second qubit is enabled. For example, referring to the above description and Figure 1 , Figure 3 and Figure 4 In the example embodiments shown, whether the resonant frequency associated with the tunable coupler 102 is higher or lower than the resonant frequencies of both the first qubit 106a and the second qubit 106b can correspond to the strength of the ZZ interaction between the first qubit 106a and the second qubit 106b (e.g., higher – corresponding to ZZ on; lower – corresponding to ZZ off). Therefore, in these example embodiments, the determination of whether the ZZ interaction is on can be performed using Figures 300, 400, and / or time diagram 402. In these example embodiments, when the resonant frequency of the tunable coupler 102 is higher than the resonant frequencies of both the first qubit 106a and the second qubit 106b (e.g., higher than the resonant frequency of the first qubit 106a and higher than the resonant frequency of the second qubit 106b), capacitive coupling (e.g., the second coupling 116) does not cancel out (e.g., non-zero, inverted, offset, etc.), tunable coupling (e.g., the first coupling 114) and the ZZ interaction between the first qubit 106a and the second qubit 106b can be increased by applying an increased flux pulse to a point where a quantum gate can be executed between the first qubit 106a and the second qubit 106b (e.g., as shown in the image). Figure 4 As shown in Figure 400, at a flux pulse of 4.50 GHz, the corresponding ZZ interaction strength is approximately 10. -.05 MHz).

[0110] If it is determined at 908 that the ZZ interaction between the first qubit and the second qubit is activated, then at 910, the computer-implemented method 900 may include performing (e.g., via a system including a computer 1012 coupled to an AWG and / or a VNA, which may be further coupled to a device 100, a tunable coupler 102, and / or a capacitor device 110) a quantum gate between the first qubit and the second qubit. For example, referring to the above description and Figure 1 , Figure 3 ,and Figure 4 The example embodiment shown illustrates that when the resonant frequency of the tunable coupler 102 is tuned to a point higher than the resonant frequencies of both the first qubit 106a and the second qubit 106b (e.g., higher than the resonant frequency of the first qubit 106a and higher than the resonant frequency of the second qubit 106b, for example, as... Figure 4 As shown in Figure 400, at a flux pulse of 4.50 GHz, the corresponding strength of the ZZ interaction between the first qubit 106a and the second qubit 106b can realize the performance of the quantum gate between the first qubit 106a and the second qubit 106b.

[0111] At 912, the computer-implemented method 900 may include tuning (e.g., via a system including a computer 1012 coupled to an AWG and / or VNA, which may be further coupled to device 100, a tunable coupler 102, and / or a capacitor device 110) to a resonant frequency associated with the tunable coupling to shut off the ZZ interaction between the first qubit and the second qubit. For example, as described above and in Figure 1 , Figure 3 and Figure 4 In the example embodiment shown, when the resonant frequency of the tunable coupler 102 is lower than the resonant frequencies of both the first qubit 106a and the second qubit 106b (e.g., lower than the resonant frequency of the first qubit 106a and lower than the resonant frequency of the second qubit 106b), capacitive coupling (e.g., second coupling 116) can cancel (e.g., zeroing, inversion, offset, etc.) the tunable coupling (e.g., first coupling 114). At this point, the ZZ interaction between the first qubit 106a and the second qubit 106b is negligible, and therefore, the ZZ interaction is effectively turned off (e.g., as shown). Figure 4 As shown in Figure 400, at a flux pulse of 3.75 GHz, the corresponding ZZ interaction strength is approximately 10. -5 MHz).

[0112] If it is determined at 908 that the ZZ interaction between the first qubit and the second qubit is not enabled, the computer-implemented method 900 may include returning to operation 906 to tune the resonant frequency associated with the tunable coupling. In various embodiments, operations 906 and 908 of the computer-implemented method 900 may be repeated until the ZZ interaction between the first qubit and the second qubit is enabled. In these embodiments, based on repeating operations 906 and 908 until the ZZ interaction between the first qubit and the second qubit is enabled, the computer-implemented method 900 may proceed to operations 910 and 912.

[0113] In order to provide context for the various aspects of the disclosed subject, Figure 10 The following discussion is intended to provide a general description of the suitable environment in which the various aspects of the disclosed subject matter can be realized. Figure 10Block diagrams illustrating example, non-limiting operating environments that can facilitate one or more embodiments described herein are shown. For example, operating environment 1000 can be used to implement the above-described embodiments as described below. Figure 1 and Figure 2 The described example is a non-limiting multi-step manufacturing sequence that can be implemented to manufacture device 100 and / or device 200 according to one or more embodiments of the present disclosure described herein. In another example, operating environment 1000 can be used to implement the above references, as described below. Figures 5-9 The examples described are one or more of the non-limiting computer-implemented methods 500, 600, 700, 800, and / or 900. For the sake of brevity, repeated descriptions of the same elements and / or processes employed in other embodiments described herein are omitted.

[0114] It can be done through a computing system (e.g., Figure 10 The operating environment 1000 shown and described below and / or computing devices (e.g., Figure 10 The computer 1012 shown and described below implements the above reference. Figure 1 and Figure 2 The described example, non-limiting, multi-step manufacturing sequence can be implemented to manufacture apparatus 100 and / or apparatus 200. In a non-limiting example embodiment, such a computing system (e.g., operating environment 1000) and / or such a computing device (e.g., computer 1012) may include one or more processors and one or more memory devices on which executable instructions may be stored, which, when executed by the one or more processors, facilitate the above reference. Figure 1 and Figure 2 The described example demonstrates the performance of a non-limiting multi-step manufacturing sequence. As a non-limiting example, the one or more processors can facilitate the above references by bootsting and / or controlling one or more systems and / or apparatuses operable to perform the manufacture of semiconductor and / or superconductor devices. Figure 1 and Figure 2 The performance of the described example, non-limiting multi-step manufacturing sequence.

[0115] In another example, the above reference Figures 5-9 The described examples, non-limiting computer-implemented methods 500, 600, 700, 800, and / or 900, one or more, can also be implemented (e.g., executed) by the operating environment 1000. As a non-limiting example, one or more processors of such a computing device (e.g., computer 1012) can facilitate the above references by booting and / or controlling one or more systems and / or equipment (e.g., AWG, VNA, etc.) operable to perform operations and / or routines of such computer-implemented methods. Figures 5-9 The described examples, non-limiting computer-implemented methods, include the performance of one or more of 500, 600, 700, 800, and / or 900.

[0116] For simplicity of explanation, the computer-implemented method is depicted and described as a series of actions. It should be understood and recognized that this invention is not limited to the actions shown and / or the order of the actions; for example, actions may occur in different orders and / or simultaneously, and may occur with other actions not presented and described herein. Furthermore, not all actions shown are necessary to implement the computer-implemented method according to the disclosed subject matter. Moreover, those skilled in the art will understand and appreciate that the computer-implemented method may alternatively be represented as a series of interrelated states via state diagrams or events. Furthermore, it should be understood that the computer-implemented method disclosed below and throughout this specification can be stored on an article of manufacture to facilitate the transfer and assignment of such computer-implemented method to a computer. As used herein, the term article of manufacture is intended to cover a computer program accessible from any computer-readable device or storage medium.

[0117] refer to Figure 10 The suitable operating environment 1000 for implementing various aspects of this disclosure may also include a computer 1012. The computer 1012 may further include a processing unit 1014, system memory 1016, and a system bus 1018. The system bus 1018 couples system components, including but not limited to system memory 1016, to the processing unit 1014. The processing unit 1014 may be any of a variety of available processors. Dual microprocessors and other multiprocessor architectures may also be used as the processing unit 1014. The system bus 1018 may be any of several types of bus architectures, including memory buses or memory controllers, peripheral buses or external buses, and / or local buses using any of the various available bus architectures, including but not limited to Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronic Devices (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire (IEEE 1394), and Small Computer System Interface (SCSI).

[0118] System memory 1016 may also include volatile memory 1020 and non-volatile memory 1022. The Basic Input / Output System (BIOS) is stored in the non-volatile memory 1022, and the BIOS contains basic routines for transferring information between components within computer 1012, such as during startup. Computer 1012 may also include removable / non-removable, volatile / non-volatile computer storage media. Figure 10Disk storage device 1024 is shown, for example. Disk storage device 1024 may also include, but is not limited to, devices such as disk drives, floppy disk drives, tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or Memory Sticks. Disk storage device 1024 may also include storage media, either alone or in combination with other storage media. To facilitate connection of disk storage device 1024 to system bus 1018, a removable or non-removable interface, such as interface 1026, is typically used. Figure 10 Software that acts as an intermediary between the user and the basic computer resources described in the suitable operating environment 1000 is also described. Such software may also include, for example, an operating system 1028. The operating system 1028, which may be stored on a disk storage device 1024, is used to control and allocate the resources of the computer 1012.

[0119] System application 1030 utilizes resource management by operating system 1028 through program modules 1032 and program data 1034 stored, for example, on system memory 1016 or disk storage device 1024. It should be understood that this disclosure can be implemented using various operating systems or combinations of operating systems. Users input commands or information into computer 1012 via input device 1036. Input device 1036 includes, but is not limited to: pointing devices such as mice, trackballs, pens, touchpads, keyboards, microphones, joysticks, game controllers, satellite dish antennas, scanners, TV tuner cards, digital cameras, digital camcorders, and webcams. These and other input devices are connected to processing unit 1014 via interface port 1038 through system bus 1018. Interface port 1038 includes, for example, serial ports, parallel ports, game ports, and Universal Serial Bus (USB). Output device 1040 uses some of the same type of ports as input device 1036. Thus, for example, a USB port can be used to provide input to computer 1012 and to output information from computer 1012 to output device 1040. Output adapter 1042 is provided to illustrate the existence of output devices 1040, such as monitors, speakers, and printers, as well as other output devices 1040 that require special adapters. By way of illustration and not limitation, output adapter 1042 includes video cards and sound cards that provide a means of connection between output devices 1040 and system bus 1018. It should be noted that other devices and / or systems of devices provide both input and output capabilities, such as remote computer 1044.

[0120] Computer 1012 can operate in a networked environment using a logical connection to one or more remote computers (such as remote computer 1044). Remote computer 1044 can be a computer, server, router, network PC, workstation, microprocessor-based appliance, peer-to-peer device, or other public network node, and typically may also include many or all of the elements described relative to computer 1012. For simplicity, memory storage device 1046 is described using only remote computer 1044 as an example. Remote computer 1044 is logically connected to computer 1012 via network interface 1048 and then physically connected via communication connection 1050. Network interface 1048 encompasses wired and / or wireless communication networks, such as local area networks (LANs), wide area networks (WANs), cellular networks, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Wire Distributed Data Interface (CDDI), Ethernet, Token Ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks (such as Integrated Services Digital Network (ISDN)) and its variants, packet-switched networks, and Digital Subscriber Line (DSL). Communication connection 1050 refers to the hardware / software used to connect network interface 1048 to system bus 1018. Although communication connection 1050 is shown as being inside computer 1012 for clarity, it can also be located outside computer 1012. For illustrative purposes only, the hardware / software used to connect to network interface 1048 may also include internal and external technologies such as modems (including conventional telephone-grade modems, cable modems, and DSL modems), ISDN adapters, and Ethernet cards.

[0121] This invention can be a system, method, apparatus, and / or computer program product at any possible level of technical detail integration. A computer program product may include a computer-readable storage medium having computer-readable program instructions thereon for causing a processor to execute aspects of the invention. A computer-readable storage medium may be a tangible device capable of retaining and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media may also include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital universal disc (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or those with raised structures in recesses on which instructions are recorded, and any suitable combination thereof. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through fiber optic cables), or electrical signals transmitted through wires.

[0122] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network) to an external computer or external storage device. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the corresponding computing / processing device. The computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). Computer-readable program instructions may execute entirely on a user's computer, partially on a user's computer, as a standalone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may be personalized to execute computer-readable program instructions by utilizing state information of the computer-readable program instructions in order to perform aspects of the present invention.

[0123] Aspects of the invention will now be described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to generate a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer-readable program instructions can also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other devices to operate in a particular manner, such that the computer-readable storage medium in which the instructions are stored includes an article of writing containing instructions that implement aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other equipment to cause a series of operations to be performed on the computer, other programmable apparatus or other equipment to generate computer-implemented processing, such that the instructions executed on the computer, other programmable apparatus or other equipment implement the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0124] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. For this purpose, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a non-linear order. For example, depending on the functions involved, two consecutively shown blocks may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0125] While the subject matter has been described above in the general context of computer-executable instructions for a computer program product running on one or more computers, those skilled in the art will recognize that this disclosure may also be implemented in combination with other program modules. Typically, program modules include routines, programs, components, data structures, etc., that perform specific tasks and / or implement specific abstract data types. Furthermore, those skilled in the art will recognize that the computer implementation methods of the present invention can be practiced with other computer system configurations, including single-processor or multi-processor computer systems, small computing devices, mainframe computers, and computers, handheld computing devices (e.g., PDAs, telephones), microprocessor-based or programmable consumer or industrial electronic products, etc. The aspects shown can also be implemented in a distributed computing environment, where tasks are performed by remote processing devices linked via a communication network. However, some (if not all) aspects of this disclosure can be practiced on a standalone computer. In a distributed computing environment, program modules may reside in both local and remote memory storage devices. For example, in one or more embodiments, the computer-executable component may be executed from memory that may include or consist of one or more distributed memory cells. As used herein, the terms “memory” and “memory cell” are interchangeable. Furthermore, one or more embodiments described herein are capable of executing the code of a computer-executable component in a distributed manner, for example, multiple processors working together or cooperating to execute code from one or more distributed memory units. As used herein, the term "memory" may cover a single memory or memory unit at one location or multiple memory or memory units at one or more locations.

[0126] As used herein, the terms “component,” “system,” “platform,” “interface,” etc., may refer to and / or include computer-related entities or entities associated with an operating machine having one or more specific functions. Entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a thread of execution, a program, and / or a computer. As an illustration, both an application running on a server and the server itself can be components. One or more components may reside within a process and / or a thread of execution, and components may reside on a single computer and / or be distributed across two or more computers. In another example, a corresponding component may be executed from various computer-readable media having various data structures stored thereon. Components may communicate via local and / or remote processes, such as according to a signal having one or more data packets (e.g., data from another component interacting with a component in a local system, a distributed system, and / or data from a component interacting with other systems across a network such as the Internet via that signal). As another example, a component may be a device having specific functions provided by mechanical parts operated by electrical or electronic circuitry, which is operated by a software or firmware application executed by a processor. In this scenario, the processor can be internal or external to the device and can execute at least a portion of the software or firmware application. As another example, the component can be a device that provides specific functionality through electronic components without mechanical parts, wherein the electronic components can include a processor or other components to execute software or firmware that at least partially endows the electronic components with their functionality. In one aspect, the component can be emulated via a virtual machine, for example, within a cloud computing system.

[0127] Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from the context, "X adopts A or B" is intended to mean any natural inclusive permutation. That is, if X adopts A; X adopts B; or X adopts both A and B, then "X adopts A or B" is satisfied in any of the foregoing cases. Additionally, the articles "a" and "a" as used in the subject matter specification and figures should generally be interpreted as meaning "one or more," unless otherwise specified or clearly indicated from the context to the singular form. As used herein, the terms "example" and / or "exemplary" are used to indicate that something is used as an example, illustration, or illustration. To avoid doubt, the subject matter disclosed herein is not limited to such examples. Furthermore, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor does it imply the exclusion of equivalent exemplary structures and techniques known to those skilled in the art.

[0128] As used herein, the term "processor" can refer to substantially any computing processing unit or device, including but not limited to a single-core processor; a single processor with software multithreading capabilities; a multi-core processor; a multi-core processor with software multithreading capabilities; a multi-core processor with hardware multithreading technology; a parallel platform; and a parallel platform with distributed shared memory. Additionally, "processor" can refer to an integrated circuit, application-specific integrated circuit (ASIC), digital signal processor (DSP), field-programmable gate array (FPGA), programmable logic controller (PLC), complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. Furthermore, processors can utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space utilization or enhance the performance of user devices. Processors can also be implemented as a combination of computing processing units. In this disclosure, terms such as "memory," "storage," "data storage," "database," and substantially any other information storage component related to the operation and function of a component are used to refer to a "memory component," an entity embodied in "memory," or a component that includes memory. It should be understood that the memory and / or memory components described herein can be volatile or non-volatile memory, or may include both volatile and non-volatile memory. By way of example and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include, for example, RAM that can serve as an external cache memory. By way of illustration and not limitation, RAM can be obtained in many forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Furthermore, the memory components of the systems or computer-implemented methods disclosed herein are intended to include, but are not limited to, these and any other suitable types of memory.

[0129] The above description includes only examples of systems and computer-implemented methods. Of course, for the purposes of describing this disclosure, it is impossible to describe every conceivable combination of components or computer-implemented methods; however, those skilled in the art will recognize that many further combinations and substitutions of this disclosure are possible. Furthermore, with respect to the use of the terms "comprising," "having," "possessing," etc., in the detailed description, claims, appendices, and drawings, these terms are intended to be interpreted in a manner similar to how the term "comprising" is interpreted when used as a transitional word in a claim.

[0130] Various embodiments have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A quantum coupler device, comprising: A tunable coupler is coupled between terminals of the same polarity of a first qubit and a second qubit, the tunable coupler being configured to control a first coupling between the first qubit and the second qubit; as well as A capacitor device coupled to terminals of opposite polarity of the first qubit and the second qubit, the capacitor device being configured to provide a second coupling opposite to the first coupling sign. The capacitor device provides the second coupling based on the fact that the resonant frequency of the tunable coupler is lower than the resonant frequencies of both the first qubit and the second qubit.

2. The quantum coupler device according to claim 1, wherein, The tunable coupler is configured to control the first coupling and the capacitor device is configured to provide the second coupling to eliminate coherent rotation between the first qubit and the second qubit, thereby promoting at least one of the following: reduced quantum gate error associated with at least one of the first qubit or the second qubit; increased speed of the quantum gate including the first qubit and the second qubit; improved performance of the quantum processor including the quantum coupler device; or improved fidelity of the quantum processor including the quantum coupler device.

3. The quantum coupler device according to claim 1 or 2, wherein, The tunable coupler includes at least one of the following: a flux-tunable coupler, a tunable coupler qubit, a flux-tunable coupler qubit, a tunable qubit, a tunable bus, or a flux-tunable qubit bus.

4. The quantum coupler device according to claim 1 or 2, wherein, At least one of the first qubit or the second qubit includes at least one of a fixed-frequency qubit, a tunable qubit, a transmon qubit, a fixed-frequency transmon qubit, or a tunable transmon qubit.

5. The quantum coupler device according to claim 1 or 2, wherein, The capacitor device includes at least one of a differential capacitor or a bypass capacitor.

6. A computer-based method for quantum coupling, comprising: The system, operatively coupled to the processor, provides tunable coupling between terminals of the same polarity for the first and second qubits; The system provides capacitive coupling between terminals of opposite polarities of the first and second qubits. as well as The system tunes the resonant frequency associated with the tunable coupling. The capacitive coupling generates coupling that cancels out the tunable coupling when the resonant frequency associated with the tunable coupling is less than the resonant frequencies of both the first qubit and the second qubit.

7. The computer-implemented method according to claim 6, further comprising: The system decouples the first qubit from the second qubit by canceling the coupling of the tunable coupling when the resonant frequency associated with the tunable coupling is less than the resonant frequencies of both the first qubit and the second qubit.

8. The computer-implemented method according to claim 6 or 7, further comprising: By eliminating coherent rotations on at least one of the first or second qubits by canceling the coupling of the tunable coupling based on the resonant frequency associated with the tunable coupling being less than the resonant frequencies of both the first and second qubits, the system promotes at least one of the following: reduced quantum gate error associated with at least one of the first or second qubits; increased speed of quantum gates including the first and second qubits; improved performance of the quantum processor; or improved fidelity of the quantum processor.

9. The computer-implemented method according to claim 6 or 7, wherein, At least one of the first qubit or the second qubit includes at least one of a fixed-frequency qubit, a tunable qubit, a transmon qubit, a fixed-frequency transmon qubit, or a tunable transmon qubit.

10. A quantum coupler device, comprising: A tunable coupler, coupled between the first qubit and the second qubit; as well as A capacitor device is coupled between the first qubit and the second qubit. Wherein, based on the fact that the resonant frequency of the tunable coupler is less than the resonant frequencies of both the first qubit and the second qubit, the capacitor device generates a coupling with the opposite sign to the coupling from the tunable coupler.

11. The quantum coupler device according to claim 10, wherein, The capacitor device includes a first terminal and a second terminal, which are cross-coupled between the first qubit and the second qubit, and wherein the tunable coupler is directly coupled between the first qubit and the second qubit.

12. The quantum coupler device according to claim 10 or 11, wherein, The tunable coupler is coupled between terminals of the same polarity of the first qubit and the second qubit, and wherein the tunable coupler is configured to control the coupling between the first qubit and the second qubit.

13. The quantum coupler device according to claim 10 or 11, wherein: The tunable coupler is coupled between terminals of the same polarity of the first qubit and the second qubit; The tunable coupler is configured to control a first coupling between the first qubit and the second qubit; The capacitor device is coupled to terminals of opposite polarities of the first and second qubits; and The capacitor device is configured to provide a second coupling opposite to the first coupling symbol.

14. The quantum coupler device according to claim 13, wherein, The tunable coupler is configured to control the first coupling and the capacitor device is configured to provide the second coupling to eliminate coherent rotation between the first qubit and the second qubit, thereby promoting at least one of the following: reduced quantum gate error associated with at least one of the first qubit or the second qubit; increased speed of the quantum gate including the first qubit and the second qubit; improved performance of the quantum processor including the quantum coupler device; or improved fidelity of the quantum processor including the quantum coupler device.

15. The quantum coupler device according to claim 10 or 11, wherein, The tunable coupler includes at least one of a flux-tunable coupler, a tunable coupler qubit, a flux-tunable coupler qubit, a tunable qubit, a tunable bus, or a flux-tunable qubit bus.

16. The quantum coupler device according to claim 10 or 11, wherein, At least one of the first qubit or the second qubit includes at least one of a fixed-frequency qubit, a tunable qubit, a transmon qubit, a fixed-frequency transmon qubit, or a tunable transmon qubit.

17. The quantum coupler device according to claim 10 or 11, wherein, The capacitor device includes at least one of a differential capacitor or a bypass capacitor.

18. An apparatus comprising: A first tunable coupler is coupled between terminals of the same polarity of the first qubit and the second qubit, and the first tunable coupler is configured to control a first coupling between the first qubit and the second qubit; A first capacitor device is coupled to a terminal of opposite polarity to the first qubit and the second qubit. The first capacitor device is configured to provide a second coupling opposite to the first coupling sign, wherein the first capacitor device provides the second coupling based on the resonant frequency of the first tunable coupler being less than the resonant frequencies of both the first qubit and the second qubit. A second tunable coupler is coupled between terminals of the same polarity of the second and third qubits, and the second tunable coupler is configured to control a third coupling between the second and third qubits; and A second capacitor device, coupled to terminals of opposite polarity of the second and third qubits, is configured to provide a fourth coupling opposite to the third coupling sign, wherein the second capacitor device provides the fourth coupling based on the resonant frequency of the second tunable coupler being less than the resonant frequencies of both the second and third qubits.

19. The device according to claim 18, wherein, The first or second tunable coupler is configured to control the first or third coupling, and the first or second capacitor device is configured to provide the second or fourth coupling, respectively, to eliminate coherent rotations between the first and second qubits or between the second and third qubits, thereby promoting at least one of the following: reduced quantum gate error associated with at least one of the first, second, or third qubits; increased speed of the quantum gate including the first and second qubits or the second and third qubits; improved performance of the quantum processor including the device; or improved fidelity of the quantum processor including the device.

20. The device according to claim 18 or 19, wherein: At least one of the first tunable coupler or the second tunable coupler includes at least one of the following: flux tunable coupler, tunable coupler qubit, flux tunable coupler qubit, tunable qubit, tunable bus, or flux tunable qubit bus. At least one of the first, second, or third qubits includes at least one of a fixed-frequency qubit, a tunable qubit, a transmon qubit, a fixed-frequency transmon qubit, or a tunable transmon qubit; and At least one of the first capacitor device or the second capacitor device includes at least one of a differential capacitor or a bypass capacitor.

21. A computer-implemented method for quantum coupling, comprising: The system, operatively coupled to the processor, provides a first tunable coupling between terminals of the same polarity of the first qubit and the second qubit, and a second tunable coupling between terminals of the same polarity of the second qubit and the third qubit. The system provides a first capacitive coupling between terminals of opposite polarity of the first qubit and the second qubit, and a second capacitive coupling between terminals of opposite polarity of the second qubit and the third qubit. as well as The system tunes a first resonant frequency associated with the first tunable coupling and a second resonant frequency associated with the second tunable coupling. Wherein, the first capacitive coupling includes a first coupling that cancels the first tunable coupling when the first resonant frequency is less than the third resonant frequency of both the first qubit and the second qubit, and wherein the second capacitive coupling includes a second coupling that cancels the second tunable coupling when the second resonant frequency is less than the fourth resonant frequency of both the second qubit and the third qubit.

22. The computer-implemented method according to claim 21, further comprising: The system performs at least one of the following based on at least one of the first tunable coupling or the second tunable coupling: decoupling the first qubit from the second qubit or decoupling the second qubit from the third qubit, wherein at least one of the first qubit, the second qubit or the third qubit includes at least one of a fixed-frequency qubit, a tunable qubit, a transmon qubit, a fixed-frequency transmon qubit or a tunable transmon qubit.

23. The computer-implemented method according to claim 21 or 22, further comprising: By eliminating coherent rotations on at least one of the first, second, or third qubits based on at least one of the first or second tunable couplings, the system facilitates at least one of the following: reduced quantum gate errors associated with at least one of the first, second, or third qubits; increased speed of quantum gates comprising the first and second qubits or the second and third qubits; improved performance of the quantum processor; or improved fidelity of the quantum processor.

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