Grouping power supplies for power saving mode

Abstract

This application relates to grouping power supplies for power saving modes. A memory device can be configured with internal power supply groups whose voltage levels can be modified in turn according to a group order signaled through an on-die timer. For example, when the memory device enters a deep sleep mode, a respective voltage level of a first internal power supply group can be modified to a respective external power supply voltage level at a first time, a respective voltage level of a second internal power supply group can be modified to a respective external power supply voltage level at a second time, and so on. When the memory device exits the deep sleep mode, the internal voltage supplier groups can be modified from the respective external power supply voltage levels to respective operating voltage levels in a group order that is the reverse of the entry group order.

Description

[0001] Cross-references

[0002] This patent application is the national phase application of International Patent Application No. PCT / US2021 / 034360, filed May 26, 2021, entitled “GROUPING POWER SUPPLIES FOR APOWER SAVING MODE”, filed by Nam et al., which claims priority to U.S. Patent Application No. 16 / 890,819, filed June 20, 2020, entitled “GROUPING POWER SUPPLIES FOR A SLEEP MODE”, each of which is assigned to the assignee, and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field involves grouping power supplies for power-saving modes. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to support one of two states, often represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write to or program the states in the memory device.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and phase-change memory (PCM). Memory devices can be volatile or non-volatile. For example, non-volatile FeRAM can maintain its stored logic state for a long time even without external power. Volatile DRAM devices, on the other hand, may lose their stored state when disconnected from external power. FeRAM can achieve densities similar to volatile memory but can also have non-volatile characteristics because it uses ferroelectric capacitors as storage devices. Summary of the Invention

[0006] Describe a method. The method may include: at a first time, receiving a command at a memory device instructing the memory device to enter a sleep mode, wherein the memory device includes a set of internal power supplies associated with a plurality of corresponding voltage levels; at least in part based on receiving the command, at a second time, modifying corresponding voltage levels for a first subset of the set of internal power supplies, wherein at least one of the first subset of the set of internal power supplies is associated with a first voltage level different from an external power supply voltage level; and at least in part based on receiving the command, at the second time, maintaining corresponding voltage levels for a second subset of the set of internal power supplies, wherein at least one of the second subset of the set of internal power supplies is associated with a second voltage level different from the external power supply voltage level.

[0007] Describe a device. The device may include: a set of internal power supplies associated with a plurality of corresponding voltage levels, the set of internal power supplies including: a first subset of internal power supplies including a first internal power supply associated with a first voltage level different from an external power supply voltage level; and a second subset of internal power supplies including a second internal power supply associated with a second voltage level different from the external power supply voltage level; and a controller configured to: at a first time, receive a command instructing the device to enter a sleep mode; at least in part based on receiving the command, at a second time, modify the corresponding voltage level for the first subset of the set of internal power supplies; and at least in part based on receiving the command, at the second time, maintain the corresponding voltage level for the second subset of the set of internal power supplies.

[0008] Describe an apparatus. The apparatus may include: a first internal power supply associated with a first voltage level different from an external power supply voltage level; a second internal power supply associated with a second voltage level different from both the first voltage level and the external power supply voltage level; a set of discharge circuits including: a first discharge circuit configured to modify the first voltage level of the first internal power supply to the first external power supply voltage level; a second discharge circuit configured to modify the second voltage level of the second internal power supply to the second external power supply voltage level; and a set of clamping circuits including: a first clamping circuit configured to maintain the first internal power supply at the first external power supply voltage level; and a second clamping circuit configured to maintain the second internal power supply at the second external power supply voltage level. Attached Figure Description

[0009] Figure 1 Examples of systems that support power grouping for power saving modes are shown, based on the examples disclosed herein.

[0010] Figure 2Examples of memory dies that support power grouping for power saving modes are shown, based on the examples disclosed herein.

[0011] Figure 3A and 3B Examples of nonlinear electrical characteristics of ferroelectric memory cells that support power grouping for power-saving modes are shown, based on the examples disclosed herein.

[0012] Figure 4 An example of a timing diagram supporting power grouping for power saving mode is shown, based on the examples disclosed herein.

[0013] Figure 5 An example of a timing diagram supporting power grouping for power saving mode is shown, based on the examples disclosed herein.

[0014] Figure 6 Examples are shown that support for modifying the voltage configuration of power groups for power saving mode, based on the examples disclosed herein.

[0015] Figure 7 Examples of circuit diagrams supporting power grouping for power saving modes are shown, based on the examples disclosed herein.

[0016] Figure 8 A block diagram of a memory device that supports power grouping for power-saving modes according to various aspects of this disclosure is shown.

[0017] Figure 9 and 10 The flowcharts shown below illustrate one or more methods for grouping power supplies for power-saving modes, based on examples disclosed herein. Detailed Implementation

[0018] Some memory devices (e.g., ferroelectric memory devices) use multiple internal power supplies to generate higher voltages for memory cell write and / or read procedures. In some cases, the memory device may enter a standby mode or sleep mode (e.g., deep sleep mode), for example, to save power or prevent overuse. When entering deep sleep mode, the memory device (e.g., the memory device's controller) may modify the corresponding voltage level of the internal power supply to a corresponding lower voltage level, and may maintain the internal power supply at the corresponding different voltage level (e.g., the lower voltage level) during deep sleep mode. In some cases, if the corresponding voltage level of the internal power supply is modified without regard to the order or sequence of modification, the voltage modification may result in data loss at some ferroelectric memory cells, or may result in latch-up at one or more components of the memory device (e.g., due to the forward bias of junctions in one or more components that form a low-impedance path between the positive supply voltage and the lower supply voltage or ground).

[0019] To mitigate the potential effects of latch-up or positive bias within components of the memory device during sleep entry or exit, the memory device may be configured with internal power supply groups whose voltage levels can be sequentially modified according to the group order signaled via on-die timers. For example, when the memory device enters sleep mode, the corresponding voltage level of the first internal power supply group can be modified to the corresponding external power supply voltage level at a first time, the corresponding voltage level of the second internal power supply group can be modified to the corresponding external power supply voltage level at a second time, and so on. When the memory device exits sleep mode, the internal voltage supply groups can be modified from the corresponding external power supply voltage level to the corresponding operating voltage level in the reverse order of the sleep entry group order.

[0020] The voltage modification mechanism may include one or more bleed circuits and one or more clamping circuits, wherein the clamping circuits can be enabled by comparing the corresponding internal power supply voltage level with a threshold associated with the corresponding external power supply voltage (e.g., enabling the clamping circuit when the internal power supply voltage is within a threshold of the external power supply voltage). This method of grouping and modifying the internal voltage supply can support power saving, reduce or prevent damage from positive bias or latch-up, reduce memory cell data loss (e.g., increase cell security and reliability), and reduce peak current when exiting deep sleep mode.

[0021] The features of this disclosure are firstly in reference to Figure 1-2 The features of this disclosure are described in the context of the memory system and die. The features of this disclosure are described in the context of the nonlinear electrical characteristics, timing diagrams, voltage modification configurations, and circuit diagrams of the ferroelectric memory cells described with reference to Figures 3-7. These and other features of this disclosure are further illustrated by reference to... Figure 8-10 The device diagrams and flowcharts describing the grouping of power supplies for power saving mode are shown and described with reference to the device diagrams and flowcharts.

[0022] Figure 1 An example of a system 100 supporting power grouping for power saving modes, according to the examples disclosed herein, is shown. System 100 may include a host device 105, a memory device 110, and multiple channels 115 coupling the host device 105 and the memory device 110. System 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0023] System 100 may include electronic device components, such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may represent aspects of a computer, laptop computer, tablet computer, smartphone, mobile phone, wearable device, internet-connected device, vehicle controller, etc. Memory device 110 may be a component in the system that can be used to store data from one or more other components of system 100.

[0024] At least a portion of system 100 may be an instance of host device 105. Host device 105 may be an instance of other circuitry within a processor or device that uses memory to perform processes (e.g., a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop, tablet, smartphone, mobile phone, wearable device, internet-connected device, vehicle controller, or other fixed or portable electronic device, and other examples). In some instances, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some instances, external memory controller 120 may be referred to as a host or host device 105.

[0025] Memory device 110 may be a separate device or component that can be used to provide physical memory address / space that can be used or referenced by system 100. In some instances, memory device 110 may be configured to work in conjunction with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be used to support one or more of the following: modulation schemes for modulated signals, various pin configurations for transmitting signals, various physical package dimensions for host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0026] Memory device 110 can be used to store data for components of host device 105. In some instances, memory device 110 may act as a slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. In some cases, commands from host device 105 may instruct memory device 110 to enter a sleep mode. For example, host device 105 may instruct memory device 110 to enter a sleep mode in which some memory device functions are turned off, while some other memory device functions remain operational. Alternatively, host device 105 may instruct memory device 110 to enter a deep sleep mode in which all but the most critical memory device functions, power supply, and voltage are turned off.

[0027] The host device 105 may include one or more of the following components: external memory controller 120, processor 125, basic input / output system (BIOS) component 130, or other components such as one or more peripheral components or one or more input / output controllers. The components of the host device may be coupled to each other via bus 135.

[0028] Processor 125 may be used to provide control or other functionality to at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or system-on-a-chip (SoC), and other instances. In some instances, external memory controller 120 may be implemented by processor 125 or may be part of the processor.

[0029] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more read-only memory (ROM), flash memory, or other non-volatile memory.

[0030] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more segments), wherein each memory cell can be used to store at least one data bit. Memory device 110 comprising two or more memory dies may be referred to as a multi-die memory or multi-die package or multi-chip memory or multi-chip package. In some cases, the memory die may include an on-die timer that can generate timing or clock pulses that can be used by components of the memory die (e.g., when executing one or more programs).

[0031] Device memory controller 155 may include circuitry, logic, or components for controlling the operation of memory device 110. Device memory controller 155 may include hardware, firmware, or instructions that enable memory device 110 to perform various operations, and may be used to receive, transmit, or execute commands, data, or control information related to components of memory device 110. Device memory controller 155 may be used to communicate with one or more of external memory controller 120, the one or more memory dies 160, or processor 125. In some instances, device memory controller 155 may control the operation of memory device 110 as described herein in conjunction with a local memory controller 165 of memory die 160. Device memory controller 155 (e.g., or other memory controllers) may control the operation of one or more components of memory device 110 when entering a sleep mode (e.g., deep sleep mode) (e.g., based on commands received from host device 105).

[0032] In some instances, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command instructing memory device 110 to store data for host device 105 or a read command instructing memory device 110 to provide data stored in memory die 160 to host device 105.

[0033] A local memory controller 165 (e.g., local to memory die 160) can be used to control the operation of memory die 160. In some instances, the local memory controller 165 can be used to communicate with device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include device memory controller 155, and either the local memory controller 165 or the external memory controller 120 can perform the various functions described herein. Thus, the local memory controller 165 can be used to communicate with device memory controller 155, other local memory controllers 165, or directly with external memory controller 120 or processor 125, or combinations thereof. Examples of components that may be included in device memory controller 155 or local memory controller 165 or both may include a receiver for receiving signals (e.g., from external memory controller 120), a transmitter for transmitting signals (e.g., to external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuitry or controllers that may be used to support the described operation of device memory controller 155 or local memory controller 165 or both.

[0034] External memory controller 120 can be used to enable the communication of one or more of the following between system 100 or a component of host device 105 (e.g., processor 125) and memory device 110: information, data, or commands. External memory controller 120 can translate or interpret communications exchanged between components of host device 105 and memory device 110. In some instances, external memory controller 120 or other components of system 100 or host device 105, or the functionality described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125 or other components of system 100 or host device 105. Although external memory controller 120 is depicted as external to memory device 110, in some instances, external memory controller 120 or the functionality described herein may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0035] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be used to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may contain one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths that can be used to carry signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be used to act as portions of a channel.

[0036] Channel 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, signaling may be conveyed through channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol of the signal (e.g., signal level) may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, both modulation symbols of the signal (e.g., signal level) may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0037] In some instances, CA channel 186 can be used to transmit commands between host device 105 and memory device 110, including control information (e.g., address information) associated with the command. For example, CA channel 186 may contain a read command with an address containing the desired data. In some instances, CA channel 186 may contain any number of signal paths for decoding one or more address or command data (e.g., eight or nine signal paths).

[0038] In some instances, clock signal channel 188 can be used to communicate one or more clock signals between host device 105 and memory device 110. Each clock signal can be used to oscillate between high and low states and can support coordination (e.g., in terms of timing) between the actions of host device 105 and memory device 110. In some instances, the clock signal can be single-ended. In some instances, the clock signal can provide a timing reference for command and addressing operations of memory device 110 or other system-wide operations of memory device 110. Therefore, the clock signal can be referred to as a control clock signal, a command clock signal, or a system clock signal. The system clock signal can be generated by a system clock, which can include one or more hardware components (e.g., an oscillator, crystal, logic gate, transistor).

[0039] To mitigate the potential effects of latch-up or positive bias associated with components of the memory device 110 during sleep entry or exit, the memory device 110 may be configured with internal power supply groups whose voltage levels can be sequentially modified according to the group order signaled via on-die timers. For example, when the memory device 110 enters sleep mode, the corresponding voltage level of the first internal power supply group can be modified to the corresponding external power supply voltage level at a first time, the corresponding voltage level of the second internal power supply group can be modified to the corresponding external power supply voltage level at a second time, and so on. When the memory device 110 exits sleep mode, the internal voltage supply groups can be modified from the corresponding external power supply voltage level to the corresponding operating voltage level in the reverse order of the sleep entry group order.

[0040] The voltage modification mechanism may include one or more bleed circuits and one or more clamping circuits, wherein the clamping circuits can be enabled by comparing the corresponding internal power supply voltage level with a threshold associated with the corresponding external power supply voltage (e.g., enabling the clamping circuit when the internal power supply voltage is within a threshold of the external power supply voltage). This method of grouping and modifying the internal voltage supply can support power saving, reduce or prevent damage from positive bias or latch-up, reduce memory cell data loss (e.g., increase cell security and reliability), and reduce peak current when exiting deep sleep mode.

[0041] Figure 2An example of a memory die 200 supporting power grouping for power-saving modes, according to the examples disclosed herein, is shown. The memory die 200 may be a reference. Figure 1 Examples of the described memory die 160. In some instances, the memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. The memory die 200 may include one or more memory cells 205, each programmable to store different logic states (e.g., programmed to be one of a set of two or more possible states). For example, memory cells 205 may be used to store one bit of information at a time (e.g., logic 0 or logic 1). In some instances, memory cells 205 (e.g., multi-level memory cells) may be used to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some instances, memory cells 205 may be arranged in an array, such as referenced in [reference]. Figure 1 The memory array 170 is described.

[0042] Memory cell 205 may store states representing programmable states (e.g., polarization states or dielectric charges) in a capacitor. In a FeRAM architecture, memory cell 205 may include capacitor 240 containing ferroelectric material for storing charges and / or polarizations representing programmable states. Memory cell 205 may include logic storage components, such as capacitor 240, and switching component 245. Capacitor 240 may be an example of a ferroelectric capacitor. A first node of capacitor 240 may be coupled to switching component 245, and a second node of capacitor 240 may be coupled to plate line 220. Switching component 245 may be an example of a transistor or any other type of switching device that selectively establishes or cancels electronic communication between two components.

[0043] The memory die 200 may include access lines (e.g., word lines 210, digital lines 215, and board lines 220) arranged in a pattern, such as a grid pattern. Access lines may be conductive lines coupled to memory cells 205 and used to perform access operations on memory cells 205. In some instances, word lines 210 may be referred to as row lines. In some instances, digital lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digital lines, bit lines, or board lines, or the like, are interchangeable and do not affect understanding or operation. Memory cells 205 may be located at the intersection of word lines 210, digital lines 215, and / or board lines 220.

[0044] Read and write operations can be performed on memory cells 205 by activating or selecting access lines such as word line 210, digital line 215, and / or board line 220. A single memory cell 205 can be accessed at its intersection by biasing word line 210, digital line 215, and board line 220 (e.g., by applying a voltage to word line 210, digital line 215, or board line 220). Activating or selecting word line 210, digital line 215, or board line 220 may involve applying a voltage to the corresponding line.

[0045] The access memory unit 205 can be controlled by a row decoder 225, a column decoder 230, and a board driver 235. For example, the row decoder 225 can receive a row address from the local memory controller 265 and activate word lines 210 based on the received row address. The column decoder 230 can receive a column address from the local memory controller 265 and activate digital lines 215 based on the received column address. The board driver 235 can receive a board address from the local memory controller 265 and activate board lines 220 based on the received board address.

[0046] Selecting or deselecting the memory cell 205 can be achieved by activating or deactivating the activation switch assembly 245. The capacitor 240 can be electrically connected to the digital line 215 using the switch assembly 245. For example, when the switch assembly 245 is deactivated, the capacitor 240 can be isolated from the digital line 215, and when the switch assembly 245 is activated, the capacitor 240 can be coupled to the digital line 215.

[0047] Sensing component 250 can determine the state (e.g., polarization state or charge) stored on capacitor 240 of memory cell 205 and determine the logic state of memory cell 205 based on the detected state. Sensing component 250 may include one or more sensing amplifiers for amplifying the signal output of memory cell 205. Sensing component 250 can compare the signal received from memory cell 205 across digital line 215 with reference 255 (e.g., reference voltage). The detected logic state of memory cell 205 can be provided as an output of sensing component 250 (e.g., provided to input / output 260) and can indicate the detected logic state to another component of memory device 110 including memory die 200.

[0048] The local memory controller 265 can control the operation of the memory cell 205 through various components (e.g., row decoder 225, column decoder 230, board driver 235, and sensing component 250). The local memory controller 265 can be a reference. Figure 1Examples of the described local memory controller 165. In some instances, one or more of the row decoder 225, column decoder 230, board driver 235, and sensing components 250 may be located in the same position as the local memory controller 265. The local memory controller 265 may be used to receive one or more commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with host device 105, another controller associated with memory die 200), translate the commands or data (or both) into information usable by memory die 200, perform one or more operations on memory die 200, and transmit data from memory die 200 to host device 105 based on the performance of said one or more operations. The local memory controller 265 may generate row signals and column address signals to activate target word line 210, target digital line 215, and target board line 220. The local memory controller 265 may also generate and control various voltages or currents used during operation of memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may vary, and may differ for the various operations discussed in the operational memory die 200.

[0049] The local memory controller 265 can be used to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. In some instances, access operations may be performed or otherwise coordinated by the local memory controller 265 in response to various access commands (e.g., from the host device 105). The local memory controller 265 can be used to perform other access operations not listed herein or other operations related to the operation of the memory die 200 (not directly related to accessing memory cells 205).

[0050] For example, a controller (e.g., local memory controller 265) can be configured to sequentially modify the voltage levels of different internal power supply groups according to the group order of on-die timer signaling. For instance, when the memory device enters a deep sleep mode, the controller can initiate a modification of the corresponding voltage level of the first internal power supply group to the corresponding external power supply voltage level at a first time, and can initiate a modification of the corresponding voltage level of the second internal power supply group to the corresponding external power supply voltage level at a second time, and so on. Similarly, when the memory device exits a deep sleep mode, the controller can modify the internal voltage supply groups from the corresponding external power supply voltage level to the corresponding operating voltage level in the reverse order of the deep sleep entry group order.

[0051] Figure 3A and 3BExamples of the nonlinear electrical characteristics of ferroelectric memory cells are illustrated using hysteresis curves 300-a and 300-b, as disclosed herein. Hysteresis curves 300-a and 300-b respectively illustrate the write and read processes of the example ferroelectric memory cells. Hysteresis curves 300-a and 300-b depict the storage of data in a ferroelectric capacitor (e.g., reference ferroelectric capacitor). Figure 2 The charge Q on the capacitor (240) described is a function of the voltage difference V.

[0052] Ferroelectric materials are characterized by spontaneous polarization, meaning they maintain a non-zero polarization in the absence of an electric field. Examples of ferroelectric materials include barium titanate (BaTiO3), lead titanate (PbTiO3), lead zirconate titanate (PZT), and strontium bismuth tantalate (SBT). The ferroelectric capacitors described herein may comprise these or other ferroelectric materials. The polarization within a ferroelectric capacitor generates a net charge at the surface of the ferroelectric material and attracts opposite charges through the capacitor terminals. Therefore, the charge is stored at the interface between the ferroelectric material and the capacitor terminals. Because the polarization can be maintained for a relatively long time, or even indefinitely, in the absence of an externally applied electric field, charge leakage is significantly reduced compared to capacitors used, for example, in DRAM arrays. This reduces the need for refresh operations.

[0053] Hysteresis curves 300-a and 300-b can be understood from the perspective of a single terminal of a capacitor. By way of example, if the ferroelectric material is negatively polarized, then positive charge accumulates at the terminal. Similarly, if the ferroelectric material is positively polarized, then negative charge accumulates at the terminal. Furthermore, the voltages in hysteresis curves 300-a and 300-b represent the voltage difference across the capacitor, and these voltages are directional. For example, a positive voltage can be achieved by applying a positive voltage to the terminal in question (e.g., the cell plate) and keeping the second terminal (e.g., the bottom of the cell) grounded (or approximately zero volts (0V)). A negative voltage can be applied by keeping the terminal in question grounded and applying a positive voltage to the second terminal, i.e., by applying a positive voltage to make the terminal in question negatively polarized. Similarly, two positive voltages, two negative voltages, or any combination of positive and negative voltages can be applied to appropriate capacitor terminals to produce the voltage difference shown in hysteresis curves 300-a and 300-b.

[0054] As depicted in hysteresis curve 300-a, ferroelectric materials can maintain positive or negative polarization with zero voltage difference, resulting in two possible charged states: charge state 305 and charge state 310. According to... Figure 3A and 3B In this example, charge state 305 represents logic 0, and charge state 310 represents logic 1. In some instances, the logic values ​​of the corresponding charge states can be reversed to accommodate other schemes for operating memory cells.

[0055] Logic 0 or 1 can be written to a memory cell by controlling the polarization of the ferroelectric material and thus the charge on the capacitor terminals by applying a voltage. For example, applying a net positive voltage 315 across the capacitor causes charge to accumulate until a charge state 305-a is reached. After removing the voltage 315, charge state 305-a follows path 320 until it reaches charge state 305 at zero voltage. Similarly, writing charge state 310 by applying a net negative voltage 325 results in charge state 310-a. After removing the negative voltage 325, charge state 310-a follows path 330 until it reaches charge state 310 at zero voltage. Charge states 305-a and 310-a can also be referred to as residual polarization (Pr) values, i.e., the polarization (or charge) remaining after removing an external bias (e.g., voltage). The coercive voltage is the voltage at which the charge (or polarization) is zero.

[0056] To read or sense the stored state of a ferroelectric capacitor, a voltage can be applied across the capacitor. In response, the stored charge Q changes, and the extent of this change depends on the initial charge state; that is, the final stored charge (Q) depends on whether the initial stored state was charge state 305-b or 310-b. For example, the hysteresis curve 300-b illustrates two possible stored charge states, 305-b and 310-b. (See reference...) Figure 2 As discussed, a voltage 335 can be applied across capacitor 240. In other instances, a fixed voltage can be applied to the unit plate; although depicted as a positive voltage, voltage 335 can be negative. In response to voltage 335, charge state 305-b can follow path 340. Similarly, if the initially stored charge state is 310-b, then it can follow path 345. The final positions of charge states 305-c and 310-c depend on one or more factors, including the specific sensing scheme and circuitry.

[0057] In some instances, the final charge may depend on the intrinsic capacitance of the digital line connected to the memory cell. For example, if a capacitor is electrically connected to the digital line and a voltage 335 is applied, the voltage of the digital line may rise due to its intrinsic capacitance. The voltage measured at the sensing component may not be equal to voltage 335 and may instead depend on the voltage of the digital line. The positions of the final charge states 305-c and 310-c on the hysteresis curve 300-b may therefore depend on the capacitance of the digital line and can be determined by load line analysis, i.e., charge states 305-c and 310-c can be defined relative to the capacitance of the digital line. As a result, the voltage of the capacitor, i.e., voltage 350 or voltage 355, may differ and may depend on the initial state of the capacitor.

[0058] The initial state of the capacitor can be determined by comparing the digital line voltage with a reference voltage. The digital line voltage can be the difference between voltage 335 and the final voltage across the capacitor (voltage 350 or voltage 355), i.e., the difference between voltage 335 and voltage 350 or the difference between voltage 335 and voltage 355. A reference voltage can be generated such that its magnitude falls between the two possible digital line voltages to determine the stored logic state, i.e., whether the digital line voltage is higher or lower than the reference voltage. After comparison by the sensing component, it can be determined whether the sensed digital line voltage is higher or lower than the reference voltage, and the stored logic value (i.e., logic 0 or 1) of the ferroelectric memory cell can be determined. In some cases, the sensing component can integrate the charge read from the capacitor and output the integrated charge level to determine the stored logic value of the ferroelectric memory cell.

[0059] In some instances, a ferroelectric memory cell can maintain its initial logic state after a read operation. For example, if charge state 305-b is stored, the charge state can travel along path 340 to charge state 305-c during a read operation, and after voltage 335 is removed, the charge state can return to the initial charge state 305-b by traveling along path 340 in the opposite direction. In some instances, a ferroelectric memory cell may lose its initial logic state after a read operation. For example, if charge state 310-b is stored, the charge state can travel along path 345 to charge state 305-c during a read operation, and after voltage 335 is removed, the charge state can relax back to charge state 305-b by traveling along path 340.

[0060] In some instances, the voltage used to read or write the logic state associated with a memory cell (e.g., a ferroelectric capacitor) may be higher than one or more voltages supplied by one or more external power supplies coupled to the memory device (e.g., a memory array). For example, one or more of voltages 315, 325, 335, etc., may be higher than any voltage that can be supplied by any external power supply associated with the memory device. Therefore, the memory device may be associated with an internal power supply (e.g., an analog power supply) or may include an internal power supply configured to provide a higher voltage for the ferroelectric memory device.

[0061] Internal power supplies can provide voltage, current, or combinations thereof through charge pumping, voltage regulation (e.g., via a regulator), etc. In some cases, the internal power supply can be configured to generate a corresponding voltage, and this corresponding voltage can generate a certain amount of current (e.g., a controlled current) in one or more components of the memory device. For example, the one or more power supplies can supply or generate the corresponding voltage for one or more memory cells (e.g., read or write operations on ferroelectric capacitors), one or more sense amplifiers, sense amplifier control logic, voltage level shifters, other peripheral circuitry, or any combination thereof.

[0062] The memory device can read or write logical states to memory cells in an operating mode or a working mode, wherein one or more internal voltage supplies can be used to supply voltage for the operation of the memory device. The one or more internal voltage supplies can be powered on during the operating mode (e.g., maintained at the operating voltage), for example, to reduce the time the one or more internal voltage supplies are powered on before performing read, write, or other memory device functions. In some cases, the memory device can enter a standby mode or a sleep mode (e.g., a deep sleep mode), for example, to save power or prevent data loss. When entering a deep sleep mode, the memory device (e.g., or one or more of its controllers) can modify the corresponding voltage level of the internal power supply to a corresponding lower voltage level, and can maintain the internal power supply at the corresponding lower voltage level during the deep sleep mode.

[0063] In some cases, if the corresponding voltage levels of the internal power supply are modified simultaneously or in a certain order, the voltage change may cause data loss at some ferroelectric memory cells or may cause latch-up at one or more components of the memory device. Latch-up can occur when low-impedance paths are formed between different parts of the circuit, such as between a combination of well structures (e.g., P-wells and N-wells) and the substrate. If latch-up occurs in one or more components of the memory device, those components may be subjected to parasitic currents or voltages, which may cause the components to lose functionality (e.g., temporarily) or may cause them to lose functionality permanently. In some cases, latch-up may be associated with forward bias, where components allow continuous current flow, which may interrupt or destroy component functionality. In some cases, high-voltage transistors (e.g., P-type metal-oxide-semiconductor (PMOS) transistors within the memory device may be associated with latch-up when the internal voltage supply is modified to corresponding lower voltage levels in a sequence that forward biases the junction.

[0064] To mitigate the potential effects of latch-up or positive bias within components of the memory device during sleep entry or exit, the memory device may be configured with internal power supply groups whose voltage levels can be sequentially modified according to a group order controlled by an on-die timer. For example, when the memory device enters sleep mode, the corresponding voltage level of the first internal power supply group can be modified to a corresponding lower voltage level at a first time, the corresponding voltage level of the second internal power supply group can be modified to a corresponding lower voltage level at a second time, and so on. When the memory device exits sleep mode, the internal voltage supply groups can be modified from the corresponding lower voltage level to the corresponding operating voltage level in the reverse order of the sleep entry group order.

[0065] The internal voltage supply can support power saving by sorting and modifying the group, reduce or prevent the damaging effects of positive bias or latch-up, reduce ferroelectric cell data loss (e.g., increase cell safety and reliability), and reduce peak current when exiting deep sleep mode.

[0066] Figure 4 An example of timing diagram 400 supporting power grouping for power saving mode is shown, based on the examples disclosed herein. See reference... Figure 3A and 3B As described, the internal power supplies of the memory device can be grouped for voltage modification operations (e.g., turning the internal power supplies off and on) when entering or exiting a deep sleep mode. Timing diagram 400 may illustrate examples of different timings of voltage modification operations when the various internal power supply groups enter or exit a deep sleep mode.

[0067] Depending on various aspects, the internal power supplies of a memory device can be grouped according to the relationships between power supplies in the memory device's circuitry. Constraints can be imposed on each power supply based on circuit relationships, and power supplies can be assigned to groups based on these constraints. For example, a memory device may contain power supplies A, B, C, D, and E, with constraints determined based on circuit elements as B≥A, C≥B, D≥A, and E≥B. Therefore, power supply A can be assigned to a first group, power supplies B and D to a second group, and power supplies C and E to a third group. Typically, power supply groups may contain suppliers with similar voltage ranges; however, some internal power supplies may be assigned to groups of other power supplies with different voltage ranges (e.g., based on constraints). Alternatively or additionally, latch-up risk can be assessed, and power supplies can be assigned to the same or different groups based on latch-up risk. For example, if power supplies A and B have the constraint B≥A, and the latch-up risk is low based on the circuit elements supplied by A and B, then they can be assigned to the same group, while higher-risk circuitry supplied by A or B may determine that power supplies A and B are placed in different groups.

[0068] In one example, the internal power supplies in the first internal power supply group may correspond to internal power supply voltages 405-a, 405-b, 405-c, 405-d, and 405-e, respectively. Similarly, in one example, the internal power supplies in the second internal power supply group may correspond to internal power supply voltages 410-a, 410-b, 410-c, 410-d, 410-e, and 410-f, respectively, and one or more internal power supplies in the third internal power supply group may correspond to internal power supply voltage 415-a. The internal power supplies (e.g., regardless of the internal power supply grouping) can be energized according to a power-on sequence, for example, at or after the device, denoted as 450, is started. At 450 (e.g., at device startup), one or more external power supplies, such as those denoted by external power supply voltages 420 and 425, may reach the external power supply operating voltage level. Subsequently or simultaneously, internal power supplies may begin to increase their respective voltage levels (e.g., higher than external power supply voltage levels, such as external power supply voltage 420 or 425) to the corresponding operating voltage levels (e.g., using charge pump circuits, etc.).

[0069] Although this article references Figure 4 The example described contains three internal power groups, but the example can be applied to any number of internal power groups. The number of internal power groups can be adjusted or configured based on operating conditions, power requirements, etc.

[0070] A host device associated with the memory device may provide or couple the one or more external power supplies to the memory device. In some cases, the host device may transmit a command to the memory device instructing it to enter or exit a deep sleep mode. For example, at 455, the host device may transmit a first command instructing the memory device to enter a deep sleep mode. The first command may generate (e.g., at the memory device) a latch signal 430 that indicates to the internal power supply that the memory device is entering a deep sleep mode. For example, the latch signal 430 may be received by an on-die timer of the memory device, wherein the on-die timer may then generate one or more signals instructing the corresponding internal power supply group to power down for the deep sleep mode. The on-die timer can be programmable to determine the order in which the deep sleep mode is entered and / or exited for the corresponding internal power supply group. The on-die timer may generate or be based on the internal clock of the memory device and may, for example, be coupled to a stable voltage supply or power supply to maintain operation during the deep sleep mode.

[0071] For example, at or after 455, an on-die timer can modify the state of the first signal 435 to indicate a flag indicating that the first internal power supply group is powered down for deep sleep mode. The internal power supplies in the first internal power supply group can be powered down by modifying their respective voltages to the corresponding external supply voltages. For example, starting at or after 455, internal power supply voltages 405-a, 405-b, and 405-c can be modified to the external power supply voltage 425, and internal power supply voltage 405-e can be modified to zero voltage or a steady-state voltage. In some cases, the internal power supply voltage 405 can be modified via one or more bleeder circuits, which are referred to herein as... Figure 6 and 7 Further description. In some cases, one or more voltages in the power supply group (e.g., internal power supply voltage 405-d) may not be modified and can remain at a stable voltage, for example, based on one or more deep sleep mode settings. Once the modified internal power supply voltage 405 reaches the corresponding external power supply voltage, the internal power supply voltage 405 can be clamped to the external power supply voltage (e.g., maintained at the external power supply voltage). The clamping operation and circuitry are described herein with reference to... Figure 6 and 7 Further description.

[0072] At 460, an on-die timer can modify the state of the second signal 440 to indicate a flag indicating that the second internal power supply group is powered down for deep sleep mode by modifying their respective voltages to the corresponding external supply voltages. For example, starting at or after 460, internal power supply voltages 410-a to 410-e can be modified to external power supply voltage 420, and internal power supply voltages 410-f can be modified to external power supply voltage 425. Similar to the first internal power supply group, the internal power supply voltage 410 can be modified via one or more bleed circuits and can be maintained at the corresponding external power supply voltage via one or more clamping circuits.

[0073] At 465, an on-die timer can modify the state of a third signal 445 to indicate a flag instructing the third internal power supply group to power down for deep sleep mode by modifying their respective voltages to the corresponding external supply voltages. For example, starting at or after 465, internal power supply voltages 415-a can be modified to external power supply voltage 420. Each of the internal power supply voltages can reach its corresponding external power supply voltage at or before 470, such that the power-down procedure can be completed at or before 470, and the entry time into deep sleep mode can be represented by the time between 455 and 470. Similar to the first and second internal power supply groups, internal power supply voltage 415 can be modified via one or more bleed circuits and can be maintained at its corresponding external power supply voltage via one or more clamping circuits.

[0074] At 475, the host device may transmit a second command instructing the memory device to exit sleep mode. This second command may modify (e.g., at the memory device) latch signal 430 such that latch signal 430 indicates to the internal power supply that the memory device is exiting sleep mode. For example, latch signal 430 may be received by an on-die timer of the memory device, which may then generate or modify one or more signals instructing the corresponding internal power supply group to power on to exit sleep mode. For example, at or after 475, the on-die timer may modify a third signal 445 to indicate a flag instructing a third internal power supply group to power on to exit sleep mode. The internal power supplies in the third internal power supply group can be powered off by modifying their respective voltages from the respective external supply voltages to the respective operating voltages of the internal power supplies. For example, starting at or after 475, the internal power supply voltage 415-a may be modified (e.g., increased) from the external power supply voltage 420.

[0075] At 480, an on-die timer can modify the second signal 440 to indicate a flag indicating that the second internal power supply group is powered on to exit deep sleep mode. The internal power supplies in the second internal power supply group can be powered off by modifying their respective voltages from their respective external supply voltages to their respective operating voltages. For example, starting at or after 480, internal power supply voltages 410-a to 410-d can be modified (e.g., increased) from external power supply voltage 420, and internal power supply voltage 410-f can be modified (e.g., increased) from external power supply voltage 425.

[0076] At 485, an on-die timer can modify a first signal 435 to indicate a flag indicating that the first internal power supply group is powered on to exit deep sleep mode. For example, starting at or after 485, internal power supply voltages 405-a, 405-b, and 405-c can be modified from external power supply voltage 425 (e.g., increased), and internal power supply voltage 405-e can be modified from zero voltage or steady-state voltage (e.g., decreased). Each of the internal power supply voltages can reach its corresponding operating voltage at or before 490, such that the power-on procedure can be completed at or before 490, and the exit time from deep sleep mode can be represented by the time between 475 and 490. In some cases, starting at 490 (e.g., after each internal power supply reaches its operating voltage level), the memory device can resume operation in wake-up mode (e.g., exit deep sleep mode).

[0077] In some cases, the order in which internal power groups exit deep sleep mode can be the reverse of the order in which they enter deep sleep mode. In some cases, the time between modifications to the voltages of consecutive internal power groups (e.g., for deep sleep entry or exit) can support modifying the corresponding voltage of one internal power group before starting to modify the corresponding voltage of another internal power group.

[0078] like Figure 4 As shown and described herein, some internal power supplies within the same group can be modified and clamped to different external voltage levels (e.g., different external power supplies). The external voltage level clamped to an internal power supply may be based on the operating voltage level of the internal power supply, the proximity of the internal power supply voltage level to the corresponding external power supply voltage level, a safety factor for clamping the internal power supply to the corresponding external power supply voltage level, or a combination thereof, and other factors.

[0079] Figure 5 An example of timing diagram 500 supporting power grouping for power-saving modes is shown, according to the examples disclosed herein. As described with reference to Figures 3 and 4, the internal power supplies of the memory device can be grouped for voltage modification operations (e.g., turning internal power off and on) when entering or exiting a deep sleep mode. Timing diagram 500 may show examples of different timings of voltage modification operations when each internal power group enters or exits a deep sleep mode. In some cases, different internal power groups may or may not enter a deep sleep mode (e.g., may be modified to an external power supply voltage level), for example, based on the duration of the deep sleep mode.

[0080] In one example, the internal power supply of a memory device can be divided into three groups, for example, reference... Figure 4 As described. Although this article references Figure 5 The example described illustrates three internal power groups, but the example is equally applicable to any number of internal power groups. The number of internal power groups can be adjusted or configured based on operating conditions, power requirements, etc.

[0081] For reference Figure 4 As described, in some cases, the host device may transmit a command to the memory device instructing the memory device to enter or exit a deep sleep mode. For example, at or before 525, the host device may transmit a first command instructing the memory device to enter a deep sleep mode. The first command may generate (e.g., at the memory device) a latch signal 505 that instructs the internal power supply to enter a deep sleep mode. For example, the latch signal 505 may be received by an on-die timer of the memory device, wherein the on-die timer may then generate one or more signals instructing the corresponding internal power group to power down for the deep sleep mode. The host device may also transmit a second command instructing the memory device to exit a deep sleep mode, and in some cases, based on the second command, the latch signal may end or be modified (e.g., to instruct the on-die timer to exit a deep sleep mode). The on-die timer is programmable to determine the order in which the corresponding internal power group enters and / or exits a deep sleep mode.

[0082] For example, the on-die timer may generate: a first signal 510, which may indicate (e.g., during a transition from a first state to a second state) a flag indicating that a first internal power group is powered down for deep sleep mode; a second signal 515, which may indicate (e.g., during a transition from a first state to a second state) a flag indicating that a second internal power group is powered down for deep sleep mode; and a third signal 520, which may indicate (e.g., during a transition from a first state to a second state) a flag indicating that a third internal power group is powered down for deep sleep mode. In some cases, one or more signals generated by the on-die timer may be based on the duration of a latch signal 505 associated with deep sleep mode. For example, if the latch signal 505 changes or ends (e.g., to indicate exiting deep sleep mode) before the on-die timer generates the second signal 515 and / or the third signal 520, then deep sleep mode may end without powering down the second and / or third internal power groups. In this way, higher voltage power supplies (e.g., associated with the second and / or third groups) may remain powered during shorter deep sleep modes, which saves power and reduces voltage interference.

[0083] In the first example, at 525, the on-die timer can receive a latch signal 505-a, and at or after 525, based on the latch signal 505-a, can modify the first signal 510-a to indicate that the first internal power group has entered a deep sleep mode. In response to the first signal 510-a, the corresponding voltage level of the first internal power group can be modified to the corresponding external power supply voltage level. At 530, and based on the latch signal 505-a, the on-die timer can modify the second signal 515-a to indicate that the second internal power group has entered a deep sleep mode. In response to the second signal 515-a, the corresponding voltage level of the second internal power group can be modified to the corresponding external power supply voltage level. At 535, based on the latch signal 505-a, the on-die timer can modify the third signal 520-a to indicate that the third internal power group has entered a deep sleep mode. In response to the third signal 520-a, the corresponding voltage level of the third internal power group can be modified to the corresponding external power supply voltage level.

[0084] At or before point 540, the host device may transmit a second command to the memory device instructing it to exit deep sleep mode. At point 540, latch signal 505-a may change state to instruct the memory device to exit deep sleep mode. At or after point 540, based on latch signal 505-a, the on-die timer may modify third signal 520-a to instruct a third internal power supply group to exit deep sleep mode. In response to the change in third signal 520-a, the corresponding voltage level of the third internal power supply group may be modified from the corresponding external power supply voltage level to the corresponding operating voltage level.

[0085] At 545, based on latch signal 505-a, the on-die timer can modify the second signal 515-a to indicate that the second internal power group has exited deep sleep mode. In response to the change in the second signal 515-a, the corresponding voltage level of the second internal power group can be modified from the corresponding external power supply voltage level to the corresponding operating voltage level. At 550, based on latch signal 505-a, the on-die timer can modify the first signal 510-a to indicate that the first internal power group has exited deep sleep mode. In response to the change in the first signal 510-a, the corresponding voltage level of the second internal power group can be modified from the corresponding external power supply voltage level to the corresponding operating voltage level.

[0086] In the second example, at 525, the on-die timer can receive latch signal 505-b, and at or after 525, based on latch signal 505-b, modify the first signal 510-b to indicate that the first internal power group has entered a deep sleep mode. In response to the first signal 510-b, the corresponding voltage level of the first internal power group can be modified to the corresponding external power supply voltage level. At 530, based on latch signal 505-b, the on-die timer can modify the second signal 515-b to indicate that the second internal power group has entered a deep sleep mode. In response to the second signal 515-b, the corresponding voltage level of the second internal power group can be modified to the corresponding external power supply voltage level. At or before 555, the host device can transmit a second command to the memory device instructing the memory device to exit deep sleep mode. For example, the host device can transmit the second command before the third internal power group enters deep sleep mode, such that the on-die timer can prevent modification of the third signal 520-b.

[0087] At 555, latch signal 505-b can change state to indicate that the memory device exits deep sleep mode. At or after 555, based on latch signal 505-b, the on-die timer can modify second signal 515-b to indicate that the second internal power group exits deep sleep mode. In response to the change of second signal 515-b, the corresponding voltage level in the second internal power group can be modified from the corresponding external power supply voltage level to the corresponding operating voltage level. At 560, based on latch signal 505-b, on-die timer can modify first signal 510-b to indicate that the first internal power group exits deep sleep mode. In response to the change of first signal 510-b, the corresponding voltage level in the second internal power group can be modified from the corresponding external power supply voltage level to the corresponding operating voltage level.

[0088] In the third example, at 525, the on-die timer can receive latch signal 505-c, and at or after 525, based on latch signal 505-c, can modify the first signal 510-c to indicate that the first internal power group has entered a deep sleep mode. In response to the first signal 510-c, the corresponding voltage level of the first internal power group can be modified to the corresponding external power supply voltage level. At or before 565, the host device can transmit a second command to the memory device instructing the memory device to exit the deep sleep mode. For example, the host device can transmit the second command before either the second or third internal power group enters a deep sleep mode, such that the on-die timer can prevent modification of the second signal 515-c and the third signal 520-c.

[0089] At position 565, latch signal 505-c can change state to indicate that the memory device exits deep sleep mode. At or after position 565, based on latch signal 505-c, the on-die timer can modify first signal 510-c to indicate that the first internal power supply group exits deep sleep mode. In response to the change in first signal 510-c, the corresponding voltage level of the second internal power supply group can be modified from the corresponding external power supply voltage level to the corresponding operating voltage level.

[0090] Figure 6 An example of a voltage modification configuration 600 supporting power grouping for power-saving modes, according to the examples disclosed herein, is illustrated. As described with reference to Figures 3-5, the internal power supply of the memory device can be grouped for voltage modification operations (e.g., turning the internal power supply off and on) when entering or exiting a deep sleep mode. The voltage modification configuration 600 may illustrate circuitry and associated operational timing for modifying (e.g., discharging) and maintaining (e.g., clamping) the internal power supply voltage 645 to a corresponding external power supply voltage 650. The internal power supply voltage 645 and the external power supply voltage 650 may correspond to the internal power supply 615 (e.g., a voltage pump and / or oscillator) of the memory device and the external power supply of the memory device, respectively.

[0091] The voltage modification configuration 600 may include a bleed circuit 605 for modifying the internal power supply voltage 645 from the operating voltage 655 to the external power supply voltage 650, and a clamping circuit 610 for maintaining the internal power supply voltage 645 at the external power supply voltage 650. As described herein, at 685, an on-die timer of the memory device may modify a signal 660 to indicate that the internal power supply has entered a deep sleep mode. As an example, the internal power supply 615 may receive the signal 660 using a VCCP pump sensing circuit 620. The signal 660 may reset a latch 630 associated with the circuit to modify the internal power supply voltage 645. In response to the signal 660, the internal power supply signal 665 may switch to an "off" state, for example, indicating that the pump of the internal power supply 615 is off. Similarly, in response to the signal 660, a bleed signal 670 may be modified, which may activate the bleed circuit 605 to modify the internal power supply voltage 645 to the external power supply voltage 650 via leakage current and the current of the bleed circuit 605. For example, one or more switching components 640 of the bleed circuit may engage in response to the bleed signal 670.

[0092] In some cases, the bleeder circuit 605 may include one or more resistors 635 or one or more current sources that can support modification of the internal power supply voltage 645 by discharging power from the internal power supply 615 and other signal traces or components connected to the internal power supply voltage 645. In some cases, the current and associated power dissipation of the bleeder circuit 605 may be less than the current and associated power dissipation of the external power supply voltage 650, such that the bleeder circuit 605 may have no effect on the external power supply voltage 650. For example, the charge injected by the current of the bleeder circuit 605 may be much less than that consumed by other components connected to the external power supply voltage 650.

[0093] In response to signal 660, comparator signal 680 can be modified to indicate the activation state of comparator 625 associated with internal power supply 615 for comparing internal power supply voltage 645 and external power supply voltage 650 (e.g., or a threshold of external power supply voltage 650). When internal power supply voltage 645 reaches a voltage within the threshold of external power supply voltage 650 (e.g., a threshold defined for deep sleep mode voltage), for example at 690, comparator 625 can deactivate discharge circuit 605 (e.g., deactivate discharge signal 670, which deactivates one or more switching components 640), and can activate clamping circuit 610 (e.g., activate or generate clamping signal 675). After deactivating discharge circuit 605 and activating clamping circuit 610, comparator 625 can be deactivated (e.g., based on comparator signal 680 being deactivated).

[0094] Clamping circuit 610 may be configured to clamp one or more instances of internal power supply voltage 645 with external power supply voltage 650, to clamp or maintain internal power supply voltage 645 at external power supply voltage 650. For example, clamping circuit 610 may include one or more transistors (e.g., PMOS or N-type metal-oxide-semiconductor (NMOS) transistors) that can be enabled by a change in the state of clamping signal 675 to couple internal power supply voltage 645 to external power supply voltage 650.

[0095] At or before 695, an on-die timer can modify signal 660 to indicate that internal power supply 615 is exiting deep sleep mode. For example, internal power supply 615 can receive signal 660 using VCCP pump sensing circuitry 620. In response to signal 660, internal power supply signal 665 can switch to an "on" signal, for example, indicating that the pump of internal power supply 615 is turned on again. Similarly, in response to signal 660, clamp signal 675 can be disconnected, which de-energizes clamp circuitry 610, allowing internal power supply voltage 645 to return to operating voltage 655, and internal power supply 615 can exit deep sleep mode.

[0096] Figure 7 An example of circuit diagram 700 supporting power grouping for power-saving modes is shown, according to the examples disclosed herein. As described with reference to Figures 3-6, the internal power supply of the memory device can be grouped for voltage modification operations (e.g., turning the internal power supply off and on) when entering or exiting a deep sleep mode. Circuit diagram 700 may show examples of voltage modification (e.g., discharge) and sustaining (e.g., clamping) operations, such as those shown in Figures 3-6. Figure 6 As described.

[0097] In one example, the internal power supplies in the first internal power supply group 702-a may correspond to internal power supply nodes 705-a, 705-b, and 705-c, respectively. Similarly, in one example, the internal power supplies in the second internal power supply group 702-b may correspond to internal power supply nodes 710-a, 710-b, and 710-c, respectively, and one or more internal power supplies in the third internal power supply group 702-c may correspond to internal power supply nodes 715-a and 715-b. In some cases, for illustration purposes, one or more voltages (e.g., voltages at nodes) described herein may represent multiple voltages of the same internal power supply group sharing the same node in circuit diagram 700. Although referenced herein... Figure 7 The example described contains three internal power groups, but the example can be adapted to any number of internal power groups.

[0098] The voltages described herein may be coupled with a corresponding bleeder circuit 740, clamping circuit 745, or a combination thereof. In some cases, the corresponding bleeder circuit 740 and / or clamping circuit 745 may be coupled with a corresponding comparator 750, for example, to compare the voltage of an internal power supply with the voltage of an external power supply (e.g., external power supply voltages 725, 730, and / or 735). For example, the bleeder circuit 740 and comparator 750 may be like a reference... Figure 6 It works as described.

[0099] The first internal power supply group 702-a (e.g., and the corresponding internal power node 705) can be modified to a corresponding external voltage based on a first signal 755, which may, for example, activate one or more transistors and a corresponding bleeder circuit 740. For example, the voltage at internal power node 705-a can be modified to an external power supply voltage 725, the voltage at internal power node 705-b can be modified to (e.g., coupled to) an external power supply voltage 730 via bleeder circuit 740, and the voltage at internal power node 705-c can be modified to an external power supply voltage 735. Similarly, the second internal power supply group 702-b (e.g., and the voltage at the corresponding internal power node 710) can be modified to a corresponding external voltage based on a second signal 760 (e.g., which may be generated by an on-die timer), which may, for example, activate a corresponding bleeder circuit 740 and a comparator 750. The corresponding voltages at internal power nodes 710-a, 710-b, and 710-c can be modified to the external power supply voltage 725, for example, using corresponding bleeder circuits 740 and clamping circuits 745. For example, activation of signal 760 (e.g., a transition to a logic state corresponding to modification of the second internal power group 702-b) can enable bleeder circuits 740-d, 740-e, and 740-f, and enable comparators 750-a, 750-b, and 750-c. Bleeder circuits 740-d, 740-e, and 740-f can be enabled until the corresponding comparator 750-a, 750-b, or 750-c determines that the voltage at the corresponding internal power node 710 is within the threshold of the external power supply voltage 725. When the voltage at the corresponding internal power node 710 is within the threshold of the external power supply voltage 725 (e.g., or in some cases, a different external power supply voltage), the corresponding internal power node 710 can be clamped (e.g., maintained) using clamps 745-a, 745-b, and 745-c respectively (e.g., and the discharge circuit 740 can be deactivated).

[0100] In some instances, the internal power supply group 702 may generate a completion signal 770 when at least one internal power supply in the internal power supply group 702 has been clamped to the corresponding external power supply voltage. For example, the completion signal 770 may be generated when at least one internal power supply in the second internal power supply group 702-c has been modified and clamped. Alternatively, the completion signal 770 may be generated when at least one internal power supply in the second internal power supply group 702-c has been modified and clamped (e.g., using an AND gate). In such cases, the third internal power supply group 702-c (e.g., the voltage at the corresponding internal power supply node 715) may be modified to the corresponding external voltage based on a fourth signal 775 generated from a third signal 765 (e.g., which may be generated by an on-chip timer) and the completion signal 770 (e.g., an AND operation of the third signal and the completion signal 770). For example, activation of signal 775 (e.g., transition to a logic state corresponding to modifying the third internal power supply group 702-c) can enable bleed circuits 740-g and 740-h, and enable comparators 750-d and 750-e.

[0101] Discharge circuits 740-g and 740-h can be enabled until the corresponding comparator 750-d or 750-e determines that the voltage at the corresponding internal power node 715 is within the threshold of the external power supply voltage 725. When the voltage at the corresponding internal power node 715 is within the threshold of the external power supply voltage 725 (e.g., or in some cases, a different external power supply voltage), the corresponding internal power node 715 can be clamped (e.g., maintained) using clampers 745-d and 745-e respectively (e.g., and the discharge circuit 740 can be deactivated). Although Figure 7 The completion signal 770 is shown to be generated using the same comparator 750 used to enable the clamping circuit 745, but in some cases, a separate comparator with a different threshold can be used. For example, the completion signal 770 can use a higher threshold than the clamping circuit 745, such that in some cases, the bleed circuitry for the next group (e.g., the third group) can be allowed to be enabled before clamping one or more internal power supplies in the second internal power supply group 702-b.

[0102] Although the first internal power supply group 702-a is shown using a discharge circuit 740 and without a clamping circuit 745 or a comparator 750 (e.g., due to a lower voltage resulting in a more defined discharge time), one or more internal power supplies in the first internal power supply group 702-a may include a clamping circuit 745 or a comparator 750. Additionally, a completion signal may be generated from both the first internal power supply group 702-a and the second internal power supply group 702-b (e.g., using a comparator 750).

[0103] Figure 8A block diagram 800 illustrates a memory device 805 supporting power grouping for power-saving modes, according to an example disclosed herein. The memory device 805 may be a reference... Figure 1-7 Examples of various aspects of the described memory device. Memory device 805 may include a sleep command component 810, a voltage modification component 815, an internal voltage sustaining component 820, a voltage recovery component 825, and an external voltage sustaining component 830. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0104] The sleep command component 810 may receive, at a first time, a command instructing the memory device to enter a sleep mode, wherein the memory device includes a set of internal power supplies associated with a set of corresponding voltage levels. In some instances, the sleep command component 810 may receive, at a third, fourth, or fifth time, a second command instructing the memory device to exit the sleep mode.

[0105] The voltage modification component 815 can, based on receiving the command, modify the corresponding voltage level for a first subset of the set of internal power supplies at a second time, wherein at least one of the first subset of the set of internal power supplies is associated with a first voltage level different from the external power supply voltage level. In some instances, the voltage modification component 815 can, based on receiving the command, modify the corresponding voltage level for a second subset of the set of internal power supplies at a third time. In some instances, the voltage modification component 815 can, based on receiving the command, modify the corresponding voltage level for a third subset of the set of internal power supplies at a fourth time.

[0106] In some cases, a first subset of the set of internal power supplies is associated with a first threshold for forward voltage bias, a first voltage level threshold for power supply operation, or a combination thereof. In some cases, a second subset of the set of internal power supplies is associated with a second threshold for forward voltage bias, a second voltage level threshold for power supply operation, or a combination thereof.

[0107] In some instances, the voltage modification component 815 may activate a corresponding discharge circuit to modify the voltage level of a corresponding voltage level of a first subset of the set of internal power supplies from a corresponding first operating voltage level to a corresponding threshold voltage level of a corresponding first external power supply voltage level. In some instances, the voltage modification component 815 may compare the corresponding voltage level of the first subset of the set of internal power supplies with the corresponding first external power supply voltage level via a corresponding comparator coupled to the corresponding discharge circuit. In some instances, the voltage modification component 815 may deactivate the corresponding discharge circuit based on a comparison of the corresponding voltage level of the first subset of the set of internal power supplies with the corresponding first external power supply voltage level. In some cases, each corresponding first voltage level of the first subset of the set of internal power supplies is higher than each corresponding first external power supply voltage level.

[0108] The internal voltage sustaining component 820 may, based on receiving the command, maintain a corresponding voltage level for a second subset of the set of internal power supplies at a second time, wherein at least one of the second subset of the set of internal power supplies is associated with a second voltage level different from the external power supply voltage level. In some instances, the internal voltage sustaining component 820 may, based on receiving the command, maintain a corresponding voltage level for a third subset of the set of internal power supplies at a second and a third time, wherein at least one of the third subset of the set of internal power supplies is associated with a third voltage level different from the external power supply voltage level.

[0109] In some instances, the internal voltage sustaining component 820 may activate the corresponding clamping circuit based at least in part on the corresponding voltage level of the corresponding internal power supply in a first subset of the set of internal power supplies reaching a corresponding threshold voltage level of the corresponding first external power supply voltage level.

[0110] The voltage recovery component 825 may, based on receiving a second command, modify the corresponding voltage level for a first subset of the set of internal power supplies at a fourth time, wherein the modification includes restoring at least one of the first subset of the set of internal power supplies to a first voltage level. In some instances, the voltage recovery component 825 may, based on receiving a second command, modify the corresponding voltage level for a second subset of the set of internal power supplies at a fifth time, wherein the modification includes restoring at least one of the second subset of the set of internal power supplies to a second voltage level.

[0111] In some instances, the voltage recovery component 825 may, based on receiving a second command, modify the corresponding voltage level for a first subset of the set of internal power supplies at a sixth time, wherein the modification includes restoring at least one of the first subset of the set of internal power supplies to a first voltage level. In some instances, the voltage recovery component 825 may, based on receiving a second command, modify the corresponding voltage level for a third subset of the set of internal power supplies at a sixth time, wherein the modification includes restoring at least one of the third subset of the set of internal power supplies to a third voltage level.

[0112] In some instances, the voltage recovery component 825 may, based on receiving a second command, modify the corresponding voltage level for a second subset of the set of internal power supplies at a seventh time, wherein the modification includes restoring at least one of the second subset of the set of internal power supplies to a second voltage level. In some instances, the voltage recovery component 825 may, based on receiving a second command, modify the corresponding voltage level for a first subset of the set of internal power supplies at an eighth time, wherein the modification includes restoring at least one of the first subset of the set of internal power supplies to a first voltage level.

[0113] The external voltage sustaining component 830 may, based on receiving a second command, maintain a corresponding voltage level for a first subset of the set of internal power supplies at a fifth time. In some instances, the external voltage sustaining component 830 may, based on receiving a second command, maintain corresponding voltage levels for a second subset and a first subset of the set of internal power supplies at a sixth time. In some instances, the external voltage sustaining component 830 may, based on receiving a second command, maintain a corresponding voltage level for a first subset of the set of internal power supplies at a seventh time.

[0114] In some instances, the external voltage sustaining component 830 may activate a corresponding clamping circuit coupled to a corresponding comparator based on a comparison of the corresponding voltage level of a first subset of the set of internal power supplies with a corresponding first external power supply voltage level, in order to sustain the corresponding voltage level of the first subset of the set of internal power supplies at a corresponding threshold voltage level of the corresponding first external power supply voltage level.

[0115] Figure 9 Flowcharts illustrating various aspects of this disclosure show one or more methods 900 supporting power grouping for power-saving modes. Operation of method 900 may be implemented by a memory device or its components described herein. For example, operation of method 900 may be provided by reference to... Figure 8 The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0116] At 905, the memory device may, at a first moment, receive a command instructing the memory device to enter a sleep mode, wherein the memory device includes a set of internal power supplies associated with a set of corresponding voltage levels. Operation 905 may be performed according to the method described herein. In some instances, aspects of operation 905 may be referenced from... Figure 8 The described sleep command component is executed.

[0117] At 910, the memory device may, based on receiving the command, modify the corresponding voltage level for a first subset of the set of internal power supplies at a second time, wherein at least one of the first subset of the set of internal power supplies is associated with a first voltage level different from the external power supply voltage level. Operation 910 may be performed according to the method described herein. In some instances, aspects of operation 910 may be referenced from... Figure 8 The described voltage modification component is executed.

[0118] At 915, the memory device may, based on receiving the command, maintain a corresponding voltage level for a second subset of the set of internal power supplies at a second time, wherein at least one of the second subset of the set of internal power supplies is associated with a second voltage level different from the external power supply voltage level. Operation 915 may be performed according to the method described herein. In some instances, aspects of operation 915 may be referenced from... Figure 8 The described internal voltage maintenance component performs.

[0119] In some instances, the device described herein may perform one or more methods, such as method 900. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: at a first time, receiving, at a memory device, a command instructing the memory device to enter a sleep mode, wherein the memory device includes a set of internal power supplies associated with a set of corresponding voltage levels; based on receiving the command, at a second time, modifying the corresponding voltage levels for a first subset of the set of internal power supplies, wherein at least one of the first subset of the set of internal power supplies is associated with a first voltage level different from an external power supply voltage level; and based on receiving the command, at a second time, maintaining the corresponding voltage levels for a second subset of the set of internal power supplies, wherein at least one of the second subset of the set of internal power supplies is associated with a second voltage level different from an external power supply voltage level.

[0120] Some examples of the method 900 and device described herein may further include operations, features, components, or instructions for: at a third time, at the memory device, receiving a second command instructing the memory device to exit sleep mode; and based on receiving the second command, at a fourth time, modifying the corresponding voltage level for a first subset of the set of internal power supplies, wherein the modification includes restoring at least one of the first subset of the set of internal power supplies to a first voltage level.

[0121] Some examples of the method 900 and device described herein may further include operations, features, components, or instructions for modifying the corresponding voltage level for a second subset of the set of internal power supplies at a third time, based on receiving the command.

[0122] Some examples of the method 900 and device described herein may further include operations, features, components, or instructions for: at a fourth time, at a memory device, receiving a second command instructing the memory device to exit sleep mode; based on receiving the second command, at a fifth time, modifying a corresponding voltage level for a second subset of the set of internal power supplies, wherein the modification includes restoring at least one of the second subset of the set of internal power supplies to a second voltage level; based on receiving the second command, at a fifth time, maintaining a corresponding voltage level for a first subset of the set of internal power supplies; and based on receiving the second command, at a sixth time, modifying a corresponding voltage level for a first subset of the set of internal power supplies, wherein the modification includes restoring at least one of the first subset of the set of internal power supplies to a first voltage level.

[0123] Some examples of the method 900 and device described herein may further include operations, features, components, or instructions for maintaining a corresponding voltage level for a third subset of the set of internal power supplies at a second and a third time, based on receiving the command, wherein at least one of the third subset of the set of internal power supplies may be associated with a third voltage level different from the external power supply voltage level.

[0124] Some examples of the method 900 and device described herein may further include operations, features, components, or instructions for modifying the corresponding voltage levels for a third subset of the set of internal power supplies at a fourth time, based on receiving the command.

[0125] Some examples of the method 900 and device described herein may further include operations, features, components, or instructions for: at a fifth time, at a memory device, receiving a second command instructing the memory device to exit sleep mode; based on receiving the second command, at a sixth time, modifying a corresponding voltage level for a third subset of the set of internal power supplies, wherein the modification includes restoring at least one of the third subset of the set of internal power supplies to a third voltage level; based on receiving the second command, at a sixth time, maintaining corresponding voltage levels for a second subset and a first subset of the set of internal power supplies; based on receiving the second command, at a seventh time, modifying a corresponding voltage level for a second subset of the set of internal power supplies, wherein the modification includes restoring at least one of the second subset of the set of internal power supplies to a second voltage level; based on receiving the second command, at a seventh time, maintaining a corresponding voltage level for a first subset of the set of internal power supplies; and based on receiving the second command, at an eighth time, modifying a corresponding voltage level for a first subset of the set of internal power supplies, wherein the modification includes restoring at least one of the first subset of the set of internal power supplies to a first voltage level.

[0126] In some instances of the method 900 and device described herein, a first subset of the set of internal power supplies may be associated with a first threshold for forward voltage bias, a first voltage level threshold for power supply operation, or a combination thereof, and a second subset of the set of internal power supplies may be associated with a second threshold for forward voltage bias, a second voltage level threshold for power supply operation, or a combination thereof.

[0127] In some instances of the method 900 and device described herein, modifying the corresponding voltage level for a first subset of the set of internal power supplies may include operations, features, components, or instructions for: activating a corresponding discharge circuit to modify the corresponding voltage level of the first subset of the set of internal power supplies from a corresponding first operating voltage level to a corresponding threshold voltage level of a corresponding first external power supply voltage level.

[0128] In some instances of the method 900 and apparatus described herein, modifying the corresponding voltage level for a first subset of the set of internal power supplies may further include operations, features, components, or instructions for: comparing the corresponding voltage level of the first subset of the set of internal power supplies with a corresponding first external power supply voltage level via a corresponding comparator coupled to a corresponding discharge circuit; deactivating the corresponding discharge circuit based on the comparison of the corresponding voltage level of the first subset of the set of internal power supplies with the corresponding first external power supply voltage level; and activating a corresponding clamping circuit coupled to a corresponding comparator based on the comparison of the corresponding voltage level of the first subset of the set of internal power supplies with the corresponding first external power supply voltage level to maintain the corresponding voltage level of the first subset of the set of internal power supplies at a corresponding threshold voltage level of the corresponding first external power supply voltage level.

[0129] Some examples of the methods 900 and devices described herein may further include operations, features, components, or instructions for activating a corresponding clamping circuit that is at least partially based on a corresponding voltage level of a corresponding internal power supply in a first subset of the set of internal power supplies reaching a corresponding threshold voltage level of a corresponding first external power supply voltage level.

[0130] In some instances of the method 900 and device described herein, each corresponding first voltage level in a first subset of the set of internal power supplies may be higher than each corresponding first external power supply voltage level.

[0131] Figure 10 Flowcharts illustrating various aspects of this disclosure show one or more methods 1000 for supporting power grouping for power-saving modes. Operation of method 1000 may be implemented by a memory device or its components as described herein. For example, operation of method 1000 may be provided by reference to... Figure 8 The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0132] At point 1005, the memory device may, at a first moment, receive a command instructing the memory device to enter a sleep mode, wherein the memory device includes a set of internal power supplies associated with a set of corresponding voltage levels. Operation 1005 may be performed according to the method described herein. In some instances, aspects of operation 1005 may be derived from references... Figure 8 The described sleep command component is executed.

[0133] At point 1010, the memory device may, based on receiving the command, modify the corresponding voltage level for a first subset of the set of internal power supplies at a second time, wherein at least one of the first subset of the set of internal power supplies is associated with a first voltage level different from the external power supply voltage level. Operation 1010 may be performed according to the method described herein. In some instances, aspects of operation 1010 may be referenced from... Figure 8 The described voltage modification component is executed.

[0134] At 1015, the memory device may, based on receiving the command, maintain a corresponding voltage level for a second subset of the set of internal power supplies at a second time, wherein at least one of the second subset of the set of internal power supplies is associated with a second voltage level different from the external power supply voltage level. Operation 1015 may be performed according to the method described herein. In some instances, aspects of operation 1015 may be referenced from... Figure 8 The described internal voltage maintenance component performs.

[0135] At point 1020, the memory device may, at a third time, receive a second command instructing the memory device to exit sleep mode. The operation of point 1020 can be performed according to the method described herein. In some instances, aspects of the operation of point 1020 can be found in references... Figure 8 The described sleep command component is executed.

[0136] At 1025, the memory device may, based on receiving a second command, modify the corresponding voltage level for a first subset of the set of internal power supplies at a fourth time, wherein the modification includes restoring at least one of the first subset of the set of internal power supplies to a first voltage level. Operation 1025 may be performed according to the method described herein. In some instances, aspects of operation 1025 may be referenced from... Figure 8 The described voltage recovery component is executed.

[0137] It should be noted that the methods described herein are possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the method can be combined.

[0138] Describe a device. The device may include a set of internal power supplies associated with a set of corresponding voltage levels, the set of internal power supplies comprising: a first subset of internal power supplies including a first internal power supply associated with a first voltage level different from an external power supply voltage level; and a second subset of internal power supplies including a second internal power supply associated with a second voltage level different from the external power supply voltage level. The device may further include a controller configured to: at a first time, receive a command instructing the device to enter a sleep mode; based on receiving the command, at a second time, modify the corresponding voltage level for the first subset of the set of internal power supplies; and based on receiving the command, at the second time, maintain the corresponding voltage level for the second subset of the set of internal power supplies.

[0139] Some instances of the controller may be further configured to: at a third time, at the device, receive a second command instructing the device to exit sleep mode; and based on receiving the second command, at a fourth time, modify the corresponding voltage level for a first subset of the set of internal power supplies, wherein the modification includes restoring the first internal power supply to a first voltage level.

[0140] Some instances of the controller can be further configured to modify the corresponding voltage level for a second subset of the set of internal power supplies at a third time, based on the received command.

[0141] Some instances of the controller may be further configured to, at a fourth time, at the device, receive a second command instructing the device to exit sleep mode; and, based on receiving the second command, at a fifth time, modify the corresponding voltage level for a second subset of the set of internal power supplies, wherein the modification includes restoring the second internal power supply to a second voltage level. The controller may be further configured to, based on receiving the second command, at a fifth time, maintain the corresponding voltage level for a first subset of the set of internal power supplies; and, based on receiving the second command, at a sixth time, modify the corresponding voltage level for the first subset of the set of internal power supplies, wherein the modification includes restoring the first internal power supply to a first voltage level.

[0142] In some instances, a first subset of the set of internal power supplies may be associated with a first threshold for forward voltage bias, a first voltage level threshold for power supply operation, or a combination thereof, and a second subset of the set of internal power supplies may be associated with a second threshold for forward voltage bias, a second voltage level threshold for power supply operation, or a combination thereof.

[0143] In some instances, the device may further include a set of bleed circuits, comprising a first subset of bleed circuits configured to modify a corresponding voltage level of a first subset of the set of internal power supplies from a corresponding first operating voltage level to a corresponding first external power supply voltage level, and a second subset of bleed circuits configured to modify a corresponding voltage level of a second subset of the set of internal power supplies from a corresponding second operating voltage level to a corresponding second external power supply voltage level, and a corresponding second threshold voltage level. The device may further include a set of comparator circuits, comprising: a first subset of comparator circuits coupled to a corresponding bleed circuit in the first subset of bleed circuits and configured to compare a corresponding voltage level of the first subset of the set of internal power supplies with a corresponding first external power supply voltage level; and a second subset of comparator circuits coupled to a corresponding bleed circuit in the second subset of bleed circuits and configured to compare a corresponding voltage level of the second subset of the set of internal power supplies with a corresponding second external power supply voltage level.

[0144] In some instances, each corresponding first operating voltage level in a first subset of the set of internal power supplies may be higher than each corresponding first external power supply voltage level, and each corresponding second operating voltage level in a second subset of the set of internal power supplies may be higher than each corresponding second external power supply voltage level.

[0145] In some instances, the device may further include a set of clamping circuits, comprising: a first subset of clamping circuits coupled to and configured to maintain a corresponding voltage level of a first subset of the set of internal power supplies at a corresponding first threshold voltage level of a corresponding first external power supply voltage level based on the corresponding comparator circuits in the first subset; and a second subset of clamping circuits coupled to and configured to maintain a corresponding voltage level of a second subset of the set of internal power supplies at a corresponding second threshold voltage level of a corresponding second external power supply voltage level based on the corresponding comparator circuits in the second subset.

[0146] Some instances of the controller may be further configured to activate a corresponding clamping circuit in a first clamping circuit subset based at least in part on a corresponding voltage level of a corresponding internal power supply in a first subset of the set of internal power supplies reaching a corresponding voltage level threshold.

[0147] Describe an apparatus. The apparatus may include: a first internal power supply associated with a first voltage level different from an external power supply voltage level; a second internal power supply associated with a second voltage level different from both the first voltage level and the external power supply voltage level; a set of discharge circuits including a first discharge circuit configured to modify the first voltage level of the first internal power supply to the first external power supply voltage level and a second discharge circuit configured to modify the second voltage level of the second internal power supply to the second external power supply voltage level; and a set of clamping circuits including a first clamping circuit configured to maintain the first internal power supply at the first external power supply voltage level and a second clamping circuit configured to maintain the second internal power supply at the second external power supply voltage level.

[0148] Some examples of the device may include: a third internal power supply associated with a third voltage level different from the first voltage level, the second voltage level, and the external power supply voltage level; a third discharge circuit in the set of discharge circuits configured to modify the third voltage level of the third internal power supply to the third external power supply voltage level; and a third clamping circuit in the set of clamping circuits configured to maintain the third internal power supply at the third external power supply voltage level.

[0149] In some instances, the first discharge circuit may include: one or more switching components configured to selectively couple a first internal power supply to a first external power supply having a first external power supply voltage level; and one or more resistors that can be selectively coupled to the first internal power supply or the first external power supply via the one or more switching components.

[0150] In some instances, each clamping circuit in the set of clamping circuits may be coupled to a corresponding comparator circuit configured to compare a corresponding voltage level of a corresponding internal power supply with a corresponding external power supply voltage level.

[0151] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may show signals as single signals; however, those skilled in the art will understand that the signals may represent signal buses, where the buses may have various bit widths.

[0152] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that supports the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0153] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. When, for example, one component of a controller couples other components together, that component triggers a change that allows signals to flow through conductive paths between those other components, paths that were previously not permitted to allow signal flow.

[0154] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, they are isolated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components from each other, the controller achieves the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0155] The devices containing memory arrays discussed herein can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals containing (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0156] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. Terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., most carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0157] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "advantageous" over other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0158] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a long dash following the reference numeral and a second numeral to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0159] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0160] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components or any combination thereof. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0161] The functionality described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functionality can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality can also be physically located in various locations, including distributed implementations such that different parts of the functionality are implemented in different physical locations. And, as used herein (included in the claims), the word "or" used in a list of items (e.g., a list of items ending with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). And, as used herein, the phrase "based on" should not be construed as referring to a set of closing conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0162] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. For example, and without limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above are also included within the scope of computer-readable media.

[0163] The description provided herein enables those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, the invention is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: At the first moment, at the memory device, a command is received instructing the memory device to enter a sleep mode, wherein the memory device includes a set of internal power supplies associated with a plurality of corresponding voltage levels; At least in part based on receiving the command, at a second time, the corresponding voltage level is modified for a first subset of the set of internal power supplies, wherein at least one of the first subset of the set of internal power supplies is associated with a first voltage level that is different from the voltage level of the external power supply. Based at least in part on receiving the command, at the second time, a corresponding voltage level is maintained constant for a second subset of the set of internal power supplies, wherein at least one of the second subset of the set of internal power supplies is associated with a second voltage level different from the voltage level of the external power supply. as well as At least in part based on receiving the command, at a third time, the corresponding voltage level is modified for the second subset of the set of internal power supplies.

2. The method according to claim 1, further comprising: At the memory device, a second command instructing the memory device to exit the sleep mode is received; as well as At least in part based on receiving the second command, at a fourth time, the corresponding voltage level is modified for the first subset of the set of internal power supplies, wherein the modification includes restoring at least one of the first subset of the set of internal power supplies to the first voltage level.

3. The method according to claim 1, further comprising: At the fourth time, at the memory device, a second command instructing the memory device to exit the sleep mode is received; Based at least in part on receiving the second command, at a fifth time, the corresponding voltage level is modified for the second subset of the set of internal power supplies, wherein the modification includes restoring at least one of the second subset of the set of internal power supplies to the second voltage level; Based at least in part on receiving the second command, at the fifth time, the corresponding voltage level is maintained for the first subset of the set of internal power supplies; as well as At least in part based on receiving the second command, at a sixth time, the corresponding voltage level is modified for the first subset of the set of internal power supplies, wherein the modification includes restoring at least one of the first subset of the set of internal power supplies to the first voltage level.

4. The method of claim 1, further comprising: Based at least in part on receiving the command, at the second and third times, a corresponding voltage level is maintained for a third subset of the set of internal power supplies, wherein at least one of the third subset of the set of internal power supplies is associated with a third voltage level different from the voltage level of the external power supply.

5. The method of claim 4, further comprising: At least in part based on receiving the command, at a fourth time, the corresponding voltage level is modified for the third subset of the set of internal power supplies.

6. The method of claim 5, further comprising: At the fifth time, at the memory device, a second command instructing the memory device to exit the sleep mode is received; At least in part based on receiving the second command, at a sixth time, the corresponding voltage level is modified for the third subset of the set of internal power supplies, wherein the modification includes restoring at least one of the third subset of the set of internal power supplies to the third voltage level; At least in part based on receiving the second command, at the sixth time, the corresponding voltage levels are maintained for the second subset and the first subset of the set of internal power supplies; Based at least in part on receiving the second command, at a seventh time, the corresponding voltage level is modified for the second subset of the set of internal power supplies, wherein the modification includes restoring at least one of the second subset of the set of internal power supplies to the second voltage level; Based at least in part on receiving the second command, at the seventh time, the corresponding voltage level is maintained for the first subset of the set of internal power supplies; as well as At least in part based on receiving the second command, at an eighth time, the corresponding voltage level is modified for the first subset of the set of internal power supplies, wherein the modification includes restoring at least one of the first subset of the set of internal power supplies to the first voltage level.

7. The method according to claim 1, wherein: The first subset of the set of internal power supplies is associated with a first threshold for positive voltage bias, a first voltage level threshold for power supply operation, or a combination thereof; and The second subset of the set of internal power supplies is associated with a second threshold for positive voltage bias, a second voltage level threshold for power supply operation, or a combination thereof.

8. The method of claim 1, wherein modifying the corresponding voltage level for the first subset of the set of internal power supplies comprises: Activate the corresponding discharge circuit to modify the corresponding voltage level of the first subset of the set of internal power supplies from the corresponding first operating voltage level to the corresponding threshold voltage level of the corresponding first external power supply voltage level.

9. The method of claim 8, wherein modifying the corresponding voltage level for the first subset of the set of internal power supplies further comprises: The voltage level of the first subset of the set of internal power supplies is compared with the voltage level of the corresponding first external power supply via a corresponding comparator coupled to the corresponding discharge circuit. The activation of the corresponding bleed circuit is deactivated based at least in part on a comparison of the corresponding voltage level of the first subset of the set of internal power supplies with the corresponding first external power supply voltage level. as well as At least in part, based on comparing the corresponding voltage level of the first subset of the set of internal power supplies with the corresponding first external power supply voltage level, a corresponding clamping circuit coupled to the corresponding comparator is activated to maintain the corresponding voltage level of the first subset of the set of internal power supplies at the corresponding threshold voltage level of the corresponding first external power supply voltage level.

10. The method according to claim 9, wherein: Activating the corresponding clamping circuit is based at least in part on the corresponding voltage level of the corresponding internal power supply in the first subset of the set of internal power supplies reaching a corresponding threshold voltage level of the corresponding first external power supply voltage level.

11. The method of claim 8, wherein each corresponding first voltage level in the first subset of the set of internal power supplies is higher than each corresponding first external power supply voltage level.

12. An apparatus comprising: A set of internal power supplies associated with multiple corresponding voltage levels, the set of internal power supplies including: A first subset of the set of internal power supplies includes a first internal power supply associated with a first voltage level different from the external power supply voltage level; and A second subset of the set of internal power supplies includes a second internal power supply associated with a second voltage level different from the external power supply voltage level; and The controller is configured as follows: Upon receiving a command instructing the device to enter sleep mode; At least in part based on receiving the command, at a second time, the corresponding voltage level is modified for the first subset of the set of internal power supplies; At least in part based on receiving the command, at the second time, the second subset of the set of internal power supplies maintains a corresponding voltage level unchanged; and At least in part based on receiving the command, at a third time, the corresponding voltage level is modified for the second subset of the set of internal power supplies.

13. The device of claim 12, wherein the controller is further configured to: At the device, a second command is received instructing the device to exit the sleep mode; and At least in part based on receiving the second command, at a fourth time, the corresponding voltage level is modified for the first subset of the set of internal power supplies, wherein the modification includes restoring the first internal power supply to the first voltage level.

14. The device of claim 12, wherein the controller is further configured to: At the fourth time, the device receives a second command instructing the device to exit the sleep mode; Based at least in part on receiving the second command, at a fifth time, the corresponding voltage level is modified for the second subset of the set of internal power supplies, wherein the modification includes restoring the second internal power supply to the second voltage level; Based at least in part on receiving the second command, at the fifth time, the corresponding voltage level is maintained for the first subset of the set of internal power supplies; as well as At least in part based on receiving the second command, at a sixth time, the corresponding voltage level is modified for the first subset of the set of internal power supplies, wherein the modification includes restoring the first internal power supply to the first voltage level.

15. The device according to claim 12, wherein: The first subset of the set of internal power supplies is associated with a first threshold for positive voltage bias, a first voltage level threshold for power supply operation, or a combination thereof; and The second subset of the set of internal power supplies is associated with a second threshold for positive voltage bias, a second voltage level threshold for power supply operation, or a combination thereof.

16. The apparatus of claim 12, wherein the apparatus further comprises: A set of bleedering circuits, comprising: A first subset of bleed circuits is configured to modify the corresponding voltage level of the first subset of the set of internal power supplies from a corresponding first operating voltage level to a corresponding first threshold voltage level of a corresponding first external power supply voltage level; and A second subset of bleeder circuits is configured to modify the corresponding voltage level of the second subset of the set of internal power supplies from the corresponding second operating voltage level to the corresponding second threshold voltage level of the corresponding second external power supply voltage level; and A set of comparator circuits, comprising: A first subset of comparator circuits, coupled to a corresponding bleeder circuit in the first subset of bleeder circuits, and configured to compare the corresponding voltage level of the first subset of the set of internal power supplies with the corresponding voltage level of the first external power supply; and A second comparator circuit subset coupled to a corresponding bleed circuit in the second bleed circuit subset and configured to compare the corresponding voltage level of the second subset of the set of internal power supplies with the corresponding second external power supply voltage level.

17. The apparatus according to claim 16, wherein: Each corresponding first operating voltage level in the first subset of the set of internal power supplies is higher than the voltage level of each corresponding first external power supply; and Each corresponding second operating voltage level in the second subset of the set of internal power supplies is higher than each corresponding second external power supply voltage level.

18. The device of claim 16, wherein the device further comprises a set of clamping circuitry, comprising: A first clamping circuit subset, coupled to a corresponding comparator circuit in the first comparator circuit subset and configured to maintain the corresponding voltage level of the first subset of the set of internal power supplies at the corresponding first threshold voltage level of the corresponding first external power supply voltage level, based at least in part on the corresponding comparator circuit in the first subset. as well as A second clamping circuit subset, coupled to a corresponding comparator circuit in the second comparator circuit subset and configured to maintain, at least in part, the corresponding voltage level of the second subset of the set of internal power supplies at the corresponding second threshold voltage level of the corresponding second external power supply voltage level, based on the corresponding comparator circuit in the second subset.

19. The device of claim 18, wherein the controller is further configured to: At least in part, based on the corresponding voltage level of the corresponding internal power supply in the first subset of the set of internal power supplies reaching the corresponding voltage level threshold, the corresponding clamping circuit in the first clamping circuit subset is activated.

20. An apparatus comprising: A first internal power supply, which is associated with a first voltage level that is different from the external power supply voltage level; A second internal power supply, which is associated with a second voltage level that is different from the first voltage level and different from the external power supply voltage level; A set of discharge circuits, comprising: A first discharge circuit is configured to modify the first voltage level of the first internal power supply to the first external power supply voltage level at a first instant; and The second discharge circuit is configured to modify the second voltage level of the second internal power supply to the second external power supply voltage level at a second time; and A set of clamping circuits, comprising: A first clamping circuit is configured to maintain the first internal power supply at the voltage level of the first external power supply; and The second clamping circuit is configured to maintain the second internal power supply at the voltage level of the second external power supply.

21. The device according to claim 20, further comprising: A third internal power supply, which is associated with a third voltage level that is different from the first voltage level, the second voltage level and the external power supply voltage level; The third discharge circuit in the set of discharge circuits is configured to modify the third voltage level of the third internal power supply to the voltage level of the third external power supply. as well as The third clamping circuit in the set of clamping circuits is configured to maintain the third internal power supply at the voltage level of the third external power supply.

22. The device of claim 20, wherein the first discharge circuit comprises: One or more switching components configured to selectively couple the first internal power supply to a first external power supply having the voltage level of the first external power supply; as well as One or more resistors that can be selectively coupled to the first internal power supply or the first external power supply via the one or more switching components.

23. The device of claim 20, wherein each clamping circuit in the set of clamping circuits is coupled to a corresponding comparator circuit, the corresponding comparator being configured to compare a corresponding voltage level of a corresponding internal power supply with a corresponding external power supply voltage level.

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