Semiconductor devices and manufacturing methods thereof

Abstract

The semiconductor device (100) includes: a semiconductor substrate (10) having a main surface (10a); a p-conductivity base region (30) formed on the main surface side of the semiconductor substrate; an n-conductivity emitter region (31) formed on the surface of the base region; an n-conductivity collector region (32) formed separately from the emitter region in the surface of the main surface side; and an STI separation portion (40) formed on the main surface. The second separation portion (402) of the STI separation portion has a thermal oxide film (402b) for contacting the bonding interface between the base region and the emitter region.

Description

[0001] Cross-referencing of related applications

[0002] This application is based on Japanese Patent Application No. 2020-103997, filed on June 16, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The disclosure in this specification relates to semiconductor devices and methods of manufacturing the same. Background Technology

[0004] Patent Document 1 discloses a semiconductor device incorporating a bipolar transistor. The contents of prior art documents are referenced hereto as explanations of the technical elements in this specification.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2010-114292 Summary of the Invention

[0008] In the semiconductor device of Patent Document 1, a self-aligned silicide layer is provided on the contact area between the emitter region and the base region. A self-aligned silicide protective layer is formed around the self-aligned silicide layer on the base region to prevent the formation of the self-aligned silicide layer. The interface between the base region and the emitter region is in contact with the self-aligned silicide protective layer. With this structure, there is a problem of low current amplification. From the above perspective, or from other perspectives not mentioned, further improvements are required for the semiconductor device.

[0009] The present invention was made in view of the following problems, and aims to provide a semiconductor device with high current amplification and a method for manufacturing the same.

[0010] The semiconductor device disclosed herein includes: a semiconductor substrate having a main surface; a base region of a first conductivity type formed on the main surface side of the semiconductor substrate; an emitter region of a second conductivity type opposite to the first conductivity type formed on the surface layer of the base region; a collector region of the second conductivity type formed separately from the emitter region in the surface layer on the main surface side; and an element separation insulating film formed on the main surface, having a thermal oxide film for contacting the junction interface between the base region and the emitter region.

[0011] According to the disclosed semiconductor device, a device separation insulating film is provided on the main surface of the semiconductor substrate. The junction interface between the base region and the emitter region is in contact with the thermal oxide film of the device separation insulating film. This suppresses the trapping of collector current by crystal defects. As a result, a semiconductor device with high current amplification can be provided.

[0012] The method for manufacturing a semiconductor device disclosed herein involves forming a device separation insulating film having a thermal oxide film on the main surface of a semiconductor substrate; in order to form a base region and an emitter region, using a common photomask, ion implanting an impurity of a first conductivity type onto the portion exposed from the opening of the device separation insulating film, followed by ion implanting an impurity of a second conductivity type opposite to the first conductivity type; and diffusing the impurities through heat treatment to form the base region and the emitter region in such a way that the junction interface between the base region and the emitter region is in contact with the thermal oxide film.

[0013] According to the disclosed manufacturing method, the interface between the base region and the emitter region is in contact with a thermally oxidized film of the device separation insulating film. This enables the formation of a semiconductor device with high current amplification. Furthermore, ion implantation is performed using a shared photomask to form impurities in the base and emitter regions. This allows for the provision of a semiconductor device with high current conversion efficiency at low cost.

[0014] The various embodiments disclosed in this specification employ different technical means to achieve their respective purposes. The reference numerals in parentheses within the claims and their items illustratively indicate the correspondence with portions of the embodiments described later, and are not intended to limit the scope of the technology. The purposes, features, and effects disclosed in this specification will become clearer with reference to the following detailed description and accompanying drawings. Attached Figure Description

[0015] Figure 1 This is a plan view showing the schematic structure of the semiconductor device according to the first embodiment.

[0016] Figure 2 It is along Figure 1 A sectional view along line II-II.

[0017] Figure 3 This is a cross-sectional view showing the periphery of the STI separation section.

[0018] Figure 4 It is a cross-sectional view showing the manufacturing process of a semiconductor device.

[0019] Figure 5 It is a cross-sectional view showing the manufacturing process of a semiconductor device.

[0020] Figure 6 It is a cross-sectional view showing the manufacturing process of a semiconductor device.

[0021] Figure 7 It is a cross-sectional view showing the manufacturing process of a semiconductor device.

[0022] Figure 8 It is a cross-sectional view showing the manufacturing process of a semiconductor device.

[0023] Figure 9 This is a graph showing the relationship between collector current Ic and current amplification hFE.

[0024] Figure 10 This is a sectional view representing a variation.

[0025] Figure 11 This is a cross-sectional view showing the semiconductor device of the second embodiment.

[0026] Figure 12 It is a floor plan showing the configuration of the wiring section. Detailed Implementation

[0027] Several embodiments are described below based on the accompanying drawings. In several embodiments, functionally and / or structurally corresponding and / or associated parts are sometimes given the same reference numerals. For details regarding corresponding and / or associated parts, please refer to the descriptions of other embodiments.

[0028] (First Embodiment)

[0029] In this embodiment, a semiconductor device having an npn-type bipolar transistor will be described. The p-type corresponds to the first conductivity type, and the n-type corresponds to the second conductivity type.

[0030] Semiconductor Devices

[0031] based on Figure 1 , Figure 2 and Figure 3 A general description of the structure of a semiconductor device is provided. Figure 1 It is a plan view of a semiconductor device. Figure 1 This shows the positional relationship between the base region, emitter region, collector region, and STI separation section. Figure 1 In this context, some elements of a semiconductor device, such as the silicide layer, are omitted for convenience. Figure 1 In the image, the STI separation section is shaded for clarity. Figure 2 It is along Figure 1 A sectional view along line II-II. Figure 3 This is a cross-sectional view showing the periphery of the STI separation section (second separation section). Figure 3 The base and emitter regions are simplified and illustrated in the diagram. Furthermore, the silicide layer or silicide barrier layer is also omitted from the illustration.

[0032] Hereinafter, the thickness direction of the semiconductor substrate is defined as the Z direction. The direction orthogonal to the Z direction and the arrangement direction of the emitter and collector regions is defined as the Y direction. The direction orthogonal to both the Z and Y directions is defined as the X direction. Unless otherwise specified, the shape observed from the Z-direction plane, in other words, the shape along the XY plane defined by the X and Y directions, is defined as a planar shape. There are cases where a planar observation from the Z direction is simply represented as a planar observation.

[0033] like Figure 1 and Figure 2 As shown, the semiconductor device 100 includes a semiconductor substrate 10, a trench separation section 20, a base region 30, an emitter region 31, a collector region 32, and an STI separation section 40.

[0034] The semiconductor substrate 10 includes a support substrate 11, a buried insulating film 12, and an active layer 13. The support substrate 11 is made of an n-type silicon substrate or the like. The buried insulating film 12 is made of a silicon oxide film or the like and is disposed on one side of the support substrate 11. The buried insulating film 12 has a thickness of, for example, a few μm to ensure insulation between the support substrate 11 and the active layer 13. The active layer 13 is stacked on the support substrate 11 with respect to the buried insulating film 12. In this embodiment, the active layer 13 is an n-type semiconductor layer formed by ion implantation of n-type impurities into a p-type semiconductor layer.

[0035] Thus, in this embodiment, an SOI substrate is used as the semiconductor substrate 10. SOI is short for Silicon On Insulator. The semiconductor substrate 10 has a main surface 10a, which includes the surface of the active layer 13.

[0036] The trench separation section 20 divides the active layer 13 into the element region 14 and the region outside the element region 14. The trench separation section 20 separates the active layer 13 into elements. The region outside the element region 14 is, for example, a field ground region.

[0037] The trench separation section 20 is formed by embedding an insulating film in a trench (groove) formed in a manner that extends from the surface of the main surface 10a, i.e., the active layer 13, to embed the insulating film 12. The insulating film is disposed in the groove by embedding insulating material through thermal oxidation and / or deposition.

[0038] The base region 30, emitter region 31, and collector region 32 are diffusion regions of impurities constituting a bipolar transistor. These diffusion regions are formed in the aforementioned element region 14. The element region 14 constituting the bipolar transistor is as follows: Figure 1 As shown, the planar shape is roughly rectangular with the Y direction as the longer direction and the X direction as the shorter direction.

[0039] A p-type base region is formed in the center of the element region 14. The base region 30 is formed in the active layer 13 on the surface of the main surface 10a. The base region 30 has a first region 301 and a second region 302. The first region 301 is formed by ion implantation from the opening 40b (described later). The second region 302 is formed by ion implantation from the opening 40a. The first region 301 is located directly below the emitter region 31. The first region 301 includes the emitter region 31. The second region 302 is a region that surrounds the first region 301. The second region 302 extends from the first region 301 towards the collector region 32 in the Y direction. Since the second region 302 is a region where the base region 30 is led out towards the side close to the collector region 32, it is also sometimes referred to as a base lead-out region.

[0040] The base region 30 has a p+ type contact region 30c, which is formed to expose from the main surface 10a and has a higher impurity concentration than other parts of the base region 30. In this embodiment, the contact region 30c is formed on the surface of the second region 302. The contact region 30c is formed at a position that overlaps with the opening 40a in planar view.

[0041] An n-type emitter region 31 is formed in the surface layer of the base region 30 at a position separate from the contact region 30c. The emitter region 31 terminates within the base region 30. The emitter region 31 has an n+ type contact region 31c, which is formed to be exposed from the main surface 10a and has a higher impurity concentration than other parts of the emitter region 31.

[0042] In this embodiment, the emitter region 31 is formed in the central portion of the element region 14. The base region 30 is formed such that the emitter region 31 is included in the plan view. The contact region 31c is formed at a position that overlaps with the opening 40b in the plan view.

[0043] The impurity concentration of the n-type collector region 32 is higher than that of the active layer 13. The collector region 32 is formed in the surface layer of the main surface 10a at a position separate from the emitter region 31. In this embodiment, the collector regions 32 are formed near both ends in the Y direction in a generally rectangular element region 14. The two collector regions 32 are arranged such that the emitter region 31 and the base region 30 are sandwiched in the Y direction. The arrangement direction of the base region 30 or the emitter region 31 and the collector region 32 is generally parallel to the Y direction.

[0044] The collector region 32 has an n+ type contact region 32c, which is formed to expose from the main surface 10a and has a higher impurity concentration than other parts of the collector region 32. Each collector region 32 has a contact region 32c. In this embodiment, the contact region 32c is formed at a position overlapping with the opening 40c in a plan view. The collector region 32 is formed to a depth greater than that of the base region 30.

[0045] STI separation section 40 is formed in element region 14 on the surface of active layer 13. STI is short for Shallow Trench Isolation. Figure 3 As shown, the STI separation section 40 is formed by creating a groove 402a of a specified depth in the surface layer of the active layer 13 from the main surface 10a side, filling the groove 402a with an insulating film, and then planarizing it using CMP or similar methods. CMP is short for Chemical Mechanical Polishing.

[0046] Specifically, a thermal oxide film 402b is formed on the surface of the active layer 13 within the trench 402a. Furthermore, a CVD oxide film 402c is formed on the thermal oxide film 402b. The inner wall of the trench 402a is covered by the thermal oxide film 402b, and the other areas within the trench 402a are filled with the CVD oxide film 402c. Thus, the STI separation section 40 is formed by the thermal oxide film 402b and the CVD oxide film 402c. Figure 3 In the diagram, the structure of the second separation section 402 is shown as the STI separation section 40, but the first separation section 401 also has the same structure. Additionally, the STI separation section 40 may also have a silicon nitride film between the thermal oxide film 402b and the CVD oxide film 402c.

[0047] The STI separation section 40 has an opening for exposing the connection area. In this embodiment, the STI separation section 40 has openings 40a, 40b, and 40c. The STI separation section 40 is provided in the component region 14 in the portion excluding openings 40a to 40c.

[0048] An opening 40a is formed to expose the contact region 30c of the base region 30. The opening 40a is frame-shaped. An opening 40b is formed to expose the contact region 31c of the emitter region 31. The opening 40b is surrounded by the frame-shaped opening 40a. An opening 40c is formed to expose the contact region 32c of the collector region 32. The STI separation section 40 has two openings 40c.

[0049] The STI separation section 40 is divided into a first separation section 401 and a second separation section 402 by a frame-shaped opening 40a. An opening 40c is formed in the first separation section 401, and an opening 40b is formed in the second separation section 402. The second separation section 402 is annular through the openings 40a and 40b. In plan view, the first separation section 401 overlaps with a portion of the collector region 32 and a portion of the base region 30. In plan view, the second separation section 402 overlaps with a portion of the emitter region 31 and a portion of the base region 30. The second separation section 402 of the STI separation section 40 corresponds to the element separation insulating film.

[0050] The semiconductor device 100 of this embodiment further includes a silicide layer 50 and a silicide barrier layer 51. The silicide layer 50 reduces the contact resistance between the silicide layer 50 and a wiring portion (not shown) disposed on the main surface 10a. The silicide barrier layer 51 is formed to prevent the formation of the silicide layer 50, i.e., to prevent silicide formation. The silicide barrier layer 51 is, for example, made of a CVD oxide film. The silicide layer 50 is formed at the opening of the silicide barrier layer 51.

[0051] A silicide layer 50 is formed on the contact regions 30c, 31c, and 32c of the base region 30, emitter region 31, and collector region 32, respectively. The silicide layer 50 is, for example, composed of cobalt silicide (CoSi). The silicide layer 50 is sometimes referred to as a self-aligned silicide layer. The silicide barrier layer 51 is sometimes referred to as a self-aligned silicide barrier layer, a self-aligned silicide protective layer, etc.

[0052] Although not shown in the figure, the semiconductor device 100 also includes wiring portions and an insulating film disposed on the main surface 100a. The wiring portions are electrically connected to the corresponding diffusion regions via the silicide layer 50.

[0053] Thus, in this embodiment, an npn-type bipolar transistor is formed in the element region 14 of the semiconductor substrate 10. The structure formed in the element region 14 has approximately quadratic symmetry about an axis that passes through the center of the element region 14 and is parallel to the Z-axis.

[0054] <Relationship between the base region, emitter region, and STI separation section>

[0055] Next, regarding the aforementioned semiconductor device 100, the relationship between the base region 30 and the emitter region 31 and the STI separation section 40 will be explained.

[0056] As described above, in this embodiment, the STI separation section 40 (second separation section 402) is provided in the two regions 30 and 31 in a manner that spans the boundary between the base region 30 and the emitter region 31 in the main surface 10a.

[0057] like Figure 1As shown, the base region 30 is arranged in a plan view to overlap with the openings 40a, 40b, the entire area of ​​the second separation portion 402, and a portion of the first separation portion 401. Figure 2 As shown, the second region 302 of the base region 30 is in contact with the bottom surface of the first separation portion 401 and the bottom surface of the second separation portion 402.

[0058] In a plan view, the emitter region 31 is arranged to overlap with the opening 40b and a portion of the second separation portion 402. The emitter region 31 extends to a position where it contacts the bottom surface of the second separation portion 402.

[0059] That is, such as Figure 3 As shown, the interface between the base region 30 and the emitter region 31 is in contact with the bottom surface of the second separation section 402 of the STI separation section 40. The end of the interface on the main surface 10a side is in contact with the thermal oxide film 402b of the second separation section 402.

[0060] <Methods for Manufacturing Semiconductor Devices>

[0061] Next, based on Figures 3-8 The manufacturing method of the semiconductor device 100 described above will be explained. Figures 4-8 Corresponding to Figure 2 .

[0062] First, the semiconductor substrate 10 described above is prepared. Next, an STI separation portion 40 is formed on the surface layer of the active layer 13 on the main surface 10a side. (As...) Figure 3 As shown, after the trench 402a is formed, an STI separation section 40 is formed by forming a thermal oxide film 402b and a CVD oxide film 402c and filling the trench 402a.

[0063] Next, in order to form the collector region 32, such as Figure 4 As shown, on the surface layer of the active layer 13, on the main surface 10a side, n-type impurities such as phosphorus (P) are ion implanted. At this time, ion implantation is performed on the portion exposed from the opening 40c of the STI separation section 40.

[0064] Next, in order to form the base region 30 and the emitter region 31, such as Figure 5 As shown, on the surface layer of the active layer 13, the main surface 10a side is ion-implanted with p-type impurities such as boron (B), followed by ion-implanted with n-type impurities such as arsenic (As). At this time, ion implantation is performed on the portion exposed from the opening 40b of the STI separation section 40. P-type impurities and n-type impurities are ion-implanted sequentially using a shared photomask.

[0065] Next, through heat treatment, such as Figure 6The impurities are diffused as shown. Through this heat treatment, the first region 301 of the base region 30, the emitter region 31, and the collector region 32 are formed.

[0066] Next, in order to form the second region 302 of the base region 30, as follows: Figure 7 As shown, p-type impurities such as boron are ion implanted onto the surface layer of the active layer 13 on the main surface 10a side. At this time, ion implantation is performed on the portion exposed from the opening 40a of the STI separation section 40.

[0067] Next, as Figure 8 As shown, for the portions of the surface layer on the main surface 10a side of the active layer 13 that are exposed from the openings 40a, 40b, and 40c of the STI separation section 40, corresponding impurities are ion-implanted. For the portion exposed from opening 40a, p-type impurities such as boron are ion-implanted. For the portion exposed from opening 40b, n-type impurities such as arsenic are ion-implanted. For the portion exposed from opening 40c, n-type impurities such as phosphorus are ion-implanted. Through this ion implantation, contact regions 30c, 31c, and 32c are formed.

[0068] Then, although not illustrated, a silicide layer 50 is formed. Furthermore, wiring portions and an insulating film are formed. Through the above, a semiconductor device 100 can be obtained. Alternatively, the order of ion implantation used to form the collector region 32 and the ion implantation used to form the base region 30 and the emitter region 31 can be replaced.

[0069] <Summary of Implementation Method 1>

[0070] In this embodiment, an STI separation section 40 (second separation section 402) is provided at the boundary between the base region 30 and the emitter region 31 on the main surface 10a of the semiconductor substrate 10. The STI separation section 40 has a thermal oxide film 402b on the surface of the trench 402a. By providing the thermal oxide film 402b, crystal defects generated in the semiconductor substrate 10 by ion implantation or the like are extracted into the oxide film.

[0071] Furthermore, the interface between the base region 30 and the emitter region 31 is in contact with the thermal oxide film 402b. This suppresses the capture of collector current by crystal defects. Consequently, a semiconductor device 100 with high current amplification can be provided. The current amplification hFE is a value obtained by dividing the collector current by the base current.

[0072] Figure 9 This is a graph showing the relationship between collector current Ic and current amplification hFE. Figure 9The result represents the average of 50 tests conducted at room temperature. The solid line represents the result of the structure of this embodiment, and the dashed line represents the result of the reference example. In the reference example, no STI separation section is provided, so that the interface between the base region and the emitter region is in contact with the CVD oxide film constituting the silicide barrier layer. Other than this, the structure is the same as that of this embodiment.

[0073] according to Figure 9 The experimental results clearly demonstrate that the structure of this embodiment can improve the current amplification rate hFE. In particular, it is clearly shown that in the low current domain of the collector current Ic, the base current can be reduced, thereby increasing the current amplification rate hFE.

[0074] Furthermore, the above-described structure can be formed through the following three steps. In the first step, an STI separation section 40 (second separation section 402) having a thermal oxide film 402b is formed on the main surface 10a of the semiconductor substrate 10. In the second step, in order to form the base region 30 (first region 301) and the emitter region 31, a p-type conductivity impurity is ion-implanted onto the portion exposed from the opening 40b of the STI separation section 40 using a shared photomask, followed by the ion-implantation of an n-type conductivity impurity. In the third step, the impurities are diffused by heat treatment, so that the junction interface between the base region 30 and the emitter region 31 is in contact with the thermal oxide film 402b, thereby forming the base region 30 (first region 301) and the emitter region 31. In this way, ion implantation of impurities for forming the base region 30 and the emitter region 31 is performed using a shared photomask. As a result, a semiconductor device 100 with a high current amplification ratio hFE can be formed at low cost.

[0075] The contact position between the interface between the base region 30 and the emitter region 31 and the thermal oxide film 402b is not particularly limited. In this embodiment, the interface between the base region 30 and the emitter region 31 is in contact with the bottom surface of the second separation portion 402. That is, the emitter region 31 extends to the lower region of the second separation portion 402. By making it so that it is in contact with the thermal oxide film 402b at the bottom surface, the hFE characteristics can be stabilized.

[0076] The base region 30 can be configured such that it at least includes the emitter region 31. For example, it can also be configured as follows: Figure 10 As shown in the modified example, a contact region 31c of the emitter region 31 is provided between the contact region 30c of the base region 30 and the contact region 32c of the collector region 32. In this structure, a first region 301 with a low impurity concentration is provided on the side closer to the collector region 32.

[0077] In this embodiment, a second region 302 with a high impurity concentration extends from the first region 301 toward the collector region 32. In the base region 30, the impurity concentration is low directly below the emitter region 31, and high at the end of the collector region 32. As a result, the path of the collector current Ic is stable, thereby stabilizing the hFE characteristics.

[0078] (Second Implementation)

[0079] This embodiment is a variation based on a prior embodiment, and the description of the prior embodiment can be referenced. In the prior embodiment, the arrangement of the wiring section was not specifically mentioned. Instead, the positions of the wiring section connected to the base region and the base region can be set to a predetermined relationship.

[0080] Figure 11 and Figure 12 This refers to the semiconductor device 100 of this embodiment. Figure 11 It is different from the prior implementation method. Figure 2 The corresponding sectional view. Figure 12 This is a plan view showing the semiconductor device 100. Figure 12 The diagram illustrates the positional relationship between the diffusion area and the wiring section. Figure 12 For simplicity, some elements constituting the semiconductor device 100, such as the STI separation section 40, silicide layer 50, silicide barrier layer 51, and insulating film 60, have been omitted. Figure 12 In the image, the wiring section was shaded for clarity.

[0081] Semiconductor device 100, except in the prior embodiment (see reference) Figure 2 In addition to the structure described herein, it also includes an insulating film 60 and wiring portions 70, 71, and 72 disposed on the insulating film 60. Wiring portions 70, 71, and 72 are formed of a metal such as aluminum. Wiring portion 70 is electrically connected to the base region 30 (contact region 30c). Wiring portion 71 is electrically connected to the emitter region 31 (contact region 31c). Wiring portion 72 is electrically connected to the collector region 32 (contact region 32c).

[0082] The wiring portion 70 connected to the base region 30 extends in the plan view to a position closer to the collector region 32 than the end portion 30e on the collector region 32 side of the base region 30.

[0083] In this embodiment, the wiring portions 70, 71, and 72 are configured as multiple layers relative to the insulating film 60 disposed on the main surface 10a. The insulating film 60 includes interlayer insulating films. The wiring portion 70 of the base region 30 surrounds the wiring portion 71 of the emitter region 31. The wiring portion 70 is ring-shaped in plan view. The wiring portion 72 of the collector region 32 is located directly above the collector region 32. In the Y direction, the wiring portion 70 is disposed between the wiring portions 71 and 72.

[0084] The wiring section 70 has a wiring 70a. The wiring 70a is the inner layer wiring closest to the main surface 10a among the multi-layer wiring constituting the wiring section 70. In a plan view, the inner peripheral end of the ring-shaped wiring section 70 is substantially consistent in the wiring of all layers including the wiring 70a. On the other hand, regarding the outer peripheral end of the wiring section 70, the wiring 70a extends further outward than the wiring of other layers, at least in the Y direction. Figure 12 The outer peripheral end of the wiring section 70 shown is the outer peripheral end of the wiring 70a.

[0085] In this embodiment, the wiring of all layers constituting the wiring section 70 extends in the Y direction closer to the collector region 32 than the end 30e of the base region 30. The wiring 70a extends outward along the entire circumference compared to the wiring of other layers.

[0086] <Summary of Implementation Method 2>

[0087] In this embodiment, as described above, the wiring portion 70 extends in plan view to a position closer to the collector region 32 than the end 30e of the base region 30. Specifically, in the wiring portion 70, one wiring 70a (the first wiring) extends towards the collector region 32 than the wirings of other layers (the second wiring). Compared to the wirings of other layers, wiring 70a extends further with respect to the end 30e. The wiring portion 70, particularly wiring 70a, connected to the base region 30, functions as a field plate. This mitigates electric field concentration, thereby improving the withstand voltage of the semiconductor device 100.

[0088] The structure of this embodiment can also be combined with the variations shown in the prior embodiments.

[0089] (Other implementation methods)

[0090] The disclosure in this specification and accompanying drawings is not limited to the illustrated embodiments. The disclosure includes the illustrated embodiments and variations based on them that would occur to those skilled in the art. For example, the disclosure is not limited to the combination of components and / or elements shown in the embodiments. The disclosure can be implemented in a wide variety of combinations. The disclosure may have additional portions that can be added to the embodiments. The disclosure includes forms after omitting components and / or elements of the embodiments. The disclosure includes substitutions or combinations of components and / or elements between one embodiment and other embodiments. The technical scope of the disclosure is not limited to the description of the embodiments. It should be understood that the disclosed technical scope is indicated by the claims, and also includes all modifications within the meaning and scope equivalent to the description of the claims.

[0091] The disclosure in this specification and accompanying drawings is not limited to the claims. The disclosure includes the technical concepts described in the claims, but also relates to more diverse and broader technical concepts than those described in the claims. Therefore, a wide variety of technical concepts can be extracted from the disclosure in this specification and accompanying drawings without being bound by the claims.

[0092] When referring to an element or layer as being "above," "connected," "joined," or "combined," there are cases where it is directly connected, joined, or combined with other elements or layers, and cases where there are intermediate elements or layers. Conversely, when referring to an element as being "directly above," "directly connected," "directly joined," or "directly combined" with other elements or layers, there are no intermediate elements or layers. Other terms used to describe relationships between elements should be interpreted in the same way (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.). As used in this specification, the term "and / or" includes any and all combinations of one or more of the listed items relating to the association.

[0093] The spatially relative terms "inner," "outer," "inside," "lower," "lower," "upper," and "higher," etc., are used herein to facilitate the description of the relationship between one element or feature as illustrated and other elements or features. These spatially relative terms can be intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figure. For example, if the device in the figure is inverted, the element described as "lower" or "directly below" other elements or features faces "upper" of those other elements or features. Therefore, the term "lower" can encompass both upward and downward orientations. The device may also face other directions (rotated 90 degrees or other orientations), and the spatially relative descriptors used in this specification will be explained accordingly.

[0094] This example illustrates that p-type corresponds to the first conductivity type and n-type corresponds to the second conductivity type, but it is not limited to this. n-type can also be designated as the first conductivity type and p-type as the second conductivity type. That is, it can also be applied to pnp type bipolar transistors.

[0095] The configuration of the base region 30, emitter region 31, and collector region 32 is not limited to the examples described above. For instance, it is also possible to configure the collector region 32 to be disposed on only one side in the Y direction. The contact region 30c of the base region 30 can be disposed between the emitter region 31 and the collector region 32.

[0096] The STI separation section 40 is shown as an example of separating the insulating film from the component with a thermally oxidized film, but it is not limited to this. For example, a LOCOS oxide film can also be used. LOCOS is an abbreviation for Local Oxidation of Silicon. For example, in fine processes such as 0.18 μm processes, the STI separation section 40 is preferred.

[0097] This illustrates an example where the base region 30 has a first region 301 and a second region 302, but it is not limited to this. It can also be made into a structure with only one region.

[0098] An example of an SOI substrate is shown as semiconductor substrate 10, but it is not limited to this. For example, a bulk substrate can also be used.

Claims

1. A semiconductor device, characterized in that, have: Semiconductor substrate, having a main surface; The base region of the first conductivity type is formed in the semiconductor substrate on the surface of the main surface. An emitter region of a second conductivity type, opposite to the first conductivity type, is formed on the surface of the base region. The collector region of the second conductivity type is formed separately from the emitter region in the surface layer of the main surface side; as well as The component separation insulating film is formed on the main surface, and has a thermally oxidized film for contacting the interface between the base region and the emitter region. The aforementioned base region has: Region 1 includes the aforementioned emitter region; and The second region extends from the first region toward the collector region and has a higher impurity concentration than the first region. Compared to the first region mentioned above, the second region, based on the main surface, is shallower. It also includes a wiring portion disposed on the main surface of the semiconductor substrate and electrically connected to the base region. When viewed in a plane from the thickness direction of the semiconductor substrate, the wiring portion extends to a position closer to the collector region than the end of the collector region in the base region.

2. The semiconductor device as claimed in claim 1, characterized in that, The interface between the base region and the emitter region is in contact with the bottom surface of the insulating film separating the components.

3. A method for manufacturing a semiconductor device, characterized in that, A device separation insulating film with a thermally oxidized film is formed on the main surface of a semiconductor substrate; In order to form the base region and the emitter region, a common photomask is used to ion implant impurities of the first conductivity type into the portion exposed from the opening of the insulating film separated from the above-mentioned element, and then impurities of the second conductivity type opposite to the first conductivity type are ion implanted. The impurities are diffused by heat treatment, so that the junction interface between the base region and the emitter region is connected to the thermal oxide film to form the base region and the emitter region.

Images