Power device, method for manufacturing power device, drive circuit, and integrated circuit board

Abstract

The application discloses a power device, a preparation method of the power device, a driving circuit and an integrated circuit board, and aims to solve the problem of the increased on-resistance of the power device caused by the oxidation of the top layer pad, and the on-resistance batch failure, so that the on-resistance of the power device returns to the normal value. The power device comprises a die, a first top layer pad, a first oxide layer, a first seed layer and a first conductive bump which are sequentially stacked on the die, and further comprises a second top layer pad, a second oxide layer, a second seed layer and a second conductive bump which are sequentially stacked on the die, and the first top layer pad is in communication with the second top layer pad through the die.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a power device, a method for fabricating the power device, a driving circuit, and an integrated circuit board. Background Technology

[0002] With the development of the power electronics industry, power devices, as core components, are gaining an increasingly larger market share. New packaging technologies such as embedded component packaging (ECP) and ribbon packaging (CLIP) are gradually being widely used in the power device packaging field due to their low parasitic inductance. In these types of packaging, the chip needs to undergo pad metallization to facilitate subsequent package layout and routing.

[0003] like Figure 1 As shown, in the chip manufacturing process, the top layer pad metal is generally made of aluminum (doped with a small amount of copper). During the fabrication of the top layer pad, the passivation layer is opened, and the top layer pad, once exposed to air, readily forms a dense aluminum oxide film. Figure 1 After attaching a seed layer (such as Ti / Cu, TiW / Cu, etc.) and plating copper on the top pad, electrodes for power devices can be formed through interconnection. Figure 2 As shown.

[0004] After electrode formation, the aluminum oxide film increases the contact resistance between the plated metal (copper) and the top pad, thus increasing the on-resistance of the power device. In other words, the aluminum oxide film between the seed layer and the top pad introduces additional package contact resistance, such as... Figure 3 The diagram shows the equivalent circuit of the power device after introducing package contact resistance. The additional package contact resistance causes the on-resistance of the power device to differ significantly from its normal value.

[0005] To address the issue of oxidation on the surface of the top-layer pads, current technologies typically employ argon plasma etching in a vacuum chamber to remove the aluminum oxide film from the top-layer pad surface. This is followed by seed layer sputtering growth, copper plating, and then interconnection to form electrodes. Figure 4 As shown.

[0006] use Figure 4 The proposed solution makes it difficult to maintain a high vacuum level in the vacuum chamber during etching, sputtering, and other operations. As a result, there will still be a large number of power devices with out-of-specification on-resistance, leading to batch defects in on-resistance. Summary of the Invention

[0007] This application provides a power device, a method for fabricating the power device, a driving circuit, and an integrated circuit board to solve the problems of increased on-resistance and batch defects in on-resistance of power devices caused by oxidation of the top layer pads, thereby restoring the on-resistance of the power device to a normal value.

[0008] In a first aspect, embodiments of this application provide a power device, which includes a die, and a first top layer pad, a first oxide layer, a first seed layer and a first conductive bump stacked sequentially on the die, and further includes a second top layer pad, a second oxide layer, a second seed layer and a second conductive bump stacked sequentially on the die, wherein the first top layer pad is connected to the second top layer pad through the die.

[0009] The first conductive bump can be used to form the drain of the power device, and the second conductive bump can be used to form the source of the power device.

[0010] Using the power device provided in the first aspect, the on-resistance value of the power device can meet the specifications without the need for etching away the oxide layer using other processes. Compared with the prior art, this reduces the number of process steps and lowers the cost of power device fabrication.

[0011] In one possible design, the first oxide layer and the second oxide layer are broken down.

[0012] Breakdown refers to the phenomenon where, when the voltage applied to an insulating medium exceeds a certain level (breakdown voltage), the insulating medium suddenly collapses, causing its resistance to drop rapidly, and subsequently, a portion of the insulating medium becomes a conductor. Taking the first oxide layer as an example, when the voltage applied to the first oxide layer exceeds a certain level, the resistance of the first oxide layer will drop rapidly, causing the first oxide layer to change from an insulating medium to a conductor.

[0013] Using the above solution, after the first oxide layer is broken down, its resistance decreases; after the second oxide layer is broken down, its resistance decreases. Therefore, the on-resistance of the power device decreases, returning to a normal value and meeting the device's specifications. This solution eliminates the need for additional etching processes to remove the oxide layer, reducing process steps and lowering the cost of power device fabrication compared to existing technologies.

[0014] In one possible design, when a first voltage that gradually increases is applied between the first conductive bump and the second conductive bump, the ratio of the first voltage to the first current can be made to reach the rated range of the on-resistance value of the power device, and the first current is the current flowing between the first conductive bump and the second conductive bump.

[0015] By applying a gradually increasing first voltage between the first oxide layer and the second oxide layer using the above method, the first and second oxide layers can be broken down, thereby reducing the on-resistance of the power device until it returns to a normal value, meeting the specifications of the power device. Furthermore, stopping the reception of the first voltage after the ratio of the first voltage to the first current decreases to within the calibrated range of the on-resistance value of the power device ensures that the on-resistance of each power device meets the specifications, preventing any issues. Figure 4 The existing technical solution shown has batch defects due to difficulties in process control (it is difficult to maintain a high vacuum level in the vacuum chamber).

[0016] In one possible design, the power device provided by the first aspect may further include a third top-layer pad, a third oxide layer, a third seed layer and a third conductive bump stacked sequentially on the die, and a fourth top-layer pad, a fourth oxide layer, a fourth seed layer and a fourth conductive bump stacked sequentially on the die, wherein the third top-layer pad is connected to the fourth top-layer pad through the die.

[0017] The third or fourth conductive bump can be used to form the gate of the power device.

[0018] By adopting the above solution, the ratio of the gate voltage to the current flowing through the power device can meet the specifications without the need for other processes to etch away the oxide layer. Compared with the prior art, this reduces the number of process steps and lowers the cost of power device fabrication.

[0019] In one possible design, the third and fourth oxide layers are breached.

[0020] By adopting the above scheme, after the third oxide layer and the fourth oxide layer are broken down, the equivalent resistance value is reduced, which can reduce the ratio of the voltage applied to the gate of the power device to the current flowing through it, until the specifications of the power device are met.

[0021] In one possible design, when a progressively increasing second voltage is applied between the third and fourth conductive bumps, the ratio of the second voltage to the second current can be made to fall within the calibrated range of the ratio of the gate voltage to the current flowing through the power device, where the second current is the current flowing between the third and fourth conductive bumps.

[0022] By adopting the above solution, a second voltage is applied between the third conductive bump and the fourth conductive bump, causing the third oxide layer and the fourth oxide layer to break down. This reduces the ratio of the second voltage to the second current to within the calibrated range of the ratio of the voltage applied to the gate of the power device to the current flowing through it. This can solve the problem of poor gate electrical connection caused by the additional packaging contact resistance introduced by the third oxide layer and the fourth oxide layer.

[0023] In one possible design, the first conductive bump and the second conductive bump are respectively coupled to the two output terminals of the first voltage source or current source, which is used to output the first voltage.

[0024] In one possible design, the third conductive bump and the fourth conductive bump are coupled to the two output terminals of the second voltage source, which is used to output the second voltage.

[0025] Secondly, embodiments of this application provide a method for fabricating a power device. The power device includes a first electrode, a second electrode, and a first oxide layer and a second oxide layer located between the first electrode and the second electrode. Specifically, the method for fabricating the power device includes the following steps: applying a first voltage between the first electrode and the second electrode, such that the ratio of the first voltage to the first current reaches within the calibrated range of the on-resistance value of the power device, wherein the first current is the current flowing between the first electrode and the second electrode.

[0026] The ratio of the first voltage to the first current is the sum of the equivalent resistances of the first electrode, the second electrode, the first oxide layer, and the second oxide layer.

[0027] Specifically, the on-resistance of a power device is the ratio of the voltage applied between the two electrodes other than the gate to the current flowing through them when the power device is operating normally. For example, for a MOSFET, the on-resistance is the ratio of the voltage applied between the drain and source to the current flowing through them when the MOSFET is operating normally.

[0028] In this context, if the power device is a MOSFET or GaN transistor, the first electrode is the drain and the second electrode is the source; if the power device is a BJT, the first electrode is the collector and the second electrode is the emitter. In other words, the first and second electrodes are the two electrodes through which current flows when the power device is turned on, rather than being the control electrodes used to control the power device's on and off states.

[0029] Furthermore, after the first voltage is stopped, the equivalent resistance of the first oxide layer is less than the equivalent resistance of the first oxide layer before the first voltage is applied, and the equivalent resistance of the second oxide layer is less than the equivalent resistance of the second oxide layer before the first voltage is applied.

[0030] The power device fabrication method provided in the second aspect involves applying a first voltage between the first and second electrodes, causing the first and second oxide layers to break down. This reduces the on-resistance of the power device until it returns to a normal value, meeting the device's specifications. This fabrication method eliminates the need for additional etching processes to remove the oxide layers, reducing process steps and lowering the cost of power device fabrication compared to existing technologies. Furthermore, stopping the application of the first voltage after the ratio of the first voltage to the first current decreases to within the calibrated range of the power device's on-resistance ensures that the on-resistance of each power device meets specifications, preventing issues such as... Figure 4 The existing technical solution shown has batch defects due to difficulties in process control (it is difficult to maintain a high vacuum level in the vacuum chamber).

[0031] Furthermore, the power device may also include a first gate, a second gate, and a third oxide layer and a fourth oxide layer located between the first gate and the second gate. Accordingly, the method for fabricating the power device may further include: applying a second voltage between the first gate and the second gate, such that the ratio of the second voltage to the second current reaches a calibrated range for the ratio of the voltage applied to the gate of the power device to the current flowing through it. Wherein, the second current is the current flowing between the first gate and the second gate.

[0032] The ratio of the second voltage to the second current is the sum of the equivalent resistances of the first gate, the second gate, the third oxide layer, and the fourth oxide layer.

[0033] By adopting the above solution, a second voltage is applied between the first gate and the second gate, causing the third oxide layer and the fourth oxide layer to break down. This reduces the ratio of the second voltage to the second current to within the calibrated range of the ratio of the voltage applied to the gate of the power device to the current flowing through it. This can solve the problem of poor gate electrical connection caused by the additional packaging contact resistance introduced by the third oxide layer and the fourth oxide layer.

[0034] Furthermore, after the second voltage is stopped, the equivalent resistance of the third oxide layer is less than the equivalent resistance of the third oxide layer before the second voltage is applied, and the equivalent resistance of the fourth oxide layer is less than the equivalent resistance of the third oxide layer before the second voltage is applied.

[0035] In one possible design, a first voltage can be applied between the first electrode and the second electrode by a first voltage source or a current source.

[0036] In one possible design, a second voltage can be applied between the first gate and the second gate via a second voltage source.

[0037] In one possible design, the fabrication method of the power device further includes: applying a control signal to the power device through a first gate or a second gate to control the power device to turn on and off.

[0038] Using the above scheme, the power device can be turned on and off by either the first gate or the second gate, and either one can be used.

[0039] Thirdly, embodiments of this application also provide a driving circuit, which includes a gate driver and a power device provided in the second aspect and any possible design thereof. The third and fourth conductive bumps of the power device are coupled to the signal output terminal of the gate driver.

[0040] Fourthly, embodiments of this application also provide an integrated circuit board, which includes a circuit board body and a power device provided in the second aspect and any possible design thereof, or a driving circuit provided in the third aspect and any possible design thereof. The integrated circuit board body has pins, and the power device or driving circuit is connected to the circuit board body via these pins.

[0041] Furthermore, it should be understood that the technical effects of the second to fourth aspects and any of their possible design methods can be found in the technical effects of the different design methods in the first aspect, and will not be repeated here. Attached Figure Description

[0042] Figure 1 A schematic diagram of the structure of a semiconductor chip provided for the prior art;

[0043] Figure 2 A schematic diagram of the structure of another semiconductor chip provided by the prior art;

[0044] Figure 3 An equivalent circuit diagram of a power device after introducing package contact resistance is provided for the prior art;

[0045] Figure 4 A schematic diagram of a process for etching alumina thin films according to existing technology;

[0046] Figure 5 This is a schematic diagram of the structure of the first type of power device provided in the embodiments of this application;

[0047] Figure 6 A schematic flowchart illustrating a method for fabricating a power device according to an embodiment of this application;

[0048] Figure 7 A schematic diagram of an Id-Vd curve provided for an embodiment of this application;

[0049] Figure 8A schematic diagram of a Vd-Id curve provided for an embodiment of this application;

[0050] Figure 9 This is a schematic diagram of the structure of a second type of power device provided in an embodiment of this application;

[0051] Figure 10 This is a schematic diagram of the structure of a third type of power device provided in an embodiment of this application;

[0052] Figure 11 A schematic diagram of an Igg-Vgg curve provided for an embodiment of this application;

[0053] Figure 12 A schematic diagram illustrating the application of a voltage between the drain and source electrodes, provided for an embodiment of this application;

[0054] Figure 13 Another schematic diagram of applying a voltage between the drain and source provided for an embodiment of this application;

[0055] Figure 14 A schematic diagram illustrating the application of a voltage between two gates, provided as an embodiment of this application;

[0056] Figure 15 This is a schematic diagram of the structure of the fourth power device provided in the embodiments of this application;

[0057] Figure 16 This is a schematic diagram of a driving circuit provided in an embodiment of this application;

[0058] Figure 17 This is a schematic diagram of the structure of an integrated circuit board provided in an embodiment of this application. Detailed Implementation

[0059] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0060] It should be noted that in the embodiments of this application, "multiple" refers to two or more. Furthermore, in the description of this application, terms such as "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order. The "coupling" mentioned in the embodiments of this application refers to electrical connection, which can specifically include both direct and indirect connections.

[0061] This application provides a method for fabricating a power device, which includes a first electrode, a second electrode, and a first oxide layer and a second oxide layer located between the first electrode and the second electrode.

[0062] The power device includes, but is not limited to, metal-oxide-semiconductor field-effect transistors (MOSFETs), gallium nitride (GaN) transistors, insulated-gate bipolar transistors (IGBTs), bipolar junction transistors (BJTs), and bipolar transistors. If the power device is a MOSFET or GaN transistor, the first electrode is the drain and the second electrode is the source; if the power device is a BJT, the first electrode is the collector and the second electrode is the emitter. In other words, the first and second electrodes are the two electrodes through which current flows when the power device is turned on, not the control electrodes used to control the power device's on and off states.

[0063] It is worth noting that in the embodiments of this application, a first oxide layer and a second oxide layer are included between the first electrode and the second electrode. That is to say, by using the embodiments of this application, the on-resistance of the power device can meet the specifications of the power device without using other processes to etch away the oxide layer.

[0064] In practical applications, the first oxide layer and the second oxide layer can be aluminum oxide thin films. Of course, if other metal materials are used for the top pads when fabricating power devices, the first oxide layer and the second oxide layer can also be thin films formed by oxidizing other metals.

[0065] Taking aluminum oxide thin films as an example, with the first and second oxide layers being aluminum oxide films, a possible structural schematic diagram of a power device can be shown as follows: Figure 5 As shown. In Figure 5 In the example, after attaching a seed layer (such as Ti / Cu, TiW / Cu, etc.) and plating copper on the top pad, the first and second electrodes of the power device are formed by interconnection. There is an aluminum oxide film (first oxide layer) between the seed layer of the first electrode and the top pad, and there is an aluminum oxide film (second oxide layer) between the seed layer of the second electrode and the top pad.

[0066] Specifically, see Figure 6 The fabrication method of this power device includes the following steps.

[0067] S601: Apply a first voltage between the first electrode and the second electrode.

[0068] S602: Increase the first voltage and measure the voltage value of the first voltage and the current value of the first current.

[0069] The first current is the current flowing between the first electrode and the second electrode.

[0070] S603: When the ratio of the first voltage to the first current reaches the calibrated range of the on-resistance value of the power device, stop applying the first voltage.

[0071] from Figure 5 As can be seen from the structure shown, the ratio of the first voltage to the first current is the sum of the equivalent resistances of the first electrode, the second electrode, the first oxide layer, and the second oxide layer.

[0072] In this embodiment, the on-resistance of a power device is the ratio of the voltage applied between the two electrodes other than the gate to the current flowing through them when the power device is operating normally. For example, for a MOSFET, the on-resistance is the ratio of the voltage applied between the drain and source to the current flowing through them when the MOSFET is operating normally. Again, taking a MOSFET as an example, the on-resistance determines the power consumed when the MOSFET is turned on. Typically, for a MOSFET of a certain specification, there is a calibrated range for its on-resistance value at the time of manufacture. For example, the calibrated range for the on-resistance value can be 25mΩ ± 5mΩ. Only when the on-resistance value is within the calibrated range is the power device considered to meet the factory requirements. In this embodiment, during the manufacturing process of the power device, the ratio of the first voltage to the first current is continuously tested. When the ratio of the first voltage to the first current falls within the calibrated range of the on-resistance value (e.g., 25mΩ ± 5mΩ), the on-resistance value of the power device can be considered to meet the factory requirements, and the application of the first voltage can be stopped.

[0073] Specifically, in S601, a first voltage can be applied between the first electrode and the second electrode by a first voltage source, or a first voltage can be applied between the first electrode and the second electrode by a current source.

[0074] In practical applications, when a first voltage is applied through a first voltage source, the output voltage of the first voltage source can be gradually increased, for example, from 0V to 5V. When the applied voltage is small, the conduction current (i.e., the first current) of the power device is very small due to the presence of the first and second oxide layers. When the voltage continues to increase, the first and second oxide layers break down under the influence of the electric field. At the instant the first oxide layer is damaged, its resistance suddenly decreases; at the instant the second oxide layer is damaged, its resistance suddenly decreases. At this point, the current can flow normally through the first and second oxide layers, and the conduction current of the power device will experience a jump, quickly returning to the ideal level. Specifically, the relationship between the output voltage Vd (i.e., the first voltage) of the first voltage source and the conduction current Id (i.e., the first current) of the power device can be expressed as follows: Figure 7As shown, when the Id-Vd curve nearly coincides with the Id-Vd curve under ideal conditions, it can be considered that the on-current of the power device has recovered to the ideal level, that is, the on-resistance of the power device has recovered to the ideal level.

[0075] In this embodiment, breakdown refers to the phenomenon where, when the voltage applied to an insulating medium exceeds a certain level (breakdown voltage), the insulating medium suddenly collapses, causing its resistance to drop rapidly, and subsequently, a portion of the insulating medium becomes a conductor. Taking the first oxide layer as an example, when the voltage applied to the first oxide layer exceeds a certain level, the resistance of the first oxide layer drops rapidly, causing the first oxide layer to change from an insulating medium to a conductor.

[0076] In practical applications, when a first voltage is applied through a current source, the output current of the current source can be gradually increased. When the applied current is small, the potential difference between the first and second electrodes is large due to the presence of the first and second oxide layers. As the current continues to increase, the first and second oxide layers break down under the influence of the electric field. The resistance of the first oxide layer suddenly decreases the instant the first oxide layer is damaged, and the resistance of the second oxide layer suddenly decreases the instant the second oxide layer is damaged, resulting in a sudden decrease in the potential difference between the first and second electrodes, which then quickly returns to the ideal level. Specifically, the relationship between the potential difference Vd between the first and second electrodes and the output current Id of the current source can be expressed as follows: Figure 8 As shown, when the Vd-Id curve nearly coincides with the Vd-Id curve under ideal conditions, the on-resistance of the power device can be considered to have recovered to the ideal level.

[0077] After the on-resistance of the power device returns to the ideal level (i.e., the ratio of the first voltage to the first current decreases to within the calibrated range of the on-resistance value of the power device), the application of the first voltage can be stopped. For example, in Figure 7 In the example, when the Id-Vd curve nearly coincides with the ideal Id-Vd curve, it can be considered that the ratio of the first voltage to the first current has reached the calibrated range of the on-resistance of the power device, and at this point, the application of the first voltage is stopped; Figure 8 In the example, when the Vd-Id curve nearly coincides with the Vd-Id curve under ideal conditions, it can be considered that the ratio of the first voltage to the first current has reached the calibration range of the on-resistance value of the power device, and at this time the application of the first voltage is stopped.

[0078] After the first voltage is stopped, the equivalent resistance of the first oxide layer is less than that before the first voltage was applied, and the equivalent resistance of the second oxide layer is also less than that before the first voltage was applied. Although the first and second oxide layers still exist in the power device, the additional package contact resistance introduced by the first and second oxide layers has a negligible effect on the on-resistance of the power device, and the on-resistance of the power device returns to its normal value.

[0079] use Figure 6 The method for fabricating the power device illustrates that by applying a first voltage between the first and second electrodes, the first and second oxide layers break down, thereby reducing the on-resistance of the power device until it returns to a normal value, meeting the device's specifications. This method eliminates the need for additional etching processes to remove the oxide layers, reducing process steps and lowering the cost of power device fabrication compared to existing technologies. Furthermore, by stopping the application of the first voltage after the ratio of the first voltage to the first current decreases to within the calibrated range of the power device's on-resistance, the on-resistance of each power device meets the specifications, preventing any issues. Figure 4 The existing technical solution shown has batch defects due to difficulties in process control (it is difficult to maintain a high vacuum level in the vacuum chamber).

[0080] Furthermore, oxidation of the top-layer pad metal can introduce package contact resistance into the control electrodes (e.g., the gate) of power devices. Since the gate of a power device cannot carry a large current, a dual-gate structure can be formed during chip design. Applying voltage between the two gates can also solve the problem of poor electrical connection caused by package contact resistance.

[0081] In this embodiment, the power device may further include a first gate, a second gate, and a third oxide layer and a fourth oxide layer located between the first gate and the second gate. The method for fabricating the power device further includes: applying a second voltage between the first gate and the second gate; increasing the voltage value of the second voltage; and measuring the ratio of the second voltage to the second current; stopping the application of the second voltage when the ratio of the second voltage to the second current reaches a calibrated range for the ratio of the voltage applied to the gate of the power device to the current flowing through it. The second current is the current flowing between the first gate and the second gate.

[0082] It is easy to understand that the ratio of the second voltage to the second current is the sum of the equivalent resistances of the first gate, the second gate, the third oxide layer, and the fourth oxide layer.

[0083] In practical applications, the third and fourth oxide layers can be aluminum oxide thin films. Of course, if other metal materials are used for the top pads when fabricating power devices, the third and fourth oxide layers can also be thin films formed by oxidizing other metals.

[0084] Taking the third and fourth oxide layers as an example of an aluminum oxide thin film, in Figure 9 In the example, the package contact resistance introduced by oxidation is equivalent to an aluminum oxide film, and two aluminum oxide films, namely a third oxide layer and a fourth oxide layer, are included between the first gate G1 and the second gate G2. In this example, a possible schematic diagram of the power device can be shown as follows: Figure 10 As shown. In Figure 10 In the example, after attaching a seed layer (such as Ti / Cu, TiW / Cu, etc.) and plating copper on the top pad, the first gate and the second gate of the power device are formed by interconnection. There is an aluminum oxide film (third oxide layer) between the seed layer of the first gate and the top pad, and there is an aluminum oxide film (fourth oxide layer) between the seed layer of the second gate and the top pad.

[0085] It should be noted that, in Figure 10 In the example, for simplicity, the first and second electrodes in the power device are not shown. The structures of the first and second electrodes can be referred to... Figure 5 Examples from the previous examples are not repeated here.

[0086] Similar to the calibration range of the on-resistance value of the aforementioned power devices, the ratio of the gate voltage to the current flowing through the power device also has a calibration range when it leaves the factory. Only when the ratio of the gate voltage to the current flowing through the power device is within the calibration range is the power device considered to meet the factory requirements. In the embodiments of this application, during the manufacturing process of the power device, the ratio of the second voltage and the second current is continuously tested. When the ratio of the second voltage and the second current falls within the calibration range of the ratio of the gate voltage to the current flowing through the power device, the on-resistance value of the power device can be considered to meet the factory requirements, and the application of the second voltage can be stopped.

[0087] Specifically, a second voltage can be applied between the first and second gates using a second voltage source. Applying the second voltage allows the output voltage of the second voltage source to gradually increase. When the applied voltage is low, the current Igg flowing between the first and second gates is small due to the presence of the third and fourth oxide layers. As the voltage increases further, the third and fourth oxide layers break down under the influence of the electric field, allowing the current to flow normally through them. Igg will experience a jump and then quickly return to the ideal level. Specifically, the relationship between the output voltage Vgg (i.e., the second voltage) and Igg (i.e., the second current) of the second voltage source can be as follows: Figure 11 As shown. When the Igg-Vgg curve nearly coincides with the Igg-Vgg curve under ideal conditions, it can be considered that the ratio of the second voltage to the second current has reached the calibrated range of the ratio of the gate voltage to the current flowing through the power device.

[0088] The application of the second voltage can be stopped after the ratio of the second voltage to the second current decreases to within the calibrated range of the ratio of the gate voltage to the current flowing through the power device. For example, in Figure 11 In the example, the application of the second voltage can be stopped when the Igg-Vgg curve nearly coincides with the ideal Igg-Vgg curve.

[0089] After the second voltage is stopped, the equivalent resistance of the third oxide layer is less than that before the second voltage is applied, and the equivalent resistance of the fourth oxide layer is less than that before the second voltage is applied. Although the third and fourth oxide layers still exist in the power device, the poor gate electrical connection caused by the additional package contact resistance introduced by the third and fourth oxide layers is almost negligible.

[0090] It should be understood that the above-described scheme of applying a second voltage between the first gate and the second gate to solve the problem of poor electrical connection of the gate is not strictly limited in terms of the order of execution as the above-described scheme of applying a first voltage between the first electrode and the second electrode to solve the problem of poor electrical connection between the first electrode and the second electrode.

[0091] Furthermore, after performing the above-described fabrication method, the on-resistance value of the power device meets the factory requirements. During use after the power device leaves the factory, a control signal can be applied to the power device through either the first gate or the second gate to control the power device's on and off states. In other words, after leaving the factory, both the first and second gates can be used as the gates of the power device to control its on and off states; in practical applications, one can be chosen for use.

[0092] It should be noted that when executing S601, a control signal needs to be applied to the gate of the power device to control the power device to turn on. In practical applications, the control signal can be applied to either the first gate or the second gate.

[0093] In summary, the power device fabrication method provided in this application applies a first voltage between the first and second electrodes, causing the first and second oxide layers to break down. This reduces the on-resistance of the power device until it returns to a normal value, meeting the device's specifications. This fabrication method eliminates the need for additional etching processes to remove the oxide layer, reducing process steps compared to existing technologies. Once the ratio of the first voltage to the first current decreases to within the calibrated range of the power device's on-resistance, the application of the first voltage is stopped, ensuring that the on-resistance of each power device meets specifications and avoiding batch defects seen in existing technologies.

[0094] Furthermore, by applying a second voltage between the first gate and the second gate, the third oxide layer and the fourth oxide layer break down, thereby reducing the ratio of the second voltage to the second current to within the calibrated range of the ratio of the voltage applied to the gate of the power device to the current flowing through it. This can solve the problem of poor gate electrical connection caused by the additional package contact resistance introduced by the third oxide layer and the fourth oxide layer.

[0095] Below, with Figure 9 Taking the power device shown as an example, the fabrication scheme of the power device provided in the embodiments of this application will be described in detail.

[0096] Step 1: Test the output characteristics of the device using a high-current tester (or a test board that can provide high current). The specific process is to apply a positive voltage Vgs to turn on the power device and apply a voltage between D and S.

[0097] Specifically, a high-current testing machine can be considered equivalent to a current source, such as... Figure 12 As shown; a high-current tester can also function as a voltage source, such as... Figure 13 As shown.

[0098] Initially, due to the presence of the oxide layer between the drain (D) and source (S), the conduction current of the power device is very small. When the voltage is increased further, the oxide layer between the drain and source begins to pass through under the influence of the electric field, and the current can pass through the oxide layer normally, and the current of the power device will return to the level of an ideal device. At this point, the voltage applied between the drain and source is stopped.

[0099] Step 2: Apply a voltage between G1 and G2, such as Figure 14 As shown. Initially, due to the presence of the oxide layer between G1 and G2, the current flowing through G1 is very small; when the voltage continues to increase, the oxide layer between G1 and G2 begins to permeate under the influence of the electric field, and the current can pass through the oxide layer normally, and the current flowing through G1 returns to the level of an ideal device. At this point, the voltage applied between G1 and G2 is stopped.

[0100] It should be noted that there is no strict restriction on the execution order of steps 1 and 2 above. You can execute step 1 first and then step 2, or you can execute step 2 first and then step 1.

[0101] This application also provides a power device, such as... Figure 15 As shown, the power device 1500 includes a die 1501, and a first top layer pad 1502a, a first oxide layer 1502b, a first seed layer 1502c, and a first conductive bump 1502d stacked sequentially on the die 1501. It also includes a second top layer pad 1503a, a second oxide layer 1503b, a second seed layer 1503c, and a second conductive bump 1503d stacked sequentially on the die 1501. The first top layer pad 1502a is connected to the second top layer pad 1503a through the die 1501.

[0102] The first conductive bump 1502d can be used to form the drain of the power device 1500, and the second conductive bump 1503d can be used to form the source of the power device 1500.

[0103] Optionally, the first oxide layer 1502b and the second oxide layer 1503b are broken down.

[0104] After the first oxide layer 1502b is broken down, the equivalent resistance value decreases; after the second oxide layer 1503b is broken down, the equivalent resistance value decreases, thus reducing the equivalent resistance value of the power device 1500 to within the rated range of the on-resistance value of the power device 1500.

[0105] Since the first top-layer pad 1502a is connected to the second top-layer pad 1503a through the die 1501, when a first voltage is applied between the first conductive bump 1502d and the second conductive bump 1503d, it is easy to understand that the path of the first current is as follows: first conductive bump 1502d → first seed layer 1502c → first oxide layer 1502b → first top-layer pad 1502a → die 1501 → second top-layer pad 1503a → second oxide layer 1503b → second seed layer 1503c → second conductive bump 1503d. Since the on-resistance of the first seed layer 1502c, the first top layer pad 1502a, the second top layer pad 1503a, and the second seed layer 1503c is relatively small, the ratio of the first voltage to the first current can be considered to be approximately equal to the sum of the equivalent resistances of the first conductive bump 1502d, the second conductive bump 1503d, the first oxide layer 1502b, and the second oxide layer 1503b.

[0106] Power device 1500 includes, but is not limited to, MOSFETs, GaN transistors, IGBTs, BJTs, and bipolar transistors. If power device 1500 is a MOSFET or GaN transistor, then the first conductive bump 1502d is the drain and the second conductive bump 1503d is the source; if power device 1500 is a BJT, then the first conductive bump 1502d is the collector and the second conductive bump 1503d is the emitter. That is, the first conductive bump 1502d and the second conductive bump 1503d are the two electrodes through which current flows when power device 1500 is turned on, rather than control electrodes (such as the gate) used to control the on and off states of power device 1500.

[0107] Optionally, when a gradually increasing first voltage is applied between the first conductive bump 1502d and the second conductive bump 1503d, the ratio of the first voltage to the first current can be made to reach the calibrated range of the on-resistance value of the power device 1500. The first current is the current flowing between the first conductive bump 1502d and the second conductive bump 1503d.

[0108] The first voltage applied between the first conductive bump 1502d and the second conductive bump 1503d can cause the first oxide layer 1502b and the second oxide layer 1503b to break down, thereby reducing the on-resistance of the power device 1500 until it returns to a normal value, meeting the specifications of the power device 1500. After the ratio of the first voltage to the first current decreases to within the calibrated range of the on-resistance value of the power device 1500, the application of the first voltage is stopped. This ensures that the on-resistance of the power device 1500 consistently meets specifications, preventing batch defects as seen in existing technologies.

[0109] In addition, the power device 1500 may also include a third top layer pad, a third oxide layer, a third seed layer and a third conductive bump stacked sequentially on the die 1501, and a fourth top layer pad, a fourth oxide layer, a fourth seed layer and a fourth conductive bump stacked sequentially on the die, wherein the third top layer pad is connected to the fourth top layer pad through the die 1501.

[0110] The third or fourth conductive bump can be used to form the gate of the power device 1500.

[0111] Optionally, the third and fourth oxide layers are broken down.

[0112] After the third and fourth oxide layers are broken down, the equivalent resistance decreases, which reduces the ratio of the voltage applied to the gate of the power device 1500 to the current flowing through it, until the specifications of the power device 1500 are met.

[0113] Optionally, when a gradually increasing second voltage is applied between the third and fourth conductive bumps, the ratio of the second voltage to the second current can be made to reach the calibrated range of the ratio of the gate voltage to the current flowing through the power device 1500. Here, the second current is the current flowing between the third and fourth conductive bumps.

[0114] Since the third top-layer pad is connected to the fourth top-layer pad via die 1501, when a second voltage is applied between the third and fourth conductive bumps, it is easy to understand that the flow path of the second current is: third conductive bump → third seed layer → third oxide layer → third top-layer pad → die 1501 → fourth top-layer pad → fourth oxide layer → fourth seed layer → fourth conductive bump. Because the on-resistance of the third seed layer, third top-layer pad, fourth top-layer pad, and fourth seed layer is relatively small, the ratio of the second voltage to the second current can be considered approximately equal to the sum of the equivalent resistances of the third conductive bump, fourth conductive bump, third oxide layer, and fourth oxide layer.

[0115] Applying a second voltage between the third and fourth conductive bumps causes the third and fourth oxide layers to break down, thereby reducing the ratio of the second voltage to the second current to within the calibrated range of the ratio of the voltage applied to the gate of the power device 1500 to the current flowing through it. This can solve the problem of poor gate electrical connection caused by the additional package contact resistance introduced by the third and fourth oxide layers.

[0116] In practical applications, the first conductive bump 1502d and the second conductive bump 1503d can be coupled to the two output terminals of the first voltage source or current source, respectively. The first voltage source or current source is used to output a first voltage and to stop outputting the first voltage when the ratio of the second voltage to the second current decreases to within the calibrated range of the ratio of the voltage applied to the gate of the power device 1500 to the current flowing through it. For example, the first conductive bump 1502d and the second conductive bump 1503d can be coupled to the two output terminals of the first voltage source in the following manner: Figure 13 As shown (where D corresponds to the first conductive bump 1502d and S corresponds to the second conductive bump 1503d), the first conductive bump 1502d and the second conductive bump 1503d are coupled to the two output terminals of the current source in the following manner: Figure 12 As shown (where D corresponds to the first conductive bump 1502d and S corresponds to the second conductive bump 1503d).

[0117] In practical applications, the third and fourth conductive bumps are coupled to the two output terminals of the second voltage source, which outputs a second voltage and stops outputting the second voltage when the ratio of the second voltage to the second current decreases to within the calibrated range of the ratio of the voltage applied to the gate of the power device 1500 to the current flowing through it. Exemplarily, the third and fourth conductive bumps are coupled to the two output terminals of the second voltage source in the following manner: Figure 14 As shown (where G1 is equivalent to the third conductive bump and G2 is equivalent to the fourth conductive bump).

[0118] In addition, the third and fourth conductive bumps can also be used to apply control signals to control the power device 1500 to turn on and off.

[0119] It should be noted that the implementation methods and technical effects of power devices 1500 that are not described in detail can be found in [reference needed]. Figure 6 The relevant descriptions of the fabrication method of the power device shown will not be repeated here.

[0120] This application also provides a driving circuit, such as... Figure 16 As shown, the driving circuit 1600 includes a gate driver 1601 and the aforementioned power device 1500. The third and fourth conductive bumps of the power device 1500 are coupled to the signal output terminal of the gate driver 1601.

[0121] Furthermore, embodiments of this application also provide an integrated circuit board, such as... Figure 17 As shown, the integrated circuit board 1700 includes a circuit board body 1701 and the power device 1500 (or drive circuit 1600). Figure 17 The integrated circuit board 1700, including the circuit board body 1701 and the power device 1500, is illustrated as an example. The circuit board body 1701 has pins, and the power device 1500 is electrically connected to the circuit board body 1701 through the pins.

[0122] It should be noted that, in Figure 17 The pin configuration shown here is merely a specific example. In practical applications, the pins of the circuit board body 1701 can be point-like, sheet-like, or surface-like. This application embodiment does not limit the specific configuration of the pins of the circuit board body 1701.

[0123] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A power device, characterized in that, It includes a bare die, and a first top layer pad, a first oxide layer, a first seed layer and a first conductive bump stacked sequentially on the bare die, and also includes a second top layer pad, a second oxide layer, a second seed layer and a second conductive bump stacked sequentially on the bare die, wherein the first top layer pad is connected to the second top layer pad through the bare die; When a first voltage that gradually increases is applied between the first conductive bump and the second conductive bump, the ratio of the first voltage to the first current reaches the calibrated range of the on-resistance value of the power device, so that the first oxide layer and the second oxide layer are broken down, and the first current is the current flowing between the first conductive bump and the second conductive bump.

2. The power device as described in claim 1, characterized in that, The first conductive bump is used to form the drain of the power device, and the second conductive bump is used to form the source of the power device.

3. The power device as described in claim 1 or 2, characterized in that, It also includes a third top layer pad, a third oxide layer, a third seed layer and a third conductive bump stacked sequentially on the die, and a fourth top layer pad, a fourth oxide layer, a fourth seed layer and a fourth conductive bump stacked sequentially on the die, wherein the third top layer pad is connected to the fourth top layer pad through the die.

4. The power device as described in claim 3, characterized in that, The third oxide layer and the fourth oxide layer were punctured.

5. The power device as described in claim 3, characterized in that, When a gradually increasing second voltage is applied between the third conductive bump and the fourth conductive bump, the ratio of the second voltage to the second current reaches the calibrated range of the ratio of the voltage applied to the gate of the power device to the current flowing through it, and the second current is the current flowing between the third conductive bump and the fourth conductive bump.

6. The power device as described in claim 5, characterized in that, The third conductive bump or the fourth conductive bump is used to form the gate of the power device.

7. The power device as described in any one of claims 1-2 or 4-6, characterized in that, The first conductive bump and the second conductive bump are respectively coupled to the two output terminals of the first voltage source or current source, and the first voltage source or current source is used to output the first voltage.

8. The power device as described in claim 3, characterized in that, The third conductive bump and the fourth conductive bump are respectively coupled to the two output terminals of the second voltage source, which is used to output the second voltage.

9. A method for fabricating a power device, characterized in that, The power device includes a first electrode, a second electrode, and a first oxide layer and a second oxide layer located between the first electrode and the second electrode. The method includes: A first voltage is applied between the first electrode and the second electrode, such that the ratio of the first voltage to the first current is within the calibrated range of the on-resistance value of the power device, so that the first oxide layer and the second oxide layer are broken down, and the first current is the current flowing between the first electrode and the second electrode.

10. The method as described in claim 9, characterized in that, The ratio of the first voltage to the first current is the sum of the equivalent resistances of the first electrode, the second electrode, the first oxide layer, and the second oxide layer.

11. The method as described in claim 9 or 10, characterized in that, The power device further includes a first gate, a second gate, and a third oxide layer and a fourth oxide layer located between the first gate and the second gate, and the method further includes: A second voltage is applied between the first gate and the second gate such that the ratio of the second voltage to the second current is within the calibrated range of the ratio of the voltage applied to the gate of the power device to the current flowing through it, wherein the second current is the current flowing between the first gate and the second gate.

12. The method as described in claim 11, characterized in that, The ratio of the second voltage to the second current is the sum of the equivalent resistances of the first gate, the second gate, the third oxide layer, and the fourth oxide layer.

13. The method according to any one of claims 9-10 or 12, characterized in that, Applying a first voltage between the first electrode and the second electrode includes: The first voltage is applied between the first electrode and the second electrode by a first voltage source or a current source.

14. The method as described in claim 11, characterized in that, Applying a second voltage between the first gate and the second gate includes: The second voltage is applied between the first gate and the second gate by a second voltage source.

15. The method according to any one of claims 9-10, 12, or 14, characterized in that, The first electrode is the drain electrode, and the second electrode is the source electrode.

16. The method as described in claim 11, characterized in that, Also includes: A control signal is applied to the power device through the first gate or the second gate to control the power device to turn on and off.

17. A driving circuit, characterized in that, The device includes a gate driver and a power device as described in any one of claims 1 to 8; the power device further includes: a third top layer pad, a third oxide layer, a third seed layer and a third conductive bump stacked sequentially on the die, and a fourth top layer pad, a fourth oxide layer, a fourth seed layer and a fourth conductive bump stacked sequentially on the die, wherein the third top layer pad is connected to the fourth top layer pad through the die; wherein the third conductive bump and the fourth conductive bump of the power device are coupled to the signal output terminal of the gate driver.

18. An integrated circuit board, characterized in that, It includes a circuit board body and a power device as described in any one of claims 1 to 8, or includes a drive circuit as described in claim 17; wherein the circuit board body has pins, and the power device is electrically connected to the circuit board body through the pins.

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