Advanced integrated passive devices (IPD) for high power handling filters

Abstract

A semiconductor package is described. The semiconductor package includes a first integrated passive device (IPD) in a first interlayer dielectric (ILD) layer on a passive substrate. The semiconductor package also includes a second ILD layer on the first ILD layer. The semiconductor package further includes a second IPD in a third ILD layer on the second ILD layer. The semiconductor package also includes a thermal mitigation structure on an inductive element of the second IPD.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Patent Application No. 16 / 898,096, filed June 10, 2020, entitled “Advanced Integrated Passive Device (IPD) with Thin Film Heat Sink (TF-HS) Layer for High Power Processing Filter in Transmission (TX) Path,” the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various aspects of this disclosure relate to integrated circuits, and more specifically, to advanced integrated passive devices (IPDs) with thin-film heat sink (TF-HS) layers for implementing high-power processing radio frequency (RF) filters in the transmission (TX) path of wireless communication devices. Background Technology

[0004] Three-dimensional (3D) packages may include two or more stacked chips (e.g., integrated circuits (ICs)) to occupy less footprint and / or have greater connectivity. For high-end chips using die stacking, heat dissipation is increasingly a concern. In particular, stacking two or more chips can lead to localized hot spots. Because these localized hot spots are embedded within the stack, this can reduce the ability to cool hot spots and achieve low junction temperatures. Conventional cooling solutions for achieving low junction temperatures include heat sinks, radiators, and / or improved printed circuit boards. Conventional techniques that simply increase the size of heat sinks and / or radiators are impractical in small-factor devices such as smartphones.

[0005] The design of complex system-on-a-chip (SoC) can be affected by communication enhancements, such as fifth-generation (5G) new radio (NR) technology. For example, to support 5G NR communications, a greater number of communication frequency bands have been specified. Supporting these additional communication bands requires packing additional components into a smaller package size, resulting in higher junction temperatures. Unfortunately, the performance of complex SoCs designed to support 5G NR communications can be adversely affected by these high junction temperatures. Summary of the Invention

[0006] A semiconductor package is described. The semiconductor package includes a passive substrate and a first integrated passive device (IPD) in a first interlayer dielectric (ILD) layer on the passive substrate. The semiconductor package also includes a second ILD layer on the first ILD layer. The semiconductor package further includes a second IPD in a third ILD layer on the second ILD layer. The semiconductor package also includes a thermal mitigation structure on an inductive element of the second IPD.

[0007] A method for fabricating a thermal mitigation structure in a semiconductor package is described. The method includes forming a first integrated passive device (IPD) in a first interlayer dielectric (ILD) layer on a passive substrate. The method further includes depositing a second ILD layer on the first ILD layer. The method further includes forming a second IPD in a third ILD layer on the second ILD layer. The method further includes depositing a thin-film heat sink (TF-HS) layer on the inductive element of the second IPD.

[0008] A semiconductor package is described. The semiconductor package includes a passive substrate and a first integrated passive device (IPD) in a first interlayer dielectric (ILD) layer on the passive substrate. The semiconductor package also includes a second ILD layer on the first ILD layer. The semiconductor package further includes a second IPD in a third ILD layer on the second ILD layer. The semiconductor package further includes components for heat dissipation from an inductive element of the second IPD.

[0009] This provides a fairly broad overview of the features and technical advantages of this disclosure in order to facilitate a better understanding of the detailed description that follows. Additional features and advantages of this disclosure will now be described. Those skilled in the art will understand that this disclosure can be readily used as the basis for modifying or designing other structures for achieving the same purpose as this disclosure. Those skilled in the art will also understand that such equivalent constructions do not depart from the teachings of this disclosure as set forth in the appended claims. The novel features considered to be features of this disclosure, both in relation to its organization and manner of operation, and in relation to further purposes and advantages, will be better understood from the following description when considered in conjunction with the accompanying drawings. However, it should be clearly understood that each drawing is provided merely for illustrative and descriptive purposes and is not intended to be a definition of limitation of this disclosure. Attached Figure Description

[0010] For a more complete understanding of this disclosure, please refer to the following description in conjunction with the accompanying drawings.

[0011] Figure 1 An example implementation of a system-on-a-chip (SoC) according to certain aspects of this disclosure is illustrated, the SoC including an advanced integrated passive device (IPD) having a thin-film heat sink (TF-HS) layer.

[0012] Figure 2 The illustrations include Figure 1 A cross-sectional view of the heat flow path within the stacked integrated circuit (IC) package of a system-on-a-chip (SoC).

[0013] Figure 3 The illustration shows a wireless device incorporated into a description of one aspect of this disclosure. Figure 2 A cross-sectional view of a stacked integrated circuit (IC) package.

[0014] Figure 4 This is a cross-sectional view of an integrated circuit (IC) package having a thin-film heat sink (TF-HS) layer according to various aspects of this disclosure.

[0015] Figure 5 This is a cross-sectional view of an integrated circuit (IC) package having a thin-film heat sink (TF-HS) layer according to various aspects of this disclosure.

[0016] Figure 6 It is according to various aspects of this disclosure, including having a thin-film heat sink (TF-HS) layer. Figure 5 Cross-sectional view of radio frequency (RF) chip in an integrated circuit (IC) package.

[0017] Figure 7 This is a process flow diagram illustrating a method for manufacturing a thermal relief structure in a semiconductor package according to one aspect of the present disclosure.

[0018] Figure 8 This is a block diagram illustrating an exemplary wireless communication system in which the configurations of this disclosure can be advantageously employed.

[0019] Figure 9 It is a block diagram of a design workstation used for the circuit, layout, and logic design of semiconductor components according to a configuration specification. Detailed Implementation

[0020] The detailed descriptions below, taken in conjunction with the accompanying drawings, are intended to describe various configurations, and not to represent the only configuration in which the described concepts can be practiced. The detailed descriptions include specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, to avoid confusion with these concepts, well-known structures and components are shown in block diagram form.

[0021] As described above, the use of the terms "and / or" is intended to mean "inclusive OR," and the use of the term "or" is intended to mean "exclusive OR." As described, the term "exemplary" as used throughout this specification means "serving as an example, instance, or illustration" and should not be construed as being more preferred or advantageous than other exemplary configurations. As described above, the term "coupled" as used throughout this specification means "connection, whether direct or indirect via an intermediate connection (e.g., a switch), electrical, mechanical, or other means," and is not necessarily limited to physical connections. Furthermore, connections can allow objects to be permanently or releasably connected. These connections can be implemented via switches. As described above, the term "proximate" as used throughout this specification means "adjacent, very close, adjacent, or near." As described above, the term "on" as used throughout this specification means "directly on" in some configurations and "indirectly on" in others.

[0022] For high-end chips using die stacking, such as complex system-on-chip (SoC) packages, heat dissipation is increasingly becoming a problem. In particular, stacking two or more chips can lead to localized hot spots. Because these localized hot spots are embedded within the stack, this can reduce the ability to cool down the hot spots and achieve low junction temperatures. Conventional cooling solutions for achieving low junction temperatures include heat sinks, radiators, and / or improved printed circuit boards. Conventional techniques for increasing the size of heat sinks and / or radiators are impractical in small-factor devices such as smartphones.

[0023] The design of complex SoC packages can be impacted by communication enhancements, such as 5G NR technology. For example, to support 5G NR communication, a greater number of communication bands have been specified. Supporting these additional communication bands requires packing additional components into a smaller package size, resulting in higher junction temperatures. Unfortunately, the performance of complex SoC packages designed to support 5G NR communication can be adversely affected by these high junction temperatures.

[0024] These SoC packages can include radio frequency (RF) integrated passive devices (IPDs) to support 5G NR communications, aluminum nitride (AlN) acoustic resonators / filters, and RF microelectromechanical systems (MEMS) switches. In fact, glass is an ideal substrate material for realizing these RF devices because it achieves low insertion loss compared to semiconductor substrates such as silicon. Unfortunately, glass exhibits the inherent disadvantage of low thermal conductivity (e.g., approximately 1.9 W / Ko-m compared to 150 W / Ko-m for silicon).

[0025] The low thermal conductivity of glass limits the application of RF integrated devices built on glass substrates to handle high power due to poor heat dissipation. This is undesirable when hot spots are located within the RF integrated device (e.g., an RF filter used in the transmit (TX) path). During operation, the glass substrate cannot adequately dissipate heat to reduce the temperature of localized hot spots. Therefore, the use of glass substrates in RF integrated devices reduces the thermal reliability of the device and may ultimately lead to package failure.

[0026] Previously disclosed approaches use alumina ceramic substrates instead of glass. In practice, alumina ceramic substrates exhibit low loss tangents while providing high thermal conductivity (e.g., 30 times higher than glass substrates). The higher thermal conductivity of the alumina substrate provides better heat dissipation for handling high-power RF devices. Unfortunately, heat may still be trapped by the low thermal conductivity interlayer dielectric (ILD) layer (e.g., polyimide (PI), polybenzoxazole (PBO), or benzocyclobutene (BCB)).

[0027] Various aspects of this disclosure provide an advanced integrated passive device (IPD) having a thin-film heat sink (TF-HS) layer. Process flows for manufacturing an advanced IPD having a TF-HS layer may include wafer-level process (WLP) technology. It should be understood that, unless otherwise stated, the term "layer" includes a film and should not be construed as indicating vertical or horizontal thickness. As mentioned above, the term "substrate" can refer to a substrate with a diced wafer or a substrate without a diced wafer. As mentioned above, the term "laminate" can refer to a multilayer board capable of packaging an IC device. The terms "substrate," "wafer," and "laminate" are used interchangeably. Similarly, the terms "chip" and "die" are used interchangeably.

[0028] Various aspects of this disclosure describe thermal mitigation structures for advanced IPD. In various aspects of this disclosure, a TF-HS layer is coated on (or beneath) a heated inductor element of an RF package including an RF integrated device. The TF-HS layer can significantly reduce the temperature generated in integrated inductor-capacitor (LC) passive devices built on a substrate material such as silicon, glass, alumina, or other similar substrate materials. In one configuration, the TF-HS layer is coated on a thermal inductor in an upper back-to-upper process (BEOL) metal layer connected to a wafer-level process (WLP) ball.

[0029] Figure 1An example embodiment of a host system-on-a-chip (SoC) 100 according to various aspects of this disclosure is illustrated. The host SoC 100 includes an advanced integrated passive device (IPD) with a thin-film heat sink (TF-HS) layer. The host SoC 100 includes processing blocks tailored for specific functions, such as a connectivity block 110. The connectivity block 110 may include fifth-generation (5G) New Radio (NR) connectivity, fourth-generation Long Term Evolution (4G LTE) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth, etc. ® Connectivity, Secure Digital (SD) connectivity, etc.

[0030] In this configuration, the host SoC 100 includes various processing units that support multi-threaded operation. For Figure 1 As shown in the configuration, the host SoC 100 includes a multi-core central processing unit (CPU) 102, a graphics processing unit (GPU) 104, a digital signal processor (DSP) 106, and a neural processing unit (NPU) 108. The host SoC 100 may also include a sensor processor 114, an image signal processor (ISP) 116, a navigation module 120 (which may include a global positioning system), and memory 118. The multi-core CPU 102, GPU 104, DSP 106, NPU 108, and multimedia engine 112 support various functions such as video, audio, graphics, games, artificial intelligence networks, etc. Each processor core of the multi-core CPU 102 can be a Reduced Instruction Set Computer (RISC) machine, an Advanced RISC machine (ARM), a microprocessor, or some other type of processor. The NPU 108 may be based on the ARM instruction set.

[0031] Figure 2 The illustration is shown. Figure 1 A cross-sectional view of the main heat flow within the stacked integrated circuit (IC) package 200 of the SoC 100. Typically, the stacked IC package 200 includes a printed circuit board (PCB) 202 connected to a package substrate 210 by interconnects 212. In this configuration, the package substrate 210 includes conductive layers 214 and 216. Above the package substrate 210 is a 3D chip stack 220, which includes stacked dies 222, 224, and 230 encapsulated by molding compound 211. In one aspect of this disclosure, die 230 is... Figure 1 The SoC includes, for example, an RF package with stacked input / output (I / O) dies 222 and 224. As indicated by arrow 208, heat is dissipated upwards (208-1) and downwards (208-2) from the active devices in the 3D chip stack 220. Figure 2 As shown, the primary heat flow path is indicated by the downward arrow 208-2, while the secondary heat flow path is indicated by the upward arrow 208-1.

[0032] Figure 3 The illustration shows an incorporation of a wireless device 300 according to one aspect of this disclosure. Figure 2 A cross-sectional view of the stacked IC package 200. As described above, the wireless device 300 may include, but is not limited to, smartphones, tablets, handheld devices, or other form factor devices configured for 5G NR communication. Typically, the stacked IC package 200 is placed within a phone case 304 including a display 306. In this configuration, a thin-film heat sink (TF-HS) layer (not shown) is integrated into the stacked IC package 200. As indicated by arrow 308, heat is dissipated upwards and downwards from the active devices in the 3D chip stack 220. That is, heat is dissipated upwards (e.g., 308-1) and downwards (e.g., 308-2) from the active devices within the 3D chip stack 220. In this configuration, the TF-HS layer provides an upward heat flow path indicated by arrow 308-1 to complement the downward heat flow path indicated by arrow 308-2.

[0033] Various aspects of the present invention are directed to, for example, Figure 4-6 The TF-HS layer is shown on an integrated passive device in an RF package. Although described with reference to an RF package, it should be understood that the TF-HS layer can be incorporated into any chip package in which improved thermal distribution is desired.

[0034] Figure 4 This is a cross-sectional view of an integrated circuit (IC) package 400 having a thin-film heat sink (TF-HS) layer according to various aspects of the present disclosure. In this configuration, the IC package 400 includes a passive substrate 402 (e.g., silicon, glass, alumina, or other similar substrate material). The IC package 400 also includes a first TF-HS layer 410 (e.g., aluminum nitride (AlN), silicon nitride (SiNx), chemical vapor deposition (CVD diamond or silicon carbide (SiC))) on the surface of the passive substrate 402. The IC package 400 further includes a first integrated passive device (IPD) 420 in a first back-to-the-end (BEOL) metallization layer M1 (e.g., copper (Cu), aluminum, or other similar conductive material) on the passive substrate 402. According to various aspects of the present disclosure, the IC package 400 may be a high-power active die, such as a server die, a radio frequency (RF) die, a mobile station modem, or other similar high-power amplifier active device.

[0035] The design of the passive substrate 402 is typically optimized for downward heat dissipation as shown in the conventional heat dissipation path 406, which increases the junction temperature and leads to performance degradation. As described above, the passive substrate 402 may be made of a material selected from silicon, glass, alumina, and alumina ceramic. According to aspects of this disclosure, the placement of the TF-HS layer on the surface of the passive substrate 402 and within the BEOL layer on the passive substrate 402 creates heat dissipation paths 408. The TF-HS layer may be made of a material selected from aluminum nitride (AlN), silicon nitride (SiNx), chemical vapor deposition (CVD diamond), and silicon carbide (SiC) to realize heat dissipation paths 408. These heat dissipation paths 408 are in the opposite direction to the conventional heat dissipation path 406.

[0036] In this configuration, the first IPD 420 is formed by a metal-insulator-metal (MIM) capacitor on the surface of a passive substrate 402. The first IPD 420 may include a first BEOL metallization layer M1 as a first terminal, a dielectric layer on the metallization layer M1 (e.g., silicon nitride (SiNx), tantalum oxide (Ta2O5), etc.), and a thick metal (TM) on a dielectric layer 422 as a second terminal. In this example, the metallization layer M1 is fixed to a first TF-HS layer 410 and is located within a first interlayer dielectric (ILD) layer (ILD-1) on the surface of the first TF-HS layer 410. Furthermore, a second BEOL metallization layer M2 is coupled to a second terminal of the first IPD 420. The second metallization layer M2 is located within a second ILD layer (ILD-2) on the first ILD layer (ILD-1).

[0037] like Figure 4 As further shown, the IC package 400 includes a second IPD 440 formed by a metallized wiring layer. In this configuration, the second IPD 440 is an inductor including a third BEOL metallization layer M3 stacked on the second metallization layer 430 through a via V2. In aspects of this disclosure, a second TF-HS layer 450 is coated on (or beneath) the heated inductor element of the second IPD 440. In this configuration, the second TF-HS layer 450 is coated on the third BEOL metallization layer M3, which is coupled to a package ball 480 (e.g., a wafer-level process (WLP) ball) via a via pad (VP). The second TF-HS layer 450 is on the sidewalls and a portion of the surface of the metallization layer M3, and on the sidewalls of the via pad VP. The via pad VP is on a metallization stack 460, which includes a metallization layer M3 on a second metallization via V2, a second metallization layer M2 on a first metallization via V1, and a first metallization layer M1.

[0038] The first TF-HS layer 410 and the second TF-HS layer 450 can significantly reduce the temperature generated in the integrated inductor-capacitor (LC) passive devices of the IC package 400. The first TF-HS layer 410 and the second TF-HS layer 450 provide a thermal mitigation structure to enable the formation of a first IPD 420 and a second IPD 440 on various substrate materials (e.g., silicon, glass, alumina, or other similar substrate materials). Although the first IPD 420 and the second IPD 440 are shown on different layers of the IC package 400, it should be understood that the first IPD 420 and the second IPD 440 can be formed in the same interlayer dielectric (ILD) layer or in different ILD layers, such as... Figure 4 As shown. The heat dissipation structure of the IC package 400 can be further improved, such as... Figure 5 As shown

[0039] Figure 5 This is a cross-sectional view of an integrated circuit (IC) package 500 having a thin-film heat sink (TF-HS) layer according to various aspects of the present disclosure. In this configuration, the IC package 500 also includes a passive substrate 402 having a first TF-HS layer 410 on its surface. The IC package 500 further includes a first IPD 420 having a first metallization layer M1 serving as a metal-insulator-metal (MIM) capacitor plate. According to various aspects of the present disclosure, the IC package 500 may be a high-power active die, such as a server die, a radio frequency (RF) die, a mobile station modem, or other similar high-power active device. The IC package 500 further includes a third TF-HS layer 470 between a first interlayer dielectric (ILD) layer (ILD-1) and a second ILD layer (ILD-2). The third TF-HS layer 470 on the surface of the second ILD layer (ILD-2) improves... Figure 4 The heat dissipation path 408 is shown.

[0040] The first ILD layer (ILD-1), the second ILD layer (ILD-2), and the third ILD layer (ILD-3) can be made of a low thermal conductivity ILD material. For example, the low thermal conductivity ILD material can be a layer of polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), or other similar low thermal conductivity ILD materials. In operation, due to the low thermal conductivity ILD material, heat may remain trapped by the ILD layers (e.g., ILD-1, ILD-2, and ILD-3) of the IC package 500. In various aspects of this disclosure, the second TF-HS layer 450 and the third TF-HS layer 470 improve the dissipation of heat trapped by the ILD layers (e.g., ILD-1, ILD-2, and ILD-3) of the IC package 500.

[0041] like Figure 5As further shown, the IC package 500 includes an inductor in a second IPD 440, which is formed by a third metallization layer M3 stacked on a second metallization layer 430 through a via V2. A second TF-HS layer 450 is also coated on the heating inductor element of the second IPD 440. In this configuration, the second TF-HS layer 450 is coated on the third metallization layer M3 coupled to the package ball 480 via a via pad VP. The via pad VP is also on the metallization stack 460.

[0042] Figure 6 It is based on all aspects of this disclosure, including Figure 5 A cross-sectional view of an radio frequency (RF) chip 600 with an IC package 500 having a thin-film heat sink (TF-HS) layer. In this configuration, the IC package 500 is encapsulated in a molding compound 404 (MC) (including a molding compound underfill 405) between the IC package 500 and a laminated substrate 490 to form the RF chip 600. The molding compound 404 may be a filled epoxy resin (e.g., G311Q-L) deposited on the surfaces of the laminated substrate 490 and the IC package 500, wherein the molding compound underfill 405 is between package balls 480 that are coupled to pads 492 of the IC package 500 to the laminated substrate 490. Figure 6 As shown, the terminal conductive structure provided by the first TF-HS layer 410, the second TF-HS layer 450, and the third TF-HS layer 470 improves the dissipation of captured heat. For example, the heat generated by the molding compound 404, the passive substrate 402, the interlayer dielectric (ILD) layers (e.g., ILD-1, ILD-2, and ILD-3), and the molding compound bottom filler 405 is dissipated through the thermally conductive structure of the RF chip 600.

[0043] Figure 7 This is a process flow diagram illustrating a method for manufacturing a thermal mitigation structure in a semiconductor package according to one aspect of this disclosure. Method 700 begins at block 702, wherein a first integrated passive device (IPD) is formed in a first interlayer dielectric (ILD) layer on a passive substrate. For example, as... Figure 4 As shown, the first IPD 420 is composed of a metal-insulator-metal (MIM) capacitor on the surface of a passive substrate 402. The first IPD 420 includes a metallization layer M1 as a first termination, a dielectric layer 422 on the metallization layer M1, and a thick metal TM on the dielectric layer 422 as a second termination. In block 704, a second ILD layer is deposited on the first ILD layer. For example, as... Figure 4 As shown, the second ILD layer (ILD-2) is deposited on the first ILD layer (ILD-1).

[0044] In box 706, a second IPD is formed in a third ILD layer (ILD-3) above the second ILD layer (ILD-2). For example, as Figure 4 As shown, the IC package 400 includes a second IPD 440 formed by a metallized wiring layer. In this configuration, the second IPD 440 is an inductor, including a third back-to-the-line (BEOL) metallization layer M3 stacked on the second metallization layer 430 via a via V2. In block 708, a thin-film heat sink (TF-HS) layer is deposited on the inductor element of the second IPD. For example, in Figure 4 In this configuration, the second TF-HS layer 450 is coated on (or beneath) the heated inductor element of the second IPD 440. The second TF-HS layer 450 is coated on the third BEOL metallization layer M3, which is coupled to the package ball 480 via the through-hole pad VP. Method 700 may further include depositing the first TF-HS layer on a passive substrate. Method 700 may further include depositing the second TF-HS layer on the metallization wiring layers of the first ILD layer and the second ILD layer, as shown below. Figure 4 As shown.

[0045] This disclosure relates to an advanced integrated passive device (IPD) having a thin-film heat sink (TF-HS) layer to provide a thermal mitigation structure for semiconductor packages. This thermal mitigation structure is proposed to improve thermal performance, thereby increasing the power handling of the IPD for use as a broadband filter deployed in the transmit (TX) path of a wireless communication device. In one configuration, the TF-HS layer (e.g., aluminum nitride (AlN), silicon nitride (SiNx), chemical vapor deposition (CVD diamond or silicon carbide (SiC)), etc.) is deposited on a heated inductor thick metal (TM) of the integrated passive inductor. Furthermore, an inter-layer dielectric (ILD) layer (e.g., Figure 4-6 Between ILD-1 and ILD-2) and between the second and third ILD layers (e.g., Figure 4-6 A thermally conductive insulating layer (AlN, SiNx, CVD diamond, or SiC) between ILD-2 and ILD-3 can be effectively coated on the thermoinductor on the upper metallization layer (e.g., M3) of the WLP ball connected to the semiconductor package.

[0046] According to various aspects of this disclosure, TF-HS materials (e.g., AlN, SiC, CVD diamond, etc.) possess desired thermal conductivity and desired electrical insulation properties (e.g., low RF loss). The use of aluminum nitride (AlN) has potential advantages for the TF-HS layer of the thermally mitigating structure due to its lower processing temperature. In one configuration, physical vapor deposition (PVD) of an aluminum nitride coating on the surface of an ILD layer (e.g., polyimide (PI)) may involve plasma etching (e.g., argon (Ar)) of the surface to improve adhesion. In another configuration, plasma-enhanced chemical vapor deposition (PECVD) of silicon nitride (SiNx) is a potential candidate for coating on a heated inductive thick metal (TM) layer of an IPD.

[0047] According to another aspect of this disclosure, an integrated circuit (IC) semiconductor package is described. In one configuration, the IC semiconductor package has components for heat dissipation from the inductive element of a second IPD. In one configuration, the heat dissipation component may be a second TF-HS layer 450, such as... Figure 4-6 As shown. On the other hand, the aforementioned component can be any structure or any material configured to perform the functions listed above.

[0048] Figure 8 This is a block diagram illustrating an exemplary wireless communication system 800 in which one aspect of this disclosure may be advantageously employed. For illustrative purposes, Figure 8 Three remote units 820, 830, and 850, and two base stations 840 are shown. It should be understood that wireless communication systems can have more remote units and base stations. Remote units 820, 830, and 850 include IC devices 825A, 825B, and 825C, which include the disclosed TF-HS layer. It should be understood that other devices may also include the disclosed TF-HS layer, such as base stations, switching equipment, and network equipment. Figure 8 The forward link signal 880 from base station 840 to remote units 820, 830 and 850 is shown, as well as the reverse link signal 890 from remote units 820, 830 and 850 to base station 840.

[0049] exist Figure 8 In this design, remote unit 820 is shown as a mobile phone, remote unit 830 is shown as a portable computer, and remote unit 850 is shown as a fixed-location remote unit in a wireless local loop system. For example, a remote unit can be a mobile phone, a handheld personal communication system (PCS) unit, a portable data unit such as a personal data assistant, a GPS-enabled device, a navigation device, a set-top box, a music player, a video player, an entertainment unit, a fixed-location data unit such as a meter reading device, or other devices that store or retrieve data or computer instructions, or combinations thereof. Figure 8 Remote units according to aspects of this disclosure are illustrated, but this disclosure is not limited to the units exemplified in these illustrations. Aspects of this disclosure can be applied to many devices that include the disclosed TF-HS layer.

[0050] Figure 9 This is a block diagram illustrating a design workstation for the circuit, layout, and logic design of semiconductor components (such as capacitors disclosed above). Design workstation 900 includes a hard disk 901 containing operating system software, support files, and design software such as Cadence or OrCAD. Design workstation 900 also includes a display 902 to facilitate the design of circuitry 910 or RF component 912, including a TF-HS layer. A storage medium 904 is provided for tangibly storing the design of circuitry 910 or RF component 912 (e.g., including a thin-film heatsink layer). The design of circuitry 910 or RF component 912 can be stored on storage medium 904 in a file format such as GDSII or GERBER. Storage medium 904 can be a CD-ROM, DVD, hard disk, flash memory, or other suitable device. Furthermore, design workstation 900 includes a drive device 903 for accepting input from storage medium 904 or writing output to storage medium 904.

[0051] The data recorded on storage medium 904 can specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial writing tools such as electron beam lithography. This data can further include logic verification data associated with logic simulation, such as timing diagrams or network circuits. Providing data on storage medium 904 facilitates the design of circuit 910 or RF component 912 by reducing the number of processes used to design semiconductor wafers.

[0052] For firmware and / or software implementations, the methodology can be implemented using modules (e.g., programs, functions, etc.) that perform the described functions. Machine-readable media that tangibly contain instructions can be used to implement the described methodology. For example, software code can be stored in memory and executed by a processor unit. Memory can be implemented within or outside the processor unit. As used, the term "memory" means long-term, short-term, volatile, non-volatile, or other types of memory, and is not limited to a particular type or number of memories, or the type of medium on which memory is stored.

[0053] If implemented as firmware and / or software, functionality may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoded with data structures and computer-readable media encoded with computer programs. Computer-readable media includes physical computer storage media. Storage media can be any available medium accessible to a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or other media that can be used to store the desired program code in the form of instructions or data structures and are accessible to a computer. Disks and discs used include compressed optical discs (CDs), laser discs, optical discs, digital versatile optical discs (DVDs), floppy disks, and Blu-ray discs. ® Optical discs, where magnetic disks typically reproduce data magnetically, and optical discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0054] In addition to being stored on a computer-readable medium, instructions and / or data may be provided as signals on a transmission medium included in a communication apparatus. For example, a communication apparatus may include a transceiver having signals indicating instructions and data. The instructions and data are configured to cause one or more processors to perform the functions outlined in the claims.

[0055] Although this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and modifications can be made without departing from the technology of this disclosure as defined in the appended claims. For example, relational terms such as "above" and "below" are used relative to a substrate or electronic device. Of course, if the substrate or electronic device is inverted, above becomes below, and vice versa. Furthermore, if lateral orientation is used, above and below may refer to the sides of the substrate or electronic device. Moreover, the scope of this application is not intended to be limited to the specific configurations of the processes, machines, manufactures, compositions of matter, components, methods, and steps described in the specification. As will be readily understood by one of ordinary skill in the art from this disclosure, processes, machines, manufactures, compositions of matter, components, methods, or steps that are existing or will be developed thereafter can be utilized to perform substantially the same function or achieve substantially the same result as the corresponding configurations described. Therefore, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, components, methods, or steps within their scope.

[0056] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithm steps described in connection with this disclosure can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented in hardware or software depends on the specific application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application; however, such implementation decisions should not be construed as departing from the scope of this disclosure.

[0057] The various illustrative logic blocks, modules, and circuits described in this disclosure may be implemented or performed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the described functions. The general-purpose processor may be a microprocessor, but alternatively, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration.

[0058] The steps of the methods or algorithms described in this disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of both. The software module may reside in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integrated into the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal. Alternatively, the processor and storage medium may reside as discrete components in the user terminal.

[0059] The foregoing description of this disclosure is intended to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the described examples and designs, but is accorded the widest scope consistent with the disclosed principles and novel features.

Claims

1. A semiconductor package, comprising: Passive substrate; The first integrated passive device (IPD) is located in the first interlayer dielectric (ILD) layer on the passive substrate; The second interlayer dielectric (ILD) layer is on top of the first interlayer dielectric (ILD) layer; The second integrated passive device (IPD) is located in a third inter-layer dielectric (ILD) layer on top of the second inter-layer dielectric (ILD) layer; as well as The heat mitigation structure is located on the inductor element of the second integrated passive device (IPD). The semiconductor package is encapsulated by a molding compound; The package substrate has pads coupled to the package balls on the semiconductor package; as well as Bottom filler, between the package balls and between the package substrate and the semiconductor package.

2. The semiconductor package of claim 1, wherein the thermal mitigation structure comprises a thin-film heat sink (TF-HS) layer on the second interlayer dielectric (ILD) layer and on the metallization wiring layer of the second integrated passive device (IPD).

3. The semiconductor package of claim 1, wherein the thermal mitigation structure includes a thin-film heat sink (TF-HS) layer, the thin-film heat sink (TF-HS) layer being on the first interlayer dielectric (ILD) layer and on a metallized wiring layer in the second interlayer dielectric (ILD) layer.

4. The semiconductor package of claim 1, wherein the thermal mitigation structure comprises a thin-film heat sink (TF-HS) layer on the passive substrate.

5. The semiconductor package of claim 1, wherein the semiconductor package includes a radio frequency (RF) die, the RF die being integrated into an RF chip package.

6. The semiconductor package of claim 1, wherein the first integrated passive device (IPD) comprises a metal-insulator-metal (MIM) capacitor, and the second integrated passive device (IPD) comprises an inductor.

7. The semiconductor package of claim 1, wherein the thermal relief structure comprises a thin-film heat sink (TF-HS) layer made of a material selected from aluminum nitride (AlN), silicon nitride (SiNx), chemical vapor deposition (CVD) diamond, and silicon carbide (SiC).

8. The semiconductor package of claim 1, wherein the passive substrate comprises a material selected from silicon, glass, alumina, and alumina ceramic.

9. A semiconductor package, comprising: Passive substrate; The first integrated passive device (IPD) is located in the first interlayer dielectric (ILD) layer on the passive substrate; The second interlayer dielectric (ILD) layer is on top of the first interlayer dielectric (ILD) layer; The second integrated passive device (IPD) is located in a third inter-layer dielectric (ILD) layer on top of the second inter-layer dielectric (ILD) layer; and The heat mitigation structure is located on the inductor element of the second integrated passive device (IPD). A first thin-film heat sink (TF-HS) layer is placed on the passive substrate; Metallization stacking is applied to the first thin-film heat sink (TF-HS) layer. The encapsulation ball is coupled to the metallization layer of the metallization stack via through-hole pads; as well as The second thin-film heat sink (TF-HS) layer is located on the sidewalls and part of the surface of the metallization layer, and on the sidewalls of the through-hole pads.

10. A method for manufacturing a thermal relief structure in a semiconductor package, the method comprising: A first integrated passive device (IPD) is formed in the first interlayer dielectric (ILD) layer on a passive substrate; A second interlayer dielectric (ILD) layer is deposited on the first interlayer dielectric (ILD) layer; A second integrated passive device (IPD) is formed in a third inter-layer dielectric (ILD) layer on top of the second inter-layer dielectric (ILD) layer. A thin-film heat sink (TF-HS) layer is deposited on the inductor element of the second integrated passive device (IPD); Deposit molding compounds to encapsulate the semiconductor package; A package substrate with pads is attached to a package ball on the semiconductor package; as well as An underfill is deposited between the packaging balls and between the package substrate and the semiconductor package.

11. The method of claim 10, further comprising: A thin-film heat sink (TF-HS) layer is deposited on the second interlayer dielectric (ILD) layer; as well as A thin-film heat sink (TF-HS) layer is deposited on the metallized wiring layer of the second integrated passive device (IPD).

12. The method of claim 10, further comprising: A first thin-film heat sink (TF-HS) layer is deposited on the passive substrate.

13. The method of claim 12, further comprising: A second thin-film heat sink (TF-HS) layer is deposited on the first interlayer dielectric (ILD) layer and on the metallized wiring layer in the second interlayer dielectric (ILD) layer.

14. The method of claim 10, further comprising: A first thin-film heat sink (TF-HS) layer is deposited on the passive substrate; A metallization stack is formed on the first thin-film heat sink (TF-HS) layer; Forming encapsulation balls that are coupled to the metallization layer of the metallization stack via through-hole pads; as well as A second thin-film heat sink (TF-HS) layer is deposited on the sidewalls and partial surfaces of the metallization layer, and on the sidewalls of the through-hole pads.

15. A semiconductor package, comprising: Passive substrate; The first integrated passive device (IPD) is located in the first interlayer dielectric (ILD) layer on the passive substrate; The second interlayer dielectric (ILD) layer is on top of the first interlayer dielectric (ILD) layer; The second integrated passive device (IPD) is located in a third inter-layer dielectric (ILD) layer on top of the second inter-layer dielectric (ILD) layer; as well as Components for dissipating heat from the inductive element of the second integrated passive device (IPD). The semiconductor package is encapsulated by a molding compound; The package substrate has pads coupled to the package balls on the semiconductor package; as well as Bottom filler, between the package balls and between the package substrate and the semiconductor package.

16. The semiconductor package of claim 15, wherein the semiconductor package includes a radio frequency (RF) die integrated into an RF chip package.

17. The semiconductor package of claim 15, wherein the first integrated passive device (IPD) comprises a metal-insulator-metal (MIM) capacitor, and the second integrated passive device (IPD) comprises an inductor.

18. The semiconductor package of claim 15, wherein the passive substrate comprises a material selected from silicon, glass, alumina, and alumina ceramic.

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