Comparator circuit and drive circuit

Abstract

The comparator circuit (30) of this embodiment includes a comparator element (31) that outputs a match signal indicating whether the value of a first input signal matches the value of a second input signal, an FF circuit (33) that holds the data of a data input terminal (D) based on a comparator clock signal (CMP_CLOCK) and outputs an enable signal (EN) for stopping the operation of the comparator element (31), and an internal signal generation circuit that outputs an internal signal (Z1) to the data input terminal (D) based on the match signal (Z) and an output signal from the FF circuit (33).

Description

Technical Field

[0001] This disclosure relates to comparator circuits and driver circuits. Background Technology

[0002] Patent Document 1 discloses a horizontal driving circuit for a liquid crystal display device. In Patent Document 1... Figure 2 In this circuit, the comparator compares the counter output with the pixel values ​​of the digital image data. The comparator outputs a consistent pulse indicating that the two values ​​match to the D-type flip-flop circuit. Furthermore, the positive and negative polarity switches switch in conjunction with the output of the D-type flip-flop.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent document 1: Japanese Patent Application Publication No. 2013-105166. Summary of the Invention

[0006] In Patent Document 1, after the counter output matches the digital image data, the comparator also performs a comparison operation between the counter output and the digital image data. That is, after the comparator outputs a matching pulse, a switching operation is also performed. Therefore, there is a problem of increased power consumption in the comparator.

[0007] This disclosure was made in view of the above-mentioned problems, and its purpose is to provide a low-power comparator circuit and a driver circuit.

[0008] The comparator circuit of this embodiment includes: a comparator element that outputs a consistency signal indicating whether the value of a first input signal is consistent with the value of a second input signal; a trigger circuit that holds the data at the data input terminal according to a comparator clock signal and outputs an enable signal to stop the operation of the comparator element; and an internal signal generation circuit that outputs an internal signal to the data input terminal according to the consistency signal and the output signal from the trigger circuit.

[0009] According to the present invention, low-power comparator circuits and driver circuits can be provided. Attached Figure Description

[0010] Figure 1 This is a circuit diagram showing the configuration of a drive circuit that uses a comparator circuit.

[0011] Figure 2 This is a circuit diagram showing the configuration of a comparator element.

[0012] Figure 3 This is a circuit diagram showing the polarity of the enable signals EN1 and EN1B.

[0013] Figure 4This is the circuit diagram of NOR circuit 111.

[0014] Figure 5 This is the circuit diagram of NAND (NAND) circuit 112.

[0015] Figure 6 This is a circuit diagram showing the configuration of the comparator circuit for a comparison example.

[0016] Figure 7 This is a diagram showing the configuration of a liquid crystal display device that uses a driving circuit. Detailed Implementation

[0017] Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments. In addition, for the sake of clarity, the following description and drawings have been appropriately simplified.

[0018] The comparator circuit of this embodiment and the drive circuit using the comparator circuit will be described below. Figure 1 This is a circuit diagram showing a drive circuit 100 including a comparator circuit 30. Specifically, Figure 1 The driving circuit shown is the horizontal driving circuit for one column of pixels in a liquid crystal display device.

[0019] The driving circuit 100 includes a latch circuit 10, a counter 20, and a comparator circuit 30. Here, 10 bits of image data DATA are input to the driving circuit 100. That is, one pixel is represented using 1024 gray levels (=10 bits). Of course, the number of bits in the image data is not particularly limited.

[0020] A latch signal LATCH and image data DATA are input to latch circuit 10. Latch circuit 10 latches 10 bits of image data DATA in response to the latch signal LATCH. Latch circuit 10 outputs the latched image data DATA in parallel to comparator circuit 30. The image data DATA output from latch circuit 10 is set as latch output A. Latch output A is 10 bits of parallel data.

[0021] The counter clock signal CNT_CLOCK and the counter reset signal CNT_RST are input to counter 20. Counter 20 performs counting operations synchronously with the counter clock signal CNT_CLOCK. For example, counter 20 increments the count value at the clock frequency of the counter clock signal CNT_CLOCK. Counter 20 outputs the count value based on the counting operation to comparator circuit 30.

[0022] Additionally, counter 20 resets its count value to its initial value in response to the counter reset signal CNT_RST. Furthermore, the counter reset signal CNT_RST corresponds to the horizontal scan frequency. The output of counter 20 is 10 bits. Therefore, counter 20 increments the count value from 0 to 1023. Counter 20 outputs the 10-bit count value to comparator circuit 30. The count value output from counter 20 is set as counter output B. Counter output B is 10 bits of parallel data.

[0023] The comparator circuit 30 includes a comparator element 31, an FF (flip-flop) circuit 33, and an internal signal generation circuit 36. The internal signal generation circuit 36 ​​includes an inverter 34 and an OR (or) circuit 35.

[0024] Comparator element 31 compares latch output A and counter output B. Comparator element 31 generates a consistency signal Z indicating that latch output A and counter output B are identical. Comparator element 31 outputs the consistency signal Z to OR circuit 35. Latch output A and counter output B are both 10-bit parallel data. Comparator element 31 compares each bit of latch output A and counter output B. Comparator element 31 determines that latch output A and counter output B are identical when all bits of latch output A and counter output B are identical.

[0025] When the latch output A and the counter output B are the same, comparator element 31 asserts the consensus signal Z. When the latch output A and the counter output B are different, comparator element 31 deassers the consensus signal Z. Therefore, the consensus signal Z becomes a positive pulse signal that is high when the latch output A and the counter output B are the same.

[0026] The internal signal generation circuit 36 ​​generates an internal signal Z1 based on the output signal OUT from the FF circuit 33 and the consistency signal Z. The internal signal generation circuit 36 ​​then outputs the internal signal Z1 to the FF circuit 33.

[0027] The FF circuit 33 is a D-type flip-flop circuit. The FF circuit 33 includes a data input terminal D, a clock input terminal CK, a non-inverting output terminal Q, and an inverting output terminal QB. The output of the internal signal generation circuit 36 ​​is connected to the data input terminal D. The internal signal Z1 from the OR circuit 35 is input to the data input terminal D. The external comparator clock signal CMP_CLOCK is input to the clock input terminal CK. In response to the comparator clock signal CMP_CLOCK, the FF circuit 33 samples and holds the data value at the data input terminal D. The FF circuit 33 holds a 1-bit value.

[0028] The in-phase output signal corresponding to the data value held by the FF circuit 33 is output from the non-inverting output terminal Q. The FF circuit 33 outputs an inverted output signal, which is the result of inverting the in-phase output signal, from the inverting output terminal QB. The inverted output signal becomes the output signal OUT from the comparator circuit 30. When the input data held by the FF circuit 33 is 1, the in-phase output signal is high and the inverted output signal is low. When the input data held by the FF circuit 33 is 0, the in-phase output signal is low and the inverted output signal is high.

[0029] The output signal OUT of FF circuit 33 is input to FF circuit 33 via inverter 34. Inverter 34 inverts the output signal OUT from FF circuit 33 and outputs it to OR circuit 35. OR circuit 35 performs a logical OR operation between the output from inverter 34 and the consensus signal Z as an internal signal Z1. OR circuit 35 outputs the internal signal Z1 to the data input terminal D of FF circuit 33.

[0030] A comparator reset signal CMP_RST is input to the FF circuit 33. The FF circuit 33 resets the held data in response to the comparator reset signal CMP_RST. Therefore, the data value held by the FF circuit 33 becomes 0. When the FF circuit 33 is reset by the comparator reset signal CMP_RST, the inverting output signal becomes high, and the non-inverting output signal becomes low.

[0031] After being reset by the comparator reset signal CMP_RST, the FF circuit 33 samples the value of the internal signal Z1 in response to the comparator clock signal CMP_CLOCK. Therefore, the output signal OUT from the inverting output terminal QB becomes a negative step signal when the internal signal Z1 is high.

[0032] Furthermore, the output signal OUT from the inverting output terminal of the FF circuit 33 becomes the enable signal EN controlling the comparator element 31. That is, the output signal OUT is input to the comparator element 31 as the enable signal EN. The comparator element 31 stops operating according to the enable signal EN. Specifically, when the enable signal is high, the comparator element 31 performs the comparison as usual; when the enable signal is low, the comparator element 31 stops the comparison. When the enable signal EN is high, the comparator element 31 compares the latched output A and the counter output B. When the enable signal EN is low, the comparator element 31 does not compare the latched output A and the counter output B, and the coincidence signal Z is fixed at a low level.

[0033] In response to the output signal OUT from the FF circuit 33, the comparator element 31 stops operating. That is, the comparator element 31 stops by the output signal OUT, which is a negative step signal. Specifically, the comparator element 31 stops operating after it outputs a positive pulse signal as a coincidence signal Z. This prevents switching operations in the comparator element 31, thus reducing power consumption.

[0034] Figure 2 This is a circuit diagram showing an example of the configuration of comparator element 31. As described above, comparator element 31 compares 10 bits of data. In latch output A and counter output B, the data of the first bit is set as latch output A[1] and counter output B[1], respectively, and the data of the tenth bit is set as latch output A

[10] and counter output B

[10] .

[0035] Comparator element 31 includes multiple 1-bit comparators 110, a NAND (NAND) circuit 150, and an inverter 160. Comparator element 31 includes ten 1-bit comparators 110 for comparing 10 bits of data. Furthermore, the number of 1-bit comparators 110 corresponds to the number of bits in the latched output A, i.e., the number of grayscale bits. The circuit configuration of the 1-bit comparators 110 is identical. Figure 2 In the text, the 1-bit comparator 110 is omitted for the data from the 2nd to the 9th bit. In the following description, the 1-bit comparator 110 for the comparison latch output A[1] and the counter output B[1] will be mainly described.

[0036] The 1-bit comparator 110 includes a NOR (or NOT) circuit 111, a NAND circuit 112, an inverter 113, and a NAND circuit 114. The latch output A[1] of the first bit and the counter output B[1] are input to the NOR circuit 111. The NOR circuit 111 outputs the NOR (or NOT) values ​​of the latch output A[1] and the counter output B[1] to the inverter 113. The inverter 113 inverts the output of the NOR circuit 111 and outputs it to the NAND circuit 114.

[0037] The latch output A[1] of the first bit and the counter output B[1] are input to NAND circuit 112. NAND circuit 112 outputs the NAND (AND) of latch output A[1] and counter output B[1] to NAND circuit 114. The output of NAND circuit 112 and the output of inverter 113 are input to NAND circuit 114. NAND circuit 114 outputs the NAND (AND) of the output of NAND circuit 112 and the output of inverter 113 as the output signal OUT[1] to NAND circuit 150. When the values ​​of latch output A[1] and counter output B[1] are the same, the output of NAND circuit 150 becomes high.

[0038] As described above, ten 1-bit comparators 110 are provided in comparator element 31. The outputs of the ten 1-bit comparators 110 are input to NAND circuit 150. For example, the 10th 1-bit comparator 110 outputs the NAND signal of NAND circuit 114 as an output signal OUT

[10] to NAND circuit 150.

[0039] NAND circuit 150 outputs the NAND signal from 10-bit output signals OUT[1] to OUT

[10] to inverter 160 via NAND. Inverter 160 inverts the output of NAND circuit 150. The signal output from inverter 160 becomes the coherence signal Z. When output signals OUT[1] to OUT

[10] are high, coherence signal Z is high. Coherence signal Z is active when each bit value of latched outputs A[1] to A

[10] is the same as each bit value of counter outputs B[1] to B

[10] . Coherence signal Z is inactive when at least one bit value of latched outputs A[1] to A

[10] is different from that of counter outputs B[1] to B

[10] .

[0040] Furthermore, enable signals EN1 and EN1B are input to the NOR circuit 111 and the NAND circuit 112. Enable signals EN1 and EN1B are based on... Figure 1 It is generated by the enable signal EN shown. Specifically, as... Figure 3 As shown, inverters 81 and 82 output enable signals EN1B and EN1 with different polarities, respectively. Enable signal EN1B is a signal that inverts enable signal EN once. Enable signal EN1 is a signal that inverts enable signal EN twice. Therefore, enable signal EN1B is the signal after inverting enable signal EN1.

[0041] When the enable signal EN1 is high, the NOR circuit 111 and the NAND circuit 112 operate. When the enable signal EN1 is low, the NOR circuit 111 and the NAND circuit 112 stop. Therefore, when the enable signal EN1 is low, the comparator element 31 stops operating.

[0042] Figure 4 This diagram shows the circuit configuration of NOR circuit 111. NOR circuit 111 is a CMOS (Complementary Metal-Oxide-Semiconductor) circuit, including seven transistors Tr1 to Tr7. Transistors Tr1 to Tr3 are p-type MOS transistors. Transistors Tr4 to Tr7 are n-type MOS transistors.

[0043] Transistors Tr1 to Tr4 are connected in series. Specifically, transistors Tr1, Tr2, Tr3, and Tr4 are arranged sequentially from the power supply potential side to the ground side. Transistors Tr5 and Tr6 are connected in parallel between transistor Tr4 and ground. The output signal C is output from the output node between transistors Tr3 and Tr4[1]. In addition, transistor Tr7 is arranged between the output node between transistors Tr3 and Tr4 and ground.

[0044] The latch output A[1] is input to the gates of transistors Tr1 and Tr5. The counter output B[1] is input to the gates of transistors Tr2 and Tr6. The enable signal EN1B is input to the gates of transistors Tr3 and Tr7. The enable signal EN1 is input to the gate of transistor Tr4.

[0045] Therefore, when the enable signal EN1 is high, the NOR circuit 111 operates normally. That is, the output signal C[1] is the "OR NOT" of the latch output A[1] and the counter output B[1]. The output signal C[1] is input to... Figure 2 Inverter 113.

[0046] When the enable signal EN1 is low, transistors Tr3 and Tr4 are turned off, and transistor Tr7 is turned on. The NOR circuit 111 does not function, and the output signal C[1] becomes low. In the NOR circuit 111, unnecessary switching operations can be prevented. Therefore, the current flowing from the power supply potential to ground can be reduced.

[0047] Figure 5 This is a diagram showing the circuit configuration of NAND circuit 112. NAND circuit 112 is a CMOS circuit, including seven transistors Tr11 to Tr17. Transistors Tr11 to Tr14 are p-type MOS transistors. Transistors Tr15 to Tr17 are n-type MOS transistors.

[0048] Transistors Tr14 to Tr17 are connected in series. Specifically, transistors Tr17, Tr16, Tr15, and Tr14 are arranged sequentially from ground to the power supply potential. Transistors Tr11 and Tr12 are connected in parallel between transistor Tr14 and the power supply potential. The output signal D is output from the output node between transistors Tr14 and Tr15[1]. In addition, transistor Tr13 is arranged between the output node between transistors Tr14 and Tr15 and the power supply potential.

[0049] Latch output A is input to the gates of transistors Tr12 and Tr16. Counter output B is input to the gates of transistors Tr11 and Tr17. Enable signal EN1 is input to the gates of transistors Tr13 and Tr15. Enable signal EN1B is input to the gate of transistor Tr14.

[0050] Therefore, when the enable signal EN1 is high, the NAND circuit 112 operates normally. The output signal D[1] is the NAND of the latch output A[1] and the counter output B[1]. The output signal D[1] is input to... Figure 2 NAND circuit 114.

[0051] When the enable signal EN1 is low, transistors Tr14 and Tr15 are off, and transistor Tr13 is on. Therefore, NAND circuit 112 does not function, and the output signal D[1] becomes high. Transistors Tr14 and Tr15 are off. In NAND circuit 112, unnecessary switching operations can be prevented. Therefore, the current flowing from the power supply potential to ground can be reduced.

[0052] Thus, the operation of the 1-bit comparator 110 is stopped by the enable signals EN1 and EN1B. When the enable signal EN1 is low, the value of the output signal C[1] becomes "0" and the value of the output signal D[1] becomes "1". That is, regardless of the values ​​of the latch output A[1] and the counter output B[1], the outputs of the NOR circuit 111 and the NAND circuit 112 are fixed.

[0053] When the enable signal EN1 is low Figure 2 The output signal OUT[1] of the NAND circuit 114 shown has a value of "0". The ten 1-bit comparators 110 respectively include... Figure 4 The NOR circuit 111 shown and Figure 5 The NAND circuit 112 is shown. When the enable signal EN1 is low, the consensus signal Z output from the comparator circuit 30 becomes low. Therefore, the consensus signal Z becomes a positive pulse signal that is high when the latch output A and the counter output B are in sync.

[0054] As described above, the output signal OUT from the FF circuit 33 becomes the enable signal EN that stops the operation of the comparator element 31. The comparator circuit 30 has a self-gating function that stops the switching operation based on the enable signal EN generated by the FF circuit 33. This allows the operation of the comparator element 31 to stop at an appropriate timing. The operation stops after the comparator element 31 outputs a positive pulse. This reduces power consumption.

[0055] Furthermore, it is possible to prevent switching operations in comparator element 31. Therefore, noise caused by switching operations can be suppressed, thereby improving reliability.

[0056] Figure 6 A drive circuit with comparator circuit 30 is shown as a comparative example. Furthermore, regarding the basic operation of latch circuit 10, counter 20, and comparator element 31, since... Figure 1 The details are the same, so a detailed explanation is omitted. For example, the output of comparator element 31 represents a coincidence signal Z that indicates the agreement between latch output A and counter output B. The coincidence signal Z is a positive pulse.

[0057] exist Figure 6 In the comparator circuit 30 shown, the output signal from the FF circuit 33 is not used as an enable signal. Therefore, after the latch output A matches the counter output B, the comparator element 31 also performs a comparison. Therefore, the power consumption of the comparator element 31 is... Figure 1 The configuration shown has been increased compared to the previous version.

[0058] In contrast, Figure 1 In the comparator circuit 30 shown, the comparator element 31 stops operating in response to the enable signal EN from the comparator circuit 30. Therefore, the power consumption in the comparator circuit 30 can be reduced.

[0059] By utilizing the comparator circuit 30 and the driving circuit 100 of this embodiment, the power consumption of the liquid crystal display device can be reduced. For example, assuming the driving circuit 100 is applied to a WUXGA LCOS (Liquid Crystal On-Silicon) device at a frame rate of 120Hz, the power consumption of the device can be reduced from 1188mW to 1126mW. That is, a power consumption reduction of 5.3% (=62mW) is possible.

[0060] use Figure 7 The configuration of the liquid crystal display device 200, in which the comparator circuit 30 is applied to the drive circuit, will be described. The liquid crystal display device 200 is an LCOS display. Figure 7 This is a block diagram showing the back panel of an LCOS display.

[0061] The liquid crystal display device 200 includes a pixel display unit 50, a vertical driving circuit 2, and a horizontal driving circuit 3. The horizontal driving circuit 3 has... Figure 1 The driving circuit 100 is shown. Specifically, the horizontal driving circuit 3 has m (where m is an integer greater than or equal to 2) driving circuits 100 corresponding to the number of pixels in one row.

[0062] The pixel display unit 50 is provided with multiple data lines 6, multiple gate lines 8, and multiple pixels 42. The multiple data lines 6 are arranged in parallel with each other. The multiple gate lines 8 are arranged in parallel with each other. The multiple data lines 6 and the multiple gate lines 8 are arranged in an intersecting manner. The gate lines 8 are row scan lines.

[0063] The liquid crystal display device 200 includes multiple sets of data lines 6, arranged in groups of two. The liquid crystal display device 200 uses one set of data lines 6 to drive the pixels 42 inverting mode. Hereinafter, the data line 6 on the positive side of the set of data lines 6 is designated as data line 6a, and the data line 6 on the negative side is designated as data line 6b. Similarly, the switch 1 and video signal lines 5 are designated as switch 1a, switch 1b, and video signal lines 5a and 5b to identify polarity. For polarity inversion, a dual-system set of data lines 6, switch 1, and video signal lines 5 is provided.

[0064] Pixels 42 are arranged at the intersection of data lines 6 and gate lines 8. Pixels 42 are arranged in a matrix (row-column configuration). Each pixel 42 is driven by one set of data lines 6 and one gate line 8. For example, if there are n gate lines 8 and 2m data lines 6, then the pixels 42 are arranged in an n-row × m-column matrix. Furthermore, m and n are integers greater than or equal to 2. Pixels 42 include pixel driving circuitry for driving the liquid crystal, pixel electrodes, etc.

[0065] The vertical drive circuit 2 selects multiple gate lines 8 for vertical driving during each horizontal scan. The vertical drive circuit 2 provides scan signals to the multiple gate lines 8. That is, the vertical drive circuit 2 provides scan signals to sequentially select gate lines 8 from row 1 to row n. Thus, pixels 42 are selected sequentially row by row. All gate lines 8 are selected within one vertical scan period. Video signals can then be written to the pixels 42 in the selected row.

[0066] The horizontal drive circuit 3 drives multiple switches 1 in the horizontal direction during horizontal scanning. This provides video signals to multiple data lines 6. As described above, two data lines 6a and 6b are connected to pixels 42 as a group. Therefore, two data lines 6a and 6b are jointly connected to pixels 42 in one row.

[0067] Data line 6a is connected to video signal line 5a via switch 1a. Data line 6b is connected to video signal line 5b via switch 1b. Video signal line 5a is supplied with the positive side video signal RAMP+. Video signal line 5b is supplied with the negative side video signal RAMP-. Horizontal drive circuit 3 controls switches 1a and 1b.

[0068] Therefore, a positive video signal RAMP+ is provided to one data line 6a of a set of data lines 6a and 6b, and a negative video signal RAMP- is provided to the other data line 6b. The positive video signal RAMP+ becomes a positive voltage relative to the common potential of the common electrode line, and the negative video signal RAMP- becomes a negative voltage relative to the common potential of the common electrode line. The horizontal drive circuit 3 can provide the positive video signal RAMP+ and the negative video signal RAMP- to the pixels 42 of the selected row, respectively. The horizontal drive circuit 3 turns each switch 1 on and off multiple times during the horizontal scan. Therefore, the positive video signal RAMP+ and the negative video signal RAMP- are alternately provided to the pixels 42.

[0069] Specifically, the horizontal drive circuit 3 includes a latch circuit 310, a counter 320, a comparator circuit 330, a shift register 360, and a buffer 370. The latch circuit 310 corresponds to... Figure 1 The latch circuit 10. That is, the latch circuit 310 includes m columns of latch circuits 10. The latch circuit 310 holds the image data DATA of the pixels 42 in the first to m columns.

[0070] Comparator circuit 330 corresponds to Figure 1 The comparator circuit 30. That is, the comparator circuit 330 has m columns of comparator circuits 30. (Source: [Insert Source Here]) Figure 1 The output signal OUT of the comparator circuit 30 shown controls switch 1. Counter 320 corresponds to... Figure 1 Counter 20. Therefore, counter 320 performs a counting action in response to the counter clock signal CNT_CLOCK.

[0071] Shift register 360 sequentially transfers m columns of image data DATA in response to the horizontal clock HCLOCK. After holding the m columns of image data DATA, shift register 360 outputs the data to latch circuit 310. Latch circuit 310 holds the image data DATA of each column in response to the latch signal LATCH.

[0072] like Figure 1 As shown, comparator circuit 330 compares latch output A and counter output B. Comparator circuit 330 controls switches 1a and 1b in pairs. In response to the output signal of comparator circuit 330, switches 1a and 1b open and close in pairs. Initially, since all switches 1 are closed in pairs, no video signal is provided to pixel 42. When the output signal of comparator circuit 330 is active, the corresponding switch 1 opens. Thus, the positive video signal RAMP+ and the negative video signal RAMP- are alternately applied to pixel 42. Liquid crystal display device 200 is able to perform grayscale display corresponding to image data DATA.

[0073] Buffer 370 buffers various signals output from the external controller. Since the pixel display unit 50 has a large number of columns, buffer 370 is used to drive heavier loads. For example, the horizontal clock signal HCLOCK is input to the shift register 360 via buffer 370. Similarly, the latch signal LATCH is input to the latch circuit 310 via buffer 370. The counter output from counter 320 is input to comparator circuit 330 via buffer 370. The comparator clock signal CMP_CLOCK is input to comparator circuit 330 via buffer 370.

[0074] In this embodiment, the comparator circuit 330 includes Figure 1 The comparator circuit 330 is shown. Therefore, the power consumption of the comparator circuit 330 can be reduced. Furthermore, since noise can be suppressed, reliability can be improved.

[0075] The invention described above is based on specific embodiments, but the invention is not limited to the above embodiments, and various modifications can be made without departing from its spirit.

[0076] This application claims priority to Japanese Patent Application No. 2021-87342, filed on May 25, 2021, the entire disclosure of which is incorporated herein by reference.

[0077] Symbol Explanation

[0078] 1. Switch

[0079] 2 Vertical drive circuit

[0080] 3 Horizontal drive circuit

[0081] 6 Data cables

[0082] 8 gate lines

[0083] 42 pixels

[0084] 50-pixel display

[0085] 100 drive circuit

[0086] 10. Latch circuit

[0087] 20 counter

[0088] 30 Comparator Circuit

[0089] 31 Comparator Components

[0090] 33 FF circuit

[0091] 34 Inverters

[0092] 35 OR circuit

[0093] 36 Internal signal generation circuit

[0094] 200 LCD display devices

[0095] 310 Latch Circuit

[0096] 320 counter

[0097] 330 comparator circuit

[0098] 360 Shift Register

[0099] 370 buffer

Claims

1. A comparator circuit, comprising: The comparator element outputs a consistency signal indicating whether the value of the first input signal is the same as the value of the second input signal; A trigger circuit includes a data input terminal, which, based on a comparator clock signal, holds the data at the data input terminal and outputs an enable signal to stop the operation of the comparator element. as well as An internal signal generation circuit generates an internal signal based on the consistency signal and the output signal from the trigger circuit, and outputs the internal signal to the data input terminal. The trigger circuit samples and holds the internal signal of the data input terminal based on the comparator clock signal, and outputs the enable signal to stop the operation of the comparator element when the consistency signal indicates that the first input signal is consistent with the second input signal.

2. The comparator circuit as described in claim 1, wherein, The inverted output signal from the inverted output terminal of the trigger circuit is the enable signal.

3. The comparator circuit as described in claim 2, wherein, The internal signal generation circuit includes: Inverter, input to the inverted output signal; and Or, the circuit outputs a logical OR of the signal from the inverter and the consensus signal.

4. The comparator circuit according to any one of claims 1 to 3, wherein, The comparator element has a PMOS transistor and an NMOS transistor connected in series between the power supply potential and ground. The PMOS transistor and the NMOS transistor operate in response to the enable signal.

5. A driving circuit for a liquid crystal display device, comprising: The comparator circuit according to any one of claims 1 to 4; A latching circuit holds the image data and outputs it as the first input signal to the comparator element; as well as The counter responds to the counter clock signal to perform a counting action and outputs the counter value as the second input signal.

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