Method of operating a converter circuit, corresponding converter circuit and driver device

Abstract

Methods of operating a converter circuit, a corresponding converter circuit and a driver device are disclosed. A first node of the converter circuit receives an input, provides an output at a second node and has a third node coupled to ground through an inductance. A first switch has a current path between the first node and the third node and a second switch has a current path between the third node and the second node. The converter circuit operates in a first state (in which the first switch is on and the second switch is off) and a second state (in which the first switch is off and the second switch is on). A current through the first switch is sensed during the first state to produce a sensed signal indicative of an inductance current. The sensed signal is averaged to produce an average sensed signal representative of an average of the current. The average sensed signal is then weighted by a time during which the second switch is on to produce a weighted signal.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Italian patent application No. 102021000018548, filed on July 14, 2021, the contents of which are incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This description relates to current sensing and the corresponding circuitry in a DC-DC converter.

[0004] One or more embodiments may be applied to display panel technologies, such as active matrix organic light-emitting diode (AMOLED) devices. Background Technology

[0005] Various power supply circuits, such as AC-DC or DC-DC switching mode power supplies, are known in the art.

[0006] There are many types of electronic converters, mainly divided into isolated and non-isolated types.

[0007] The converter, currently referred to as a "buck", "boost", "buck-boost", "Cuk", "SEPIC", and "ZTA" converter, is an example of a non-isolated electronic converter.

[0008] The converters currently referred to as "flyback," "forward," "half-bridge," and "full-bridge" converters are examples of isolated electronic converters.

[0009] These converters are known to those skilled in the art, as exemplified, for example, by STMicroelectronics’ application note AN513 / 0393 “Topologies for Switched Mode Power Supplies”, L. Wuidart, 1999 (incorporated herein by reference).

[0010] DC-DC converters, especially boost converters, can be used in a variety of applications. Depending on the application, to provide sufficient efficiency and performance levels, it is desirable for the converter circuitry to operate in different modes (e.g., continuous conduction mode (CCM), discontinuous conduction mode (DCM), asynchronous mode, synchronous mode, etc.) and to operate reliably in different scenarios. In such cases, the design of DC-DC converters becomes quite complex.

[0011] For example, DC-DC converters can be used as display drivers for AMOLED display panels. These can include different DC-DC converters configured to generate differential supply voltages for the display panel.

[0012] In such application scenarios, any ripple / transient on the (positive) regulated power supply directly affects display performance, for example, causing display flicker. This constrains the output regulated voltage to be as flat and smooth as possible.

[0013] Therefore, panel current measurement can be a key quality factor for circuits configured to drive AMOLED display panels.

[0014] Existing solutions can be envisioned using current sensing on the high-side switch of the boost converter.

[0015] The drawbacks of these existing solutions include, for example: the introduction of additional quiescent current; increased chip footprint; additional current consumption, which may lead to lower efficiency, especially under light load conditions; and the introduction of errors due to the unidirectionality of current measurability, making them difficult to be compatible with the forced CCM operation of boost converters.

[0016] There is a need in this field to contribute to addressing the shortcomings discussed above. Summary of the Invention

[0017] One or more embodiments may relate to a method. A method of operating a converter circuit may be an example of such a method.

[0018] One or more embodiments may relate to corresponding converter circuits.

[0019] One or more embodiments may relate to a corresponding driving device configured to drive a load (e.g., an AMOLED display panel).

[0020] One or more embodiments facilitate the measurement of panel current by sensing the high-side (HS) switching current via an inverter-type buck-boost converter (e.g., on the negative rail of the panel power supply), a sample and hold circuit block, and (e.g., a low-pass weighted) filter.

[0021] One or more embodiments improve accuracy and / or efficiency under light panel current.

[0022] One or more embodiments can help save chip area and current consumption.

[0023] One or more embodiments help reduce quiescent current consumption.

[0024] One or more embodiments may provide a tunable solution with relatively easy tunability.

[0025] For example, one or more embodiments may integrate fine-tuning for offset cancellation and sensitivity. Attached Figure Description

[0026] One or more embodiments will now be described by way of non-limiting example only with reference to the accompanying drawings, in which:

[0027] Figure 1 This is an exemplary diagram of a driver device for a display panel;

[0028] Figure 2 This is an exemplary diagram of a converter circuit according to the present disclosure;

[0029] Figure 3A , Figure 3B and Figure 3C yes Figure 2 An exemplary timing diagram of signals in a converter circuit;

[0030] Figure 4 and Figure 5 This is an exemplary timeline of another signal in one or more embodiments;

[0031] Figure 6 This is an exemplary diagram of a converter circuit according to the present disclosure;

[0032] Figure 7 These are exemplary diagrams of alternative embodiments of the converter circuit according to the present disclosure;

[0033] Figure 8 and Figure 9 yes Figure 7 Exemplary timelines of signals in alternative embodiments; and

[0034] Figure 10 and Figure 11 These are exemplary diagrams of alternative embodiments of the converter circuit according to the present disclosure. Detailed Implementation

[0035] In the following description, one or more specific details are shown to provide a thorough understanding of examples of embodiments described herein. Embodiments may be obtained without one or more of these specific details, or by utilizing other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been detailed or described so as not to obscure certain aspects of the embodiments.

[0036] References to "embodiment" or "one embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to at least one embodiment is included. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear at one or more points in this specification do not necessarily refer to the same embodiment.

[0037] Furthermore, in one or more embodiments, a particular conformation, structure, or property may be combined in any suitable manner.

[0038] These diagrams are simplified and not to precise scale.

[0039] In the figures attached to this document, similar parts or elements are represented by similar references / numbers, and for the sake of brevity, the corresponding descriptions will not be repeated.

[0040] The reference symbols used herein are provided for convenience only and therefore do not define the scope of protection or the scope of embodiments.

[0041] like Figure 1 As shown, the driver circuit system 10 is coupled to the display panel DP via a first (e.g., positive) rail 100a and a second (e.g., negative) rail 100b. For example, due to coupling to rails 100a and 100b, the current I... OUT The current flows into the panel. For example, the drive circuit system 10 is configured to drive the current I in the panel DP.

[0042] like Figure 1 As shown, the driver 10 includes: a first DC-DC converter circuit 12, such as a boost converter, configured to provide a first voltage level V to the first rail 100a. 01 The first DC-DC converter circuit 12 operates in forced CCM mode; and the second DC-DC converter circuit 14, such as an inverter buck-boost converter, is configured to provide a second voltage level V to the second rail 100b. 02 .

[0043] In one or more embodiments, the second converter 12 may include a multiphase inverter buck-boost converter whose operating mode can be changed according to the load current without causing any flickering of the panel DP.

[0044] like Figure 2 As shown, the inverter-type buck-boost converter 14 includes: input node V IN It is configured to receive DC input voltage V IN (e.g., supplied by a battery); and output node V O2 It is configured to couple to the second rail 100b to provide a regulated voltage to the display panel load DP. A pair of electronic switches HS and LS (with their current paths) are coupled in series (e.g., directly) at the output node V. O2 and input node V IN Between, where the intermediate node between electronic switches S1 and S2 represents switching node LX. Inductor L, such as an inductor, is coupled (e.g., directly) between switching node LX and ground.

[0045] Specifically, the pair of switches HS and LS includes coupling (e.g., directly) at the input node V. INThe first (e.g., high-side) electronic switch HS between the switching node LX and the (negative) output node V, and the coupling (e.g., direct) between the switching node LX and the (negative) output node V. O2 The second (e.g., low-side) electronic switch LS is between them. In other words, the (high-side) switch HS and the (low-side) switch LS are arranged in a half-bridge configuration.

[0046] For example, the switches LS and / or HS are transistors, such as field-effect transistors (FETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), N-channel FETs, and NMOS.

[0047] like Figure 2 As shown, the first switch HS and the second switch LS each have their own control nodes, which are configured to receive, for example, a drive signal D from the control circuit 20. HS D LS Based on each control signal D having a first (e.g., "1") value HS D LS Switches HS and LS switch from a first (e.g., open) state to a second (e.g., closed) state, and vice versa. Specifically, control circuit 20 can be configured to provide a signal D that varies periodically over time. HS D LS So that, for example, the second switch LS (or a similar diode) is open during the time THS when the first switch HS is closed, and the second switch LS (or a similar diode) is closed during the time TLS when the first switch HS is closed.

[0048] This controlled switching helps regulate the voltage level at the switching node LX (i.e., the voltage at the first switch HS) and the current I through the inductor L. L Therefore, the current I L It can be used to power the display panel's DP output.

[0049] like Figure 2 As shown, converter 14 also includes a control node D coupled to the first transistor HS. HS And another switch SW0 for switching node LX, and coupled to input node V IN And the sensing resistor R0 of another switch SW0.

[0050] like Figure 2 As shown, when the first transistor HS is closed, the other transistor SW0 is also closed. Therefore, the voltage drop across resistor R0 can be expressed as V. R0 =V HS -V SW0 V HS It is the voltage drop across the first transistor, while V SW0 It is the voltage drop across another switch, SW0.

[0051] For example, the resistance of SW0 is negligible, so the voltage drop across R0 is essentially equal to the voltage drop across the first transistor HS, i.e. .

[0052] like Figure 2 As shown, the current sensing circuit block 15 is coupled to the converter 14.

[0053] For example, current sensing circuit block 15 includes: a buffer 150, such as an operational amplifier, having a first buffer input node between a sensing resistor R0 and another switch 15 and coupled to a second buffer input node (via a feedback branch FB) and a buffer transistor M. B The buffer output node; the first resistor R UP With sensing resistor R0 and buffer output node M B Parallel coupling; and the second resistor R D It is coupled to the buffer output node and ground GND.

[0054] like Figure 2 As shown, when the first transistor HS is closed, the voltage drop V across the sensing resistor R0 is... HS The first transistor R is switched to the sensing circuit block 15 via the buffer 150. UP Above. Therefore, as the current I flowing in the inductor L. L The function of current I R_UP Flow into the first transistor R UP And the voltage drop V on the second transistor RD RD It can be represented as:

[0055]

[0056] Where R onHS It is the on-resistance of the first transistor, I. L It is the current flowing in the inductor L.

[0057] The output current I flowing in the display panel DP OUT The relationship between the current and the inductor current can be expressed as:

[0058]

[0059] like Figure 2 As shown, sensing circuit block 15 is coupled to sample-and-hold (S&H) circuit block 16. For example, S&H circuit 16 includes: a first switch SW1, and a second resistor R coupled to sensing circuit 15. D and RC network R1,C B The first switch SW1 is configured to receive a drive signal (e.g., D) from the control circuit 20.HS The corresponding control node is driven to switch accordingly; and the second switch SW2 is coupled to the first switch SW1 and the output node V. B The second switch SW2 is configured to receive signals different from those received by the first switch (e.g., D). HS The drive signal received from the control circuit 20 is used to drive the corresponding control node to switch accordingly. Circuit 16 may also optionally include a buffer 160, which has coupling to the RC network R1,C. B The first buffer input node is coupled to the output node V. B The second buffer input node and the buffer output node coupled to the second switch SW2.

[0060] like Figure 3A , Figure 3B , Figure 3C As shown, the current I flowing in the inductor L L Based on the half-bridge arrangement of the first HS transistor or the second LS transistor relative to the total periodic switching time T SW The conduction time varies over time.

[0061] For example: Figure 3A As shown, the control circuit 20 can be configured to provide signal D according to a so-called CCM mode known in itself. HS D LS Optionally, such as Figure 3B As shown, the control circuit 20 can be configured to provide signal D according to a so-called critical mode. HS D LS The critical mode is located at the boundary between CCM and DCM operations, and the critical mode itself is known. Furthermore, as... Figure 3C As shown, control circuit 20 can be configured to provide signal D according to the so-called (depth) DCM mode (known per se). HS D LS The DCM mode includes a duration time interval T. IDLE The idle phase, in which the first HS transistor and the second LS transistor are both in the same "on" state.

[0062] like Figure 3A , Figure 3B , Figure 3C As shown, regardless of the control method used to drive the switch, the first time interval T during the conduction of the low-side transistor LS is calculated. LS During the second time interval T when the high-side transistor HS is turned on. HS Average during the period L >, can obtain current I L The same average L ​​(For example, integration can be performed within the corresponding time intervals).

[0063] Figure 4 yes Figure 2 The nodes V of the S&H circuit 16 illustrated in the figure RD V A and V B An example of a time graph of the signal at a given location.

[0064] like Figure 2 and Figure 4 As shown, the S&H circuit 16 is operated to perform: in the first time interval T HS During this period, capacitor C in the RC circuit of S&H circuit 16... B Charge so that in several switching cycles T SW Then the average value can be sensed; and during the switching period T SW During the remaining time period, for example, the average value is maintained in capacitor C via the low impedance of buffer 160. B In, and provide it to the output node V. B .

[0065] For example, obtaining the current I that indicates the current flowing in the display panel DP. OUT The sensing signal V SENSE Including the induced current L The average weighted value of the sensed signal V. SENSE It can be used in a variety of ways. For example, consider the efficiency of a DC-DC converter, which is the ratio of its power output to the sum of its power output and power losses. This power loss is directly related to the operation of the transistors HS and LS. There are two types of losses: ohmic losses and dynamic losses. Depending on the technology and topology of the DC-DC converter, there exists a current relative to which the size of the HS and / or LS transistors can preferably be varied. For example, if the load is high, a very conductive transistor is preferred; on the other hand, if the load is low, a smaller transistor can be used. To achieve this level of control, each of the HS and LS transistors is typically implemented using multiple parallel devices that need to be selectively driven. By sensing the signal V... SENSE By comparing with multiple benchmarks, the requirements in digital operating mode can be determined, and the appropriate number of devices to be turned on / off by driving the HS and LS transistors can be determined to improve efficiency.

[0066] Multiple DC-DC converters can also be connected in parallel to drive the load. These converters can be selectively driven according to the load requirements. This is achieved using the sensing signal V. SENSE It can control the selective drive of the DC-DC converter.

[0067] Sensing signal V SENSE ​It can also be used to reduce quiescent current consumption and improve efficiency under light load conditions. The quiescent current can be adjusted (increased or decreased) based on the sensed output current for greater efficiency.

[0068] In addition, the sensing signal V SENSE It can be used as a decision-related control input to switch between different control loops for DC-DC converter operation (e.g., when changing between pulse width modulation (PWM) and pulse frequency modulation (PFM) operation).

[0069] like Figure 2 As shown, the weighting circuit 18 is coupled to the S&H circuit 16. The weighting circuit 18 includes: a third switch SW3, coupled to the output node V of the S&H circuit 16. B And another RC network R C C C The third switch SW3 has a corresponding control node configured to receive drive signals (e.g., D) from the control circuit 20. LS The fourth switch SW4 is coupled to the second switch SW1 and the output node V, and is driven to switch accordingly. SENSE The fourth switch SW4 has a corresponding control node configured to receive a drive signal from the control circuit 20 that is different from the drive signal received by the first switch, and is driven to switch a specific time interval (e.g., T) accordingly. LS With T IDLE Perform a logical OR.

[0070] Figure 5 yes Figure 2 The nodes V of the weighted circuit 18 illustrated in the figure B V C and V SENSE An example of a time graph of the signal at a given location.

[0071] like Figure 5 and Figure 2 As shown, the weighting circuit 18 operates as follows: in the first time interval (e.g., T... LS During this period, the third switch SW3 is closed and receives the indicated average current. L >V B And in the switching period T SW The remaining time (e.g., T) HS With T IDLE During the logical OR operation, the fourth switch SW4 closes and forces node V to... C Grounding.

[0072] In this way, the RC filter R C C C In terms of average value, we see the output node V of converter 14.​O2 The same thing, providing the corresponding output value V SENSE It can be represented as:

[0073] V SENSE = <V C >=(R D / R UP ) (R onHS ) L > T LS / T SW

[0074] like Figure 6 As shown, sensitivity and offset can be achieved, for example, through a second resistor R coupled to sensing circuit 15. D The fine-tuning circuit 19 includes: a current generator configured to compensate for possible DC errors introduced by the buffer 150; and a set of resistors, such as R2, R3 coupled to the output of the second switch and the buffer 160 and R4, R5 coupled to the input and output nodes of the buffer, configured to tune the gain in the S&H circuit 16, facilitating maximization of the output voltage range and facilitating reduction of the gain caused by the RC filters R1, C B Any integral error introduced.

[0075] like Figure 6 As shown, especially when there is a non-zero idle time T IDLE At that time, the third switch SW3 and the fourth switch SW4 in the weighting circuit 18 respond to the idle time T IDLE The switching is driven by a control signal during the period. For example, the third switch SW3 can be configured to switch during the idle phase T. IDLE During this period, the switch is turned on, while the second switch SW2 and the fourth switch SW4 can be turned on during the idle phase T. IDLE The period is closed.

[0076] In one or more embodiments, the performance of the sensing circuit 15 may be affected by non-idealities, such as: a finite bandwidth representing non-idealities in the dynamic range of the circuit 15, and a non-zero DC error representing a negligible second-order problem.

[0077] As is well known, the bandwidth of a circuit represents its ability to "follow" a signal during its transient evolution. Limited bandwidth can cause, for example, the voltage at the feedback branch FB of sensing circuit 15 to deviate from the expected, ideal behavior over time. Therefore, this error is reflected in the voltage V. R_D The voltage V propagates from sensing circuit 15 to S&H circuit 16 and weighting circuit 18, causing the sensed voltage V to... SENSE ​It can be affected by variable offset, for example, the variable offset varies depending on the corner temperature and load conditions.

[0078] Figure 7 Alternative embodiments that take into account these non-idealities are shown.

[0079] like Figure 7 As shown, this alternative embodiment arranges an S&H circuit 16' between the insertion converter circuit 14 and the sensing circuit 15, wherein the sensing circuit 15 is coupled to the weighting circuit 18.

[0080] like Figure 7 As shown, the S&H circuit 16' may include an RC network R1, C B It is selectively coupled between the sensing resistor R0 of converter 14 and another transistor SW0 via the first switch SW1.

[0081] For example: in the first time interval T HS During this period, in the S&H circuit 16', the RC filter R1, C B Capacitor C B The instantaneous current value I of the current flowing in the sensing resistor R0 is accumulated. L And "average" L >; and during the switching time T SW During the remainder of the period, buffer 150 "replicates" the average value. L >

[0082] Therefore, the buffer 150 is affected by small dynamic changes in the input signal, resulting in a reduction in the impact of bandwidth non-ideality.

[0083] like Figure 9 As shown, use as Figure 8 The arrangement shown can be implemented in the second resistor R of the sensing circuit 15. D The voltage signal V is generated on the top RD The voltage signal V RD A more precise representation of the current value relative to the input, such as... Figure 2 The same signal V obtained by the arrangement shown RD Rapid changes.

[0084] Figure 9 In the exemplary case where the control circuit 20 is configured to drive the switch pairs HS and LS of the converter 10 using a deep DCM mode, Figure 7 The circuit layout shown includes each node V. RD V C V FB and V SENSE ​​An example of a timing diagram of the signal at the location. Note that when control circuit 20 is configured to operate converter 14 according to CCM or DCM or virtually any other operating mode known per se, except that there is no phase duration T. IDLE Besides, the same signal diagram can exist.

[0085] about Figure 2 The embodiment illustrated in Figure 7 The alternative embodiments illustrated primarily use passive components / switches, which facilitate adjustments based on current I. L The ripple signal is used to adjust the bandwidth of buffer 150.

[0086] Figure 7 The sensitivity and offset of the circuit shown can be determined by... Figure 10 The arrangement shown is tuned. Skip mode circuit block 102 can facilitate the input dynamics of adaptive buffer 150. For example, due to the drain-source voltage V of high-side transistor HS in skip mode... DS The input may be too small to be replicated, so an offset can be added to the input to achieve the desired input level of the buffer input, and blocks 106 and 104 can be used, for example, to remove the offset at the output. Low-pass filter circuit block 104 is coupled to weighting circuit 18 to increase the output swing and decrease the output V. SENSE The impedance at the location is adjusted to improve measurement accuracy. Offset setting circuit block 106 includes a current generator configured to compensate for the DC error introduced by buffer 150 (similar to...). Figure 6 The fine-tuning circuit shown in the example is 19).

[0087] like Figure 11 As shown, the weighting circuit 18 may include a resistor R inserted into the sensing circuit 15. D Another RC network R between the third switch SW3 and the fourth switch SW4 C ', C C For example, another RC network R C ', C C 'Configured to further smooth the measurement of V SENSE The signal or in the second time interval T LS The average value is directly applied during this period.

[0088] It is worth noting that although the discussion is mainly focused on the application context of AMOLED display panels DP, the proposed solution can actually be applied to any type of switching converter circuit.

[0089] In one or more embodiments, the method can be applied to also measure (e.g., additionally or alternatively) other currents in a DC-DC converter (e.g., switches and inductors) by sensing the current of a (single) switch.

[0090] In an alternative embodiment, signal V RD It can be used to generate a sensing signal V by applying filtering to it. SENSE To provide measurement of input current.

[0091] In alternative embodiments, such as Figure 7 The buffer capacitor C in the RC circuit of the illustrated block 16' B The voltage at both ends can be provided, for example, as a weighted signal to the buffer stage 150 of block 15.

[0092] As illustrated herein, a driver device (e.g., 10) is configured to generate a differential supply voltage (e.g., V) for the load between a first supply rail (e.g., 100a) and a second supply rail (e.g., 100b). O1 V O2 ).

[0093] For example, the driver device includes: a first converter circuit (e.g., 12) coupled to a first power supply rail, the first boost converter circuit being configured to operate in continuous conduction mode (CCM); and a second converter circuit (e.g., 14) according to the invention, having a second node (e.g., V) coupled to a load (e.g., DP) via a second rail (100b) of a pair of power supply rails. O2 The second converter circuit is configured to provide a weighted signal (e.g., V). SENSE ), weighted signal V SENSE Indicates that the flow is coupled to a second node (e.g., V). O2 The current of the load (e.g., I, I) OUT The intensity of ).

[0094] For example, the driver device is configured to change the differential supply voltage (e.g., V) generated for the load based on a weighted signal. O1 V O2 ).

[0095] As illustrated herein, a system includes a driver device according to the present disclosure and a load (e.g., a display panel, preferably an AMOLED display panel), the load being coupled across a first power supply rail and a second power supply rail of the driver device to receive a differential power supply voltage therefrom.

[0096] As illustrated in this article, one approach includes providing a DC output signal (e.g., V) via a converter circuit (e.g., 14). O2 I OUT The converter circuit has a first node (e.g., V) to the user circuit (e.g., DP). IN ), receiving input signals from an energy source (e.g., 10); the second node (e.g., V) O2The converter circuit includes a first electronic switch (e.g., HS) having a current path passing through it, coupled between the first and third nodes; and a second electronic switch (e.g., LS) having a current path passing through it, coupled between the third and second nodes. The first and second electronic switches are configured to selectively (e.g., D...) provide a DC output signal to the user circuit; and a third node (e.g., LX) coupled to a ground-based inductor (e.g., L), wherein the converter circuit includes a first electronic switch (e.g., HS) having a current path passing through it, coupled between the third and second nodes. HS D LS (Conducting and non-conducting)

[0097] As illustrated herein, the method includes operating the converter circuitry: in a first operating state (e.g., T... HS During this period, the first electronic switch is turned on while the second electronic switch is not turned on, and in the second operating state (e.g., T...). LS During this period, the first electronic switch is not turned on while the second electronic switch is turned on; the current (I) flowing through the first electronic switch that was turned on during the first operating state is sensed (e.g., SW0, R0, I5). L ), to generate a sensing signal (e.g., V) representing the intensity of the current flowing through the inductor. HS V RD V The sensed signal is averaged (e.g., 16, 16') to produce an average value representing the intensity of the current flowing through it (e.g., L The average sensed signal (e.g., V) of > B ); and weight the average sensed signal (e.g., 18; 18') over a time to generate a weighted signal (e.g., V). SENSE During this period, the second electronic switch is turned on, and the weighted signal indicates the strength of the current supplied to the user circuit via the second node (e.g., I, I). OUT ).

[0098] As illustrated in this article, the method includes a third operating state (e.g., T). IDLE In the third operating state, neither the first nor the second electronic switch of the converter circuit is turned on.

[0099] As illustrated herein, the method includes averaging the sensed signal over an averaging time (e.g., T). HS T LS T IDLE T SW An average sensing signal is generated on the device, during which at least one of the first and second electronic switches is not conducting during the average time.

[0100] ​As illustrated herein, the converter circuit (e.g., 14) includes: a first node (e.g., V... IN The second node (e.g., V) is configured to receive an input signal from an energy source (e.g., 10); O2 ), configured to provide a DC output signal (e.g., V) to a user circuit (e.g., DP). O2 I OUT ); and a third node (e.g., LX), which is coupled to a ground-based inductor (e.g., L). A first electronic switch (e.g., HS) has a current path coupled through it between the first and third nodes, and a second electronic switch (e.g., LS) has a current path coupled through it between the third and second nodes. A control circuit system (e.g., 20) coupled to the first and second electronic switches is configured to operate in a first operating state and a second operating state (e.g., T). LS In ) the first electronic switch and the second electronic switch selectively (e.g., D) HS D LS The first electronic switch is on and the second electronic switch is off in a first operating state, and in a second operating state, the first electronic switch is off and the second electronic switch is on. A sensing circuit system (e.g., SW0, R0, I5) is configured to sense the current flowing through the first electronic switch, which is on during the first operating state, in the current flow path to generate an indication of the current flowing through the inductor (e.g., L) (e.g., I). L The sensing signal has an intensity of 16.16'. An averaging circuit system (e.g., 16; 16') is coupled to the sensing circuit, wherein the averaging circuit is configured to average the sensing signal to produce an average value representing the current (e.g., IL) flowing through the inductor. L The average sensed signal (e.g., VB) is weighted by a weighting circuitry (e.g., 18; 18'). The weighting circuitry is configured to weight the average sensed signal over a time to produce a weighted signal (e.g., V). SENSE During this time period, the second electronic switch is turned on, and the weighted signal indicates that the signal is transmitted via the second node (e.g., V). O2 The current supplied to the user circuit (e.g., I, I) OUT The intensity of ).

[0101] As illustrated herein, the control circuit is configured to put the first and second electronic switches in a third operating state (e.g., T). IDLE None of them are conductive.

[0102] As illustrated herein, the averaging circuit system is configured to generate an average sensing signal over an averaging time, wherein at least one of the first electronic switch and the second electronic switch is not turned on.

[0103] ​As illustrated in this article, the average circuit system includes: a low-pass filter (e.g., R1, C) B ), is configured to be activated (e.g., SW1) during the time when the first electronic switch is on and the second electronic switch is off (e.g., T). HS The sensed signal is filtered on the circuit; and a buffer circuit (e.g., 160) is configured to couple (e.g., SW2) to a low-pass filter to filter the signal during the time when at least one of the first and second electronic switches is not conducting (e.g., T). LF T IDLE The filtered sensing signal is buffered on top.

[0104] As illustrated herein, the buffer circuit (e.g., 160) has a buffer gain, and the converter circuit includes a resistor network (e.g., R2, R3, R4, R5) coupled to the buffer circuit and configured to adjust the buffer gain.

[0105] As illustrated herein, the sensing circuit system includes a corresponding buffer circuit (e.g., 150) having at least one input node, the buffer circuit being configured to operate during the time when the first electronic switch is on and the second electronic switch is off (e.g., T). HS During the period, the sensor receives the sensing signal; and the output node (e.g., FB, V) receives the sensing signal. RD Each buffer circuit is configured to be selectively de-energized for at least one of the first and second electronic switches during the time (e.g., T). LS T IDLE The sensing signal is provided at the output node, and the sensing signal at the output node has a DC error superimposed on it. The resistor (e.g., R) D The circuit is coupled to the output node of the corresponding buffer to receive the sensed signal and has a current flowing through the signal. The fine-tuning circuitry (e.g., 19) is coupled to a resistor and configured to eliminate the DC error superimposed on the sensed signal provided at the output node by changing the current flowing through the resistor.

[0106] It will also be understood that the various individual implementation options illustrated throughout the accompanying drawings are not necessarily intended to be used in the same combinations illustrated in the drawings. Therefore, one or more embodiments may employ these (otherwise non-mandatory) options individually and / or in different combinations relative to the combinations illustrated in the drawings.

[0107] The claims are an integral part of the technical teachings provided herein with reference to the embodiments.

[0108] Without prejudice to the fundamental principles, details and embodiments may be changed, even significantly, relative to the description by way of example only, without departing from the scope of protection. The appended claims define the scope of protection.

Claims

1. A method for operating a converter circuit, comprising: The converter circuit is operated, the converter circuit including a first electronic switch and a second electronic switch, the first electronic switch having a current flow path between a first node and a third node, the second electronic switch having a current flow path between the third node and the second node, wherein the third node is coupled to a ground-based inductor, the first electronic switch is turned on and the second electronic switch is turned off during a first operating state, and the first electronic switch is turned off and the second electronic switch is turned on during a second operating state. The current flowing in the current flow path of the first electronic switch during the first operating state is sensed to generate a sensing signal indicating the intensity of the current flowing through the inductor. The sensed signal is averaged to produce an average sensed signal, which indicates the average value of the intensity of the current flowing through the inductor, and The average sense signal is weighted according to the duration of the second electronic switch being turned on in the second operating state to generate a weighted signal, wherein the weighted signal indicates the strength of the current supplied to the user circuit via the second node.

2. The method for operating the converter circuit according to claim 1, further comprising: The converter circuit is operated in a third operating state, during which neither the first electronic switch nor the second electronic switch is turned on.

3. The method of operating the converter circuit according to claim 1, wherein averaging comprises: The sensed signal is averaged over an average time period during which at least one of the first electronic switch and the second electronic switch is not conducting.

4. A converter circuit, comprising: The first node is configured to receive input signals from the energy source; The second node is configured to provide a DC output signal to the user circuitry. The third node is coupled to a ground-based inductor; A first electronic switch having a current flow path between the first node and the third node; The second electronic switch has a current flow path between the third node and the second node; A control circuit system, coupled to the first electronic switch and the second electronic switch, is configured to turn on the first electronic switch and turn off the second electronic switch in a first operating state, and is further configured to turn off the first electronic switch and turn on the second electronic switch in a second operating state. A sensing circuit system is configured to sense the current flowing through the first electronic switch that is turned on during the first operating state in the current flow path, wherein the sensing circuit system is configured to generate a sensing signal indicating the intensity of the current flowing through the inductor. An averaging circuit system coupled to the sensing circuit system, wherein the averaging circuit system is configured to average the sensing signal to generate an average sensing signal indicating the average value of the current flowing through the inductor. as well as A weighting circuit system coupled to the averaging circuit system, wherein the weighting circuit system is configured to weight the average sense signal according to the on-time of the second electronic switch to generate a weighted signal, the weighted signal indicating the strength of the current supplied to the user circuit via the second node.

5. The converter circuit according to claim 4, wherein the control circuit system is further configured to prevent the first electronic switch and the second electronic switch from conducting in the third operating state.

6. The converter circuit of claim 4, wherein the averaging circuit system is configured to generate the average sensing signal during an averaging time, wherein at least one of the first electronic switch and the second electronic switch is not turned on during the averaging time.

7. The converter circuit of claim 4, wherein the averaging circuit system comprises: A low-pass filter is configured to be activated to filter the sensed signal during the time when the first electronic switch is on and the second electronic switch is off; as well as A buffer circuit is configured to be coupled to the low-pass filter to buffer the filtered sensing signal during the time when at least one of the first and second electronic switches is not turned on.

8. The converter circuit of claim 7, wherein the buffer circuit has a buffer gain, and the converter circuit includes a resistor network coupled to the buffer circuit and configured to adjust the buffer gain.

9. The converter circuit of claim 4, wherein the sensing circuit system comprises: The corresponding buffer circuit has at least one input node, which is configured to receive the sensing signal during the time when the first electronic switch is turned on and the second electronic switch is not turned on. as well as Output node; The corresponding buffer circuit is configured to provide the sensing signal at the output node during the time when at least one of the first and second electronic switches is selectively de-energized.

10. The converter circuit of claim 9, wherein the sensing signal at the output node has a DC error superimposed on the sensing signal, and wherein the sensing circuit system further comprises: A resistor, coupled to the output node of the corresponding buffer circuit to receive the sensed signal from the output node, and having a current flowing through the resistor; as well as A fine-tuning circuit system, coupled to the resistor, is configured to eliminate the DC error superimposed on the sensing signal provided at the output node by changing the current flowing through the resistor.

11. A driver device configured to generate a differential supply voltage for a load between a first supply rail and a second supply rail, the driver device comprising: A first converter circuit, coupled to the first power supply rail, is configured to operate in continuous conduction mode (CCM). as well as The second converter circuit, which is the converter circuit according to claim 4, has a second node, the second node being coupled to the load via a second power rail in a power rail pair, and the second converter circuit being configured to provide the weighting signal, the weighting signal indicating the strength of the current flowing through the load coupled to the second node; The driver device is configured to change the differential supply voltage generated for the load based on the weighted signal.

12. An electronic device, comprising: The driver device according to claim 11; as well as The load is coupled to the first and second power rails of the driver device to receive the differential power supply voltage from the first and second power rails.

13. The electronic device of claim 12, wherein the load includes a display panel.

14. The electronic device of claim 13, wherein the display panel is an AMOLED display panel.

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