Image sensing device

Abstract

An image sensing device includes: a first substrate layer configured to include a photoelectric conversion region for converting incident light into photocharges and a floating diffusion region for storing the photocharges therein; a first interconnect layer formed on the first substrate layer and configured to include a switch transistor gate formed to overlap at least a portion of the floating diffusion region; a second substrate layer formed on the first interconnect layer; a second interconnect layer formed on the second substrate layer; and a capacitor electrically connected to the floating diffusion region through the switch transistor gate. The capacitor includes a first electrode and a second electrode arranged across the first interconnect layer, the second substrate layer, and the second interconnect layer, wherein a portion of the first interconnect layer, a portion of the second substrate layer, and a portion of the second interconnect layer are arranged between the first electrode and the second electrode.

Description

Technical Field

[0001] Technologies and implementations disclosed in this patent document generally relate to image sensing devices. Background Art

[0002] Image sensing devices are devices for capturing optical images by converting light into electrical signals using photosensitive semiconductor materials that react to light. With the development of the automotive, medical, computer, and communication industries, the demand for high-performance image sensing devices is increasing in various fields such as smartphones, digital cameras, game consoles, IoT (Internet of Things), robots, security cameras, and medical micro cameras.

[0003] Image sensing devices can be roughly divided into CCD (charge coupled device) image sensing devices and CMOS (complementary metal oxide semiconductor) image sensing devices. CCD image sensing devices provide better image quality, but they tend to consume more power and are larger than CMOS image sensing devices. CMOS image sensing devices are smaller in size and consume less power than CCD image sensing devices. In addition, CMOS sensors are manufactured using CMOS manufacturing technology, and therefore photosensors and other signal processing circuits can be integrated into a single chip, enabling miniaturized image sensing devices to be produced at a lower cost. For these reasons, CMOS image sensing devices are being developed for many applications including mobile devices. Summary of the invention

[0004] Various embodiments of the disclosed technology relate to an image sensing device capable of reducing pixel size while securing a dynamic range.

[0005] According to an embodiment of the disclosed technology, an image sensing device may include: a first substrate layer, which is configured to include a photoelectric conversion region for converting incident light into photocharges and a floating diffusion region for storing the photocharges therein; a first interconnect layer, which is formed on the first substrate layer and is configured to include a switch transistor gate formed to overlap at least a portion of the floating diffusion region; a second substrate layer, which is formed on the first interconnect layer; a second interconnect layer, which is formed on the second substrate layer; and a capacitor, which is electrically connected to the floating diffusion region through the switch transistor gate. The capacitor may include a first electrode and a second electrode arranged across the first interconnect layer, the second substrate layer, and the second interconnect layer, wherein a portion of the first interconnect layer, a portion of the second substrate layer, and a portion of the second interconnect layer are arranged between the first electrode and the second electrode.

[0006] In some implementations, the first electrode may include a plurality of first through silicon vias (TSVs) disposed across the first interconnect layer, the second substrate layer, and the second interconnect layer, and a connecting electrode disposed in the second interconnect layer and formed to interconnect the first through silicon vias (TSVs).

[0007] In some implementations, the second electrode may include a plurality of second through silicon vias (TSVs) disposed across the first interconnect layer, the second substrate layer, and the second interconnect layer, and a ground contact portion disposed in the first interconnect layer and formed to interconnect the second through silicon vias (TSVs).

[0008] In some implementations, the ground contact portion can be coupled to a ground voltage.

[0009] In some implementations, the connection electrode may be disposed perpendicular to the first through silicon via (TSV).

[0010] In some implementations, the first substrate layer may include a contact region formed to overlap at least a portion of a gate of the switching transistor, wherein the first through silicon via (TSV) contacts the contact region.

[0011] In some implementations, the contact region may be doped with a higher concentration of impurities than the floating diffusion region.

[0012] In some implementations, the second interconnect layer may include a drive transistor gate formed to overlap at least a portion of the photoelectric conversion region, and the floating diffusion region may be coupled to the gate of the drive transistor through a through interconnect structure. The through interconnect structure may be disposed across the second interconnect layer, the second substrate layer, and the first interconnect layer.

[0013] In some implementations, each of the through-interconnect structure, the first electrode, and the second electrode may include at least one of copper (Cu) and tungsten (W).

[0014] According to another embodiment of the disclosed technology, an image sensing device may include: a first substrate layer, which is configured to include a photoelectric conversion region for converting incident light into photocharges, and a floating diffusion region for storing the photocharges therein; a first interconnect layer, which is configured to include a transfer transistor gate overlapping at least a portion of the photoelectric conversion region and a switch transistor gate overlapping at least a portion of the floating diffusion region, and is disposed on the first substrate layer; a second substrate layer, which is configured to include a first terminal region of a drive transistor and a second terminal region of the drive transistor, and is disposed on the first interconnect layer; a second interconnect layer, which is configured to include a gate of a drive transistor connected to the floating diffusion region through a through interconnect structure, and is disposed on the second substrate layer; and a capacitor, which is disposed across the first interconnect layer, the second substrate layer, and the second interconnect layer. The capacitor may be electrically connected to the floating diffusion region through the switch transistor gate.

[0015] In some implementations, the capacitor may include a first electrode and a second electrode. The first electrode may include a first through silicon via (TSV) disposed across the first interconnect layer, the second substrate layer, and the second interconnect layer, and a connection electrode disposed in the second interconnect layer. The second electrode may include a second through silicon via (TSV) disposed across the first interconnect layer, the second substrate layer, and the second interconnect layer, and a ground contact portion disposed in the first interconnect layer.

[0016] In some implementations, the capacitor may further include a dielectric region disposed between the first electrode and the second electrode, wherein the dielectric region includes a portion of the first interconnect layer, a portion of the second substrate layer, and a portion of the second interconnect layer.

[0017] In some implementations, the ground contact portion can be coupled to a ground voltage.

[0018] In some implementations, the first electrode can be electrically coupled to the floating diffusion region through a switching transistor gate.

[0019] It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are illustrative and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other features and advantageous aspects of the disclosed technology will become apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0021] Figure 1 is a block diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0022] Figure 2Some implementations based on the disclosed technology are illustrated in Figure 1 An example of a schematic diagram of an example of a layout structure of any one unit pixel in a pixel array is shown in FIG.

[0023] FIG. 3A to FIG. 3C Schematic diagrams showing examples of some constituent elements formed on the same substrate layer or the same interconnect layer (also referred to as an interconnect layer or a wiring layer) among constituent elements included in a unit pixel based on some implementations of the disclosed technology.

[0024] Figure 4 is a circuit diagram illustrating an example of a unit pixel based on some implementations of the disclosed technology.

[0025] Figure 5 This is an example of some implementations based on the disclosed technology. Figure 2 2 is a cross-sectional view of an example of some areas of a unit pixel intercepted by a first cutting line shown in FIG.

[0026] FIG. 6A to FIG. 6J is a cross-sectional view illustrating an example of a method for forming a unit pixel based on some implementations of the disclosed technology. DETAILED DESCRIPTION

[0027] This patent document provides implementations and examples of image sensing devices capable of reducing pixel size while ensuring dynamic range. Some implementations of the disclosed technology relate to image sensing devices for miniaturizing size while ensuring high dynamic range (HDR).

[0028] Hereinafter, various embodiments will be described with reference to the accompanying drawings. However, it should be understood that the disclosed technology is not limited to a specific embodiment, but includes various modifications, equivalents and / or substitutes of the embodiments. The embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized by the disclosed technology.

[0029] Figure 1 is a block diagram illustrating an image sensing device 100 based on some implementations of the disclosed technology.

[0030] Reference Figure 1 , the image sensing device 100 may include a pixel array 110 , a row driver 120 , a correlated double sampler (CDS) 130 , an analog-to-digital converter (ADC) 140 , an output buffer 150 , a column driver 160 , and a timing controller 170 . Figure 1 The components of image sensing device 100 shown in FIG. 1 are discussed by way of example only, and this patent document encompasses many other alterations, substitutions, variations, variations, and modifications.

[0031] The pixel array 110 may include a plurality of unit imaging pixels arranged in rows and columns. In one example, the plurality of unit imaging pixels may be arranged as a two-dimensional pixel array including rows and columns. In another example, the plurality of unit imaging pixels may be arranged as a three-dimensional pixel array. The plurality of unit pixels may convert optical signals into electrical signals based on unit pixels or pixel groups, wherein the unit pixels in the pixel group share at least some internal circuits. The pixel array 110 may receive a drive signal including a row selection signal, a pixel reset signal, and a transfer signal from the row driver 120. Upon receiving the drive signal, the corresponding imaging pixel in the pixel array 110 may be activated to perform operations corresponding to the row selection signal, the pixel reset signal, and the transfer signal.

[0032] The row driver 120 may activate the pixel array 110 to perform certain operations on the imaging pixels in the corresponding row based on the command and control signals provided by the controller circuit (e.g., the timing controller 170). In some implementations, the row driver 120 may select one or more imaging pixels arranged in one or more rows of the pixel array 110. The row driver 120 may generate a row selection signal to select one or more rows among a plurality of rows. The row decoder 120 may sequentially enable a pixel reset signal for resetting the imaging pixels corresponding to at least one selected row and a transfer signal for the pixels corresponding to the at least one selected row. Thus, a reference signal and an image signal, which are analog signals generated by each imaging pixel of the selected row, may be sequentially transferred to the CDS 130. The reference signal may be an electrical signal provided to the CDS 130 when a sensing node (e.g., a floating diffusion region node) of the imaging pixel is reset, and the image signal may be an electrical signal provided to the CDS 130 when a photocharge generated by the imaging pixel is accumulated in the sensing node.

[0033] CMOS image sensors can use correlated double sampling (CDS) to remove the difference between the two samples by sampling the pixel signal twice, thereby removing the undesirable offset value of the pixel, which is called fixed pattern noise. In one example, correlated double sampling (CDS) can remove the undesirable offset value of the pixel by comparing the pixel output voltage obtained before and after the photocharge generated by the incident light is accumulated in the sensing node, so that only the pixel output voltage based on the incident light can be measured. In some embodiments of the disclosed technology, CDS130 can sequentially sample and maintain the voltage levels of the reference signal and the image signal provided to each of the multiple column lines from the pixel array 110. That is, CDS130 can sample and maintain the voltage levels of the reference signal and the image signal corresponding to each of the respective columns of the pixel array 110.

[0034] In some implementations, the CDS 130 may transfer the reference signal and the image signal of each of the respective columns to the ADC 140 as a correlated double sampling signal based on a control signal from the timing controller 170 .

[0035] ADC 140 is used to convert the analog CDS signal into a digital signal. In some implementations, ADC 140 can be implemented as a ramp comparison ADC. The ramp comparison ADC may include a comparator circuit and a timer, the comparator circuit is used to compare the analog pixel signal with a reference signal such as a ramp signal that ramps up or down, and the timer counts until the voltage of the ramp signal matches the analog pixel signal. In some embodiments of the disclosed technology, ADC 140 can convert the correlated double sampling signal generated by CDS 130 for each of the columns into a digital signal and output the digital signal. ADC 140 can perform counting operations and calculation operations based on the correlated double sampling signal for each of the columns and the ramp signal provided from the timing controller 170. In this way, ADC 140 can eliminate or reduce noise such as reset noise generated by imaging pixels when generating digital image data.

[0036] The ADC 140 may include a plurality of column counters. Each column of the pixel array 110 is connected to a column counter, and image data may be generated by converting a correlated double sampling signal received from each column into a digital signal using the column counter. In another embodiment of the disclosed technology, the ADC 140 may include a global counter to convert the correlated double sampling signal corresponding to each column into a digital signal using a global code provided from the global counter.

[0037] The output buffer 150 may temporarily save the column-based image data provided from the ADC 140 to output the image data. In one example, the image data provided from the ADC 140 to the output buffer 150 may be temporarily stored in the output buffer 150 based on a control signal of the timing controller 170. The output buffer 150 may provide an interface to compensate for a data rate difference or a transfer rate difference between the image sensing device 100 and other devices.

[0038] The column driver 160 may select a column of the output buffer upon receiving a control signal from the timing controller 170, and sequentially output the image data temporarily stored in the selected column of the output buffer 150. In some implementations, upon receiving an address signal from the timing controller 170, the column driver 160 may generate a column selection signal based on the address signal and select a column of the output buffer 150, and output the image data from the selected column of the output buffer 150 as an output signal.

[0039] The timing controller 170 may control operations of the row driver 120 , the ADC 140 , the output buffer 150 , and the column driver 160 .

[0040] The timing controller 170 may provide clock signals required for operations of the corresponding components of the image sensing device 100, control signals for timing control, and address signals for selecting rows or columns to the row driver 120, the column driver 160, and the output buffer 150. In an embodiment of the disclosed technology, the timing controller 170 may include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, and the like.

[0041] Figure 2 Some implementations based on the disclosed technology are illustrated in Figure 1 2 is a schematic diagram of an example of a layout structure 200 of any one unit pixel in the pixel array 110 shown in FIG.

[0042] In some implementations, a unit pixel may include a photoelectric conversion region 212 , a floating diffusion (FD) region 214 , a transfer transistor gate 222 , a switch transistor gate 224 , a drive transistor gate 242 , and a capacitor 250 .

[0043] Figure 2 The structures shown in are merely examples, and in some embodiments the relative sizes and positions of the corresponding constituent elements (eg, 212, 214, 222, 224, 242, 250, etc.) may vary.

[0044] Each photoelectric conversion region 212 may generate photocharges corresponding to incident light. Each photoelectric conversion region 212 may include an organic photodiode or an inorganic photodiode.

[0045] For example, the photoelectric conversion region 212 may be formed in a substrate layer, and may be formed in a stacked structure in which impurity regions (a P-type impurity region and an N-type impurity region) having complementary conductivity are vertically stacked.

[0046] The photoelectric conversion region 212 may be arranged to occupy as large an area as possible to easily generate photocharges corresponding to incident light. A region where the photoelectric conversion region 212 and the transfer transistor gate 222 overlap each other may extend along a side of the transfer transistor gate 222 .

[0047] The photoelectric conversion region 212 may be electrically coupled to or separated from the floating diffusion (FD) region 214 in response to a voltage applied to the transfer transistor gate 222 .

[0048] The transfer transistor gate 222 may be disposed between the floating diffusion (FD) region 214 and the photoelectric conversion region 212. The transfer transistor gate 222 may be disposed to overlap at least a portion of the photoelectric conversion region 212 and at least a portion of the floating diffusion (FD) region 214.

[0049] In some implementations, the transfer transistor gate 222 may be formed in a triangular shape having sides overlapping the photoelectric conversion region 212 and the floating diffusion (FD) region 214. The length of the side of the transfer transistor gate 222 overlapping the photoelectric conversion region 212 may be longer than the length of the side overlapping the floating diffusion (FD) region 214.

[0050] One side of the transfer transistor gate 222 overlapping the photoelectric conversion region 212 may extend along the photoelectric conversion region 212, and one side of the transfer transistor gate 222 overlapping the floating diffusion (FD) region 214 may extend along the floating diffusion (FD) region 214. The transfer transistor gate 222 may be formed of or include metal or polysilicon.

[0051] The floating diffusion (FD) region 214 may temporarily store photo charges generated by the photoelectric conversion region 212. The image sensing device 100 may generate a pixel signal based on a voltage signal corresponding to the photo charges stored in the floating diffusion (FD) region 214.

[0052] The floating diffusion (FD) region 214 may be disposed between the transfer transistor gate 222 and the switch transistor gate 224. The floating diffusion (FD) region 214 may be formed in a square shape, and other implementations are also possible. For example, when a plurality of unit pixels construct a shared pixel, the floating diffusion (FD) region 214 may be formed in a polygonal shape such as a rhombus shape or an octagonal shape. In some implementations, the floating diffusion (FD) region 214 may be an N-type impurity doped region formed on a semiconductor substrate.

[0053] The floating diffusion (FD) region 214 may be coupled to a first electrode of the capacitor 250 through a switching transistor gate 224 disposed to overlap the floating diffusion (FD) region 214 .

[0054] The switching transistor gate 224 may be disposed to overlap at least a portion of the floating diffusion (FD) region 214 and at least a portion of the capacitor 250. The floating diffusion (FD) region 214 may be coupled to or separated from the capacitor 250 in response to a switching signal applied to the switching transistor gate 224.

[0055] For example, the switching transistor gate 224 may be formed in a rectangular shape. A long side among the multiple sides of the switching transistor gate 224 may be arranged to overlap the floating diffusion (FD) region 214 and the capacitor 250 so that electrons can easily move between the floating diffusion (FD) region 214 and the capacitor 250.

[0056] The capacitor 250 may be formed on a plurality of substrate layers and a plurality of interconnect layers, and may include a first electrode, a second electrode, and a dielectric region. In addition, at least a portion of a contact region included in the capacitor 250 may overlap with the switching transistor gate 224.

[0057] The capacitor 250 may store overflowing charges (an amount exceeding the capacitance of the floating diffusion (FD) region 214 ) and may be coupled to the floating diffusion (FD) region 214 such that the capacitor 250 may provide additional capacitance to the floating diffusion (FD) region 214 .

[0058] The capacitor 250 may be arranged to have a vertical structure in such a manner that an area occupied by the unit pixel layout structure 200 can be miniaturized and sufficient capacitance can be secured. For example, the capacitor may be a lateral overflow integration capacitor.

[0059] In some implementations, the capacitor 250 may include a first electrode and a second electrode, each of which includes a plurality of vertical through interconnects (also referred to as vertical through wiring). The vertical through interconnects may be coupled to a doped region included in the substrate, or may be coupled to a connection electrode formed on an interconnect layer or a ground contact portion formed on the interconnect layer. The capacitor 250 may be formed to have a predetermined capacitance and may have, for example, a metal-insulator-metal (MIM) structure.

[0060] The driving transistor gate 242 may be disposed to overlap with the photoelectric conversion region 212. The driving transistor gate 242 is formed to overlap with the photoelectric conversion region 212 so that a gate region of a sufficient size can be secured.

[0061] The driving transistor gate 242 may be coupled to the floating diffusion (FD) region 214 and may amplify a signal corresponding to a voltage of the floating diffusion (FD) region 214 .

[0062] In this example, the drive transistor gate 242 overlaps the photoelectric conversion region 212. Other implementations are also possible, such that the drive transistor gate 242, the reset transistor gate (not shown), the select transistor gate (not shown), or other elements may be arranged to overlap the photoelectric conversion region 212.

[0063] FIG. 3A to FIG. 3C 1 is a schematic diagram illustrating an example of some constituent elements formed on the same substrate layer or the same interconnection layer among constituent elements included in a unit pixel based on some implementations of the disclosed technology.

[0064] Figure 3A is a schematic diagram ( 300 a ) illustrating an example of a constituent structure formed on a first substrate layer among a plurality of constituent elements included in a unit pixel based on some implementations of the disclosed technology.

[0065] The first substrate layer may be a semiconductor substrate doped with impurities. For example, the first substrate layer may be a semiconductor substrate doped with P-type impurities.

[0066] The first substrate layer may include a photoelectric conversion region 212 , a floating diffusion (FD) region 214 , and a contact region 216 .

[0067] The photoelectric conversion region 212 may include an organic photodiode or an inorganic photodiode formed on a substrate layer. In addition, the photoelectric conversion region 212 may be formed as a stacked structure having a P-type doped region doped with a P-type impurity and / or an N-type doped region doped with an N-type impurity. As described above, the photoelectric conversion region 212 may be configured to occupy as large an area as possible in the active region of the unit pixel.

[0068] The floating diffusion (FD) region 214 may be formed by doping N-type impurities on the first substrate layer.

[0069] The contact region 216 may be formed by doping N-type impurities on the first substrate layer. The contact region 216 may be coupled to first through silicon vias (TSVs) 254a, 254b, 254c, and 254d of the capacitor 250.

[0070] In some implementations, the contact region 216 may be formed to have a higher doping concentration than the floating diffusion (FD) region 214. The first TSVs 254a, 254b, 254c, and 254d are coupled to the contact region 216 doped with high-concentration impurities (e.g., N-type impurities), resulting in a reduced resistance between the first electrode and the contact region 216.

[0071] The first TSVs 254a, 254b, 254c, and 254d may be included in the first electrode of the capacitor 250. The first TSVs 254a, 254b, 254c, and 254d may be formed of a metal or include a metal (e.g., copper (Cu) or tungsten (W) or a combination of copper (Cu) and tungsten (W)). The first TSVs 254a, 254b, 254c, and 254d may be formed perpendicular to one surface of the contact region 216, and may be formed to cross a first interconnect layer, a second substrate layer, and a second interconnect layer described later.

[0072] Additionally, the contact region 216 may operate as one terminal of a switching transistor including the switching transistor gate 224. When the contact region 216 operates as one terminal of the switching transistor, the first electrode of the capacitor 250 may be coupled to the switching transistor without an additional connecting wire.

[0073] Figure 3B 300b is a schematic diagram illustrating an example of a constituent structure formed on a first interconnect layer among a plurality of constituent elements in a unit pixel based on some implementations of the disclosed technology. The first interconnect layer may be formed on or disposed on a first substrate layer. The first interconnect layer may include an insulating material such as silicon oxide.

[0074] The first interconnect layer may include a transfer transistor gate 222 , a switch transistor gate 224 , and a ground contact portion 252 .

[0075] The transfer transistor gate 222 may be coupled to a transmission signal line 226. A transmission signal may be applied to the transfer transistor gate 222 through the transmission signal line 226. In some implementations, the transfer transistor gate 222 may be formed of or include polysilicon, and the transmission signal line 226 may be formed of or include metal.

[0076] The switch transistor gate 224 may be coupled to a switch signal line 228. A switch signal may be applied to the switch transistor gate 224 through the switch signal line 228. In some implementations, the switch transistor gate 224 may be formed of or include polysilicon, and the switch signal line 228 may be formed of or include metal.

[0077] The ground contact portion 252 may be formed of or include a metal and may be included in a second electrode of the capacitor 250. The ground contact portion 252 may be grounded (GND). The second electrode of the capacitor 250 may refer to an electrode that does not contact the contact region 216.

[0078] In some implementations, the second electrode of the capacitor 250 may include a ground contact portion 252 and second TSVs 256a, 256b, and 256c. Each of the second TSVs 256a, 256b, and 256c may be formed of a metal or include a metal (e.g., copper (Cu) or tungsten (W) or a combination of copper (Cu) and tungsten (W)). Although the second TSVs 256a, 256b, and 256c may be formed to span the first interconnect layer, the second substrate layer, and the second interconnect layer, the second TSVs 256a, 256b, and 256c may be different in length from the first TSVs 254a, 254b, 254c, and 254d.

[0079] Figure 3C is a schematic diagram (300c) illustrating an example of a constituent structure formed on a second interconnect layer among a plurality of constituent elements included in a unit pixel based on some implementations of the disclosed technology. The second interconnect layer may be formed on the first interconnect layer.

[0080] The second interconnect layer may be disposed on a second substrate layer distinguished from the first substrate layer. In some implementations, the second interconnect layer may refer to a layer formed to include an insulating material such as silicon oxide.

[0081] The second interconnection layer may include a driving transistor gate 242 , a through interconnect (also referred to as a through wiring) 244 , and a connection electrode 258 .

[0082] In some implementations, the drive transistor gate 242 can be coupled to the floating diffusion (FD) region 214 through a through interconnect 244 .

[0083] The through-interconnect 244 may include a first through-portion 244b contacting the driving transistor gate 242, a second through-portion 244c contacting the floating diffusion (FD) region 214, and a connecting portion 244a for connecting the first through-portion 244b to the second through-portion 244c. The shape of the connecting portion 244a included in the through-interconnect 244 may be varied according to an interconnection layout structure.

[0084] The through interconnect 244 may be formed of or include a metal. In some implementations, the metal may include copper (Cu) or tungsten (W), or a combination of copper (Cu) and tungsten (W).

[0085] The connection electrode 258 may be included in the first electrode of the capacitor 250. In some implementations, the connection electrode 258 may be coupled to the four first TSVs 254a, 254b, 254c, and 254d.

[0086] Since the connection electrode 258 is coupled to the first TSVs 254 a , 254 b , 254 c , and 254 d to form a first electrode, the capacitor 250 may ensure additional capacitance generated between the connection electrode 258 and the second TSVs 256 a , 256 b , and 256 c .

[0087] Figure 4 is a circuit diagram (400) illustrating an example of a unit pixel based on some implementations of the disclosed technology.

[0088] As from Figure 4 As can be seen, the connection relationship between the photoelectric conversion region (PD), transfer transistor (TX), floating diffusion (FD) region, switching transistor (SW), capacitor (C), reset transistor (RST), drive transistor (DX) and selection transistor (SX) included in each unit pixel (PX) is illustrated.

[0089] Figure 4 The photoelectric conversion region (PD) shown in Figure 2 and Figure 3A The photoelectric conversion region shown in Figure 2 212) corresponds to.

[0090] The photoelectric conversion region (PD) may be coupled to the floating diffusion (FD) region through a transfer transistor (TX).

[0091] The transfer transistor (TX) may include Figure 2 and Figure 3B The transfer transistor gate (eg, Figure 2 of 222). Figure 4 The floating diffusion (FD) region shown in FIG. Figure 2 and Figure 3A The floating diffusion region shown in FIG. Figure 2 214).

[0092] The photoelectric conversion region (PD) may generate photocharges corresponding to the incident light during an integration time for accumulating photocharges. In this case, the time during which the photocharges corresponding to the incident light are generated by the photoelectric conversion region (PD) may be referred to as an integration time.

[0093] When a transmission signal (TS) having an activation voltage level is applied to the transfer transistor (TX), photocharges generated by the photoelectric conversion region (PD) may be applied to the floating diffusion (FD) region.

[0094] The transmission signal (TS) may have an activation voltage level or a deactivation voltage level. The transfer transistor (TX) may control movement of photo charges in response to the voltage level of the transmission signal (TS).

[0095] When a transmission signal (TS) having an activation voltage level is applied to the transfer transistor (TX), photo charges generated by the photoelectric conversion region (PD) may be accumulated in the floating diffusion (FD) region.

[0096] The floating diffusion (FD) region may be coupled to a gate (eg, Figure 2 and Figure 3C 242). A voltage signal corresponding to the photocharge accumulated in the floating diffusion (FD) region may be amplified by the driving transistor (DX).

[0097] The drain region of the driving transistor (DX) may be coupled to the selection transistor (SX). The selection transistor (SX) may selectively output the signal amplified by the driving transistor (DX) in response to the selection control signal (SS). The signal output from the selection transistor (SX) may be referred to as a pixel signal (Vout).

[0098] The floating diffusion (FD) region may be coupled to one terminal of the reset transistor (RST) and a first electrode of the capacitor (C) through a switching transistor (SW).

[0099] The switching transistor (SW) may include Figure 2 and Figure 3B The switching transistor gate (eg, Figure 2 224). Figure 4 The capacitor C shown in the figure can be connected with Figure 2 corresponds to the capacitor 250 shown in FIG.

[0100] A first electrode of the capacitor C may be coupled to one terminal of the switching transistor SW and one terminal of the reset transistor RST, and a second electrode may be grounded.

[0101] In a high-illuminance environment, when photocharges exceeding the capacitance of the photoelectric conversion region (PD) are generated, the generated photocharges may overflow into the floating diffusion (FD) region and the capacitor C. In this case, the term "overflow" means that the photocharges move beyond the potential barriers of the transfer transistor (TX) and the switching transistor (SW) to which no activation voltage is applied.

[0102] When the capacitor C is not present Figure 4 When the unit pixel shown in FIG. 1 is used, leakage current may occur due to the leaked overflowing photocharge. The generated leakage current may cause noise to appear in the pixel signal, thereby possibly distorting the pixel signal.

[0103] On the other hand, when the capacitor C is present Figure 4In the unit pixel shown in , the overflowing photocharge can be temporarily stored in the capacitor C, the saturation of the floating diffusion (FD) region can be prevented, and the leakage current can be prevented from occurring.

[0104] In some implementations, the floating diffusion (FD) region may be coupled to or separated from the capacitor C in response to a switching signal (SWS) applied to a switching transistor (SW).

[0105] When the floating diffusion (FD) region is connected to the capacitor C, the total capacitance of the floating diffusion (FD) region can be increased. The conversion gain of the floating diffusion (FD) region can be inversely proportional to the capacitance of the floating diffusion (FD) region. Therefore, in a comparison between a first case in which the capacitor C is connected to the floating diffusion (FD) region and a second case in which the capacitor C is not connected to the floating diffusion (FD) region, under the assumption that the same amount of photocharge is accumulated in the first case and the second case, a smaller pixel signal may be output in the first case compared to the second case. In other words, the capacitor C and the switching transistor SW can adjust the conversion gain of the unit pixel.

[0106] In some implementations, the capacitor C may have a higher capacitance than the floating diffusion (FD) region. Since the capacitor C has a higher capacitance than the floating diffusion (FD) region, the capacitor C may easily store overflowing photocharges received from the floating diffusion (FD) region, so that a change in conversion gain of the floating diffusion (FD) region may be greatly increased.

[0107] The reset transistor (RST) may reset the constituent elements (e.g., floating diffusion (FD) region, photoelectric conversion region (PD), etc.) included in the unit pixel to a predetermined potential level (e.g., pixel voltage VDD). The signal applied to the reset transistor (RST) may be referred to as a reset signal (RS). When the reset signal (RS) has an activation voltage level, each of the transmission signal (TS) and the switch signal (SWS) may have an activation voltage level.

[0108] Figure 5 This is an example of some implementations based on the disclosed technology. Figure 2 FIG. 5 is a cross-sectional view ( 500 ) of an example of some areas of a unit pixel intercepted by a first cutting line AA′.

[0109] In some implementations, a unit pixel may be formed across multiple substrate layers and interconnect layers. For example, a unit pixel may be formed across a first substrate layer 210 , a first interconnect layer 220 , a second substrate layer 230 , and a second interconnect layer 240 .

[0110] The first substrate layer 210 may include a photoelectric conversion region 212, a floating diffusion region 214, and a contact region 216. In some implementations, the first substrate layer 210 may be a silicon substrate doped with N-type impurities or P-type impurities. In some other implementations, the first substrate layer 210 may include an epitaxial layer formed on a silicon substrate.

[0111] The photoelectric conversion region 212 may include an impurity-doped region formed on the first substrate layer 210 .

[0112] The floating diffusion region 214 may include a region doped with conductive impurities different from those of the first substrate layer 210. For example, the floating diffusion region 214 formed on a silicon substrate doped with P-type impurities may include an N-type doped region doped with N-type impurities.

[0113] The first substrate layer 210 may include a contact region 216. The contact region 216 may be doped with impurities different from those of the first substrate layer 210. For example, when the first substrate layer 210 is doped with P-type impurities, the contact region 216 may be doped with N-type impurities. In some implementations, the contact region 216 may be doped with a higher concentration of impurities than the floating diffusion region 214.

[0114] When the contact region 216 is doped with high-concentration impurities, resistance between the contact region 216 and each of the first TSVs 254 a , 254 b , 254 c , and 254 d may be reduced.

[0115] The first interconnection layer 220 may be formed on the first substrate layer 210. For example, the first interconnection layer 220 may include silicon oxide.

[0116] In some implementations, the first interconnect layer 220 may include a first dielectric layer 221. The first dielectric layer 221 may be formed or disposed between the first interconnect layer 220 and the first substrate layer 210. At least a portion of the first dielectric layer 221 may serve as an insulating layer for the transfer transistor gate 222 and the switch transistor gate 224.

[0117] The first interconnect layer 220 may include a transfer transistor gate 222 , a switch transistor gate 224 , a transmission signal line 226 , a switch signal line 228 , and a portion of a capacitor 250 .

[0118] In some implementations, the transfer transistor gate 222 and the switch transistor gate 224 may be formed of or include polysilicon. In addition, the transmission signal line 226 and the switch signal line 228 may be formed of or include a metal such as copper (Cu) or tungsten (W) or a combination of copper (Cu) and tungsten (W).

[0119] The metal line (or metal wiring) formed in the first interconnection layer may include a ground contact portion 252 connected to the second electrode of the capacitor 250. The ground contact portion 252 may be connected to a ground voltage (GND).

[0120] The ground contact portion 252 may be used to illustrate the fact that the ground contact portion 252 is connected to the second TSVs 256a, 256b, and 256c. As can be seen from the cross-sectional view of the unit pixel taken along the first cutting line AA', the ground contact portion 252 may be covered by the first interconnect layer 220 and the second TSVs 256a, 256b, and 256c. In addition, in the device, the ground contact portion 252 may be coupled to the second TSVs 256a, 256b, and 256c without contacting the first TSVs 254a, 254b, 254c, and 254d.

[0121] The transfer transistor gate 222 may be included in Figure 4 The transfer transistor (TX) shown in FIG. 1 and the switch transistor gate 224 may also be included in Figure 4 In the switching transistor (SW) shown in FIG.

[0122] The second substrate layer 230 may be a silicon-on-insulator (SOI) substrate formed on the first interconnect layer 220 .

[0123] The second substrate layer 230 may include a driving transistor (eg, Figure 4 DX), a first terminal region 232 of the drive transistor, a second terminal region 234 of the drive transistor, and a portion of the capacitor 250. The first terminal region 232 of the drive transistor can be coupled to the pixel voltage, and the second terminal region 234 of the drive transistor can be coupled to the select transistor (e.g., Figure 4 SX).

[0124] The second interconnect layer 240 may be formed on the second substrate layer 230. The second dielectric layer 241 may be formed between the second interconnect layer 240 and the second substrate layer 230. In some implementations, the second dielectric layer 241 may be formed only in a local region disposed between the second interconnect layer 240 and the second substrate layer 230. The local region may be a region where the drive transistor DX is formed or disposed.

[0125] The driving transistor gate 242 may include polysilicon. The driving transistor gate 242 may be coupled to the floating diffusion region 214 through a through interconnect 244 .

[0126] The through interconnection 244 may include a first through portion 244b formed to contact the driving transistor gate 242, a second through portion 244c formed to contact the floating diffusion region 214, and a connection portion 244a for connecting the first through portion 244b to the second through portion 244c.

[0127] In some implementations, the capacitor 250 may be formed across the first interconnect layer 220, the second substrate layer 230, and the second interconnect layer 240. The capacitor 250 may be formed to have a metal insulator metal (MIM) structure including a plurality of TSVs 254a, 254b, 254c, 254d, 256a, 256b, and 256c and dielectric regions (e.g., the first dielectric layer 221, the first interconnect layer 220, the second substrate layer 230, and the second interconnect layer 240) disposed between the TSVs 254a, 254b, 254c, 254d, 256a, 256b, and 256c.

[0128] Although not shown in the drawings, an insulating layer may be formed or disposed between each of the TSVs 254a, 254b, 254c, 254d, 256a, 256b, and 256c and each of the dielectric regions 221, 220, 230, and 240. The TSVs 254a, 254b, 254c, 254d, 256a, 256b, and 256c may be formed to be perpendicular to one surface of the first substrate layer 210. In some implementations, the TSVs (254a, 254b, 254c, 254d, 256a, 256b, 256c) may be formed or disposed in a region where the stacked substrate layers (e.g., 210 and 230), the interconnection layers (e.g., 220 and 240), and the first dielectric layer 221 are etched.

[0129] The first TSVs 254a, 254b, 254c, and 254d may be directly coupled to the contact region 216 included in the first substrate layer 210. In addition, the first TSVs 254a, 254b, 254c, and 254d may be interconnected through a connection electrode 258 formed in the second interconnect layer 240. The first TSVs 254a, 254b, 254c, and 254d and the connection electrode 258 may form a first electrode of the capacitor 250.

[0130] The second TSVs 256a, 256b, and 256c may be interconnected through the ground contact portion 252 formed in the first interconnect layer 220. The second TSVs 256a, 256b, and 256c may form a second electrode of the capacitor 250, and the formed second electrode may be grounded.

[0131] As from Figure 5As can be seen, the first TSVs 254 a , 254 b , 254 c , and 254 d and the second TSVs 256 a , 256 b , and 256 c of the capacitor 250 may be formed in an alternating structure.

[0132] Each of the second TSVs 256a, 256b, and 256c may be shorter in vertical length than each of the first TSVs 254a, 254b, 254c, and 254d. Therefore, a portion of the first interconnect layer 220 and a portion of the second interconnect layer 240 may be disposed between the second TSVs (256a, 256b, 256c) and the first TSVs (254a, 254b, 254c, 254d). A portion of the first interconnect layer 220 and a portion of the second interconnect layer 240 may be used as a dielectric region of the capacitor 250.

[0133] Capacitor 250 can be coupled to switching transistor SW through contact region 216. In some implementations, contact region 216 can operate as one terminal of switching transistor SW.

[0134] FIG. 6A to FIG. 6J is a cross-sectional view illustrating an example of a method for forming a unit pixel based on some implementations of the disclosed technology.

[0135] For illustrative purposes, FIG. 6A to FIG. 6J , and thus other implementations are possible. For example, the positions and sizes of the constituent elements used in the device may be different from FIG. 6A to FIG. 6J The position and size are different.

[0136] Reference Fig. 6A , the first substrate layer 210 may include a photoelectric conversion region 212 , a floating diffusion region 214 , and a contact region 216 .

[0137] The photoelectric conversion region 212 , the floating diffusion region 214 , and the contact region 216 may be formed by doping impurities on the first substrate layer 210 .

[0138] In some implementations, the photoelectric conversion region 212 may have a stacked structure doped with N-type impurities and P-type impurities. In addition, each of the floating diffusion region 214 and the contact region 216 may be doped with N-type impurities.

[0139] As from Figure 6B As can be seen from the cross-sectional view of FIG. 2 , the first dielectric layer 221 can be formed or disposed on the first substrate layer 210 , and the transfer transistor gate 222 and the switch transistor gate 224 can be formed or disposed on the first dielectric layer 221 .

[0140] The first dielectric layer 221 may include, for example, silicon oxide. Each of the transfer transistor gate 222 and the switch transistor gate 224 may be formed of or include polysilicon. Each of the transfer transistor gate 222 and the switch transistor gate 224 may be formed by a silicon deposition process.

[0141] As from Figure 6C As can be seen from the cross-sectional view of FIG. 2 , a portion of the first interconnection layer 220 a , the transmission signal line 226 , the switching signal line 228 , and the second TSV patterns 255 a , 255 b , and 255 c may be formed on the first dielectric layer 221 .

[0142] A portion 220a of the first interconnect layer may include a low dielectric constant material such as silicon oxide.

[0143] The transmission signal line 226 , the switching signal line 228 , and the second TSV patterns 255 a , 255 b , and 255 c may be formed by etching a portion of the first interconnection layer 220 a .

[0144] The second TSV patterns 255a, 255b, and 255c may indicate where the second TSV will be formed. In addition, the transmission signal line 226, the switch signal line 228, and the second TSV patterns 255a, 255b, and 255c may be formed of or include the same metal (e.g., copper (Cu) or tungsten (W) or a combination of copper (Cu) and tungsten (W)).

[0145] As from Fig.6D As can be seen from the cross-sectional view of FIG. 2 , a first interconnect layer 220 can be formed, and a second substrate layer 230 can be formed on the first interconnect layer 220. In some implementations, the second substrate layer 230 can be formed of or include polysilicon doped with P-type impurities. The second substrate layer 230 can be formed by a silicon deposition process. The first interconnect layer 220 may include a first dielectric layer 221.

[0146] As from Fig. 6E As can be seen from the cross-sectional view of FIG. 2 , a first terminal region 232 of the driving transistor and a second terminal region 234 of the driving transistor may be formed on the second substrate layer 230 . A second dielectric layer 241 and a driving transistor gate 242 may be formed on the second substrate layer 230 .

[0147] In some implementations, the first terminal region 232 of the driving transistor and the second terminal region 234 of the driving transistor may be doped with impurities complementary to the impurities of the second substrate layer 230. For example, when the second substrate layer 230 is doped with P-type impurities, the first terminal region 232 of the driving transistor and the second terminal region 234 of the driving transistor may be doped with N-type impurities.

[0148] The second dielectric layer 241 may be formed in a region where the driving transistor gate 242 is disposed. The second dielectric layer 241 may include silicon oxide. The driving transistor gate 242 may include polysilicon.

[0149] As from Fig. 6F As can be seen from the cross-sectional view of FIG. 2 , a portion 240 a of the second interconnection layer and a through interconnection pattern (also referred to as a through wiring pattern) 243 b may be formed on the second substrate layer 230 .

[0150] A portion 240a of the second interconnection layer may include a low dielectric constant material such as silicon oxide.The through interconnection pattern 243b may indicate a location of a through interconnection (or through wiring) to be formed.

[0151] As from Figure 6G As can be seen from the cross-sectional view of FIG. 2 , a portion 240b of the second interconnection layer may be stacked to overlap with the through interconnection pattern 243b. According to the thickness of the portion 240b of the second interconnection layer, the lengths of the second TSVs 256a, 256b, and 256c to be formed in subsequent processes may be variously determined.

[0152] As from Figure 6H As can be seen from the cross-sectional view of FIG. 2 , a through interconnection 244 and second TSVs 256 a , 256 b , and 256 c may be formed.

[0153] The through-interconnect 244 may include a first through portion 244 b , a second through portion 244 c , and a connecting portion 244 a for connecting the first through portion 244 b to the second through portion 244 c .

[0154] The first through portion 244b, the second through portion 244c, and the second TSV 256a, 256b, and 256c may be formed by etching the interconnect layer and the substrate layer (e.g., 220, 230, and 240b) and then laminating a metal material on the etched region. In some implementations, the through interconnect 244 and the second TSV 256a, 256b, and 256c may be formed of or include copper (Cu) or tungsten (W), or a combination of copper (Cu) and tungsten (W).

[0155] Second TSVs 256 a , 256 b , and 256 c may be formed at positions corresponding to the second TSV patterns 255 a , 255 b , and 255 c .

[0156] The ground contact portion 252 may be coupled to the second TSVs 256a, 256b, and 256c and may be formed to receive a ground voltage (GND). In some implementations, after forming the second TSVs 256a, 256b, and 256c, the ground contact portion 252 may be formed by an interconnection structure connected to the second TSVs 256a, 256b, and 256c. The second electrode of the capacitor 250 may be grounded through the ground contact portion 252.

[0157] In some other implementations, the ground contact portion may be formed simultaneously with the formation of the second TSV patterns 255 a , 255 b , and 255 c .

[0158] As from Fig.6I As can be seen from the cross-sectional view of FIG. 2 , the capacitor 250 may be formed across the first interconnect layer 220 , the second substrate layer 230 , and a portion 240 c of the second interconnect layer.

[0159] The lengths of the first TSVs 254 a , 254 b , 254 c , and 254 d formed in a subsequent process may be variously determined according to the thickness of the portion 240 c of the second interconnection layer.

[0160] The first TSVs 254a, 254b, 254c, and 254d may be formed by etching substrate layers (eg, 221, 220, 230, 240c) and then stacking a metal material on the etched regions. Since the first dielectric layer 221 is etched, the first TSVs 254a, 254b, 254c, and 254d may be directly coupled to the contact regions 216.

[0161] In some implementations, an insulating layer may be formed between the etched dielectric layer, the etched interconnect layer, the etched substrate layer (eg, 221 , 220 , 230 , 240 c ), and the first TSV ( 254 a , 254 b , 254 c , 254 d ).

[0162] The first TSVs 254a, 254b, 254c, and 254d may be interconnected by a connection electrode 258. The first electrode of the capacitor 250 may include the connection electrode 258 and the first TSVs 254a, 254b, 254c, and 254d.

[0163] Figure 6J is a cross-sectional view illustrating an example of a unit pixel. Figure 6J , the second interconnection layer 240 may be stacked on the capacitor 250 , thereby forming a unit pixel.

[0164] As is apparent from the above description, an image sensing device based on some implementations of the disclosed technology may guarantee a high dynamic range (HDR) while being miniaturized.

[0165] Embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized through the above-mentioned patent documents.

[0166] Those skilled in the art will appreciate that the disclosed technology may be implemented in other specific ways different from those described herein. In addition, claims that are not explicitly presented in the appended claims may be presented as a combination of one embodiment, or may be included as new claims by subsequent amendments after the application is submitted.

[0167] Although a number of exemplary embodiments have been described, it should be understood that modifications and / or enhancements to the disclosed embodiments and other embodiments may be designed based on what is described and / or illustrated in this patent document.

[0168] CROSS-REFERENCE TO RELATED APPLICATIONS

[0169] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2021-0096598, filed on July 22, 2021, the disclosure of which is incorporated by reference in its entirety as a part of the disclosure of this patent document.

Claims

1. An image sensing device, comprising: a first substrate layer, the first substrate layer comprising a photoelectric conversion region and a floating diffusion region, the photoelectric conversion region is used to convert incident light into photocharges, and the floating diffusion region is used to store the photocharges in the floating diffusion region; a first interconnect layer disposed on the first substrate layer and including a switch transistor gate overlapping at least a portion of the floating diffusion region; a second substrate layer, the second substrate layer being disposed on the first interconnect layer; a second interconnect layer, the second interconnect layer being disposed on the second substrate layer; as well as a capacitor electrically coupled to the floating diffusion region through the switching transistor gate, in, The capacitor includes a first electrode and a second electrode, each of the first electrode and the second electrode includes a plurality of vertical through-interconnects interconnected with each other and arranged across the first interconnect layer, the second substrate layer, and the second interconnect layer, wherein the plurality of vertical through-interconnects of the first electrode and the plurality of vertical through-interconnects of the second electrode are formed in an alternating structure, and Wherein, a portion of the first interconnection layer, a portion of the second substrate layer, and a portion of the second interconnection layer are disposed between the vertical through-interconnection of the first electrode and the vertical through-interconnection of the second electrode.

2. The image sensing device according to claim 1, wherein: The first electrode comprises: a plurality of first through silicon vias TSV, the plurality of first through silicon vias TSV being arranged across the first interconnect layer, the second substrate layer, and the second interconnect layer; and A connection electrode is provided in the second interconnection layer and interconnects the first through silicon vias TSV.

3. The image sensing device according to claim 1, wherein: The second electrode comprises: a plurality of second through silicon vias TSVs, the plurality of second through silicon vias TSVs being arranged across the first interconnect layer, the second substrate layer, and the second interconnect layer; and A ground contact portion is provided in the first interconnection layer and is formed to interconnect the second through silicon vias TSV.

4. The image sensing device according to claim 3, wherein: The ground contact portion is coupled to a ground voltage.

5. The image sensing device according to claim 2, wherein: The connection electrode is disposed perpendicular to the first through silicon via TSV.

6. The image sensing device according to claim 2, wherein: The first substrate layer comprises: a contact region overlapping at least a portion of a gate of the switching transistor, The first through silicon via TSV is in contact with the contact area.

7. The image sensing device according to claim 6, wherein: The contact region is doped with impurities at a higher concentration than the floating diffusion region.

8. The image sensing device according to claim 1, wherein: The second interconnect layer includes a drive transistor gate overlapping at least a portion of the photoelectric conversion region; and The floating diffusion region is coupled to the gate of the driving transistor through a through interconnect structure, The through interconnect structure is arranged across the second interconnect layer, the second substrate layer and the first interconnect layer.

9. The image sensing device according to claim 8, wherein: Each of the through interconnect structure, the first electrode, and the second electrode includes at least one of copper (Cu) and tungsten (W).

10. The image sensing device according to claim 1, wherein: The first interconnect layer further includes a transfer transistor gate, and the transfer transistor gate overlaps the photoelectric conversion region along a first side of the transfer transistor gate.

11. The image sensing device according to claim 10, wherein: The transfer transistor gate overlaps the floating diffusion region along a second side of the transfer transistor gate.

12. The image sensing device according to claim 11, wherein: The length of the first side is longer than the length of the second side.

13. An image sensing device, comprising: a first substrate layer, the first substrate layer comprising a photoelectric conversion region and a floating diffusion region, the photoelectric conversion region is used to convert incident light into photocharges, and the floating diffusion region is used to store the photocharges in the floating diffusion region; a first interconnect layer disposed on the first substrate layer and including a transfer transistor gate overlapping at least a portion of the photoelectric conversion region and a switch transistor gate overlapping at least a portion of the floating diffusion region; a second substrate layer disposed on the first interconnect layer and including a first terminal region of a drive transistor and a second terminal region of the drive transistor; a second interconnect layer disposed on the second substrate layer and including a gate of the drive transistor, the gate of the drive transistor being coupled to the floating diffusion region through a through-interconnect structure; as well as a capacitor, the capacitor being arranged across the first interconnect layer, the second substrate layer, and the second interconnect layer, wherein the capacitor is electrically connected to the floating diffusion region through the gate of the switching transistor, wherein the capacitor comprises a first electrode and a second electrode, each of the first electrode and the second electrode comprises a plurality of vertical through interconnects interconnected with each other and arranged across the first interconnect layer, the second substrate layer and the second interconnect layer, and Wherein, the plurality of vertical through-interconnects of the first electrode and the plurality of vertical through-interconnects of the second electrode are formed into an alternating structure.

14. The image sensing device according to claim 13, wherein: The first electrode comprises: A first through silicon via TSV, the first through silicon via TSV being arranged across the first interconnect layer, the second substrate layer, and the second interconnect layer; and a connecting electrode disposed in the second interconnect layer; and Wherein, the second electrode comprises: a second through silicon via TSV, the second through silicon via TSV being arranged across the first interconnect layer, the second substrate layer, and the second interconnect layer; and A ground contact portion is provided in the first interconnect layer.

15. The image sensing device according to claim 14, wherein: The capacitor further comprises: a dielectric region disposed between the first electrode and the second electrode, The dielectric region includes a portion of the first interconnect layer, a portion of the second substrate layer, and a portion of the second interconnect layer.

16. The image sensing device according to claim 14, wherein: The ground contact portion is coupled to a ground voltage.

17. The image sensing device according to claim 14, wherein: The first electrode is electrically coupled to the floating diffusion region through the switching transistor gate.

18. The image sensing device according to claim 14, wherein: The transfer transistor gate overlaps the floating diffusion region such that a length of a side of the transfer transistor gate overlapping the photoelectric conversion region is longer than a length of another side of the transfer transistor gate overlapping the floating diffusion region.

19. The image sensing device according to claim 14, wherein: The first substrate layer further includes a contact region doped with an impurity different from an impurity of the first substrate layer and overlapping at least a portion of the gate of the switching transistor.

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