Electronic device

Abstract

This disclosure provides an electronic device including a substrate, signal lines, and spacers. The signal lines are disposed on the substrate and include at least one curved line segment. The spacers are disposed on the substrate and are correspondingly disposed to the at least one curved line segment.

Description

Technical Field

[0001] This disclosure relates to an electronic device. Background Technology

[0002] Most devices (such as displays or optical switches) have multiple spacers randomly arranged among pixels to support cell gaps. These spacers are typically shielded by light-blocking patterns to reduce light leakage. When a device needs to increase its aperture ratio (or transmittance), the space for these spacers becomes limited. Summary of the Invention

[0003] This disclosure provides an electronic device that can improve aperture ratio or transmittance.

[0004] According to embodiments disclosed herein, an electronic device includes a substrate, signal lines, and spacers. The signal lines are disposed on the substrate and include at least one curved line segment. The spacers are disposed on the substrate and correspondingly disposed to the at least one curved line segment.

[0005] To make the above-mentioned features and advantages disclosed herein more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0006] Figure 1 , Figure 5 as well as Figures 9A to 9C This is a partial top view schematic diagram of an electronic device according to some embodiments of the present disclosure;

[0007] Figure 2 yes Figure 1 A magnified schematic diagram of the middle region R;

[0008] Figure 3 as well as Figure 4 They are Figure 1 Midsection line A-A' and Figure 2 A schematic diagram of the cross section along the center section line B-B';

[0009] Figures 6A to 6D , Figure 8A as well as Figure 8B It is a top view schematic diagram showing the various relative arrangements of signal lines and spacers;

[0010] Figure 7 This is a schematic diagram showing the relative arrangement of liquid crystal molecules and spacers. Detailed Implementation

[0011] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0012] Throughout this specification and the appended claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same elements. This document is not intended to distinguish between elements that have the same function but different names. In the following specification and claims, words such as "containing" and "comprising" are open-ended terms and should therefore be interpreted as "containing but not limited to...".

[0013] The directional terms used herein, such as "up," "down," "front," "back," "left," and "right," are for reference only when referring to the accompanying drawings. Therefore, the directional terms used are illustrative and not intended to limit this disclosure. In the accompanying drawings, each figure illustrates general features of the methods, structures, and / or materials used in specific embodiments. However, these figures should not be construed as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative dimensions, thicknesses, and locations of various films, regions, and / or structures may be reduced or enlarged.

[0014] In this disclosure, a structure (or layer, element, substrate) located on / above another structure (or layer, element, substrate) can refer to the two structures being adjacent and directly connected, or to the two structures being adjacent but not directly connected. Indirect connection means that there is at least one intermediate structure (or intermediate layer, intermediate element, intermediate substrate, intermediate spacer) between the two structures, with the lower surface of one structure adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure can be composed of a single or multiple solid or non-solid structures, without limitation. In this disclosure, when a structure is placed "on" other structures, it may mean that the structure is "directly" on other structures, or that the structure is "indirectly" on other structures, meaning that at least one structure is sandwiched between the structure and other structures.

[0015] The terms “approximately,” “equal to,” “same,” “substantially,” or “roughly” are generally interpreted as being within 20% of a given value or range, or as being within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range.

[0016] The ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify elements, do not in themselves imply or represent any prior ordinal number of that element (or those elements), nor do they represent the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another element with the same name. The claims and specification may not use the same terminology; therefore, a first element in the specification may be a second element in the claims.

[0017] The electrical connections or couplings described in this disclosure can refer to direct or indirect connections. In the case of a direct connection, the endpoints of the components in two circuits are directly connected or connected to each other by a conductor segment. In the case of an indirect connection, there is a switch, diode, capacitor, inductor, resistor, other suitable components, or combinations of the above components between the endpoints of the components in two circuits, but not limited to these.

[0018] In this disclosure, the thickness, length, and width can be measured using an optical microscope (OM), while thickness or width can be measured from cross-sectional images in an electron microscope, but is not limited to these methods. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. Additionally, the terms "equal to," "equivalent to," "identical," "substantially," or "approximately" used in this disclosure generally mean falling within 10% of a given value or range. Moreover, the phrases "given range is from a first value to a second value" or "given range falls within the range of the first value to the second value" indicate that the given range includes the first value, the second value, and other values ​​in between. If the first direction is perpendicular to the second direction, the angle between the first and second directions can be between 80 and 100 degrees; if the first direction is parallel to the second direction, the angle between the first and second directions can be between 0 and 10 degrees.

[0019] It should be understood that the features in the following embodiments can be replaced, recombined, or mixed to complete other embodiments without departing from the spirit of this disclosure. Features between embodiments can be arbitrarily mixed and combined as long as they do not violate the spirit of the invention or conflict with it.

[0020] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that these terms, for example, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0021] In this disclosure, the electronic device may include, but is not limited to, a display device, a backlight device, an antenna device, a sensing device, or a splicing device. The electronic device may be a bendable or flexible electronic device. The display device may be a non-emissive display device or a self-emissive display device. The electronic device may include, for example, liquid crystal, light-emitting diode, fluorescence, phosphorescence, quantum dot (QD), other suitable display media, or combinations thereof. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device. The sensing device may be a sensing device for capacitance, light, heat, or ultrasound, but is not limited to these. In this disclosure, the electronic device may include electronic components, which may include passive and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light-emitting diode or a photodiode. The light-emitting diode may include, for example, an organic light-emitting diode (OLED), a mini LED, a micro LED, or a quantum dot LED, but is not limited to these. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any arrangement or combination of the aforementioned, but is not limited thereto. Furthermore, the electronic device may be rectangular, circular, polygonal, have curved edges, or other suitable shapes. The electronic device may have a drive system, control system, light source system, etc., and other peripheral systems to support the display device, antenna device, wearable device (e.g., including augmented reality or virtual reality), in-vehicle device (e.g., including a car windshield), or splicing device.

[0022] It should be noted that the technical solutions provided in the different embodiments below can be substituted for, combined or mixed with each other to constitute another embodiment without violating the spirit of this disclosure.

[0023] Figure 1 , Figure 5 as well as Figures 9A to 9C This is a partial top view schematic diagram of an electronic device according to some embodiments of the present disclosure. Figure 2 yes Figure 1 A magnified schematic diagram of the middle region R. Figure 3 as well as Figure 4 They are Figure 1 Midsection line A-A' and Figure 2 A schematic diagram of the cross section along the midline B-B'. Figures 6A to 6D , Figure 8A as well as Figure 8B This is a top view diagram showing the various relative arrangements of signal lines and spacers. Figure 7This is a schematic diagram showing the relative arrangement of liquid crystal molecules and spacers.

[0024] Please refer to Figures 1 to 4 The electronic device 1 may include a substrate 10, signal lines 12, and spacers 14. The signal lines 12 are disposed on the substrate 10 and include at least one curved line segment (e.g., ...). Figure 5 The spacer 14 is disposed on the substrate 10 and corresponds to the at least one curved line segment 120, that is, the spacer 14 at least partially overlaps with the at least one curved line segment 120 in the top view direction (e.g., direction D3) of the electronic device 1. The electronic device 1 disclosed herein can be used, for example, in augmented reality and for dimming (light switching) to increase the contrast of the display, but is not limited thereto. The “curve” in this disclosure is, for example, a non-linear line segment or a line segment with at least one radius of curvature, and the curve may be, for example, S-shaped or a line segment with at least one inflection point.

[0025] In detail, the substrate 10 can be a rigid substrate or a flexible substrate. The material of the substrate 10 includes, for example, glass, quartz, ceramic, sapphire, or plastic, but is not limited thereto. In some embodiments, the substrate 10 can be a flexible substrate, and the material of the substrate 10 may include polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), other suitable flexible materials, or combinations of the foregoing materials, but is not limited thereto.

[0026] Signal line 12 may be, for example, a scan line, a data line, or other type of signal line. The material of signal line 12 may include metal, metal alloy, metal oxide, transparent conductive material, any conductor, or a combination thereof, but is not limited thereto. In some embodiments, signal line 12 may be formed of a highly conductive material such as metal or metal alloy to reduce impedance or facilitate signal transmission. In other embodiments, signal line 12 may be formed of a transparent conductive material, which can reduce optical interference (e.g., diffraction) to improve the display quality of the electronic device.

[0027] Figure 1 The diagram schematically illustrates that signal line 12 comprises multiple curved segments, which are arranged in direction D1 and connected to form a wavy shape. However, it should be understood that the type of signal line 12, the number of curved segments, the arrangement of the curved segments, or the shape formed by the connection of the curved segments can be changed according to actual needs, and not necessarily... Figure 1The embodiments shown are limited to those shown. In other embodiments, the electronic device further includes signal lines 13 extending generally in another direction (e.g., direction D2), and a plurality of curved segments of signal lines 13 may be arranged and interconnected in direction D2, but are not limited thereto. In this disclosure, direction D1 is, for example, the extension direction of signal line 12, direction D2 is, for example, the extension direction of signal line 13, direction D2 and direction D3 may be generally perpendicular, direction D3 is, for example, parallel to the normal direction of the surface of substrate 10, and direction D3 may be perpendicular to direction D1 and direction D2.

[0028] Spacer 14 may include a main spacer, a secondary spacer, or a combination thereof. The opposite ends of the main spacer may respectively contact the active element array substrate SUB-A and the opposing substrate SUB-B, such as... Figure 4 As shown in spacer 15. One end of the secondary spacer can contact one of the active component array substrate SUB-A and the opposing substrate SUB-B, and the other end of the secondary spacer does not contact the other of the active component array substrate SUB-A and the opposing substrate SUB-B when the electronic device 1 is not pressed, as shown in the figure. Figure 3 The spacer 14 is shown. The active element array substrate SUB-A may include, for example, a substrate 10 and film layers (e.g., insulating layer, conductive layer, and semiconductor layer) on the substrate 10, and the opposing substrate SUB-B may include, for example, a substrate 11 and film layers (e.g., insulating layer and conductive layer) on the substrate 11. In some embodiments, the maximum thickness of the secondary spacer (e.g., ...) Figure 3 The maximum thickness T14 of the intermediate spacer 14 in direction D3 is less than the maximum thickness of the main spacer (e.g., Figure 4 The maximum thickness T15 of the intermediate spacer 15 in direction D3. In other embodiments, the main spacer and / or the secondary spacer may be disposed corresponding to another support element (not shown). For example, when the main spacer is disposed on the active element array substrate, a support element may be disposed on the opposing substrate and at least partially overlap with the main spacer in direction D3, that is, one end of the main spacer contacts the support element at the other end of the substrate; another support element may also be disposed corresponding to the secondary spacer, but this disclosure is not limited thereto.

[0029] The electronic device 1 may include a plurality of spacers 14. In this embodiment, the plurality of spacers 14 may be, for example, a plurality of secondary spacers, but is not limited thereto. In other embodiments, although not shown, the plurality of spacers 14 may be a plurality of primary spacers; or, the plurality of spacers 14 may be a combination of a plurality of primary spacers and a plurality of secondary spacers, i.e., some spacers 14 are primary spacers and others are secondary spacers.

[0030] Multiple spacers 14 can be configured to correspond to multiple curved line segments of the signal line 12. Figure 1For example, multiple spacers 14 can correspond to the peaks C, troughs T, or combinations thereof of the signal line 12. That is, multiple spacers 14 can overlap with multiple peaks C of the signal line 12; or, multiple spacers 14 can overlap with multiple troughs T of the signal line 12; or, multiple spacers 14 can overlap with multiple peaks C and multiple troughs T of a wave shape. However, it should be understood that the relative arrangement of the multiple spacers 14 and the multiple curved line segments can be changed according to actual needs, and not necessarily based on... Figure 1 The display is limited.

[0031] By designing the spacers 14 to correspond with the signal lines 12, the spacers 14 can be shielded using the signal lines 12 or a light-shielding pattern (not shown) that shields the signal lines 12, thereby increasing the space and density of the spacers. Therefore, the electronic device 1 can maintain the required resilience or uniformity of the gaps while maintaining the required resolution and / or aperture ratio.

[0032] In some embodiments, the electronic device 1 may further include a dielectric layer ML and a substrate 11, with substrate 10 and substrate 11 correspondingly disposed. The dielectric layer ML is disposed between substrate 10 and substrate 11 and has an alignment direction DA. The at least one curved line segment 120 of the signal line 12 extends along a direction DE, the direction DE having an angle θ with the alignment direction DA, for example greater than or equal to 0 degrees and less than or equal to 20 degrees.

[0033] For example, the dielectric layer ML may include, but is not limited to, liquid crystal materials. Please refer to [reference needed]. Figure 3 and Figure 4 The electronic device 1 may further include alignment layers AL1 and AL2, which are respectively disposed on opposite sides of the dielectric layer ML to control the alignment direction DA of the dielectric layer ML. The alignment direction DA of the dielectric layer ML can be measured using instruments such as a polarimeter (e.g., AxoScan) or a phase difference measurement system (e.g., RETS), but is not limited thereto. In other embodiments, the alignment direction can be measured by observing drag marks around the spacer using an optical microscope. Please refer to [reference needed]. Figure 6A The extension direction (direction DE) of the curve segment 120 can be the tangent direction TD of the vertex A of the curve segment 120; or, the extension direction (direction DE) of the curve segment 120 can be the major axis direction L around the smallest rectangle RT of the curve segment 120.

[0034] like Figure 7As shown, liquid crystal molecules M adjacent to spacer 14 in dielectric layer ML are easily affected by the terrain of spacer 14, leading to alignment anomalies / defects (mura) and causing light leakage LL1. Furthermore, liquid crystal molecules M on the side opposite to the alignment direction DA adjacent to spacer 14 are prone to alignment anomalies / defects due to insufficient friction, causing light leakage LL2. The visibility of light leakage LL1 can be reduced by shielding spacer 14 with signal line 12 or a light-shielding pattern (not shown) overlapping with signal line 12. Alternatively, the affected area of ​​light leakage LL2 can be reduced by a design of 0 degrees ≤ included angle θ ≤ 20 degrees, or light leakage LL2 can be shielded with a light-shielding pattern without significantly affecting the aperture ratio.

[0035] Please refer to Figure 2 and Figure 4 In some embodiments, the electronic device 1 may further include an active element AD and another spacer 15. The active element AD is disposed on the substrate 10 and electrically connected to the signal line 12. The active element AD may include, but is not limited to, a transistor. For example, the active element AD may include a gate GE, a semiconductor pattern CH, a source SE, and a drain DE, but is not limited to. The region RAD in which the active element AD is located is defined, for example, by a minimum rectangular frame surrounding the gate GE, the semiconductor pattern CH, the source SE, and the drain DE.

[0036] The spacer 15 overlaps at least a portion of the active element AD, meaning that the spacer 15 and the region RAD containing the active element AD at least partially overlap in direction D3. This design, where the spacer 15 at least partially overlaps with the active element AD, allows the spacer 15 to be shielded using a light-shielding pattern (not shown) that shields the active element AD, thus increasing the space available for the spacer. Therefore, the electronic device 1 can maintain the required resilience or uniformity of the gap while maintaining the desired resolution and / or aperture ratio.

[0037] The spacers 15 may include primary spacers, secondary spacers, or combinations thereof. The electronic device 1 may include a plurality of spacers 15. In this embodiment, the plurality of spacers 15 may be, for example, a plurality of primary spacers, but is not limited thereto. In other embodiments, although not shown, the plurality of spacers 15 may be a plurality of secondary spacers; or, the plurality of spacers 15 may be a combination of a plurality of primary spacers and a plurality of secondary spacers, i.e., some spacers 15 are primary spacers, and others are secondary spacers.

[0038] Depending on the specific requirements, electronic device 1 may also include other components or films. For example, such as Figure 3 as well as Figure 4As shown, the electronic device 1 may also include a light-shielding layer LS, an insulating layer BF, a semiconductor layer SL, an insulating layer GI, a first conductive layer C1, an insulating layer ILD, a second conductive layer C2, an insulating layer PLN, a third conductive layer C3, and a fourth conductive layer C4, but is not limited thereto. The electronic device 1 may add or remove one or more components / film layers according to different needs.

[0039] Active element array substrate SUB-A includes, for example, substrate 10, light-shielding layer LS, insulating layer BF, semiconductor layer SL, insulating layer GI, first conductive layer C1, insulating layer ILD, second conductive layer C2, insulating layer PLN, third conductive layer C3, and alignment layer AL1. Opposing substrate SUB-B includes, for example, substrate 11, fourth conductive layer C4, and alignment layer AL2.

[0040] A light-shielding layer LS is disposed on the substrate 10. The light-shielding layer LS may be formed of a reflective material (such as metal or metal alloy) or a light-absorbing material (such as a black matrix). The light-shielding layer LS may include a light-shielding pattern LSP. The light-shielding pattern LSP may be disposed corresponding to the channel region RCH of the semiconductor layer SL, that is, the light-shielding pattern LSP and the channel region RCH overlap in the direction D3.

[0041] An insulating layer BF is disposed on the substrate 10 and covers the light-shielding layer LS. The material of the insulating layer BF may include inorganic insulating materials, such as silicon oxide or silicon nitride, but is not limited thereto.

[0042] A semiconductor layer SL is disposed on an insulating layer BF. The material of the semiconductor layer SL may include oxide semiconductor materials, such as indium gallium zinc oxide (IGZO), but is not limited thereto. In other embodiments, the material of the semiconductor layer SL may include amorphous silicon, polysilicon, metal oxide, or combinations thereof (e.g., when there are multiple active elements). The semiconductor layer SL may include a semiconductor pattern CH. The semiconductor pattern CH may include a channel region RCH, a source region RSE, and a drain region RDE, but is not limited thereto.

[0043] An insulating layer GI is disposed on the semiconductor layer SL. For example, the material of the insulating layer GI may include inorganic materials, such as silicon oxide or silicon nitride, but is not limited thereto.

[0044] A first conductive layer C1 is disposed on an insulating layer GI. For example, the material of the first conductive layer C1 includes a metal or a metal stack, such as aluminum, molybdenum, or titanium / aluminum / titanium. The first conductive layer C1 may include a gate GE, signal lines (such as...) Figure 2Signal line 13 shown is an example, but not limited to. The gate GE corresponds to the channel region RCH, that is, the gate GE and the channel region RCH overlap in direction D3. Signal line 13 can be a scan line, a data line, or other types of signal line. Figure 1 The diagram schematically illustrates that signal line 13 comprises multiple curved segments, which are arranged in direction D2 and connected to form a wavy shape. However, it should be understood that the type of signal line 13, the number of curved segments, the arrangement of the curved segments, or the shape formed by the connection of the curved segments can be changed according to actual needs, and not necessarily... Figure 1 The display is limited.

[0045] An insulating layer ILD is disposed on the first conductive layer C1. For example, the material of the insulating layer ILD may include inorganic materials such as silicon oxide or silicon nitride, but is not limited thereto. In some embodiments, although not shown, the insulating layer ILD may be a stack of multiple insulating materials.

[0046] The second conductive layer C2 is disposed on the insulating layer ILD. For example, the material of the second conductive layer C2 includes metals, metal oxides, or metal stacks, such as aluminum, molybdenum, or titanium / aluminum / titanium, indium tin oxide. The second conductive layer C2 may include, but is not limited to, a source SE, a drain DE, and signal lines (such as signal line 12). The source SE penetrates the insulating layer ILD and the insulating layer GI and is connected to the source region RSE. The drain DE penetrates the insulating layer ILD and the insulating layer GI and is connected to the drain region RDE.

[0047] An insulating layer PLN is disposed on the insulating layer ILD and covers the second conductive layer C2. For example, the material of the insulating layer PLN includes organic or polymeric materials, such as polymethyl methacrylate (PMMA), epoxy resin, acylic-based resin, silicone, polyimide polymer, or combinations thereof, but is not limited thereto. In some embodiments, although not shown, the insulating layer PLN may be a stacked layer of multiple organic or polymeric materials.

[0048] A third conductive layer C3 is disposed on the insulating layer PLN. The material of the third conductive layer C3 includes, but is not limited to, transparent conductive materials such as metal oxides. The third conductive layer C3 may include, but is not limited to, the pixel electrode PE. The pixel electrode PE penetrates the insulating layer PLN and is connected to the drain electrode DE.

[0049] Alignment layer AL1 is disposed on the third conductive layer C3. Alignment layer AL1 can be a photoalignment layer, but is not limited thereto.

[0050] A fourth conductive layer C4 and an alignment layer AL2 are sequentially disposed on the surface of substrate 11 facing the active element array substrate SUB-A. Substrate 11 can be a rigid substrate or a flexible substrate. The material of substrate 11 can be the same as or similar to the material of substrate 10, and will not be described in detail here. The material of the fourth conductive layer C4 includes transparent conductive materials, such as metal oxides, but is not limited thereto. The fourth conductive layer C4 can be a conductive layer covering the entire surface, but is not limited thereto. The alignment layer AL2 can be a photoalignment layer, but is not limited thereto.

[0051] Please refer to Figure 5 Electronic device 1A and Figure 1 The main difference in the electronic device 1 is that multiple spacers 14 are respectively arranged to overlap with signal lines 12 and 13. Furthermore, Figure 5 The alignment direction DA of the intermediate dielectric layer (not shown) is different from that of the intermediate dielectric layer. Figure 1 The alignment direction DA of the dielectric layer (not shown) is changed according to the alignment direction DA of the dielectric layer to satisfy the design that the angle between the extension direction (direction DE) of the curve segment 120 of the signal line 12 (or the curve segment 130 of the signal line 13) and the alignment direction DA is greater than or equal to 0 degrees and less than or equal to 20 degrees.

[0052] In some embodiments, the spacer 14 overlapping the signal line 12 (or signal line 13) may be a single spacer (such as...). Figure 6A (As shown) to have greater supporting strength; or, spacer 14 can be a group of spacers (such as... Figures 6B to 6D (As shown) to reduce the risk of spacer peeling.

[0053] In some embodiments, the spacer 14 may be linear (e.g., ...). Figure 5 As shown), curved (as shown) Figure 6A , Figure 6B As shown), dotted (e.g.) Figure 6C , Figure 6D (as shown in circles or polygons) or combinations thereof, to provide different prepressing heights.

[0054] In some embodiments, for the purpose of shielding Figure 7 Light leakage LL2 is caused by insufficient friction on the DA side of the intermediate spacer 14, which is opposite to the alignment direction, resulting in an alignment abnormality / defect. Figure 8A as well as Figure 8BAs shown, the relative arrangement of spacer 14 and signal line 12 (or signal line 13) can be changed according to the alignment direction DA of the dielectric layer (not shown) so that the rubbing trace area RT (i.e., the area of ​​spacer 14 facing away from the alignment direction DA where alignment is abnormal / defective due to insufficient friction) falls in the area RAD where the active element is located, so as to use the light-shielding pattern (not shown) of the shielding area RAD to shield. Figure 7 Light leakage LL2 in the middle.

[0055] In some embodiments, such as Figures 9A to 9C As shown, signal lines 12 and / or 13 can be straight lines or broken lines, and the area enclosed by two adjacent signal lines 12 and two adjacent signal lines 13 can be quadrilaterals, hexagons, or other polygons. Figures 9A to 9C For reference, see below. Figure 1 or Figure 5 The design and / or the angle between the extension direction (direction DE) and the alignment direction DA of the signal line 12 is greater than or equal to 0 degrees and less than or equal to 20 degrees. Figure 8A or Figure 8B The design of the alignment trace area RT falling within the area RAD is intended to reduce light leakage caused by the placement of spacer 14.

[0056] In embodiments of the present invention, by designing spacers corresponding to signal lines, the spacers can be shielded using the signal lines or light-shielding patterns that shield the signal lines, thereby increasing the space for spacer placement and eliminating the need to reduce the number or density of spacers based on resolution and / or aperture ratio considerations. Therefore, the electronic device can maintain the required resilience or uniformity of the gaps while maintaining the desired resolution and / or aperture ratio.

[0057] The above embodiments are only used to illustrate the technical solutions disclosed herein, and are not intended to limit them. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments disclosed herein.

[0058] While the embodiments and advantages of this disclosure have been described above, it should be understood that anyone skilled in the art can make changes, substitutions, and modifications without departing from the spirit and scope of this disclosure, and features between the embodiments can be arbitrarily mixed and substituted to form other new embodiments. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps described in the specific embodiments of the specification. Anyone skilled in the art can understand from the content of this disclosure that current or future developed processes, machines, manufacturing, material composition, apparatus, methods, and steps can be used according to this disclosure as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this disclosure also includes combinations of various claims and embodiments. The scope of protection of this disclosure shall be determined by the appended claims.

Claims

1. An electronic device, characterized by comprising: include: substrate; A signal line is disposed on the substrate and includes at least one curved line segment; as well as A spacer is disposed on the substrate and corresponding to the at least one curved line segment, wherein the orthogonal projection of the spacer on the substrate is completely located within the orthogonal projection of the at least one curved line segment on the substrate. as well as A dielectric layer is disposed on the substrate and has an alignment direction, wherein at least one curved segment of the signal line extends along a direction, the direction having an angle with the alignment direction, the angle being greater than or equal to 0 degrees and less than or equal to 20 degrees. 2.The electronic device of claim 1, wherein, The spacers include primary spacers, secondary spacers, or combinations thereof. 3.The electronic device of claim 1, wherein, The dielectric layer includes a liquid crystal material. 4.The electronic device of claim 1, wherein, Also includes: An active component is disposed on the substrate and electrically connected to the signal line; as well as Another spacer, wherein the other spacer overlaps with at least a portion of the active element. 5.The electronic device of claim 1, wherein, The electronic device includes a plurality of spacers, and the at least one curved line segment overlaps with a plurality of the plurality of spacers. 6.The electronic device of claim 1, wherein, The spacers can be straight, curved, dotted, or a combination thereof. 7.The electronic device of claim 1, wherein, The signal lines are either scan lines or data lines. 8.The electronic device of claim 1, wherein, Also includes: An alignment layer is disposed on the substrate, wherein the alignment layer is a photoalignment layer. 9.The electronic device of claim 1, wherein, The electronic device includes multiple spacers, and the multiple spacers correspond to the peaks, troughs, or combinations thereof of the signal lines.

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