Semiconductor devices and methods for manufacturing them

Abstract

This invention discloses a semiconductor device and a method for manufacturing the same. The semiconductor device may include a first capacitor and a second capacitor. The first capacitor may include a first lower electrode, a first upper electrode, and a first dielectric layer disposed between the first lower electrode and the first upper electrode at a first height. The second capacitor may be positioned spaced apart from the first capacitor. The second capacitor may include a second lower electrode, a second upper electrode, and a second dielectric layer disposed between the second lower electrode and the second upper electrode at a second height different from the first height.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean application No. 10-2021-0095796, filed on July 21, 2021, with the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0003] The various embodiments may generally relate to semiconductor devices and methods of manufacturing them, and more specifically, to capacitors and methods of manufacturing capacitors. Background Technology

[0004] Recently, due to advancements in electronic technology, the miniaturization of semiconductor devices has progressed rapidly. Consequently, the patterns in electronic devices have become more intricate. Furthermore, various structures and methods can be developed to improve the operational reliability of semiconductor devices. Summary of the Invention

[0005] In embodiments of this disclosure, the semiconductor device may include a first capacitor and a second capacitor. The first capacitor may include a first lower electrode, a first upper electrode, and a first dielectric layer disposed between the first lower electrode and the first upper electrode at a first height. The second capacitor may be positioned spaced apart from the first capacitor. The second capacitor may include a second lower electrode, a second upper electrode, and a second dielectric layer disposed between the second lower electrode and the second upper electrode at a second height different from the first height.

[0006] In embodiments of this disclosure, according to a method of manufacturing a semiconductor device, a first-1 conductive pattern and a first-2 conductive pattern can be formed through a first insulating layer. A second conductive pattern can electrically contact the first-1 conductive pattern. The second conductive pattern can have a cylindrical shape including a closed lower surface and an open upper surface. A first dielectric layer can be formed on the second conductive pattern. A second insulating layer can be formed on the first dielectric layer. A third-1 conductive pattern and a third-2 conductive pattern can be formed in the second insulating layer. The third-1 conductive pattern can be configured to contact the first dielectric layer. The third-2 conductive pattern can be configured to contact the first-2 conductive pattern. A fourth conductive pattern can be formed on the second insulating layer. The fourth conductive pattern can be configured to electrically contact the third-2 conductive pattern. The fourth conductive pattern can have a cylindrical shape including a closed lower surface and an open upper surface. A second dielectric layer can be formed on the fourth conductive pattern. A third insulating layer can be formed on the second dielectric layer. A fifth-1 conductive pattern and a fifth-2 conductive pattern can be formed in the third insulating layer. The fifth-1 conductive pattern can be configured to contact the third-1 conductive pattern. The 5-2 conductive pattern can be configured to contact the second dielectric layer. Attached Figure Description

[0007] The above and other aspects, features, and advantages of the subject matter of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 This is a perspective view showing a semiconductor device according to various embodiments;

[0009] Figure 2A and Figure 2B This is a view illustrating a semiconductor device according to various embodiments;

[0010] Figures 3A to 3H This is a cross-sectional view showing a capacitor according to various embodiments;

[0011] Figures 4A to 4L This is a plan view illustrating a method of forming a capacitor according to various embodiments;

[0012] Figures 5A to 5L This is a cross-sectional view illustrating a method of forming a capacitor according to various embodiments;

[0013] Figure 6 This is a block diagram illustrating a storage system according to various embodiments;

[0014] Figure 7 This is a block diagram illustrating a storage system according to various embodiments;

[0015] Figure 8 This is a block diagram illustrating a computing system according to various embodiments; and

[0016] Figure 9 This is a block diagram illustrating a computing system according to various embodiments. Detailed Implementation

[0017] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. The drawings are schematic illustrations of various embodiments (and intermediate structures). Therefore, variations in the illustrated configurations and shapes can be expected as, for example, due to manufacturing techniques and / or tolerances. Consequently, the described embodiments should not be construed as limited to the specific configurations and shapes illustrated herein, but may include deviations in configuration and shape that do not depart from the spirit and scope of the invention as defined by the appended claims.

[0018] The invention has been described herein with reference to cross-sectional and / or plan views of preferred embodiments. However, the embodiments of the invention should not be construed as limiting the inventive concept. Although a few embodiments of the invention have been shown and described, those skilled in the art will understand that changes can be made to these embodiments without departing from the principles and spirit of the invention.

[0019] Figure 1This is a perspective view illustrating a semiconductor device according to various embodiments, and Figure 2A and Figure 2B This is a view illustrating a semiconductor device according to various embodiments. Figure 2A This is a plan view illustrating a semiconductor device according to various embodiments. Figure 2B It is along Figure 2A The sectional view intercepted by line A-A' in the diagram.

[0020] refer to Figure 1 , Figure 2A and Figure 2B The semiconductor device may include multiple capacitors CAP1, CAP2 and CAP3.

[0021] Each of capacitors CAP1, CAP2, and CAP3 may have a rod shape extending in a first direction. Capacitors CAP1, CAP2, and CAP3 may include lower electrodes LE1, LE2, and LE3, dielectric layers CS1, CS2, and CS3, and upper electrodes UE1, UE2, and UE3. Lower electrodes LE1, LE2, and LE3 may include polysilicon, metals, metal nitrides, conductive metal oxides, combinations thereof, etc. For example, lower electrodes LE1, LE2, and LE3 may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO2), iridium oxide (IrO2), combinations thereof, etc. Dielectric layers CS1, CS2, and CS3 may have a single-layer or multi-layer structure. Dielectric layers CS1, CS2, and CS3 may include materials with a dielectric constant higher than silicon oxide. For example, dielectric layers CS1, CS2, and CS3 may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), titanium strontium oxide (SrTiO3), etc. Upper electrodes UE1, UE2, and UE3 may include (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO2), iridium oxide (IrO2), and combinations thereof.

[0022] In various embodiments, capacitors CAP1, CAP2, and CAP3 can be classified as a first capacitor CAP1, a second capacitor CAP2, and a third capacitor CAP3 based on the location of the dielectric layers. The first capacitor CAP1 may include a first dielectric layer CS1 corresponding to the lower layer. The second capacitor CAP2 may include a second dielectric layer CS2 corresponding to the middle layer. The third capacitor CAP3 may include a third dielectric layer CS3 corresponding to the upper layer.

[0023] Capacitors CAP1, CAP2, and CAP3 may be spaced apart from each other along a second direction and a third direction. The second direction and the third direction may be perpendicular to each other, and both directions may be perpendicular to the first direction. In various embodiments, a plurality of first capacitors CAP1, a plurality of second capacitors CAP2, and a plurality of third capacitors CAP3 may be spaced apart from each other along the second direction and the third direction. For example, the first capacitors CAP1, CAP2, and CAP3 in the first row may be arranged alternately with uniform gaps along the second direction. The first capacitors CAP1, CAP2, and CAP3 in the second row may be arranged alternately with uniform gaps along the second direction. The third capacitors CAP3 in the second row may be arranged to fill the space between the first capacitors CAP1 and CAP2 in the first row. The first capacitors CAP1 in the second row may be arranged to fill the space between the second capacitors CAP2 and CAP3 in the first row. The second capacitors CAP2 in the second row may be arranged to fill the space between the third capacitors CAP3 and CAP1 in the first row.

[0024] The positions and order of capacitors CAP1, CAP2, and CAP3 in the third row can be basically the same as those in the first row.

[0025] The first capacitor CAP1 may include a first lower electrode LE1, a first dielectric layer CS1, and a first upper electrode UE1. The first lower electrode LE1 may include a first portion 102A_L having a rod shape, and a second portion 106A_L having a cylindrical shape including a closed lower surface and an open upper surface. The first upper electrode UE1 may include a first portion 112A_U having a rod shape, a second portion 120A_U having a rod shape, and a third portion 128A_U having a rod shape. The first portion 112A_U of the first upper electrode UE1 may extend centrally into the second portion 106A_L of the first lower electrode LE1 without contacting the walls of the second portion 106A_L. The first dielectric layer CS1 may be arranged to fill the space between the second portion 106A_L of the first lower electrode LE1 and the first portion 112A_U of the first upper electrode UE1.

[0026] The second capacitor CAP2 may include a second lower electrode LE2, a second dielectric layer CS2, and a second upper electrode UE2. The second lower electrode LE2 may include a first portion 102B_L having a rod shape, a second portion 112B_L having a rod shape, and a third portion 114B_L having a cylindrical shape including a closed lower surface and an open upper surface. The first portion 102B_L of the second lower electrode LE2 may have a height substantially the same as the height of the first portion 102A_L of the first lower electrode LE1. The second upper electrode UE2 may include a first portion 120B_U having a rod shape and a second portion 128B_U having a rod shape. The second portion 128B_U of the second upper electrode UE2 may have a height substantially the same as the height of the third portion 128A_U of the first upper electrode UE1. The first portion 120B_U of the second upper electrode UE2 may extend centrally into the third portion 114B_L of the second lower electrode LE2. The second dielectric layer CS2 can be arranged to fill the space between the third portion 114B_L of the second lower electrode LE2 and the first portion 120B_U of the second upper electrode UE2.

[0027] The third capacitor CAP3 may include a third lower electrode LE3, a third dielectric layer CS3, and a third upper electrode UE3. The third lower electrode LE3 may include: a first portion 102C_L having a rod shape, a second portion 112C_L having a rod shape, a third portion 120C_L having a rod shape, and a fourth portion 122C_L having a cylindrical shape including a closed lower surface. The first portion 102C_L of the third lower electrode LE3 may have a height substantially the same as the height of the first portion 102A_L of the first lower electrode LE1 and the height of the first portion 102B_L of the second lower electrode LE2. The second portion 112C_L of the third lower electrode LE3 may have a height substantially the same as the height of the second portion 112B_L of the second lower electrode LE2. The third upper electrode UE3 may have only one rod-shaped portion centrally extending into the fourth portion 122C_L of the third lower electrode LE3. The third dielectric layer CS3 may be arranged to fill the space between the fourth portion 122C_L of the third lower electrode LE3 and the rod-shaped portion of the third upper electrode UE3.

[0028] In such Figure 2AIn the plan view shown, the cylindrical second portion 106A_L of the first lower electrode LE1 can partially overlap with the cylindrical third portion 114B_L of the second lower electrode LE2. Additionally, the cylindrical second portion 106A_L of the first lower electrode LE1 can partially overlap with the cylindrical fourth portion 122C_L of the third lower electrode LE3. However, in the cross-sectional view, because the second portion 106A_L of the first lower electrode LE1, the third portion 114B_L of the second lower electrode LE2, and the fourth portion 122C_L of the third lower electrode LE3 can be located at different horizontal levels, they can therefore not be in electrical contact with each other. Thus, the distance between the first capacitor CAP1, the second capacitor CAP2, and the third capacitor CAP3 can be reduced, thereby providing a semiconductor device with higher integration density.

[0029] Figures 3A to 3H This is a cross-sectional view showing a capacitor according to various embodiments. Figures 3A to 3H yes Figure 2B The enlarged view of part "B" in the diagram is used to show the various structures of the upper electrode, dielectric layer, and lower electrode.

[0030] refer to Figure 3A The lower electrode LE may include a first portion LPT1 and a second portion LPT2. The first portion LPT1 may have a cylindrical shape including a closed lower surface and an open upper surface. The second portion LPT2 may have a rod shape projecting downward from the first portion LPT1. The upper electrode UE may include a first portion UPT1 and a second portion UPT2. The first portion UPT1 may have a rod shape extending into the first portion LPT1 of the lower electrode LE. The second portion UPT2 may project upward. The second portion UPT2 may have a width (or diameter) larger than the width (or diameter) of the first portion UPT1. The dielectric layer CS may be arranged to fill the space between the first portion LPT1 of the lower electrode LE and the first portion UPT1 of the upper electrode UE.

[0031] refer to Figure 3B The lower electrode LE can have essentially the same as Figure 3AThe structure of the lower electrode LE is the same as that of the upper electrode UE. The upper electrode UE may include a first portion UPT1, a second portion UPT2, and a third portion UPT3. The first portion UPT1 may have a rod shape extending into the first portion LPT1 of the lower electrode LE. The second portion UPT2 may have a width (or diameter) larger than the width (or diameter) of the first portion UPT1. The second portion UPT2 may protrude upward from the central portion of the upper surface of the third portion UPT3. The third portion UPT3 may be disposed between the first portion UPT1 and the second portion UPT2 and has a disk shape. The dielectric layer CS may be arranged to fill the space between the first portion LPT1 of the lower electrode LE and the first portion UPT1 and the third portion UPT3 of the upper electrode UE.

[0032] refer to Figure 3C The lower electrode LE may include a first portion LPT1, a second portion LPT2, and a third portion LPT3. The first portion LPT1 may have a cylindrical shape including a closed lower surface and an open upper surface. The second portion LPT2 may protrude downwards from the central portion of the lower surface of the first portion LPT1. The third portion LPT3 may protrude downwards from the central portion of the lower surface of the second portion LPT2. The third portion LPT3 may have a diameter smaller than that of the second portion LPT2. The upper electrode UE may include a first portion UPT1, a second portion UPT2, a third portion UPT3, and a fourth portion UPT4. The first portion UPT1 may have a rod shape extending into the first portion LPT1 of the lower electrode LE. The second portion UPT2 may have a width (or diameter) larger than that of the first portion UPT1. The second portion UPT2 may protrude upwards from the central portion of the upper surface of the third portion UPT3. The third portion UPT3 may be disposed between the first portion UPT1 and the second portion UPT2 and has a disk shape. The fourth portion UPT4 may protrude upwards from the central portion of the upper surface of the second portion UPT2. The fourth part, UPT4, can have a smaller diameter than the second part, UPT2. The dielectric layer CS can be arranged to fill the space between the first part, LPT1, of the lower electrode LE, and the first part, UPT1, and the third part, UPT3, of the upper electrode UE.

[0033] refer to Figure 3DThe lower electrode LE may include a first portion LPT1, a second portion LPT2, and a third portion LPT3. The first portion LPT1 may have a cylindrical shape including a closed lower surface and an open upper surface. The second portion LPT2 may protrude downward from the central portion of the lower surface of the first portion LPT1. The third portion LPT3 may protrude downward from the central portion of the lower surface of the second portion LPT2. The third portion LPT3 may have a diameter smaller than that of the second portion LPT2. The upper electrode UE may include a first portion UPT1, a second portion UPT2, third portions UPT3_1 and UPT3_2, and a fourth portion UPT4. The first portion UPT1 may have a rod shape extending into the first portion LPT1 of the lower electrode LE. The second portion UPT2 may have a width (or diameter) larger than that of the first portion UPT1. The second portion UPT2 may protrude upward from the central portion of the upper surface of the third portions UPT3_1 and UPT3_2. The third portions UPT3_1 and UPT3_2 may be arranged between the first portion UPT1 and the second portion UPT2. The fourth portion, UPT4, may protrude upward from the central portion of the upper surface of the second portion, UPT2. The fourth portion, UPT4, may have a diameter smaller than that of the second portion, UPT2. The third portions, UPT3_1 and UPT3_2, of the upper electrode UE may have a cylindrical shape including a closed upper surface and an open lower surface. The first portion, LPT1, of the lower electrode LE may be arranged to extend within the third portions, UPT3_1 and UPT3_2, of the upper electrode UE. The dielectric layer CS may be formed in the space defined by the first portion, LPT1, of the lower electrode LE and the third portions, UPT3_1 and UPT3_2, of the upper electrode UE.

[0034] refer to Figure 3E The upper electrode UE may include a first portion UPT1 and a second portion UPT2. The first portion UPT1 may include a closed upper surface and an open lower surface. The second portion UPT2 may protrude upward from the central portion of the upper surface of the first portion UPT1. The lower electrode LE may include a first portion LPT1 and a second portion LPT2. The first portion LPT1 may have a rod shape extending into the first portion UPT1 of the upper electrode UE. The second portion LPT2 may have a width (or diameter) larger than the width (or diameter) of the first portion LPT1. The second portion LPT2 may protrude downward from the central portion of the lower surface of the first portion LPT1. The dielectric layer CS may be arranged to fill the space between the first portion LPT1 of the lower electrode LE and the first portion UPT1 of the upper electrode UE.

[0035] refer to Figure 3F The upper electrode UE can have essentially the same as Figure 3EThe upper electrode UE has the same structure as the lower electrode LE. The lower electrode LE may include a first portion LPT1, a second portion LPT2, and a third portion LPT3. The first portion LPT1 may have a rod shape extending into the first portion LPT1 of the upper electrode UE. The second portion LPT2 may have a width (or diameter) larger than the width (or diameter) of the first portion LPT1. The second portion LPT2 may protrude downward from the central portion of the lower surface of the third portion LPT3. The third portion LPT3 may be disposed between the first portion LPT1 and the second portion LPT2 and has a disk shape. The dielectric layer CS may be arranged to fill the space between the first portion LPT1 of the upper electrode UE and the first portion LPT1 and the third portion LPT3 of the lower electrode LE.

[0036] refer to Figure 3G The upper electrode UE may include a first portion UPT1, a second portion UPT2, and a third portion UPT3. The first portion UPT1 may have a cylindrical shape including a closed upper surface and an open lower surface. The second portion UPT2 may protrude upward from the central portion of the upper surface of the first portion UPT1. The third portion UPT3 may protrude upward from the central portion of the upper surface of the second portion UPT2. The third portion UPT3 may have a diameter smaller than that of the second portion UPT2. The lower electrode LE may include a first portion LPT1, a second portion LPT2, a third portion LPT3, and a fourth portion LPT4. The first portion LPT1 may have a rod shape extending into the first portion UPT1 of the upper electrode UE. The second portion LPT2 may have a width (or diameter) larger than that of the first portion LPT1. The second portion LPT2 may protrude downward from the central portion of the lower surface of the third portion LPT3. The third portion LPT3 may be disposed between the first portion LPT1 and the second portion LPT2 and has a disk shape. The fourth portion LPT4 may protrude downward from the central portion of the lower surface of the second portion LPT2. The fourth part, LPT4, can have a smaller diameter than the second part, LPT2. The dielectric layer CS can be arranged to fill the space between the first part, UPT1, of the upper electrode UE, and the first part, LPT1, and the third part, LPT3, of the lower electrode LE.

[0037] refer to Figure 3HThe upper electrode UE may include a first portion UPT1, a second portion UPT2, and a third portion UPT3. The first portion UPT1 may have a cylindrical shape including a closed upper surface and an open lower surface. The second portion UPT2 may protrude upward from the central portion of the upper surface of the first portion UPT1. The third portion UPT3 may protrude upward from the central portion of the upper surface of the second portion UPT2. The third portion UPT3 may have a diameter smaller than that of the second portion UPT2. The lower electrode LE may include a first portion LPT1, a second portion LPT2, third portions LPT3_1 and LPT3_2, and a fourth portion LPT4. The first portion LPT1 may have a rod shape extending into the first portion UPT1 of the upper electrode UE. The second portion LPT2 may have a width (or diameter) larger than that of the first portion LPT1. The second portion LPT2 may protrude downward from the central portion of the lower surface of the third portions LPT3_1 and LPT3_2. The third portions LPT3_1 and LPT3_2 may be arranged between the first portion LPT1 and the second portion LPT2. The fourth portion, LPT4, may protrude downward from the central portion of the lower surface of the second portion, LPT2. The fourth portion, LPT4, may have a diameter smaller than that of the second portion, LPT2. The third portions, LPT3_1 and LPT3_2, of the lower electrode LE may have a cylindrical shape including a closed lower surface and an open upper surface. The first portion, UPT1, of the upper electrode UE may be arranged to extend within the third portions, LPT3_1 and LPT3_2, of the lower electrode LE. The dielectric layer CS may be formed in the space defined by the first portion, UPT1, of the upper electrode UE and the third portions, LPT3_1 and LPT3_2, of the lower electrode LE.

[0038] In various embodiments, the capacitor may have various structures, and is not limited to those mentioned above.

[0039] The method of manufacturing a semiconductor device including a capacitor according to an embodiment will be described in detail below.

[0040] Figures 4A to 4L This is a plan view illustrating methods for forming capacitors according to various embodiments, and Figures 5A to 5L This is a cross-sectional view illustrating a method of forming a capacitor according to various embodiments. Figures 5A to 5L It is along Figures 4A to 4L The sectional view intercepted by line A-A' in the diagram.

[0041] refer to Figure 4A and Figure 5AMultiple first conductive patterns 102A_L, 102B_L, and 102C_L can be formed. The first conductive patterns 102A_L, 102B_L, and 102C_L can be formed by etching the first insulating layer 100 to form holes and by filling the holes with conductive material.

[0042] Although not depicted in the figure, an underlying structure can be formed beneath the first insulating layer 100. The first conductive patterns 102A_L, 102B_L, and 102C_L can be electrically connected to the underlying structure.

[0043] In the following text, for ease of explanation, the first conductive patterns 102A_L, 102B_L and 102C_L may be referred to as the first-1 conductive pattern 102A_L, the first-2 conductive pattern 102B_L and the first-3 conductive pattern 102C_L.

[0044] refer to Figure 4B and Figure 5B The second conductive pattern 106A_L can be electrically connected to at least one of the first conductive patterns 102A_L, 102B_L and 102C_L.

[0045] Specifically, a second insulating layer 104 may be formed on a first insulating layer 100 having first conductive patterns 102A_L, 102B_L, and 102C_L. The second insulating layer 104 may be etched to form a hole configured to expose the first conductive pattern 102A_L. This hole may have a dimension larger than the width (or diameter) of the first conductive pattern 102A_L. A second conductive pattern 106A_L may be conformally formed on the inner wall of this hole. The second conductive pattern 106A_L may have a cylindrical shape including a closed lower surface and an open upper surface.

[0046] Here, the first conductive pattern 102A_L and the second conductive pattern 106A_L can be used as the first lower electrode LE1 of the first capacitor CAP1 formed by the following process.

[0047] refer to Figure 4C and Figure 5C Then the second insulating layer 104 can be removed. A first dielectric layer 108 can be conformally formed on the second conductive pattern 106A_L, the first insulating layer 100, the first-second conductive pattern 102B_L, and the first-third conductive pattern 102C_L. The first dielectric layer 108 can be formed on the inner and outer walls of the second conductive pattern 106A_L, but it does not need to fill the entire space of the second conductive pattern 106A_L.

[0048] refer to Figure 4D and Figure 5DThen, a third insulating layer 110 can be formed on the first dielectric layer 108. The third insulating layer 110 can be etched to form a plurality of holes. At least one hole can be configured to expose the first dielectric layer 108 in the second conductive pattern 106A_L. The remaining holes can be formed by etching the third insulating layer 110 and the first dielectric layer 108 to expose the first-second conductive pattern 102B_L and the first-third conductive pattern 102C_L. The first dielectric layer 108 can be partially etched to form the first dielectric pattern 108A. The first dielectric pattern 108A can be used as... Figure 2B The first dielectric layer CS1 of the first capacitor CAP1 in the middle.

[0049] refer to Figure 4E and Figure 5E The holes in the third insulating layer 110 can be filled using the third conductive patterns 112A_U, 112B_L, and 112C_L. In the following text, for ease of explanation, the third conductive patterns 112A_U, 112B_L, and 112C_L can be referred to as the 3-1 conductive pattern 112A_U, the 3-2 conductive pattern 112B_L, and the 3-3 conductive pattern 112C_L.

[0050] The 3-1 conductive pattern 112A_U can be configured to contact the first dielectric pattern 108A. The 3-2 conductive pattern 112B_L can be configured to contact the 1-2 conductive pattern 102B_L. The 3-3 conductive pattern 112C_L can be configured to contact the 1-3 conductive pattern 102C_L.

[0051] refer to Figure 4F and Figure 5F A fourth conductive pattern 114B_L can be formed on the third insulating layer 110. The fourth conductive pattern 114B_L can electrically contact the third-second conductive pattern 112B_L. The fourth conductive pattern 114B_L can have a cylindrical shape including a closed lower surface and an open upper surface. It can be formed substantially with... Figure 4B and Figure 5B The same process used to form the second conductive pattern 106A_L is used to form the fourth conductive pattern 114B_L. Therefore, for the sake of brevity, further description of the process used to form the fourth conductive pattern 114B_L is omitted herein.

[0052] Here, the first-second conductive pattern 102B_L, the third-second conductive pattern 112B_L, and the fourth conductive pattern 114B_L can be used as the second lower electrode LE2 of the second capacitor CAP2.

[0053] refer to Figure 4G and Figure 5GA second dielectric layer 116 can be conformally formed on the fourth conductive pattern 114B_L. The second dielectric layer 116 can be formed on the inner and outer walls of the fourth conductive pattern 114B_L, but it does not have to fill the entire space of the fourth conductive pattern 114B_L.

[0054] refer to Figure 4H and Figure 5H Then, a fourth insulating layer 118 can be formed on the second dielectric layer 116. The fourth insulating layer 118 can be etched to form a plurality of holes. At least one hole can be configured to expose the second dielectric layer 116 in the fourth conductive pattern 114B_L. The remaining holes can be formed by etching the fourth insulating layer 118 and the second dielectric layer 116 to expose the upper surfaces of the third-1 conductive pattern 112A_U and the third-3 conductive pattern 112C_L. The second dielectric layer 116 can be partially etched to form a second dielectric pattern 116B. The second dielectric pattern 116B can be used as... Figure 2B The second dielectric layer CS2 of the second capacitor CAP2 in the middle.

[0055] refer to Figure 4I and Figure 5I The holes in the fourth insulating layer 118 can be filled using the fifth conductive patterns 120A_U, 120B_U, and 120C_L. In the following text, for ease of explanation, the fifth conductive patterns 120A_U, 120B_U, and 120C_L can be referred to as the 5-1 conductive pattern 120A_U, the 5-2 conductive pattern 120B_U, and the 5-3 conductive pattern 120C_L.

[0056] Conductive pattern 120B_U (5-2) can be configured to contact the second dielectric layer 116B (or CS2). Conductive pattern 120A_U (5-1) can be configured to contact conductive pattern 112A_U (3-1). Conductive pattern 120C_L (5-3) can be configured to contact conductive pattern 112C_L (3-3).

[0057] refer to Figure 4J and Figure 5J A sixth conductive pattern 122C_L can be formed on the fourth insulating layer 118. The sixth conductive pattern 122C_L can electrically contact the fifth-third conductive pattern 120C_L. The sixth conductive pattern 122C_L can have a cylindrical shape including a closed lower surface and an open upper surface. It can be formed substantially with... Figure 4B and Figure 5B The same process used to form the second conductive pattern 106A_L is used to form the sixth conductive pattern 122C_L. Therefore, for the sake of brevity, further description of the process used to form the sixth conductive pattern 122C_L is omitted herein.

[0058] Here, the first-third conductive pattern 102C_L, the third-third conductive pattern 112C_L, the fifth-third conductive pattern 120C_L, and the sixth conductive pattern 122C_L can be used as the third lower electrode LE3 of the third capacitor CAP3.

[0059] refer to Figure 4K and Figure 5K A third dielectric layer 124 can be conformally formed on the sixth conductive pattern 122C_L. The third dielectric layer 124 can be formed on the inner and outer walls of the sixth conductive pattern 122C_L, but it does not have to fill the entire space of the sixth conductive pattern 122C_L.

[0060] refer to Figure 4L and Figure 5L Then, a fifth insulating layer 126 can be formed on the third dielectric layer 124. The fifth insulating layer 126 can be etched to form a plurality of holes. At least one hole can be configured to expose the third dielectric layer 124 in the sixth conductive pattern 122C_L. The remaining holes can be formed by etching the fifth insulating layer 126 and the third dielectric layer 124 to expose the upper surfaces of the 5-1 conductive pattern 120A_U and the 5-2 conductive pattern 120B_U. The third dielectric layer 124 can be partially etched to form the third dielectric pattern 124C. The third dielectric pattern 124C can be used as... Figure 2B The third dielectric layer CS3 of the third capacitor CAP3 in the middle.

[0061] refer to Figure 2A and Figure 2B The holes in the fifth insulating layer 126 can be filled using the seventh conductive patterns 128A_U, 128B_U, and UE3. In the following text, for ease of explanation, the seventh conductive patterns 128A_U, 128B_U, and UE3 may be referred to as the 7-1 conductive pattern 128A_U, the 7-2 conductive pattern 128B_U, and the 7-3 conductive pattern UE3.

[0062] Conductive pattern UE3 (7-3) can be configured to contact third dielectric pattern 124C. Conductive pattern 128A_U (7-1) can be configured to contact conductive pattern 120A_U (5-1). Conductive pattern 128B_U (7-2) can be configured to contact conductive pattern 120B_U (5-2).

[0063] Therefore, a first capacitor CAP1, a second capacitor CAP2, and a third capacitor CAP3 can be completed. The first capacitor CAP1 may include a first lower electrode LE1, a first dielectric pattern 108A, and a first upper electrode UE1. The first lower electrode LE1 may include a first-1 conductive pattern 102A_L and a second conductive pattern 106A_L. The first upper electrode UE1 may include a third-1 conductive pattern 112A_U, a fifth-1 conductive pattern 120A_U, and a seventh-1 conductive pattern 128A_U. The second capacitor CAP2 may include a second lower electrode LE2, a second dielectric pattern 116B, and a second upper electrode UE2. The second lower electrode LE2 may include a first-2 conductive pattern 102B_L, a third-2 conductive pattern 112B_L, and a fourth conductive pattern 114B_L. The second upper electrode UE2 may include a fifth-2 conductive pattern 120B_U and a seventh-2 conductive pattern 128B_U. The third capacitor CAP3 may include a third lower electrode LE3, a third dielectric pattern 124C, and a third upper electrode UE3. The third lower electrode LE3 may include the first-third conductive pattern 102C_L, the third-third conductive pattern 112C_L, the fifth-third conductive pattern 120C_L, and the sixth conductive pattern 122C_L. The third upper electrode UE3 may include the seventh-third conductive pattern UE3.

[0064] Figure 6 This is a block diagram illustrating a storage system according to various embodiments.

[0065] refer to Figure 6 The storage system 1000 may include a storage device 1200 and a controller 1100.

[0066] Storage device 1200 can be used to store data information such as text, graphics, and software code. Storage device 1200 may include non-volatile memory. Additionally, storage device 1200 may include... Figures 1 to 5L A capacitor in which the dielectric layers can be positioned differently to improve the integration density of the capacitor.

[0067] The storage device 1200 may include storage blocks divided by slits having insulating bridging elements.

[0068] The controller 1100 can be connected to the host and the storage device 1200. The controller 1100 accesses the storage device 1200 in response to requests from the host. For example, the controller 1100 can control read operations, write operations, erase operations, background operations, etc. of the storage device 1200.

[0069] The controller 1100 may include random access memory (RAM) 1110, central processing unit (CPU) 1120, host interface 1130, error correction code (ECC) circuitry 1140, and storage interface 1150.

[0070] RAM 1110 can be used as operating memory for CPU 1120, cache memory for storage device 1200, buffer memory between storage device 1200 and host, etc. RAM 1110 can be replaced by static random access memory (SRAM), read-only memory (ROM), etc.

[0071] CPU 1120 can control the operation of controller 1100. For example, CPU 1120 can use firmware such as flash translation layer (FTL) stored in RAM 1110.

[0072] Host interface 1130 can interface with a host. For example, host interface 1130 can interface with a host via at least one of the following protocols: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, High Speed ​​PCI protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, proprietary protocols, etc.

[0073] ECC circuit 1140 can use error correction codes (ECC) to detect and correct errors in data read from storage device 1200.

[0074] Storage interface 1150 can interface with storage device 1200. For example, storage interface 1150 may include NAND interface, NOR interface, etc.

[0075] The controller 1100 may further include a buffer memory configured to temporarily store data. The buffer memory may temporarily store data transmitted to an external device via the host interface 1130. The buffer memory may temporarily store data transmitted to the storage device 1200 via the storage interface 1150. The controller 1100 may further include a ROM configured to store code data for interfacing the controller 1100 with a host.

[0076] Therefore, insulating bridging components can correct structural defects in memory blocks to improve the characteristics of memory system 1000.

[0077] Figure 7 This is a block diagram illustrating a storage system according to various embodiments.

[0078] refer to Figure 7The storage system 1000' may include a storage device 1200' and a controller 1100'. The controller 1100' may include RAM 1110, CPU 1120, host interface 1130, ECC circuit 1140 and storage interface 1150.

[0079] Storage device 1200' may include non-volatile memory. Additionally, storage device 1200' may include... Figures 1 to 5L A capacitor in which the dielectric layers can be positioned differently to improve the integration density of the capacitor.

[0080] Additionally, the storage device 1200' may include a multi-chip package comprising multiple memory chips. The memory chips may be divided into multiple groups. Each group can communicate with the controller 1100' via a first channel CH1 to a k-th channel CHk. Memory chips within a group can communicate with the controller 1100' via a common channel. The storage system 1000' may include channels respectively connected to corresponding memory chips in the storage device 1200'.

[0081] Therefore, the positions of the dielectric layers in each capacitor of the storage system 1000' can be different from each other to improve the integration of the capacitors.

[0082] Figure 8 This is a block diagram illustrating a computing system according to various embodiments.

[0083] refer to Figure 8 The computing system 2000 may include a storage device 2100, a CPU 2200, RAM 2300, a user interface 2400, a power supply 2500, and a system bus 2600.

[0084] Storage device 2100 can store data provided through user interface 2400, data processed by CPU 2200, and so on. Furthermore, storage device 2100 can be electrically coupled to CPU 2200, RAM 2300, user interface 2400, and power supply 2500 via system bus 2600. For example, storage device 2100 can be directly connected to system bus 2600, or indirectly connected to system bus 2600 via a controller. When storage device 2100 is directly connected to system bus 2600, the functions of the controller can be performed by CPU 2200, RAM 2300, etc.

[0085] Storage device 2100 may include non-volatile memory. Additionally, storage device 2100 may include... Figures 1 to 5L The capacitor may have dielectric layers positioned differently to improve capacitor integration. The memory device 2100 may include a multi-chip package comprising multiple memory devices according to the embodiments.

[0086] In various embodiments, the computing system 2000 may include a computer, a super mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable gaming device, a navigator, a black box, a digital camera, a 3D television, a digital recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, a telematics network, RFID, etc.

[0087] Therefore, the integration density of capacitors can be improved, thereby enhancing the characteristics of the computing system 2000.

[0088] Figure 9 This is a block diagram illustrating a computing system according to various embodiments.

[0089] refer to Figure 9 The computing system 3000 may include a software layer, which includes an operating system (OS) 3200, applications 3100, a file system 3300, a translation layer 3400, and so on. The computing system 3000 may also include a hardware layer such as a storage device 3500.

[0090] OS 3200 manages the software and hardware of computing system 3000. OS 3200 controls the programmed operations of the CPU. Application 3100 may include various applications running on computing system 3000. Application 3100 may include utilities running by OS 3200.

[0091] The file system 3300 can be a logical structure used in the computing system 3000 to manage data, files, etc. The file system 3300 can organize files or data for storage in the storage device 3500. The file system 3300 can be determined based on the OS 3200 used in the computing system 3000. For example, when the OS 3200 is Microsoft Windows, the file system 3300 may include File Allocation Table (FAT), NT File System (NTFS), etc. When the OS 3200 is Unix / Linux, the file system 3300 may include Extended File System (EXT), Unix File System (UFS), Journal File System (JFS), etc.

[0092] In various embodiments, OS 3200, application 3100, and file system 3300 can be represented by separate boxes in the figures. Alternatively, OS 3200 may include application 3100 and file system 3300.

[0093] Translation layer 3400 can translate addresses into the appropriate form for storage device 3500 in response to requests from file system 3300. For example, translation layer 3400 can translate logical addresses generated by file system 3300 into physical addresses of storage device 3500. The mapping information between logical and physical addresses can be stored as an address translation table. For example, translation layer 3400 may include flash translation layer (FTL), universal flash storage link layer (ULL), etc.

[0094] Storage device 3500 may include non-volatile storage devices, which include Figures 1 to 5L Any one of the capacitors. The computing system 3000 can be classified into an OS layer that executes in the upper region and a controller layer that executes in the lower region. The application 3100, OS 3200, and file system 3300 can be included in the OS layer to be driven by the operating memory of the computing system 3000. The translation layer 3400 can be included in either the OS layer or the controller layer.

[0095] Therefore, the computing system 3000 can have improved integration of the capacitors used therein.

[0096] The embodiments described above are intended to be illustrative and not to limit the invention. Various alternatives and equivalents are possible. The invention is not limited to the embodiments described herein. The invention is also not limited to any particular type of semiconductor device. Other additions, subtractions, or modifications will be apparent in consideration of this disclosure, and are intended to fall within the scope of the appended claims.

Claims

1. A semiconductor device, comprising: A first capacitor includes a first lower electrode, a first upper electrode, and a first dielectric layer disposed at a first height between the first lower electrode and the first upper electrode. as well as A second capacitor, spaced apart from the first capacitor, includes a second lower electrode, a second upper electrode, and a second dielectric layer disposed between the second lower electrode and the second upper electrode at a second height different from the first height. The first lower electrode includes: The first part has a cylindrical shape comprising a closed lower surface and an open upper surface; and The second part extends downward from the first part of the first lower electrode. The first upper electrode includes: The first portion has a rod shape extending into the first portion of the first lower electrode; and The second part extends upward from the first part of the first upper electrode.

2. The semiconductor device according to claim 1, wherein, The first lower electrode and the second lower electrode partially overlap each other in a plan view.

3. The semiconductor device according to claim 1, wherein, in, The first dielectric layer is disposed on the first portion of the first lower electrode.

4. The semiconductor device according to claim 3, wherein, The second lower electrode includes: The first part has a cylindrical shape comprising a closed lower surface and an open upper surface; and The second part extends downward from the first part of the second lower electrode. Wherein, the second dielectric layer is disposed on the first portion of the second lower electrode, and The height of the second portion of the second lower electrode is higher than the height of the second portion of the first lower electrode.

5. The semiconductor device according to claim 4, wherein, The first portion of the first lower electrode and the first portion of the second lower electrode overlap each other in a plan view.

6. The semiconductor device according to claim 1, wherein, The first dielectric layer is disposed between the first portion of the first lower electrode and the first portion of the first upper electrode.

7. The semiconductor device according to claim 1, wherein, The first upper electrode further includes: The third part has a disk shape between the first part and the second part of the first upper electrode, and The first dielectric layer is disposed between the first portion of the first lower electrode and the first portion and the third portion of the first upper electrode.

8. The semiconductor device according to claim 1, wherein, The first upper electrode further includes: The third part has a cylindrical shape comprising a closed upper surface and an open lower surface between the first part and the second part of the first upper electrode. Wherein, the third portion of the first upper electrode surrounds the first portion of the first lower electrode, and The first dielectric layer is disposed between the first portion of the first lower electrode and the third portion of the first upper electrode.

9. The semiconductor device according to claim 1, further comprising: A third capacitor, spaced apart from the first capacitor and the second capacitor, includes a third lower electrode, a third upper electrode, and a third dielectric layer disposed between the third lower electrode and the third upper electrode at a third height different from the first height and the second height.

10. The semiconductor device according to claim 9, wherein, The first lower electrode, the second lower electrode, and the third lower electrode partially overlap each other in a plan view.

11. The semiconductor device according to claim 10, wherein, The third lower electrode includes: The first part has a cylindrical shape comprising a closed lower surface and an open upper surface; and The second part extends downward from the first part, and The third dielectric layer is disposed on the first portion of the third lower electrode.

12. A method for manufacturing a semiconductor device, the method comprising: Conductive patterns 1-1 and 1-2 are formed through the first insulating layer; A second conductive pattern is formed, the second conductive pattern having a cylindrical shape including a closed lower surface and an open upper surface, the second conductive pattern being in electrical contact with the first conductive pattern; A first dielectric layer is formed on the second conductive pattern; A second insulating layer is formed on the first dielectric layer; A third-1 conductive pattern and a third-2 conductive pattern are formed in the second insulating layer, wherein the third-1 conductive pattern contacts the first dielectric layer, and the third-2 conductive pattern contacts the third-2 conductive pattern. A fourth conductive pattern is formed on the second insulating layer, the fourth conductive pattern having a cylindrical shape including a closed lower surface and an open upper surface, and the fourth conductive pattern electrically contacting the third-second conductive pattern. A second dielectric layer is formed on the fourth conductive pattern; A third insulating layer is formed on the second dielectric layer; as well as A 5-1 conductive pattern and a 5-2 conductive pattern are formed in the third insulating layer, wherein the 5-1 conductive pattern contacts the 3-1 conductive pattern and the 5-2 conductive pattern contacts the second dielectric layer.

13. The method of claim 12, further comprising: The first-third conductive pattern is formed through the first insulating layer; A third-third conductive pattern is formed in the second insulating layer, the third-third conductive pattern contacting the first-third conductive pattern; A 5-3rd conductive pattern is formed in the third insulating layer, and the 5-3rd conductive pattern contacts the 3-3rd conductive pattern; A sixth conductive pattern is formed on the third insulating layer, the sixth conductive pattern is in contact with the fifth-third conductive pattern, and the sixth conductive pattern has a cylindrical shape including a closed lower surface and an open upper surface; A third dielectric layer is formed on the sixth conductive pattern; A fourth insulating layer is formed on the third dielectric layer; as well as Conductive patterns 7-1, 7-2, and 7-3 are formed in the fourth insulating layer, wherein conductive pattern 7-1 contacts conductive pattern 5-1, conductive pattern 7-2 contacts conductive pattern 5-2, and conductive pattern 7-3 contacts the third dielectric layer.

14. A semiconductor device, comprising: The first and second capacitors are spaced apart from each other. Each of the first capacitor and the second capacitor includes: An upper electrode, the upper electrode having a cylindrical portion with a closed upper surface and an open lower surface, and a rod portion extending upward from the cylindrical portion, and The lower electrode has a rod portion extending into the open lower surface of the cylindrical portion. The dielectric layer is disposed between the cylindrical portion of the upper electrode and the rod portion of the lower electrode of the respective first capacitor and second capacitor. The dielectric layer of each of the first capacitor and the second capacitor is disposed at different heights in the semiconductor device.

15. The semiconductor device according to claim 14, wherein, The lower electrode further includes: The first portion extends downward from the rod portion of the lower electrode; and The second part has a disk shape between the rod portion in the lower electrode and the first part, and The dielectric layer is disposed between the cylindrical portion of the upper electrode and the rod portion and the second portion of the lower electrode.

16. The semiconductor device according to claim 14, wherein, The lower electrode further includes: The first portion extends downward from the rod portion of the lower electrode; and The second part has a cylindrical portion comprising a closed lower surface and an open upper surface between the rod portion in the lower electrode and the first part, and The second portion of the lower electrode surrounds the cylindrical portion of the upper electrode, and the dielectric layer is disposed between the cylindrical portion of the upper electrode and the second portion of the lower electrode.

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