An interrupt signal generation method, a chip and a computer storage medium

Abstract

The embodiment of the present application discloses a method for generating an interrupt signal, which is used for generating an interrupt signal required by a chip, the chip comprising a timer, a memory and a processor, comprising: obtaining a configuration descriptor of a timing event from the memory, parsing the configuration descriptor, storing the parsed information into a register of the timer, generating an interrupt signal of the timing event and routing information of the interrupt signal according to a value of a comparator register in the register and routing information of an interrupt routing register, and executing the interrupt signal by the processor according to the routing information of the interrupt signal. The embodiment of the present application also simultaneously provides a chip and a computer storage medium.

Description

Technical Field

[0001] This application relates to timing technology in chips, and more particularly to a method for generating an interrupt signal, a chip, and a computer storage medium. Background Technology

[0002] Currently, control systems, as complex communication systems, are used in industrial control systems or automotive central control units. Typically, a control system includes a set of timers, which are managed in real time by a processor for timing-related activities. Therefore, timers play a crucial role in the performance and reliability of the control system.

[0003] The timer includes a set of registers that are accessible to the processor based on the timing configuration written. Specifically, to write a new timing configuration to a timer that has a historical timing configuration and is currently running, the processor first stops the timer and writes the new timing configuration to the timer's register. If the new timing configuration is written, the processor must reconfigure the historical timing configuration in order to make it still available. This reconfiguration introduces additional overhead to the control system. Furthermore, a set of timers is typically used to handle multiple timing activities, and the more timers there are, the better the performance of the control system.

[0004] However, in evolving control systems, System-on-Chip (SoC) is designed for applications where energy efficiency, low circuit area, and high performance are all increasingly important factors. The more timers there are, and the higher their operating frequency, the more challenging it becomes to implement in mixed-signal processes. Furthermore, the more logic gates are used for a given SoC, the more data space incremental timers require for all necessary register sets, consuming a significant portion of the SoC's total gate count. On the other hand, insufficient timers cannot support more timing activities simultaneously. Here, timing reconfiguration must be applied to the insufficient timer devices to support more timing activities, but this degrades the performance of the control system. Therefore, it is clear that existing chip-based timers cannot simultaneously meet the requirements in terms of both the number of logic gates and performance. Summary of the Invention

[0005] This application provides an interrupt signal generation method, a chip, and a computer storage medium, which enables the timer in the chip to simultaneously meet the requirements in terms of the number and performance of logic gates.

[0006] The technical solution of this application is implemented as follows:

[0007] In a first aspect, embodiments of this application provide a method for generating an interrupt signal, used to generate an interrupt signal required by a chip, wherein the chip further includes a timer, a memory, and a processor, comprising:

[0008] Retrieve the configuration descriptor of the timing event from the memory;

[0009] The configuration descriptor is parsed, and the parsed information is stored in the timer's register;

[0010] Based on the value of the comparator register in the register and the routing information of the interrupt routing register, the interrupt signal of the timing event and the routing information of the interrupt signal are generated.

[0011] The processor executes the interrupt signal according to the routing information of the interrupt signal.

[0012] Secondly, embodiments of this application provide a chip, the chip comprising: a timer, a memory, and a processor, wherein the timer is configured to:

[0013] Retrieve the configuration descriptor of the timing event from the memory;

[0014] The configuration descriptor is parsed, and the parsed information is stored in the timer's register;

[0015] Based on the value of the comparator register in the register and the routing information of the interrupt routing register, the interrupt signal of the timing event and the routing information of the interrupt signal are generated.

[0016] The processor is configured to execute the interrupt signal based on the routing information of the interrupt signal.

[0017] Thirdly, embodiments of this application provide a chip, the chip including: a timer, a processor, and a storage medium storing processor-executable instructions; the storage medium performs operations dependent on the processor via a communication bus, and when the instructions are executed by the processor, the interrupt signal generation method described in one or more of the above embodiments is executed.

[0018] Fourthly, embodiments of this application provide a computer storage medium storing executable instructions, wherein when the executable instructions are executed by one or more processors, the processors execute the interrupt signal generation method described in one or more of the above embodiments.

[0019] This application provides an interrupt signal generation method, chip, and computer storage medium for generating interrupt signals required by a chip. The chip includes a timer, a memory, and a processor. The method includes: obtaining a configuration descriptor for a timing event from the memory; parsing the configuration descriptor; storing the parsed information in a register of the timer; generating an interrupt signal for the timing event and routing information for the interrupt signal based on the value in the timer and routing information in an interrupt routing register; and the processor executing the interrupt signal according to the routing information. In other words, in this application embodiment, by obtaining the configuration descriptor for the timing event from the memory and parsing the configuration descriptor, the parsed information is stored in a register, allowing the processor to generate an interrupt signal for the timing event and routing information for the interrupt signal based on the routing information in the timer. The system uses information to generate interrupt signals and routing information for timer events. Compared to traditional timers, when multiple timer events exist, it eliminates the need to reconfigure multiple timer events in the registers or increase the number of timers to implement multiple timing activities. Instead, it stores configuration descriptors for the timer events in memory and uses these descriptors to configure the registers to implement the current timer event. That is, by setting configuration descriptors for multiple timer events and reading the configuration descriptors, the current timer event is read into the register to implement the current timer event. This eliminates the overhead of reconfiguration for multiple timer events and avoids increasing the number of logic gates in the SOC by increasing the number of timers, thus ensuring the SOC's system performance while reducing the number of logic gates. Attached Figure Description

[0020] Figure 1 A schematic diagram of a chip structure provided in this application embodiment. Figure 1 ;

[0021] Figure 2 A flowchart illustrating an optional interrupt signal generation method provided in an embodiment of this application;

[0022] Figure 3 This is a block diagram of the timer structure in related technologies;

[0023] Figure 4 This is a schematic diagram of the timing activities of the physical layer in a control system in related technologies;

[0024] Figure 5 This is a schematic diagram illustrating the allocation of timing activities in the physical layer of a control system in related technologies.

[0025] Figure 6 A schematic diagram of an optional timer provided in an embodiment of this application;

[0026] Figure 7 A schematic diagram illustrating the structure of an example of an optional timer provided in this application embodiment;

[0027] Figure 8 A flowchart illustrating an example of an optional interrupt signal generation method provided in this application embodiment;

[0028] Figure 9 A timing diagram for an optional timer to execute a timed event, provided as an embodiment of this application;

[0029] Figure 10 A schematic diagram of a chip structure provided in this application embodiment. Figure 2 . Detailed Implementation

[0030] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0031] Example 1

[0032] This application provides a method for generating interrupt signals, used to generate interrupt signals required by a chip. Figure 1 A schematic diagram of a chip structure provided in this application embodiment. Figure 1 ,like Figure 1 As shown, the chip 100 may include: a timer 11, a memory 12, and a processor 13; wherein the timer 11 is connected to the memory 12 and the processor 13 respectively.

[0033] Figure 2 A flowchart illustrating an optional interrupt signal generation method provided in this application embodiment is shown below. Figure 2 As shown, the method for generating the above-mentioned interrupt signal may include:

[0034] S201: Retrieve the configuration descriptor of the timing event from memory 12;

[0035] Figure 3 This is a block diagram of the timer structure in related technologies, such as... Figure 3 As shown, when the timer receives a clock signal, the trigger controller receives an internal clock signal, generating a reset signal, an enable signal, or a count signal. The prescaler divides the timer's clock source to obtain a clock signal of a predetermined frequency, which is then transmitted to the counter register. When the value in the counter register reaches the value in the comparator register, the timer generates an interrupt signal. In addition, the value in the increment register is automatically loaded into the comparator register after the timer generates an interrupt signal, automatically completing the reloading of the comparator register during periodic timing activities.

[0036] Table 1 below describes the registers in the timer in related technologies, including the register's offset address, type, remaining value, and specific description.

[0037] Table 1

[0038]

[0039] For example, Figure 4 This is a schematic diagram of the timing activities of the physical layer in a control system in related technologies, such as... Figure 4 As shown, in the physical layer of the modem in a 4G / 5G controller system, there will be three different types of timing activities according to the design:

[0040] The first type is TTI period timers: used for TTI boundary timed updates and TTI task triggering, occurring periodically; the second type is TTI semi-static timers: used for task triggering that is not possible at subframe boundaries, occurring periodically; the third type is TTI dynamic timers: used for dynamic timers of DCI triggered events, especially for tasks with a defined time limit.

[0041] Figure 5 This is a schematic diagram illustrating the allocation of timing activities in the physical layer of a control system in related technologies, such as... Figure 5 As shown, each carrier component group uses two timers for static and periodic timing activities. For dynamic timing activities, the system uses timer indices 8-17 for downlink carrier timing activities, timer indices 18-21 for uplink carrier timing activities, and timer indices 22-31 are reserved for future use.

[0042] Table 2 below shows the resource mapping of timers in the physical layer of the control system in related technologies. Specifically, 32 timers are reserved in the modem physical layer of the 4G / 5G control system.

[0043] Table 2

[0044]

[0045] It is evident that in related technologies, more timers are needed to serve more timed activities. Since more timed activities greatly increase the possibility of interrupt conflicts, it is necessary to optimize the timed activities specifically to address conflicts. However, optimization will bring greater overhead and inefficiency to the system. In other words, increasing the number of timers not only increases the number of logic gates in the SOC, but also affects the system performance.

[0046] To reduce the number of logic gates in a System-on-a-Chip (SoC) while maintaining system performance, this application provides a generation method. First, the configuration descriptor of the timing event is obtained from memory 12. That is, the configuration information of the timing event, i.e., the configuration data of the timing event, is stored in memory in advance in the chip, instead of being pre-configured in the timer register. This eliminates the overhead of configuring the timing event in the timer. By configuring the timing event through the configuration descriptor, only operations such as modifying, adding, combining, canceling, and reconfiguring the configuration descriptor are needed to configure the timing event to be served, thus achieving the goal of more flexible configuration of timing events.

[0047] Figure 6 A schematic diagram of an optional timer provided in an embodiment of this application is shown below. Figure 6 As shown, the timer 11 may include a control circuit 111, a register 112 and a processing circuit 113, with the control circuit 111, register 112 and processing circuit 113 connected in pairs.

[0048] In order to retrieve the configuration descriptor for the timing event from memory 12, in an optional embodiment, S201 may include:

[0049] When timer 11 starts, the control circuit 111 of timer 11 obtains the initial storage location from the memory location register in register 112;

[0050] The control circuit 111 retrieves the configuration descriptor from the memory 12 according to the initial storage location.

[0051] Specifically, regarding reading the first configuration descriptor, when Timer 11 starts, it stores the storage location of the configuration descriptor of the first timer event, i.e., the initial storage location, in the memory location register of Timer 11's register. This is consistent with the above... Figure 1 Compared to the registers in timers in related technologies, the timer register in this embodiment adds a memory location register, which is used to store the configuration descriptor of the first timing event.

[0052] Thus, when timer 11 starts, control circuit 111 first reads the storage location of the configuration descriptor of the first timer event from the memory location register, i.e. the initial storage location. Then, control circuit 111 reads the configuration descriptor of the first timer event from memory 12 according to the initial storage location.

[0053] The above describes the configuration descriptor for the first timed event. In an optional embodiment, for the configuration descriptors of subsequent timed events, S201 may include:

[0054] When the control circuit 111 of timer 11 receives the processing completion signal of the processing circuit 113 of timer 11 for the previous timing event, the control circuit 111 obtains the storage location of the configuration descriptor according to the configuration descriptor of the previous timing event.

[0055] The control circuit 111 retrieves the configuration descriptor from the memory 12 according to the storage location of the configuration descriptor.

[0056] Specifically, when the timer 11 in the chip needs to serve multiple timed events, the memory 12 will store multiple configuration descriptors for the timed events. The storage location of the configuration descriptor for the first timed event is stored in a register in memory. The storage location of the configuration descriptor for subsequent timed events is obtained by using the configuration descriptor of the previous timed event.

[0057] It should be noted that when timer 11 is serving each timed event, when the timer processing circuit 113 finishes processing the timed event, it needs to send a processing completion signal back to the control circuit 111 to indicate that the timed event has been processed. Since the configuration descriptor of the previous timed event carries the storage location of the configuration descriptor of the current timed event, the control circuit 111 obtains the configuration descriptor of the current timed event based on the configuration descriptor of the previous timed event. In this way, the configuration descriptor of the timed event can be obtained, and the processing of the current timed event can begin.

[0058] S202: Parse the configuration descriptor and store the parsed information in the register of Timer 11;

[0059] After obtaining the configuration descriptor of the timing event, in order to complete this timing event, the chip needs to parse the configuration descriptor and store the parsed information in register 112. Only by storing it in register 112 can the timing event be executed based on the information in register 112.

[0060] It should be noted that the configuration descriptor for the timing event provided in this application embodiment contains the configuration information for this timing event. Specifically, the description of the configuration descriptor is shown in Table 3 below:

[0061] Table 3

[0062]

[0063]

[0064] As shown in Table 3 above, the configuration descriptor carries the configuration data of the timing event. In order to obtain the configuration data, each bit of the configuration descriptor is parsed. The information obtained from the parsing is the configuration data of the timing event. Furthermore, in order to implement the timing event, the parsed information is stored in register 112. Specifically, different information is stored in different registers 112. This allows the processing circuit to determine whether to generate an interrupt signal based on the parsed information.

[0065] Table 4 below shows the format of configuration descriptors:

[0066] Table 4

[0067]

[0068] Furthermore, in order to store the parsed information into the appropriate register 113, in an optional embodiment, S202 may include:

[0069] The control circuit 111 of timer 11 parses the configuration descriptor. When the parsed information indicates that the interrupt is disabled, the interrupt enable bit of the control register in register 112 is marked as disabled.

[0070] In other words, after parsing the configuration descriptor, the control circuit 111 can tell from the parsed information that the bit name is "int enable" that the interrupt of the timing event is disabled. That is, the configuration descriptor is a virtual node and does not actually contain a timing event. Therefore, when executing this timing event, the interrupt enable bit of the control register in register 112 is marked as disabled. In this way, when the processing circuit 113 processes this timing event and reads the value of the interrupt enable bit of the control register, no interrupt signal will be generated.

[0071] It should be noted that the configuration descriptor set in the embodiments of this application, when the configuration descriptor indicates that the interrupt is disabled, means that the configuration descriptor is equivalent to a virtual node. Through the setting of the virtual node, when the application uses the configuration descriptor as a placeholder with a linked list, the virtual node can support timed activities such as insertion and reconfiguration. In this way, it is beneficial to the configuration of timed activities without incurring system overhead.

[0072] To implement the timed event, in one optional embodiment, S202 may include:

[0073] The control circuit 111 of timer 11 parses the configuration descriptor and determines the value of the comparator register according to the mode of the comparator register in register 112 indicated in the parsed information.

[0074] The control circuit 111 stores the value of the comparator register into the comparator register.

[0075] Specifically, in the embodiment of this application, the register 112 of the timer 11 still includes a comparator register. The value in the comparator register is determined by the obtained configuration descriptor. After parsing the configuration descriptor, the parsed information determines the mode of the comparator register. As can be seen from Table 3 above, the mode of the comparator register can include relative mode and absolute mode.

[0076] After determining the mode of the comparator register from the parsed information, the value of the comparator register is determined according to the mode of the comparator register, and the determined value of the comparator register is stored in the comparator register, so that the processing circuit 113 can determine when to generate an interrupt signal based on the value in the comparator register.

[0077] Further, in order to determine the value of the comparator register, in an optional embodiment, the value of the comparator register is determined based on the pattern of the comparator register in the register indicated in the parsed information, including:

[0078] When the parsed information indicates that the comparator register is in relative mode, the control circuit 111 determines the value of the comparator register as the sum of the current value and the relative value.

[0079] When the parsed information indicates that the comparator register is in absolute mode, the control circuit 111 determines the current value of the comparator register as the value of the comparator register.

[0080] In other words, when the parsed information indicates that the comparator register is in relative mode, as can be seen from the description in Table 3, the control circuit 111 obtains the current value of the comparator register and determines the value of the comparator register by summing the current value and the relative value. When the parsed information indicates that the comparator register is in absolute mode, the control circuit 111 directly determines the current value of the comparator register as the value of the comparator register, that is, the value of the comparator register is not modified and the processing circuit can use it directly.

[0081] In addition to the comparator register, Timer 11 also contains an interrupt routing register, which stores interrupt routing information corresponding to the timing event. In an optional embodiment, S202 may include:

[0082] The control circuit 111 of timer 11 parses the configuration descriptor and stores the interrupt routing information in the parsed information into the interrupt routing register in the register.

[0083] The control circuit 111 parses the configuration descriptor and stores the interrupt routing information in the parsed information into the interrupt routing register. This enables the processing circuit 113 to determine the response routing information for each interrupt signal, so that the processor 13 can transmit the interrupt signal according to the routing information.

[0084] In addition, a new logic register has been added to the timer 11 in this embodiment to store the identifier of the timing event. In an optional embodiment, S202 may include:

[0085] The control circuit 111 of timer 11 parses the configuration descriptor and stores the identifier of the timing event in the parsed information into the logic register in register 112.

[0086] As shown in Table 3, since each timed event has a corresponding identifier to distinguish different timed events, the identifier of the current timed event can be obtained by parsing each configuration descriptor. In this embodiment of the application, after the identifier of the timed event is obtained, the identifier of the timed event is stored in the logic register.

[0087] By using the identifier of the timing event stored in the logic register, the processor 13 can read the identifier of the current timing event from the logic register when processing the interrupt signal, thereby enabling the processor to distinguish and process the timing event.

[0088] S203: Generate the interrupt signal and interrupt signal routing information for the timer event based on the value of the comparator register in the register and the routing information of the interrupt routing register;

[0089] After the parsed information is stored in the register, the configuration data of the timing event is stored in register 112. Then, the processing circuit 113 in the timer can generate an interrupt signal for the timing event and the routing information of the interrupt signal according to the value of the comparator register and the routing information of the terminal routing register.

[0090] In order to generate the interrupt signal and its routing information, in an optional embodiment, S203 may include:

[0091] When the value of the counter register in register 112 reaches the value of the comparator register, the processing circuit 113 of timer 11 generates an interrupt signal;

[0092] The processor 13 circuit generates the routing information for the interrupt signal based on the routing information in the interrupt routing register.

[0093] Specifically, the processing circuit 113 compares the value of the counter register with the value of the comparator register. When the value of the counter register reaches the value of the comparator register, the processing circuit 113 generates an interrupt signal. Since the interrupt routing register stores the routing information of the timing event, the processing circuit 113 can generate the routing information of the interrupt signal based on the routing information in the interrupt routing register.

[0094] S204: Processor 13 executes the interrupt signal according to the interrupt signal routing information.

[0095] Finally, the processor 13 receives the interrupt signal and the interrupt signal routing information, transmits the interrupt signal according to the interrupt signal routing information, and executes it.

[0096] Regarding the logic register, since the logic register stores the identifier of the timing event, in an optional embodiment, S204 may include:

[0097] Processor 13 reads the identifier of the timing event from the logic register;

[0098] The processor 13 obtains the logic function for the interrupt signal based on the identifier of the timer event;

[0099] The processor 13 executes the interrupt signal according to the routing information and logic function of the interrupt signal.

[0100] In other words, when the processor 13 executes an interrupt signal, it can read the identifier of the timer event from the logic register. Since each interrupt signal has a different function, some interrupt signals are used to light up an indicator light, while others are used to open a peripheral device. Therefore, the logic function of the interrupt signal can be obtained by reading the identifier of the timer event. For example, if the logic function is to open a peripheral device, the processor will transmit the interrupt signal according to the interrupt signal routing information and execute the interrupt signal according to the logic function to realize the function of the interrupt in the system.

[0101] In addition, the register 112 of the timer 11 provided in this application embodiment also includes an interrupt status register. In an optional embodiment, after S204, the above method may include:

[0102] The control circuit 111 of timer 11 sets the status in the interrupt status register in register 112 to the interrupt status.

[0103] The interrupt status register is set to an interrupt state by the control circuit 111 after the timer 11 generates an interrupt signal. This allows the processor 13 to read the current state of the timer 11 from the interrupt status register. Table 5 below describes the timer registers, including the offset address, type, remaining value, and specific details of each register.

[0104] Table 5

[0105]

[0106] It should be noted that when there are multiple timing events in timer 11, multiple timing events can be implemented by configuring multiple configuration descriptors during configuration. In this way, multiple configuration descriptors are stored in memory 12, and the storage location of the next configuration descriptor is stored in the preceding configuration descriptor, thus forming a linked list.

[0107] When timer 11 starts, it reads the configuration descriptor of a timer event. After the first timer event is completed, it can read the descriptor of the next timer event based on the descriptor of the first timer event, and so on.

[0108] Based on this, during the configuration phase of the timed event, the timed event can be reconfigured by configuring a linked list. In addition, the periodic timed settings can be organized using a circular linked list. Through this circular linked list, the control circuit 11 can repeatedly transmit the timed configuration data to the processing circuit 113, thereby improving the efficiency of the timer 11.

[0109] The following examples illustrate the method for generating interrupt signals described in one or more of the above embodiments.

[0110] Figure 7 A schematic diagram of an example of an optional timer provided in an embodiment of this application is shown below. Figure 7 As shown, the timer 700 may include: a control circuit 71, a processing circuit 72, and a register group 73. The control circuit 71 is connected to the memory 701 and is used to retrieve configuration descriptors from the memory 701. The memory 701 stores a linked list of configuration descriptors, including: configuration descriptor 1, configuration descriptor 2, configuration descriptor 3, and null (NULL).

[0111] Based on the above Figure 7 , Figure 8 A flowchart illustrating an example of an optional interrupt signal generation method provided in this application embodiment is shown below. Figure 8 As shown, the method for generating the interrupt signal may include:

[0112] S801: Application configuration of register group 73 in timer 700;

[0113] Specifically, the application mainly configures the memory location register, timer register, and control register, so that the configuration descriptor of the first timer event is stored in the memory location register.

[0114] S802: The application starts timer 700, and timer 700 obtains the storage location of the first configuration descriptor;

[0115] When timer 700 starts, the control circuit 71 in timer 700 obtains the storage location of the first timing event from the memory location register.

[0116] S803: Timer 700 retrieves the configuration descriptor;

[0117] For the first timer event, after obtaining the configuration descriptor of the first timer event, the configuration descriptor of the first timer event is retrieved from memory, i.e. Figure 7 Configuration descriptor 1 in the configuration file.

[0118] For subsequent timer events following the first timer event, the configuration descriptor of the current timer event can be obtained from the configuration descriptor of the previous timer event. Taking the second timer event as an example, the storage location of configuration descriptor 2 can be parsed from configuration descriptor 1. The control circuit can read configuration descriptor 2 from the memory based on the obtained storage location of configuration descriptor 2. The configuration descriptor of the second timer event is similar, so it will not be described in detail here.

[0119] S804: Timer 700 executes the timed events indicated by the configuration descriptor according to the configuration descriptor;

[0120] After obtaining the configuration descriptor of the timing event, the control circuit 71 parses the configuration descriptor to obtain the configuration data of the timing event and stores the configuration data in the register group 73. Here, the main purpose is to update the logic register, interrupt routing register and comparator register by parsing the configuration descriptor, so that the processor 72 can generate interrupt signals and interrupt signal routing information according to the interrupt routing register and comparator register. Finally, the processor executes the interrupt signal.

[0121] S805: Check if the configuration descriptor read by Timer 700 is empty. If yes, return to execute S802; otherwise, return to execute S803.

[0122] When the timer events are executed sequentially, the control circuit 71 reads the configuration descriptor. If the read configuration descriptor is NULL, it executes S802 to start the next round of configured timer events; otherwise, it executes S803 to read the next configuration descriptor and execute the next timer event, until all timer events are completed.

[0123] Based on the above Figure 8 , Figure 9 A timing diagram for an optional timer executing a timed event, as provided in an embodiment of this application, is shown below. Figure 9 As shown, the timeline includes four time nodes: T1, T2, T3, and T4. Before T1, the application kicks off timer 700. The control circuitry 71 reads configuration descriptor 1 (Descriptor(T1)) from memory 701. The processing circuitry 72 reads the counter value as T1 and generates an interrupt signal at time T1. Then, the control circuitry 71 reads configuration descriptor 2 (Descriptor(T2)) from memory. The processing circuitry 72 reads the counter value as T2 and generates an interrupt signal at time T2. The control circuitry 71 reads configuration descriptor 3 (Descriptor(T3)) from memory. The processing circuitry 72 reads the counter value as T3 and generates an interrupt signal at time T3. The control circuitry 71 reads configuration descriptor 4 (Descriptor(T4)) from memory. The processing circuitry 72 reads the counter value as T4 and generates an interrupt signal at time T4. The control circuitry 71 reads the configuration descriptor as NULL from memory, and timer 700 terminates the timed event set by the application.

[0124] The configuration descriptors mentioned above are stored in memory. Since the preceding configuration descriptor stores the storage location of the following configuration descriptor, the configuration descriptors are essentially linked together as a list, such as... Figure 7 As shown in the memory.

[0125] This example provides a scalable, high-performance timer to support a flexible number of timing activities, while reducing the total number of gates in the SOC for low circuit area and energy efficiency. It also reduces the total number of timers set up and makes interrupt assertions dynamically configurable. Furthermore, it eliminates the timing setup overhead of timer operations such as reconfiguration, cancellation, insertion, and combination.

[0126] by Figure 5For example, in the modem physical layer of a 4G / 5G control system with 95% timers, the number of register groups is reduced from 5 (registers) * 32 (timer devices) = 160 to 7, resulting in a reduction in circuit area. Furthermore, the more timers the control system uses, the higher the efficiency of the timers in this example. Additionally, assuming that an average of two timing setting updates are required for a running timer within a time slot duration (125µs), then... Figure 5 In the 4G / 5G control system, the total number of operations at the modem physical layer is 2 (operations) * 8000 (slots) * 32 (timers) = 512000 times / second, but this example can omit this operation.

[0127] This application provides a method for generating an interrupt signal, used to generate an interrupt signal required by a chip. The chip includes a timer, a memory, and a processor. The method includes: obtaining a configuration descriptor of a timing event from the memory; parsing the configuration descriptor; storing the parsed information in a register of the timer; generating an interrupt signal for the timing event and routing information of the interrupt signal based on the value of the timer in the register and the routing information of an interrupt routing register; and the processor executing the interrupt signal according to the routing information of the interrupt signal. In other words, in this application embodiment, by obtaining the configuration descriptor of the timing event from the memory and parsing the configuration descriptor, the parsed information is stored in a register, allowing the timer to generate an interrupt signal based on the information in the register. The system generates interrupt signals and their routing information for timer events. Compared to traditional timers, when multiple timer events exist, it eliminates the need to reconfigure multiple timer events in registers or increase the number of timers to implement multiple timing activities. Instead, it stores configuration descriptors for timer events in memory and uses these descriptors to configure registers to implement the current timer event. In other words, by setting configuration descriptors for multiple timer events and reading them, the current timer event is read into the register to implement the current timer event. This eliminates the reconfiguration overhead associated with multiple timer events and avoids increasing the number of logic gates in the SOC by increasing the number of timers, thus ensuring SOC system performance while reducing the number of logic gates.

[0128] Example 2

[0129] Based on the same inventive concept, embodiments of this application provide a chip, such as... Figure 1 As shown, the chip also includes: a timer 11, a memory 12, and a processor 13; wherein, the timer 11 is configured to:

[0130] Retrieve the configuration descriptor for the timing event from memory 12;

[0131] The configuration descriptor is parsed, and the parsed information is stored in the register of Timer 11;

[0132] Based on the value of the comparator register in the register and the routing information of the interrupt routing register, the interrupt signal of the timer event and the routing information of the interrupt signal are generated.

[0133] Processor 13 is configured to execute an interrupt signal based on the interrupt signal routing information.

[0134] In an optional embodiment, the configuration descriptor for the timing event retrieved by the chip from memory 12 includes:

[0135] When Timer 11 starts, the control circuit of Timer 11 obtains the initial storage location from the memory location register in the register;

[0136] The control circuit retrieves the configuration descriptor from memory 12 according to the initial storage location.

[0137] In an optional embodiment, the configuration descriptor for the timing event retrieved by the chip from memory 12 includes:

[0138] When the control circuit of timer 11 receives the processing completion signal of the processing circuit of timer 11 for the previous timing event, the control circuit obtains the storage location of the configuration descriptor according to the configuration descriptor of the previous timing event.

[0139] The control circuit 111 retrieves the configuration descriptor from the memory 12 according to the storage location of the configuration descriptor. In an optional embodiment, the chip parses the configuration descriptor and stores the parsed information in the register of the timer 11, including:

[0140] The control circuit of Timer 11 parses the configuration descriptor. When the parsed information indicates that the interrupt is disabled, it marks the interrupt enable bit of the control register in the register as disabled.

[0141] In one optional embodiment, the chip parses the configuration descriptor and stores the parsed information in the register of timer 11, including:

[0142] The control circuit of Timer 11 parses the configuration descriptor and determines the value of the comparator register based on the mode of the comparator register in the register indicated in the parsed information.

[0143] The control circuit stores the value of the comparator register into the comparator register.

[0144] In one optional embodiment, the chip determines the value of the comparator register, including the following, based on the mode of the comparator register in the register indicated in the parsed information:

[0145] When the parsed information indicates that the comparator register is in relative mode, the control circuit determines the value of the comparator register by summing the current value of the comparator register with the relative value.

[0146] When the parsed information indicates that the comparator register is in absolute mode, the control circuit determines the current value of the comparator register as the value of the comparator register.

[0147] In one optional embodiment, the chip parses the configuration descriptor and stores the parsed information in the register of timer 11, including:

[0148] The control circuit of Timer 11 parses the configuration descriptor and stores the interrupt routing information in the parsed information into the interrupt routing register in the register.

[0149] In one optional embodiment, the chip parses the configuration descriptor and stores the parsed information in the register of timer 11, including:

[0150] The control circuit of Timer 11 parses the configuration descriptor and stores the identifier of the timing event in the parsed information into the logic register in the register.

[0151] In one alternative embodiment, the chip is further used for:

[0152] After the processor 13 executes the interrupt signal according to the interrupt signal routing information, the control circuit sets the status in the interrupt status register in the register to the interrupt status.

[0153] In one optional embodiment, the chip generates an interrupt signal and the interrupt signal routing information based on the value of the comparator register in the register and the routing information in the interrupt routing register, including:

[0154] When the value of the counter register in the register reaches the value of the comparator register, the processing circuit of Timer 11 generates an interrupt signal;

[0155] The processor 13 circuit generates the routing information for the interrupt signal based on the routing information in the interrupt routing register.

[0156] In an optional embodiment, the processor 13 executes the interrupt signal according to the routing information of the interrupt signal, including:

[0157] Processor 13 reads the identifier of the timing event from the logic register;

[0158] The processor 13 obtains the logic function for the interrupt signal based on the identifier of the timer event;

[0159] The processor 13 executes the interrupt signal according to the routing information and logic function of the interrupt signal.

[0160] Figure 10 A schematic diagram of a chip structure provided in this application embodiment. Figure 2 ,like Figure 10 As shown, this application provides a chip 1000, which includes a timer 101, a processor 102, and a storage medium 103 storing processor-executable instructions. The storage medium 103 performs operations via a communication bus 104 in dependence on the processor 102. When the instructions are executed by the processor, the interrupt signal generation method described in one or more of the above embodiments is executed.

[0161] It should be noted that in practical applications, the various components in the terminal are coupled together via the communication bus 104. It can be understood that the communication bus 104 is used to achieve communication between these components. In addition to the data bus, the communication bus 104 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 10 The general labeled all buses as communication bus 104.

[0162] This application provides a computer storage medium storing executable instructions. When the executable instructions are executed by one or more processors, the processors execute the interrupt signal generation method described in one or more of the above embodiments.

[0163] The computer-readable storage medium can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.

[0164] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0165] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0166] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0167] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0168] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application.

Claims

1. A method for generating an interrupt signal required for a chip including a timer, a memory, and a processor, the method comprising: The method includes: ​ When the timer is started, the control circuit of the timer obtains the initial storage location from the memory location register in the timer's register; The control circuit retrieves the configuration descriptor of the timing event from the memory according to the initial storage location; When the control circuit of the timer receives the processing completion signal of the processing circuit of the timer for the previous timed event, the control circuit obtains the storage location of the configuration descriptor of the timed event according to the configuration descriptor of the previous timed event; The control circuit retrieves the configuration descriptor of the timing event from the memory according to the storage location of the configuration descriptor; The configuration descriptor is parsed, and the parsed information is stored in the timer's register; Based on the value of the comparator register in the register and the routing information of the interrupt routing register, the interrupt signal of the timing event and the routing information of the interrupt signal are generated. The processor executes the interrupt signal according to the routing information of the interrupt signal.

2. The method according to claim 1, characterized in that, The configuration descriptor is parsed, and the parsed information is stored in the timer's register, including: The timer's control circuit parses the configuration descriptor. When the parsed information indicates that interrupts are disabled, it marks the interrupt enable bit of the control register in the register as disabled.

3. The method according to claim 1, characterized in that, The configuration descriptor is parsed, and the parsed information is stored in the timer's register, including: The control circuit of the timer parses the configuration descriptor and determines the value of the comparator register according to the mode of the comparator register in the register indicated in the parsed information. The control circuit stores the value of the comparator register into the comparator register.

4. The method according to claim 3, characterized in that, Based on the mode of the comparator register in the register indicated in the parsed information, determine the value of the comparator register, including: When the parsed information indicates that the comparator register is in relative mode, the control circuit determines the value of the comparator register as the sum of the current value and the relative value. When the parsed information indicates that the comparator register is in absolute mode, the control circuit determines the current value of the comparator register as the value of the comparator register.

5. The method according to claim 1, characterized in that, The configuration descriptor is parsed, and the parsed information is stored in the timer's register, including: The timer's control circuit parses the configuration descriptor and stores the interrupt routing information from the parsed information into the interrupt routing register in the register.

6. The method according to claim 1, characterized in that, The configuration descriptor is parsed, and the parsed information is stored in the timer's register, including: The timer's control circuit parses the configuration descriptor and stores the identifier of the timing event in the parsed information into a logical register in the register.

7. The method according to claim 1, characterized in that, The method further includes: After the processor executes the interrupt signal according to the routing information of the interrupt signal, The timer's control circuit sets the status in the interrupt status register of the register to the interrupt status.

8. The method according to claim 1, characterized in that, Based on the value of the comparator register in the aforementioned register and the routing information in the interrupt routing register, an interrupt signal and its routing information are generated, including: When the value of the counter register in the register reaches the value of the comparator register, the timer processing circuit generates the interrupt signal; The timer's processing circuit generates the routing information for the interrupt signal based on the routing information in the interrupt routing register.

9. The method according to claim 6, characterized in that, The processor executes the interrupt signal according to the routing information of the interrupt signal, including: The processor reads the identifier of the timing event from the logic register; The processor obtains the logic function of the interrupt signal based on the identifier of the timing event; The processor executes the interrupt signal according to the routing information of the interrupt signal and the logic function of the interrupt signal.

10. A chip, characterized in that, The chip includes: a timer, a memory, and a processor, wherein the timer is configured to: When the timer is started, the control circuit of the timer obtains the initial storage location from the memory location register in the timer's register; The control circuit retrieves the configuration descriptor of the timing event from the memory according to the initial storage location; When the control circuit of the timer receives the processing completion signal of the processing circuit of the timer for the previous timed event, the control circuit obtains the storage location of the configuration descriptor of the timed event according to the configuration descriptor of the previous timed event; The control circuit retrieves the configuration descriptor of the timing event from the memory according to the storage location of the configuration descriptor; The configuration descriptor is parsed, and the parsed information is stored in the timer's register; Based on the value of the comparator register in the register and the routing information of the interrupt routing register, the interrupt signal of the timing event and the routing information of the interrupt signal are generated. The processor is configured to execute the interrupt signal based on the routing information of the interrupt signal.

11. A chip, characterized in that, The chip includes: a timer, a processor, and a storage medium storing instructions executable by the processor; the storage medium performs operations via a communication bus dependent on the processor, and when the instructions are executed by the processor, it performs the interrupt signal generation method according to any one of claims 1 to 9.

12. A computer storage medium, characterized in that, The device stores executable instructions, which, when executed by one or more processors, enable the processors to perform the interrupt signal generation method according to any one of claims 1 to 9.

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