Display device

Abstract

The display device includes: a first substrate including a display area, a non-display area at least partially surrounding the display area, and a groove that overlaps with the non-display area and is recessed in the thickness direction; a pixel located on the first substrate and overlapping with the display area; a driver chip located in the groove; and a printed circuit board located in the non-display area and overlapping with the driver chip in a plan view.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2021-0101533, filed on August 2, 2021, with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device having a non-display area with a reduced size. Background Technology

[0004] With the gradual development of the information society, the requirements for display devices used to display images have increased. A display device includes a display area for displaying images and a non-display area for not displaying images. In recent years, research has been actively conducted on increasing the display area of ​​a display device by reducing the non-display area. Summary of the Invention

[0005] The display device may include a display panel, a printed circuit board, and a driver chip for driving the display panel. The driver chip and the printed circuit board may be located in the non-display area of ​​the display panel.

[0006] One or more embodiments include a display device in which the non-display area where the driver chip and printed circuit board are located can be reduced.

[0007] Additional aspects of this disclosure will be set forth in part in the description which follows, or will be apparent in part from the description, or may be learned by practicing embodiments of this disclosure.

[0008] According to one or more embodiments, a display device may include: a first substrate including a display area, a non-display area at least partially surrounding the display area, and a groove that overlaps with the non-display area and is recessed in the thickness direction; a plurality of pixels located on the first substrate and overlapping the display area; a driver chip located in the groove; and a printed circuit board located in the non-display area and overlapping the driver chip in a plan view.

[0009] The display device may further include: a first pad adjacent to the slot and electrically connected to the printed circuit board; a second pad located in the slot and electrically connected to the driver chip; and connection wiring extending from the first pad to the second pad, wherein the driver chip and the printed circuit board are electrically connected to each other.

[0010] The first and second pads can be arranged side by side in the direction extending from the edge of the first substrate in the plan view.

[0011] The display device may further include: a third pad located in a slot and electrically connected to a driver chip; and fan-out wiring extending from the third pad to the display area, wherein the first pad, the second pad, and the third pad are arranged side by side with each other in the direction of the edge extension of the first substrate in a plan view.

[0012] The groove may include a first edge adjacent to the display area, a second edge between the first pad and the second pad, and a third edge adjacent to the edge of the first substrate, and the connecting wiring extends to intersect at least one of the first edge and the second edge.

[0013] The display device may further include: a third pad located in a slot and electrically connected to a driver chip; a fan-out wiring extending from the third pad to the display area; and a data line electrically connected to the fan-out wiring, wherein the data line is electrically connected to at least one of a plurality of pixels.

[0014] The non-display area may include a groove region overlapping with the groove and a peripheral region adjacent to the groove region, and the thickness of the first substrate in the groove region is less than the thickness of the first substrate in the peripheral region.

[0015] The depth of the groove can be greater than the thickness of the driver chip.

[0016] The display device may further include: a second substrate facing the first substrate; a display element layer between the first substrate and the second substrate; and an anti-reflective layer located on the second substrate.

[0017] The first substrate may include glass.

[0018] According to one or more embodiments, a display device includes: a first substrate including a display area, a non-display area at least partially surrounding the display area, and a groove overlapping the non-display area and recessed in a thickness direction; a plurality of pixels located on the first substrate and overlapping the display area; a driver chip located in the groove; a printed circuit board located in the non-display area; a first pad adjacent to the groove and electrically connected to the printed circuit board; and a second pad located in the groove and electrically connected to the driver chip, wherein the first pad and the second pad are arranged side by side with each other in a plan view in a direction extending from the edge of the first substrate.

[0019] In a plan view, the printed circuit board can overlap with the driver chip.

[0020] The display device may further include: connection wiring extending from the first pad to the second pad, wherein the driver chip and the printed circuit board are electrically connected to each other.

[0021] The groove may include a first edge adjacent to the display area, a second edge between the first pad and the second pad, and a third edge adjacent to the edge of the first substrate, and the connecting wiring extends to intersect at least one of the first edge and the second edge.

[0022] The display device may further include: a third pad located in a slot and electrically connected to a driver chip; and fan-out wiring extending from the third pad to the display area, wherein the first pad, the second pad, and the third pad are arranged side by side with each other in the direction of the edge extension of the first substrate in a plan view.

[0023] The display device may further include: a data line electrically connected to a fan-out wiring, wherein the data line is electrically connected to at least one of a plurality of pixels.

[0024] The non-display area may include a groove region overlapping with the groove and a peripheral region adjacent to the groove region, and the thickness of the first substrate in the groove region is less than the thickness of the first substrate in the peripheral region.

[0025] The depth of the groove can be greater than the thickness of the driver chip.

[0026] The display device may further include: a second substrate facing the first substrate; a display element layer between the first substrate and the second substrate; and an anti-reflective layer located on the second substrate.

[0027] The first substrate may include glass. Attached Figure Description

[0028] The above and other aspects, features and advantages of the embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 This is a schematic plan view illustrating a display device according to an embodiment;

[0030] Figure 2 The diagram shows along Figure 1 A schematic cross-sectional view of the display device taken by line A-A';

[0031] Figure 3 This is an equivalent circuit diagram showing one pixel of the display panel;

[0032] Figure 4 It is shown in the figure. Figure 1 A partial enlarged view of part B of the display device;

[0033] Figure 5 The diagram shows along Figure 4 A schematic cross-sectional view of the display device taken by line C-C';

[0034] Figure 6The diagram shows along Figure 4 A schematic cross-sectional view of the display device taken by line D-D';

[0035] Figure 7 The diagram shows along Figure 1 A schematic cross-sectional view of the display device taken by line E-E';

[0036] Figure 8 This is a schematic plan view of a display device according to a comparative example;

[0037] Figure 9 The diagram shows along Figure 8 A schematic cross-sectional view of the display device taken by line F-F'; and

[0038] Figure 10A , Figure 10B and Figure 10C This is a schematic plan view illustrating a display device according to various embodiments. Detailed Implementation

[0039] Reference will now be made in detail to the embodiments and accompanying drawings, wherein the same reference numerals refer to the same elements throughout. In this respect, embodiments may take different forms and should not be construed as limited to the description set forth herein. Accordingly, embodiments are described below with reference to the accompanying drawings only to explain aspects of this disclosure. As used herein, the term “and / or” includes any and all combinations of one or more of the listed associated items. Throughout this disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0040] Because this disclosure allows for various modifications and numerous embodiments, embodiments will be illustrated in the accompanying drawings and described in the detailed description. The effects and features of this disclosure, as well as the methods for achieving these effects and features, will become apparent from the embodiments described in detail below in conjunction with the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below and can be implemented in various forms.

[0041] Reference will now be made in detail to the embodiments, examples of which are illustrated in the accompanying drawings, in which the same elements are indicated by the same reference numerals, and therefore repeated descriptions thereof will be omitted.

[0042] Although terms such as "first" and "second" can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0043] As used herein, the singular forms “a” and “the (said)” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0044] It will be further understood that the terms “comprising” or “including” as used herein indicate the presence of a stated feature or component, but do not exclude the presence or addition of one or more other features or components.

[0045] It will be further understood that when a layer, area, or component is referred to as being "on" another layer, area, or component, it can be directly on that other layer, area, or component, or it can be indirectly on that other layer, area, or component with an intervening layer, area, or component located therebetween.

[0046] For ease of explanation, the dimensions of components in the accompanying drawings may be exaggerated or reduced. For example, the dimensions and thicknesses of elements in the drawings are arbitrarily shown for ease of explanation, but this disclosure is not limited thereto.

[0047] When embodiments can be implemented differently, the specific process sequence may differ from the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description.

[0048] It will be understood that when a layer, area, or component is referred to as a “connection,” the layer, area, or component may be directly connected, or may be indirectly connected with an intermediary layer, area, or component located therebetween. For example, when a layer, area, or component is referred to as an “electrical connection,” these layers, areas, or components may be directly electrically connected, or may be indirectly electrically connected with an intermediary layer, area, or component located therebetween.

[0049] Furthermore, in this specification, the phrase "in a plan view" refers to the view of the object portion from above, and the phrase "in a schematic cross-sectional view" refers to the view of a cross-section taken by vertically cutting the object portion from the side. Additionally, the terms "overlapping" or "overlapping" mean that the first object may be above, below, or to the side of the second object, and vice versa. Furthermore, the term "overlapping" can include layering, stacking, facing or confronting, extending over, covering or partially covering, or any other suitable term known and understood by one of ordinary skill in the art. The terms "facing" and "confronting" mean that the first object may be directly or indirectly opposite the second object. In the case where a third object is located between the first and second objects, the first and second objects can be understood as indirectly opposite each other, although still facing each other.

[0050] When a layer, region, substrate, or area is referred to as being "on" another layer, region, substrate, or area, it can be directly on that other layer, region, substrate, or area, or an intervening layer, region, substrate, or area may exist therein. Conversely, when a layer, region, substrate, or area is referred to as being "directly on" another layer, region, substrate, or area, an intervening layer, region, substrate, or area may not exist therein. Furthermore, when a layer, region, substrate, or area is referred to as being "below" another layer, region, substrate, or area, it can be directly below that other layer, region, substrate, or area, or an intervening layer, region, substrate, or area may exist therein. Conversely, when a layer, region, substrate, or area is referred to as being "directly below" another layer, region, substrate, or area, an intervening layer, region, substrate, or area may not exist therein. Furthermore, "on" or "above" can include being positioned on or below an object and does not necessarily imply a direction based on gravity.

[0051] For ease of description, the spatial relative terms “below,” “below,” “down,” “above,” or “upper,” etc., may be used herein to describe the relationship between one element or component and another, as illustrated in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. For example, in the case where the device illustrated in the drawings is flipped, a device positioned “below” or “below” another device may be placed “above” the other device. Accordingly, the illustrative term “below” may include both a lower position and an upper position. The device may also be oriented in other directions, and therefore, the spatial relative terms may be interpreted differently depending on the orientation.

[0052] A display device used to display images can be a portable mobile device such as a game console, multimedia device, or mini personal computer. Embodiments of the display device described below may include liquid crystal displays, electrophoretic displays, organic light-emitting displays, inorganic light-emitting displays, field emission displays, surface conduction electron emission displays, quantum dot displays, plasma displays, and cathode ray displays. Although an organic light-emitting display device is used as the display device according to the embodiments, any of the various display devices described above may be used.

[0053] Figure 1 This is a schematic plan view of the display device 1 according to an embodiment.

[0054] refer to Figure 1 The display device 1 can display images. In an embodiment, the display device 1 may include a display panel DP, a driver chip D-IC, and a printed circuit board PCB. The display panel DP may include a first substrate 10, pixels PX, scan lines SL, data lines DL, and fan-out wiring FWL.

[0055] In one embodiment, the first substrate 10 may include glass. In another embodiment, the first substrate 10 may include a polymeric resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate. In another embodiment, the first substrate 10 may have a multilayer structure including a barrier layer and a base layer (not shown) comprising a polymeric resin. The following description assumes that the first substrate 10 comprises glass.

[0056] The first substrate 10 may include a display area DA and a non-display area NDA. The display area DA may be an area for displaying an image. Pixels PX may be located in the display area DA. In an embodiment, multiple pixels PX may be arranged in the display area DA.

[0057] The non-display area NDA can be an area where no image is displayed. The non-display area NDA can at least partially surround the display area DA. In an embodiment, the non-display area NDA can completely surround the display area DA. The driving circuitry and / or power wiring of the display panel DP can be located in the non-display area NDA.

[0058] A slot Gv can be provided in the first substrate 10. In an embodiment, the slot Gv may overlap with the non-display area NDA. In an embodiment, the slot Gv may be... Figure 1 The slot Gv is spaced apart from the display area DA in the -y direction. In one embodiment, one slot Gv may overlap with the non-display area NDA. In another embodiment, multiple slots Gv may overlap with the non-display area NDA.

[0059] The groove Gv can be recessed in the thickness direction of the first substrate 10. For example, the groove Gv can be... Figure 1 The recess is in the -z direction. The driver chip D-IC can be provided in the slot Gv.

[0060] Pixel PX can be located within the display area DA. Pixel PX can emit light. Accordingly, the display panel DP can display an image using the light emitted from the pixel PX. In an embodiment, pixel PX can be located on the first substrate 10 and overlap with the display area DA. Pixel PX can be arranged in a first direction and / or a second direction intersecting the first direction. For example, an acute angle, a right angle, or an obtuse angle can be formed between the first direction and the second direction. The first direction will be assumed below to be... Figure 1 The x-direction or -x-direction and the second direction is Figure 1 The y-direction or -y-direction can be described in detail.

[0061] A pixel (PX) may include pixel circuitry (PC) and a display element (DPE). The pixel circuitry (PC) may be electrically connected to a scan line (SL) configured to transmit scan signals and a data line (DL) configured to transmit data signals. The pixel circuitry (PC) can receive scan signals and data signals and can drive the display element (DPE).

[0062] In one embodiment, the display element DPE can be an organic light-emitting diode (OLED) including an organic emitting layer. In another embodiment, the display element DPE can be a light-emitting diode (LED). The LED can have micrometer-scale or nanometer-scale dimensions. For example, the LED can be a micro LED. In another embodiment, the LED can be a nanorod LED. The nanorod LED can include gallium nitride (GaN). In another embodiment, a color conversion layer can be located on the nanorod LED. The color conversion layer can include quantum dots. In another embodiment, the display element DPE can be a quantum dot LED including a quantum dot emitting layer. In yet another embodiment, the display element DPE can be an inorganic LED including inorganic semiconductors.

[0063] A scan line SL can transmit a scan signal. In an embodiment, the scan line SL can extend in a first direction (e.g., the x-direction or the -x-direction). The scan line SL can be electrically connected to a pixel PX. In an embodiment, the scan line SL can be electrically connected to at least one of the pixels PX. In an embodiment, the scan line SL can receive a scan signal from a driving circuit (not shown).

[0064] The data line DL can transmit data signals. In an embodiment, the data line DL can extend in a second direction (e.g., the y-direction or the -y-direction). The data line DL can be electrically connected to the pixel PX. In an embodiment, the data line DL can be electrically connected to at least one of the pixels PX.

[0065] The fan-out wiring (FWL) can extend from the non-display area NDA to the display area DA. In one embodiment, the fan-out wiring (FWL) can be electrically connected to the data line DL. In another embodiment, the fan-out wiring (FWL) and the data line DL can be integrated with each other. In yet another embodiment, the fan-out wiring (FWL) can be a wiring different from the data line DL but electrically connected to it.

[0066] The fan-out wiring (FWL) can extend from the display area DA to the slot Gv provided in the non-display area NDA. In an embodiment, the fan-out wiring (FWL) can be electrically connected to the driver chip D-IC in the slot Gv.

[0067] The driver chip D-IC can receive control signals and power supply voltages. In an embodiment, the driver chip D-IC can generate and output signals and voltages for driving the display panel DP. The signals and / or voltages generated by the driver chip D-IC can be transmitted via fan-out wiring (FWL). The driver chip D-IC may include an integrated circuit. The driver chip D-IC may be located in a slot Gv. In an embodiment, the driver chip D-IC can be provided in a slot Gv. For example, the driver chip D-IC can be mounted in a slot Gv.

[0068] The printed circuit board (PCB) can be electrically connected to the display panel (DP). In one embodiment, the PCB can be electrically connected to the driver chip (D-IC). In another embodiment, the PCB can apply control signals and power supply voltages to the driver chip (D-IC). In yet another embodiment, for example, an integrated circuit can be located on the PCB.

[0069] The printed circuit board (PCB) can be located within the non-display area (NDA). In an embodiment, in a plan view, the PCB can overlap with the driver chip (D-IC). Accordingly, the area occupied by the driver chip (D-IC) and the PCB within the NDA can be reduced. For example, the NDA located at the lower end of the display panel (DP) can be reduced. Furthermore, the area occupied by the display area (DA) within the display panel (DP) can be increased.

[0070] In one embodiment, the printed circuit board (PCB) can be a flexible printed circuit board that can be bent. In another embodiment, the PCB can be a rigid printed circuit board, and therefore may not be able to bend well. In other embodiments, the PCB can be a hybrid printed circuit board that includes both rigid and flexible printed circuit boards.

[0071] Figure 2 The diagram shows along Figure 1 A schematic cross-sectional view of display device 1 taken by line A-A'. Figure 2 In, with Figure 1 The same components are indicated by the same reference numerals, and therefore, repeated descriptions of them will be omitted.

[0072] refer to Figure 2 The display device 1 may include a display panel DP. The display panel DP may include a first substrate 10, a display element layer 20, a second substrate 30, a sealing member 40, and an anti-reflective layer 50.

[0073] The display element layer 20 may be located on the first substrate 10. The display element layer 20 may include display elements. In an embodiment, the display element layer 20 may include multiple display elements.

[0074] although Figure 2 Although not shown, the pixel circuit layer may be arranged between the display element layer 20 and the first substrate 10. The pixel circuit layer may include pixel circuits. In an embodiment, the pixel circuit layer may include multiple pixel circuits.

[0075] The second substrate 30 may be located on the display element layer 20. In an embodiment, the display element layer 20 may be disposed between the first substrate 10 and the second substrate 30. The second substrate 30 may be a transparent component. In an embodiment, the second substrate 30 may include glass. The first substrate 10 and the second substrate 30 may be connected to each other by a sealing member 40. Accordingly, the internal space between the first substrate 10 and the second substrate 30 may be sealed. A moisture-absorbing material and / or a filling material may be located in this internal space.

[0076] A sealing member 40 may be disposed between the first substrate 10 and the second substrate 30. The sealing member 40 may be a sealant. In another embodiment, the sealing member 40 may include a material that can be laser-cured. For example, the sealing member 40 may be a glass frit. The sealing member 40 may include a polyurethane resin, epoxy resin, or acrylic resin that is an organic sealant, or may include a silicone containing a material that is an inorganic sealant, an organic sealant, or an organic / inorganic hybrid sealant. For example, the polyurethane resin may include polyurethane acrylate. For example, the acrylic resin may include butyl acrylate and ethylhexyl acrylate. The sealing member 40 may include a thermosetting material.

[0077] In another embodiment, the encapsulation layer, replacing the second substrate 30, may be located on the display element layer 20. The encapsulation layer may include at least one inorganic encapsulation layer and at least one organic encapsulation layer covering the display element layer 20. In embodiments, the at least one inorganic encapsulation layer and at least one organic encapsulation layer may be stacked alternately. The inorganic encapsulation layer may include alumina (Al2O3), titanium dioxide (TiO2), tantalum oxide (Ta2O5), or zinc oxide (ZnO). x It can be ZnO or ZnO2), silicon oxide (SiO2), or silicon nitride (SiN). x The encapsulation layer may contain at least one inorganic material selected from silicon oxynitride (SiON). The organic encapsulation layer may include polymeric materials. For example, polymeric materials may include acrylic resins, epoxy resins, polyimides, and polyethylene. In one embodiment, the organic encapsulation layer may include acrylates. In another embodiment, the encapsulation layer and the second substrate 30 may be simultaneously disposed on the display element layer 20.

[0078] An anti-reflective layer 50 may be located on the second substrate 30. The anti-reflective layer 50 can reduce the reflectivity of light incident on the display device 1. In an embodiment, the anti-reflective layer 50 may include a phase retarder and / or a polarizer. The phase retarder may be a film-type phase retarder or a liquid crystal-coated phase retarder, and may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may be a film-type polarizer or a liquid crystal-coated polarizer. A film-type polarizer may include a stretched synthetic resin film, and a liquid crystal-coated polarizer may include liquid crystals arranged in a given or predetermined configuration. The phase retarder and polarizer may further include a protective film.

[0079] In another embodiment, the antireflective layer 50 may include a black matrix and color filters. The color filters may be arranged to take into account the color of light emitted by each of the plurality of display elements of the display device 1. Each of the color filters may include a red, green, or blue pigment or dye. In one embodiment, in addition to pigments or dyes, each of the color filters may further include quantum dots. In other embodiments, some of the color filters may not include pigments or dyes and may include scattering particles such as titanium dioxide.

[0080] In another embodiment, the antireflection layer 50 may have a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer located in different layers. The first reflected light and the second reflected light reflected by the first reflective layer and the second reflective layer, respectively, can destructively interfere with each other, thereby reducing the reflectivity of external light.

[0081] In some embodiments, a touch sensor layer may be disposed between the second substrate 30 and the anti-reflective layer 50. The touch sensor layer can obtain coordinate information based on external input (e.g., a touch event).

[0082] Figure 3 This is an equivalent circuit diagram showing a pixel PX of a display panel.

[0083] refer to Figure 3 A pixel PX may include a pixel circuit PC and a display element DPE electrically connected to the pixel circuit PC. The pixel circuit PC may include a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. For example, the pixel PX may emit red, green, or blue light through the display element DPE, or it may emit red, green, blue, or white light.

[0084] The switching thin-film transistor T2 can be electrically connected to the scan line SL and the data line DL, and can transmit the data voltage or data signal Dm input from the data line DL to the driving thin-film transistor T1 according to the scan voltage or scan signal Sn input from the scan line SL.

[0085] The storage capacitor Cst can be electrically connected to the switching thin-film transistor T2 and the drive voltage line PL, and can store a voltage corresponding to the difference between the voltage received from the switching thin-film transistor T2 and the first power supply voltage ELVDD supplied to the drive voltage line PL.

[0086] The driving thin-film transistor T1 can be electrically connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL to the display element DPE in response to the value of the voltage stored in the storage capacitor Cst. Due to the driving current, the display element DPE can emit light with a certain brightness. The counter electrode (e.g., cathode) of the display element DPE can receive a second power supply voltage ELVSS.

[0087] Despite Figure 3 The pixel circuit PC shown includes two thin-film transistors, but the pixel circuit PC may include three or more thin-film transistors.

[0088] Figure 4 It is shown in the figure. Figure 1 A partially enlarged schematic diagram of part B of the display device 1. Figure 4 In, with Figure 1 The same components are indicated by the same reference numerals, and therefore, repeated descriptions of them will be omitted.

[0089] refer to Figure 4 The display device 1 may include a display panel DP, a driver chip D-IC, and a printed circuit board PCB. The display panel DP may include a first substrate 10, pads PAD, connection wiring CWL, fan-out wiring FWL, additional fan-out wiring AFWL, and data lines DL.

[0090] In this embodiment, the first substrate 10 may include glass. The first substrate 10 may include a display area DA and a non-display area NDA. The display area DA may be an area for displaying an image. Pixels may be located in the display area DA. In this embodiment, multiple pixels may be located in the display area DA.

[0091] The non-display area NDA can be an area where no image is displayed. The non-display area NDA can at least partially surround the display area DA. The non-display area NDA can include the slot area GA and the peripheral area PA.

[0092] The slot region GA may be a region overlapping with the slot Gv in the non-display region NDA. The peripheral region PA may be adjacent to or located outside the slot region GA. In an embodiment, the peripheral region PA may at least partially surround the slot region GA. For example, the peripheral region PA may completely surround the slot region GA. In an embodiment, the slot region GA may be a portion of the non-display region NDA that is recessed relative to the peripheral region PA in the thickness direction of the first substrate 10.

[0093] A groove Gv can be provided in the first substrate 10. In one embodiment, the groove Gv may overlap with the non-display area NDA. In another embodiment, the groove Gv may overlap with the groove area GA. The groove Gv may be recessed in the thickness direction of the first substrate 10. For example, the groove Gv may have a... Figure 4 The groove Gv has a concave shape in the -z direction. It can have a shape to accommodate the driver chip D-IC.

[0094] The slot Gv may include edges. In an embodiment, the slot region GA and the peripheral region PA may be defined or divided by the edges of the slot Gv. In an embodiment, the slot Gv may include a first edge ED1, a second edge ED2, a third edge ED3, and a fourth edge ED4. The first edge ED1 may be adjacent to the display region DA. For example, the display region DA may be located on one side of the first edge ED1. The third edge ED3 may be adjacent to the edge 10E of the first substrate 10. In other words, the third edge ED3 may be located between the edge 10E of the first substrate 10 and the first edge ED1. Each of the second edge ED2 and the fourth edge ED4 may extend from one end of the first edge ED1 to one end of the third edge ED3.

[0095] The pads (PADs) can electrically connect the components of the display device 1 to the display panel (DP). The pads (PADs) can be located in the non-display area (NDA). In this embodiment, multiple pads (PADs) can be provided. The pads (PADs) can be spaced apart from each other. The pads (PADs) can include a first pad (PAD1), a second pad (PAD2), a third pad (PAD3), and a fourth pad (PAD4).

[0096] The first pad PAD1 can be located outside the slot Gv. The fourth pad PAD4 can be adjacent to or located outside the slot Gv. For example, the first pad PAD1 and the fourth pad PAD4 can be located in the peripheral region PA. In an embodiment, multiple first pads PAD1 can be provided. In an embodiment, multiple fourth pads PAD4 can be provided.

[0097] The second pad PAD2 can be located in slot Gv. The third pad PAD3 can be located in slot Gv. For example, the second pad PAD2 and the third pad PAD3 can be located in slot region GA. In an embodiment, multiple second pads PAD2 can be provided. In an embodiment, multiple third pads PAD3 can be provided.

[0098] In a plan view, the first pad PAD1 and the second pad PAD2 can be arranged side by side with each other. In an embodiment, in a plan view, the first pad PAD1 and the second pad PAD2 can be arranged side by side with each other along the edge 10E of the first substrate 10. For example, in a plan view, the first pad PAD1 and the second pad PAD2 can be arranged side by side with each other in a first direction (e.g., the x-direction and the -x-direction).

[0099] In a plan view, the first pad PAD1, the second pad PAD2, and the third pad PAD3 can be arranged side by side with each other. In an embodiment, in a plan view, the first pad PAD1, the second pad PAD2, and the third pad PAD3 can be arranged side by side with each other along the edge 10E of the first substrate 10. For example, in a plan view, the first pad PAD1, the second pad PAD2, and the third pad PAD3 can be arranged side by side with each other in a first direction (e.g., the x-direction or the -x-direction).

[0100] In a plan view, the first pad PAD1, the second pad PAD2, the third pad PAD3, and the fourth pad PAD4 can be arranged side by side with each other. In an embodiment, in a plan view, the first pad PAD1, the second pad PAD2, the third pad PAD3, and the fourth pad PAD4 can be arranged side by side with each other along the edge 10E of the first substrate 10. Accordingly, in the display panel DP, the area occupied by the pads in the non-display area NDA can be reduced in a second direction (e.g., the y-direction or the -y-direction).

[0101] The connection routing line (CWL) can extend from the first pad PAD1 to the second pad PAD2. In an embodiment, the connection routing line (CWL) can electrically connect the first pad PAD1 to the second pad PAD2. In an embodiment, the connection routing line (CWL) can extend to the slot Gv. For example, the connection routing line (CWL) can extend from the peripheral region PA to the slot region GA.

[0102] The connection routing CWL can extend to intersect at least one of a first edge ED1 and a second edge ED2. In an embodiment, the second edge ED2 can be disposed between the first pad PAD1 and the second pad PAD2. A fourth edge ED4 can be disposed between the first pad PAD1 and the second pad PAD2. The connection routing CWL can include a first connection routing CWL1 and a second connection routing CWL2. The first connection routing CWL1 can extend to intersect the first edge ED1. For example, the first connection routing CWL1 can extend from the first pad PAD1 in a second direction (e.g., the y-direction or the -y-direction). The first connection routing CWL1 can extend in a first direction (e.g., the x-direction or the -x-direction). The first connection routing CWL1 can extend in the -y-direction and can intersect the first edge ED1. The second connection routing CWL2 can extend to intersect the second edge ED2. For example, the second connection routing CWL2 can extend from the first pad PAD1 in a first direction (e.g., the x-direction or the -x-direction) and can intersect the second edge ED2. In an embodiment, the second connection trace CWL2 may extend to intersect the fourth edge ED4. For example, the second connection trace CWL2 may extend from the first pad PAD1 in a first direction (e.g., the x-direction or the -x-direction) and may intersect the fourth edge ED4.

[0103] In some embodiments, the connection wiring CWL may not intersect with the third edge ED3. Accordingly, the area of ​​the non-display area NDA may be reduced in the second direction (e.g., the y-direction or the -y-direction). In some embodiments, the connection wiring CWL may intersect with the third edge ED3.

[0104] The fan-out routing (FWL) can extend from the third pad PAD3 to the display area DA. In an embodiment, the fan-out routing (FWL) can extend from the slot area GA to the peripheral area PA. Alternatively, the fan-out routing (FWL) can extend from the peripheral area PA to the display area DA. In an embodiment, multiple fan-out routing (FWL) lines can be provided.

[0105] In one embodiment, the fan-out wiring FWL can be electrically connected to the data line DL. In another embodiment, the fan-out wiring FWL and the data line DL can be integrated together. In yet another embodiment, the fan-out wiring FWL can be a wiring different from the data line DL but electrically connected to it.

[0106] Additional fan-out routing (AFWL) can extend from the fourth pad PAD4. For example, the additional fan-out routing (AFWL) can extend from the fourth pad PAD4 to the display area DA. In an embodiment, multiple additional fan-out routing (AFWL) can be provided.

[0107] The driver chip D-IC can be located in slot Gv. In this embodiment, the driver chip D-IC can be provided in slot Gv. The driver chip D-IC can be mounted in slot Gv. The driver chip D-IC can be electrically connected to the second pad PAD2. The driver chip D-IC can be electrically connected to the third pad PAD3. Accordingly, the signals and / or voltages generated by the driver chip D-IC can be transmitted via fan-out wiring FWL.

[0108] The printed circuit board (PCB) can be located within the non-display area (NDA). In an embodiment, in a plan view, the PCB can overlap with the driver chip (D-IC). Accordingly, the area occupied by the driver chip (D-IC) and the PCB within the NDA can be reduced. For example, the NDA located at the lower end of the display panel (DP) can be reduced.

[0109] The printed circuit board (PCB) can be electrically connected to the display panel (DP). The PCB can be electrically connected to the first pad (PAD1). Accordingly, the PCB and the driver chip (D-IC) can be electrically connected to each other. For example, the PCB and the driver chip (D-IC) can be electrically connected to each other via the first pad (PAD1), the connection trace (CWL), and the second pad (PAD2). Accordingly, the PCB can transmit control signals and / or power supply voltage to the driver chip (D-IC).

[0110] The printed circuit board (PCB) can be electrically connected to the fourth pad, PAD4. Accordingly, signals and / or voltages generated by the PCB can be transmitted via an additional fan-out wiring (AFWL). In other embodiments, signals generated by the display panel (DP) can be transmitted to the PCB via the additional fan-out wiring (AFWL). For example, coordinate information obtained from the display panel (DP) can be transmitted to the PCB via the additional fan-out wiring (AFWL).

[0111] Figure 5 The diagram shows along Figure 4 A schematic cross-sectional view of display device 1 taken by line C-C'. Figure 6 The diagram shows along Figure 4 A schematic cross-sectional view of display device 1 taken by line D-D'. Figure 5 and Figure 6 In, with Figure 4 The same components are indicated by the same reference numerals, and therefore, repeated descriptions of them will be omitted.

[0112] refer to Figure 5 and Figure 6 The display device 1 may include a display panel DP, a driver chip D-IC, and a printed circuit board PCB. The display panel DP may include a first substrate 10, pads, and connection wiring CWL.

[0113] The first substrate 10 may include a top surface 10US and a bottom surface 10LS. The top surface 10US and the bottom surface 10LS of the first substrate 10 may be opposite to each other. The first substrate 10 may include an edge 10E. The edge 10E of the first substrate 10 may extend from the top surface 10US of the first substrate 10 to the bottom surface 10LS of the first substrate 10. The edge 10E of the first substrate 10 may connect the top surface 10US of the first substrate 10 to the bottom surface 10LS of the first substrate 10.

[0114] The first substrate 10 may include a display area and a non-display area NDA. The non-display area NDA may at least partially surround the display area. The non-display area NDA may include a groove area GA and a peripheral area PA.

[0115] The slot region GA may overlap with the slot Gv in the non-display region NDA. The peripheral region PA may be adjacent to or located outside the slot region GA. In an embodiment, the peripheral region PA may at least partially surround the slot region GA. In an embodiment, the slot region GA may be a portion of the non-display region NDA that is recessed relative to the peripheral region PA in the thickness direction of the first substrate 10. The slot region GA may be a portion of the non-display region NDA where the top surface 10US of the first substrate 10 is recessed relative to the peripheral region PA.

[0116] The thickness 10t2 of the first substrate 10 in the trench region GA can be less than the thickness 10t1 of the first substrate 10 in the peripheral region PA. The thickness 10t2 of the first substrate 10 in the trench region GA can be the distance between the top surface 10US and the bottom surface 10LS of the first substrate 10 in the trench region GA. The thickness 10t1 of the first substrate 10 in the peripheral region PA can be the distance between the top surface 10US and the bottom surface 10LS of the first substrate 10 in the peripheral region PA.

[0117] A groove Gv can be provided in the first substrate 10. In one embodiment, the groove Gv may overlap with the non-display area NDA. In another embodiment, the groove Gv may overlap with the groove area GA. The groove Gv may be recessed in the thickness direction of the first substrate 10. For example, the groove Gv may have a... Figure 6 The groove Gv has a recessed shape in the -z direction. It can have a shape for accommodating the driver chip D-IC. In an embodiment, the groove Gv can be formed by performing wet etching and / or dry etching on the first substrate 10. Alternatively, the groove Gv can be formed by performing wet etching on the first substrate 10 followed by dry etching.

[0118] In an embodiment, the groove Gv may be defined by a first surface S1 and a second surface S2. The first surface S1 and the second surface S2 may be portions of the top surface 10US of the first substrate 10 that overlap with the groove region GA. The first surface S1 may be the portion of the top surface 10US of the first substrate 10 closest to the bottom surface 10LS of the first substrate 10. In an embodiment, the first surface S1 may be flat. In an embodiment, the depth Gvd of the groove Gv may be... Figure 6 The distance between the top surface 10US of the first substrate 10 in the peripheral region PA and the first surface S1 in the z-direction. In an embodiment, the sum of the depth Gvd of the groove Gv and the thickness 10t2 of the first substrate 10 in the groove region PA can be the thickness 10t1 of the first substrate 10 in the peripheral region PA. The second surface S2 can extend from the first surface S1 to the top surface 10US of the first substrate 10 in the peripheral region PA. In an embodiment, the second surface S2 can be inclined.

[0119] The groove Gv may include an edge. In an embodiment, the edge of the groove Gv may be the portion where the top surface 10US of the first substrate 10 in the peripheral region PA intersects with the second surface S2. In an embodiment, the groove region GA and the peripheral region PA may be defined or divided by the edge of the groove Gv. In an embodiment, the groove Gv may be defined by a first edge ED1 and a third edge ED3. The first edge ED1 may be adjacent to the display area. The third edge ED3 may be adjacent to the edge 10E of the first substrate 10. For example, the third edge ED3 may be located between the edge 10E of the first substrate 10 and the first edge ED1.

[0120] The pads can electrically connect the components of the display device 1 to the display panel DP. The pads can be located in the non-display area NDA. In an embodiment, multiple pads can be provided. The pads can be spaced apart from each other. In an embodiment, the pads can include a first pad PAD1 and a second pad PAD2.

[0121] The first pad PAD1 can be adjacent to or located outside the slot Gv. For example, the first pad PAD1 can be located in the peripheral region PA. The second pad PAD2 can be located in the slot Gv. For example, the second pad PAD2 can be located in the slot region GA.

[0122] The connection wiring CWL can extend from the first pad PAD1 to the second pad PAD2. In an embodiment, the connection wiring CWL can electrically connect the first pad PAD1 to the second pad PAD2. In an embodiment, the connection wiring CWL can extend to the slot Gv. For example, the connection wiring CWL can extend from the peripheral region PA to the slot region GA. The connection wiring CWL can extend from the top surface 10US of the first substrate 10 in the peripheral region PA to the second surface S2. The connection wiring CWL can extend from the second surface S2 to the first surface S1.

[0123] Despite Figure 5 and Figure 6 The fan-out wiring is not shown, but it can extend to the slot Gv. For example, the fan-out wiring can extend from the peripheral region PA to the slot region GA. The fan-out wiring can extend from the top surface 10US of the first substrate 10 in the peripheral region PA to the second surface S2. The fan-out wiring can extend from the second surface S2 to the first surface S1.

[0124] exist Figure 5 and Figure 6 In this embodiment, the connection trace CWL, the first pad PAD1, and the second pad PAD2 are integrally formed with each other. In another embodiment, at least one of the first pad PAD1 and the second pad PAD2 is not integral with the connection trace CWL. The connection trace CWL may be a different trace from at least one of the first pad PAD1 and the second pad PAD2, and may be electrically connected to the first pad PAD1 and the second pad PAD2.

[0125] The driver chip D-IC can be located in a slot Gv. In an embodiment, the driver chip D-IC can be provided in the slot Gv. The driver chip D-IC can be mounted in the slot Gv. In an embodiment, the driver chip D-IC can include a driver chip electrode D-ICE. The driver chip electrode D-ICE can be electrically connected to the second pad PAD2. In an embodiment, the driver chip electrode D-ICE and the second pad PAD2 can be electrically connected to each other through an anisotropic conductive film. In another embodiment, the driver chip electrode D-ICE and the second pad PAD2 can be electrically connected to each other by soldering. In another embodiment, the driver chip electrode D-ICE and the second pad PAD2 can be directly electrically connected to each other. For example, a portion of the driver chip electrode D-ICE and a portion of the second pad PAD2 can be melted and adhered to each other.

[0126] In this embodiment, the thickness D-ICt of the driver chip D-IC can be less than the depth Gvd of the slot Gv. The thickness D-ICt of the driver chip D-IC can be within... Figure 6The distance between the bottom surface of the driver chip electrode D-ICE and the top surface of the driver chip D-IC in the z-direction. The depth Gvd of the groove Gv can be greater than the thickness D-ICt of the driver chip D-IC. Accordingly, the driver chip D-IC can be completely provided in the groove Gv.

[0127] The printed circuit board (PCB) can be located within the non-display area (NDA). In an embodiment, in a plan view, the PCB can overlap with the driver chip (D-IC). Accordingly, the area occupied by the driver chip (D-IC) and the PCB within the NDA can be reduced. For example, the NDA located at the lower end of the display panel (DP) can be reduced.

[0128] A printed circuit board (PCB) can be electrically connected to a display panel (DP). In one embodiment, the PCB may include a printed circuit board electrode (PCBE). The PCBE can be electrically connected to a first pad (PAD1). In one embodiment, the PCBE and the first pad (PAD1) can be electrically connected to each other via an anisotropic conductive film. In another embodiment, the PCBE and the first pad (PAD1) can be electrically connected to each other by soldering. In yet another embodiment, the PCBE and the first pad (PAD1) can be directly electrically connected to each other. For example, a portion of the PCBE and a portion of the first pad (PAD1) can be melted and adhered to each other.

[0129] The printed circuit board (PCB) and the driver chip (D-IC) can be electrically connected to each other. For example, the PCB and the driver chip (D-IC) can be electrically connected to each other via a first pad (PAD1), a connection trace (CWL), and a second pad (PAD2). Accordingly, the PCB can apply control signals and / or power supply voltages to the driver chip (D-IC).

[0130] Figure 7 The diagram shows along Figure 1 A schematic cross-sectional view of display device 1 taken by line E-E'.

[0131] refer to Figure 7 The display device 1 may include a display panel DP. The display panel DP may include a first substrate 10, a pixel circuit layer PCL, and a display element layer 20. The pixel circuit layer PCL and the display element layer 20 may be sequentially arranged on the first substrate 10.

[0132] In one embodiment, the first substrate 10 may include a display area DA.

[0133] A barrier layer (not shown) may be further disposed between the pixel circuit layer PCL and the first substrate 10. The barrier layer for preventing the penetration of external foreign matter may have a composition such as silicon nitride (SiN).x It is a single-layer or multi-layer structure of inorganic materials such as silicon dioxide (SiO2).

[0134] The pixel circuit layer PCL may be located on the first substrate 10. The pixel circuit layer PCL may include a thin film transistor TFT and a buffer layer 111, a first gate insulating layer 112, a second gate insulating layer 113, an interlayer insulating layer 114, and an organic insulating layer 115 located below and / or above the elements of the thin film transistor TFT.

[0135] The buffer layer 111 may be located on the first substrate 10. The buffer layer 111 may include materials such as silicon nitride (SiN). x Inorganic insulating materials, such as silicon oxynitride (SiON) or silicon oxide (SiO2), may have a single-layer or multi-layer structure including inorganic insulating materials.

[0136] A thin-film transistor (TFT) may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. The semiconductor layer Act may include polycrystalline silicon. In embodiments, the semiconductor layer Act may include amorphous silicon, oxide semiconductor, or organic semiconductor. The semiconductor layer Act may include a channel region Act1 and a source region Act2 and a drain region Act3 located on either side of the channel region Act1.

[0137] The gate electrode GE may overlap with the channel region Act1. The gate electrode GE may comprise a low-resistance metallic material. The gate electrode GE may comprise a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer or multi-layer structure comprising the aforementioned materials.

[0138] The first gate insulating layer 112 between the semiconductor layer Act and the gate electrode GE may include materials such as silicon oxide (SiO2) and silicon nitride (SiN). x Silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO) x It can be an inorganic insulating material (ZnO or ZnO2).

[0139] The second gate insulating layer 113 may cover the gate electrode GE. Similar to the first gate insulating layer 112, the second gate insulating layer 113 may include materials such as silicon oxide (SiO2) and silicon nitride (SiN). x Silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO) x It can be an inorganic insulating material (ZnO or ZnO2).

[0140] The upper electrode Cst2 of the storage capacitor Cst may be located on the second gate insulating layer 113. The upper electrode Cst2 may overlap with the gate electrode GE located below the upper electrode Cst2. For example, the gate electrode GE and the upper electrode Cst2, which overlap each other and are located between the second gate insulating layer 113, can constitute the storage capacitor Cst. The gate electrode GE can be used as the lower electrode Cst1 of the storage capacitor Cst. The storage capacitor Cst and the thin-film transistor TFT may overlap each other. In some embodiments, the storage capacitor Cst may not overlap with the thin-film transistor TFT.

[0141] The upper electrode Cst2 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and may have a single-layer or multi-layer structure comprising the above materials.

[0142] The interlayer insulating layer 114 may cover the upper electrode Cst2. The interlayer insulating layer 114 may include silicon oxide (SiO2) or silicon nitride (SiN). x Silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO) x (It can be ZnO or ZnO2). The interlayer insulation layer 114 can have a single-layer or multi-layer structure including the above-mentioned inorganic insulating material.

[0143] Each of the source electrode SE and the drain electrode DE may be located on the interlayer insulating layer 114. Each of the source electrode SE and the drain electrode DE may include a material with high conductivity. Each of the source electrode SE and the drain electrode DE may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a single-layer or multi-layer structure comprising the aforementioned materials. In an embodiment, each of the source electrode SE and the drain electrode DE may have a multi-layer structure comprising Ti / Al / Ti.

[0144] Organic insulating layer 115 may include organic insulating materials. Organic insulating layer 115 may include organic insulating materials such as general polymers (e.g., polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or mixtures thereof.

[0145] The display element layer 20 may be located on the pixel circuit layer PCL. The display element layer 20 may include an organic light-emitting diode (OLED) that is a display element and a pixel defining film 240. For example, the organic light-emitting diode (OLED) may emit red, green, or blue light, or it may emit red, green, blue, or white light. The organic light-emitting diode (OLED) may include a pixel electrode 210, an emitting layer 220, and a counter electrode 230.

[0146] Pixel electrode 210 may be located on organic insulating layer 115. Pixel electrode 210 may be electrically connected to thin-film transistor (TFT) through contact holes in organic insulating layer 115. Pixel electrode 210 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, pixel electrode 210 may include a reflective film comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. In another embodiment, pixel electrode 210 may further include a film formed of ITO, IZO, ZnO, or In2O3 above / below the reflective film.

[0147] A pixel defining film 240 with an opening 240OP can be located on the pixel electrode 210, with the central portion of the pixel electrode 210 exposed through the opening 240OP. The pixel defining film 240 can include an organic insulating material and / or an inorganic insulating material. The opening 240OP can define an emission region EA of light emitted by an organic light-emitting diode (OLED). For example, the width of the opening 240OP can be the width of the emission region EA.

[0148] The emitting layer 220 may be located in the opening 240OP of the pixel-defining film 240. The emitting layer 220 may comprise a high-molecular-weight organic material or a low-molecular-weight organic material that emits light of a single color. Although Figure 7 Not shown, but the first and second functional layers can be disposed below and above the emitter layer 220, respectively. For example, the first functional layer may include a hole transport layer (HTL), or may include a hole transport layer and a hole injection layer (HIL). The second functional layer disposed above the emitter layer 220 may be optional. The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL). Similar to the counter electrode 230 described below, the first and / or second functional layers may be a common layer that completely covers the first substrate 10.

[0149] Counter electrode 230 may be located on emitter layer 220. Counter electrode 230 may be formed of a conductive material having a low work function. For example, counter electrode 230 may include a (semi-)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Alternatively, counter electrode 230 may further include a layer formed of ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer comprising the above-described materials.

[0150] Figure 8 This is a schematic plan view of the display device 1-1 according to the comparative example. Figure 9 The diagram shows along Figure 8 A schematic cross-sectional view of display device 1-1 taken by line F-F'.

[0151] refer to Figure 8 and Figure 9 The display device 1-1 may include a display panel DP-1, a driver chip D-IC, and a printed circuit board PCB. The display panel DP-1 may include a first substrate 10, a pixel PX, a first pad PAD1, a second pad PAD2, a third pad PAD3, a connection wiring CWL, a fan-out wiring FWL, and an additional fan-out wiring AFWL.

[0152] The first substrate 10 may include a display area DA and a non-display area NDA. In a comparative example, the first substrate 10 may not include a groove in the non-display area NDA. For example, the thickness 10t of the first substrate 10 in the non-display area NDA may be constant. The top surface 10US and the bottom surface 10LS of the first substrate 10 may extend in a first direction (e.g., the x-direction or the -x-direction) and / or a second direction (e.g., the y-direction or the -y-direction).

[0153] The first pad PAD1, the second pad PAD2, and the third pad PAD3 can be arranged side by side in a second direction (e.g., the y-direction or the -y-direction).

[0154] The driver chip D-IC may be located on the top surface 10US of the first substrate 10. The driver chip D-IC may include driver chip electrodes D-ICE. In a comparative example, the driver chip electrodes D-ICE may include a first driver chip electrode D-ICE1 and a second driver chip electrode D-ICE2. The first driver chip electrode D-ICE1 may be electrically connected to a second pad PAD2. The second driver chip electrode D-ICE2 may be electrically connected to a third pad PAD3.

[0155] The printed circuit board (PCB) can be arranged side-by-side with the driver chip (D-IC). The PCB and D-IC can also be arranged side-by-side in a second direction (e.g., the y-direction or the -y-direction). The PCB may include printed circuit board electrodes (PCBE). The PCBE can be electrically connected to the first pad (PAD1).

[0156] In the comparative example, the driver chip D-IC and the printed circuit board (PCB) can be arranged side-by-side in a second direction (e.g., the y-direction or the -y-direction). Accordingly, the length of the non-display area NDA in the second direction (e.g., the y-direction or the -y-direction) can be increased.

[0157] However, return to reference Figure 1 The first substrate 10 may include a groove that overlaps with the non-display area NDA and is recessed in the thickness direction. A driver chip D-IC may be provided in the groove. Accordingly, the length of the non-display area NDA in a second direction (e.g., the y-direction or the -y-direction) may be reduced.

[0158] Figure 10A , Figure 10B and Figure 10C This is a schematic plan view illustrating a display device 1 according to various embodiments. Figure 10A , Figure 10B and Figure 10C In, with Figure 1 The same components are indicated by the same reference numerals, and therefore, repeated descriptions of them will be omitted.

[0159] refer to Figure 10A , Figure 10B and Figure 10C The display device 1 may include a display panel DP, a driver chip D-IC, and a printed circuit board PCB. The display panel DP may include a first substrate 10 and pixels PX.

[0160] The first substrate 10 may include a display area DA and a non-display area NDA. The display area DA may be the area where the display panel DP displays an image. Pixels PX may be located in the display area DA. The non-display area NDA may be an area where no image is displayed.

[0161] A groove Gv can be provided in the first substrate 10. The groove Gv can be recessed in the thickness direction of the first substrate 10. The groove Gv can accommodate a driver chip D-IC. In an embodiment, the groove Gv can overlap with a non-display area NDA. (Reference) Figure 10A The slot Gv can be Figure 10A It is spaced apart from the display area DA in the x-direction. (Reference) Figure 10B The slot Gv can be Figure 10B It is spaced apart from the display area DA in the -x direction. (Reference) Figure 10C The slot Gv can be Figure 10C It is spaced apart from the display area DA in the y-direction. The position of slot Gv can be changed in various ways.

[0162] As described above, a display device according to one or more embodiments may include: a first substrate including a groove that overlaps with a non-display area and is recessed in the thickness direction; and a driving chip located in the groove. Accordingly, the non-display area of ​​the display device may be reduced, and the display area may be increased.

[0163] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made to these embodiments without departing from the spirit and scope defined by the claims.

Claims

1. A display device, comprising: The first substrate includes a display area, a non-display area at least partially surrounding the display area, and a groove that overlaps with the non-display area and is recessed in the thickness direction; Multiple pixels are located on the first substrate and overlap with the display area; The driver chip is located in the slot; A printed circuit board is located in the non-display area and overlaps with the driver chip in the plan view; The first pad is adjacent to the slot and electrically connected to the printed circuit board; The second pad is located in the slot and is electrically connected to the driver chip; as well as The connection wiring extends from the first pad along the top surface of the first substrate surrounding the trench, the side surface of the trench, and the bottom surface of the trench to the second pad.

2. The display device according to claim 1, wherein The driver chip and the printed circuit board are electrically connected to each other.

3. The display device of claim 2, wherein, The first pad and the second pad are arranged side by side in the plan view in the direction extending from the edge of the first substrate.

4. The display device according to claim 2, further comprising: The third pad is located in the slot and is electrically connected to the driver chip; as well as Fan-out wiring extends from the third pad to the display area, wherein... The first pad, the second pad, and the third pad are arranged side by side in the plan view in the direction extending from the edge of the first substrate.

5. The display device according to claim 2, wherein, The groove includes a first edge adjacent to the display area, a second edge between the first pad and the second pad, and a third edge adjacent to the edge of the first substrate. The connecting wiring extends to intersect at least one of the first edge and the second edge.

6. The display device according to claim 1, further comprising: The third pad is located in the slot and is electrically connected to the driver chip; Fan-out wiring extends from the third pad to the display area; as well as The data cable is electrically connected to the fan-out wiring, wherein, The data line is electrically connected to at least one of the plurality of pixels.

7. The display device according to claim 1, wherein, The non-display area includes a slot area overlapping the slot and a peripheral area adjacent to the slot area, and The thickness of the first substrate in the trench region is less than the thickness of the first substrate in the peripheral region.

8. The display device according to claim 1, wherein The depth of the groove is greater than the thickness of the driver chip.

9. The display device according to any one of claims 1 to 8, further comprising: The second substrate faces the first substrate; The display element layer is located between the first substrate and the second substrate; as well as An anti-reflective layer is located on the second substrate.

10. The display device according to any one of claims 1 to 8, wherein, The first substrate includes glass.

11. A display device, comprising: The first substrate includes a display area, a non-display area at least partially surrounding the display area, and a groove that overlaps with the non-display area and is recessed in the thickness direction; Multiple pixels are located on the first substrate and overlap with the display area; The driver chip is located in the slot; The printed circuit board is located in the non-display area; The first pad is adjacent to the slot and electrically connected to the printed circuit board; as well as The second pad, located in the slot and electrically connected to the driver chip, wherein... The first pad and the second pad are arranged side by side in the plan view in the direction extending from the edge of the first substrate.

12. The display device of claim 11, wherein, The printed circuit board overlaps with the driver chip in the plan view.

13. The display device according to claim 11, further comprising: Connecting traces extend from the first pad to the second pad, wherein... The driver chip and the printed circuit board are electrically connected to each other.

14. The display device according to claim 13, wherein, The groove includes a first edge adjacent to the display area, a second edge between the first pad and the second pad, and a third edge adjacent to the edge of the first substrate. The connecting wiring extends to intersect at least one of the first edge and the second edge.

15. The display device according to claim 11, further comprising: The third pad is located in the slot and is electrically connected to the driver chip; as well as Fan-out wiring extends from the third pad to the display area, wherein... The first pad, the second pad, and the third pad are arranged side by side with each other in the direction extending from the edge of the first substrate in the plan view.

16. The display device according to claim 15, further comprising: The data cable is electrically connected to the fan-out wiring, wherein, The data line is electrically connected to at least one of the plurality of pixels.

17. The display device according to claim 11, wherein, The non-display area includes a slot area overlapping the slot and a peripheral area adjacent to the slot area, and The thickness of the first substrate in the trench region is less than the thickness of the first substrate in the peripheral region.

18. The display device of claim 11, wherein, The depth of the groove is greater than the thickness of the driver chip.

19. The display device according to any one of claims 11 to 18, further comprising: The second substrate faces the first substrate; The display element layer is located between the first substrate and the second substrate; as well as An anti-reflective layer is located on the second substrate.

20. A display device according to any one of claims 11 to 18, wherein, The first substrate includes glass.

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