RF amplifier with shielded transmission line structure

Abstract

An RF transistor amplifier includes an RF transistor amplifier die having a semiconductor layer structure, a coupling element on an upper surface of the semiconductor layer structure, and an interconnect structure on an upper surface of the coupling element such that the RF transistor amplifier die and the interconnect structure are in a stacked arrangement. The coupling element includes a first shielded transmission line structure.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Patent Application Serial No. 16 / 888,957, filed June 1, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to microelectronic devices, and more particularly to high-power, high-frequency transistor amplifiers. Background Technology

[0004] Circuits requiring high power handling capabilities when operating at high frequencies (such as R-band (0.5-1 GHz), S-band (3 GHz), X-band (10 GHz), Ku-band (12-18 GHz), K-band (18-27 GHz), Ka-band (27-40 GHz), and V-band (40-75 GHz)) have become more prevalent. In particular, there is now a high demand for radio frequency (“RF”) transistor amplifiers used to amplify RF signals at frequencies such as 500 MHz and higher (including microwave frequencies). These RF transistor amplifiers may need to exhibit high reliability, good linearity, and the ability to handle high output power levels.

[0005] Most RF transistor amplifiers are implemented using silicon or wide-bandgap semiconductor materials such as silicon carbide (“SiC”) and group III nitride materials. As used herein, the term “group III nitride” refers to those semiconductor compounds formed between nitrogen and a group III element of the periodic table (typically aluminum (Al), gallium (Ga), and / or indium (In)). The term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN. These compounds have empirical formulas in which one mole of nitrogen is combined with a total of one mole of group III element.

[0006] Silicon-based RF transistor amplifiers are typically implemented using laterally diffused metal-oxide-semiconductor (“LDMOS”) transistors. Silicon LDMOS RF transistor amplifiers can exhibit high levels of linearity and can be manufactured relatively inexpensively. Group III nitride-based RF transistor amplifiers are typically implemented as high electron mobility transistors (“HEMT”) and are primarily used in applications requiring high power and / or high frequency operation, where LDMOS RF transistor amplifiers may have inherent performance limitations.

[0007] An RF transistor amplifier may include one or more amplification stages, each typically implemented as a transistor amplifier. To increase output power and current handling capability, RF transistor amplifiers are often implemented in a "unit cell" construction, where a large number of individual "unit cell" transistors are arranged in parallel. An RF transistor amplifier may be implemented as a single integrated circuit chip or "die," or may include multiple dies. When multiple RF transistor amplifier dies are used, they may be connected in series and / or parallel.

[0008] RF transistor amplifiers often include matching circuitry, such as (1) impedance matching circuitry, designed to improve impedance matching between the RF transistor amplifier die and the transmission lines connected thereto (for RF signals at the amplifier's fundamental operating frequency) and (2) harmonic termination circuitry, designed to at least partially terminate harmonics, such as second and third harmonics, that are generated during device operation. One or more RF transistor amplifier dies, along with the impedance matching and harmonic termination circuitry, may be encapsulated in a package. Electrical leads may extend from the package for electrically connecting the RF transistor amplifier to external circuitry elements such as input and output RF transmission lines and bias voltage sources.

[0009] As mentioned above, group III nitride-based RF transistor amplifiers are often used in high-power and / or high-frequency applications. Typically, a significant amount of heat is generated within the die of a group III nitride-based RF transistor amplifier during operation. If the RF transistor amplifier die becomes too hot, its performance (e.g., output power, efficiency, linearity, gain, etc.) will deteriorate and / or the RF transistor amplifier die may be damaged. Therefore, group III nitride-based RF transistor amplifiers are typically housed in packages optimized for heat dissipation.

[0010] Figures 1A to 1D These are schematic illustrations of various views of a conventional group III nitride-based RF transistor amplifier die 10. Specifically, Figure 1A This is a schematic plan view of an RF transistor amplifier die 10 based on group III nitrides, and Figure 1B It is along Figure 1A A side view of the RF transistor amplifier die 10 taken from line 1B-1B. Figure 1C It is along Figure 1B A schematic cross-sectional view taken along line 1C-1C shows the metallization on the top surface of the semiconductor layer structure of the RF transistor amplifier die 10, and Figure 1D It is along Figure 1C A cross-sectional view of the RF transistor amplifier die 10 taken by line 1D-1D. Figure 1E and 1F It is a diagram. Figure 1A-1DThe RF transistor amplifier die 10 can be packaged to provide schematic cross-sectional views of two example configurations of packaged RF transistor amplifiers 1A and 1B, respectively. It will be appreciated that... Figure 1A-1F (And many other figures in this application) are highly simplified figures, and actual RF transistor amplifiers may include more unit cells and various circuit systems and elements not shown in the simplified figures herein.

[0011] like Figure 1A As shown, the RF transistor amplifier die 10 includes a gate terminal 22 and a drain terminal 24 exposed on the top side of the RF transistor amplifier die 10. A first circuit element (not shown) can be connected to the gate terminal 22 via, for example, a bonding wire (not shown), and a second circuit element (not shown) can be connected to the drain terminal 24 via, for example, a bonding wire (not shown). For example, the first circuit element can pass an input RF signal to be amplified to the RF transistor amplifier die 10, while the second circuit element can receive the amplified RF signal output by the RF transistor amplifier die 10. A protective insulating layer or pattern 28 may cover the remainder of the top surface of the RF transistor amplifier die 10.

[0012] like Figure 1B-1D As shown, the RF transistor amplifier die 10 also includes a semiconductor layer structure 30, a top-side metallization structure 20, and a back-side metallization structure die 10 that serves as the source terminal 26 of the RF transistor amplifier die 10.

[0013] The semiconductor layer structure 30 includes multiple semiconductor layers. The RF transistor amplifier die 10 can be a HEMT-based RF transistor amplifier die; therefore, the semiconductor layer structure 30 can include at least a channel layer and a barrier layer. (Reference) Figure 1D In the illustrated example, a total of three layers are shown: a semiconductor channel layer 34 and a semiconductor barrier layer 36, which are sequentially formed on a growth substrate 32, which can be a semiconductor or insulating substrate (such as a SiC or sapphire substrate). Even if formed of a non-semiconductor material, the growth substrate 32 is considered to be part of the semiconductor layer structure 30.

[0014] Refer again Figure 1BThe semiconductor layer structure 30 has a top side 12 and a bottom side 14. A top-side metallization structure 20 is formed on the top side 12 of the semiconductor layer structure 30, and a source terminal 26 is formed on the bottom side 14 of the semiconductor layer structure 30. The top-side metallization structure 20 includes (among other things) a conductive (typically metallic) gate manifold 42 and a conductive (typically metallic) drain manifold 44, conductive gate and drain vias 43 and 45, conductive gate and drain terminals 22 and 24, and gate, drain, and source fingers 52, 54, and 56 (described below). The gate manifold 42 is electrically connected to the gate terminal 22 through the gate via 43, and the drain manifold 44 is electrically connected to the drain terminal 24 through the conductive drain via 45. The gate and drain vias 43 and 45 may include, for example, metal-plated vias or metal pillars formed of a dielectric material such as silicon oxide or silicon nitride.

[0015] like Figure 1C As shown, the RF transistor amplifier die 10 includes a plurality of unit cell transistors 16, one of which is composed of Figure 1C The dashed box indicates this. Each unit cell transistor 16 includes a gate finger 52, a drain finger 54, and a source finger 56. The gate, drain, and source fingers 52, 54, and 56 are formed on the upper surface of the semiconductor layer structure 30 and include a portion of the top-side metallization structure 20. The top-side metallization structure 20 also includes a gate manifold 42 and a drain manifold 44. The gate finger 52 is electrically connected to the gate manifold 42, and the drain finger 54 is electrically connected to the drain manifold 44. The source finger 56 is electrically connected to the source terminal 26 via a plurality of conductive power vias 66 extending through the semiconductor layer structure 30. Figure 1B The conductive electrode via 66 may include a via that extends completely through the plated metal of the semiconductor layer structure 30.

[0016] Figure 1E It includes Figure 1A-1D A schematic side view of a group III nitride-based RF transistor amplifier 1A packaged with an RF transistor amplifier die 10. (See diagram) Figure 1E As shown, the packaged RF transistor amplifier 1A includes an RF transistor amplifier die 10 and an open cavity package 70. The package 70 includes a metal gate lead 72, a metal drain lead 74, a metal base 76, a ceramic sidewall 78, and a ceramic cap 80.

[0017] The RF transistor amplifier die 10 is mounted on the upper surface of the metal base 76 (which may be a metal flange) within a cavity defined by the metal base 76, ceramic sidewalls 78, and ceramic cap 80. The source terminal 26 of the RF transistor amplifier die 10 can directly contact the metal base 76. The metal base 76 provides electrical connection to the source terminal 26 and also serves as a heat dissipation structure for dissipating heat generated within the RF transistor amplifier die 10. Heat is primarily generated in the upper part of the RF amplifier die 10, where a relatively high current density is generated in, for example, the channel region of the unit cell transistor 16. This heat can be transferred to the source terminal 26 via the source via 66 and the semiconductor layer structure 30, and then to the metal base 76.

[0018] Input matching circuit 90 and / or output matching circuit 92 may also be installed within package 70. Matching circuits 90 and 92 may be impedance matching circuits that match the impedance of the fundamental component of the RF signal input to or output from the RF transistor amplifier 1A to the impedance at the input or output terminal of the RF transistor amplifier die 10, respectively, and / or are configured to ground or terminate harmonics of the fundamental RF signal that may exist at the input or output terminal of the RF transistor amplifier die 10. More than one input matching circuit 90 and / or output matching circuit 92 may be provided. Figure 1E As schematically shown, input and output matching circuits 90, 92 can be mounted on a metal base 76. Gate lead 72 can be connected to input matching circuit 90 via one or more first bonding wires 82, and input matching circuit 90 can be connected to the gate terminal 22 of RF transistor amplifier die 10 via one or more second bonding wires 84. Similarly, drain lead 74 can be connected to output matching circuit 92 via one or more fourth bonding wires 88, and output matching circuit 92 can be connected to the drain terminal 24 of RF transistor amplifier die 10 via one or more third bonding wires 86. Bonds 82, 84, 86, and 88 can form part of the input and / or output matching circuitry. Gate lead 72 and drain lead 74 can extend through ceramic sidewall 78. The interior of package 70 may include an inflatable cavity.

[0019] Figure 1FThis is a schematic side view of another conventionally packaged group III nitride-based RF transistor amplifier 1B. The RF transistor amplifier 1B differs from the RF transistor amplifier 1A in that it includes a different package 70'. Package 70' includes a metal base 76 (which acts as a metal heat sink and can be implemented as a metal block), and gate and drain leads 72', 74'. The RF transistor amplifier 1B also includes a plastic overmolded component 78' that at least partially surrounds the RF transistor amplifier die 10, leads 72', 74', and metal base 76. Other components of the RF transistor amplifier 1B may be identical to those of similarly numbered components in the RF transistor amplifier 1A, and therefore further description of them will be omitted. Summary of the Invention

[0020] According to an embodiment of the present invention, an RF transistor amplifier is provided, comprising an RF transistor amplifier die having a semiconductor layer structure, a coupling element on the upper surface of the semiconductor layer structure, and an interconnect structure on the upper surface of the coupling element such that the RF transistor amplifier die and the interconnect structure are arranged in a stacked configuration. The coupling element includes a first shielded transmission line structure.

[0021] In some embodiments, the first shielded transmission line structure may include a first conductive post electrically connected to a first input / output terminal of the RF transistor amplifier die, and first and second conductive ground posts on opposite sides of the first conductive post, the first and second conductive ground posts being electrically connected to the ground terminal of the RF transistor amplifier die. The first shielded transmission line structure may further include third and fourth conductive ground posts on opposite sides of the first conductive post, the third and fourth conductive ground posts being electrically connected to the ground terminal of the RF transistor amplifier. In some embodiments, the first to fourth conductive ground posts may surround the first conductive post.

[0022] In some embodiments, the first conductive post may vertically overlap the active region of the RF transistor amplifier die. In some embodiments, the first conductive ground post may additionally or alternatively vertically overlap a manifold of the RF transistor amplifier die, wherein the manifold is connected to a plurality of conductive fingers extending across the active region of the RF transistor amplifier die. In some embodiments, the second conductive ground post may vertically overlap a portion of the RF transistor amplifier die outside the active region. In some embodiments, both the first conductive post and the first conductive ground post may vertically overlap the first input / output terminal.

[0023] In some embodiments, the first input / output terminal may be a gate terminal and the ground terminal may be a source terminal, and the coupling element may further include a second shielded transmission line structure, the second shielded transmission line structure including a second conductive post electrically connected to the drain terminal of the RF transistor amplifier die and fifth and sixth conductive ground posts located on opposite sides of the second conductive post, the fifth and sixth conductive ground posts being electrically connected to the source terminal.

[0024] In some embodiments, the first input / output terminal may include a gate terminal and the ground terminal may include a source terminal, and the RF transistor amplifier die may also include a drain terminal. In such embodiments, the source terminal may be on the opposite side of the gate terminal and may be on the opposite side of the drain terminal.

[0025] In some embodiments, the first conductive post and the third conductive post may be electrically connected to the gate manifold of the RF transistor amplifier die, and the first conductive ground post may be located between the first and third conductive posts.

[0026] In some embodiments, the second conductive grounding post may include a metal block having a cross-sectional area in a first plane parallel to the main surface of the RF transistor amplifier die that is at least five times the cross-sectional area of ​​the first conductive post in the first plane.

[0027] In some embodiments, the first conductive grounding post may have a first end and a second end, and the second end may not be connected to a conductive element.

[0028] In some embodiments, the coupling element may further include an injectable underfill material surrounding the first conductive post, the first conductive ground post, and the second conductive ground post.

[0029] In some embodiments, the interconnect structure may include a second shielded transmission line structure. The second shielded transmission line structure may include, for example, a stripline transmission line segment, a coplanar waveguide transmission line segment, or a grounded coplanar waveguide transmission line segment.

[0030] In some embodiments, the semiconductor layer structure may be a group III nitride-based semiconductor layer structure. In some embodiments, the interconnect structure may include a redistribution layer laminate or a printed circuit board. In some embodiments, multiple circuit elements (such as, for example, surface mount capacitors or surface mount inductors) may be mounted on the interconnect structure.

[0031] In some embodiments, the side of the RF transistor amplifier die that is not connected to the interconnect structure can be packaged.

[0032] In some embodiments, the RF transistor amplifier die may further include a gate terminal, a drain terminal, and a source terminal on the upper surface of the semiconductor layer structure. In such embodiments, the first shielded transmission line structure may include a gate post electrically connected to the gate terminal and first and second ground posts on opposite sides of the gate post, the first and second ground posts being electrically connected to the source terminal.

[0033] In some embodiments, the first shielded transmission line structure may include a plurality of conductive posts arranged such that a first conductive post is a signal-carrying post, which is surrounded on at least two sides by additional conductive posts coupled to a ground voltage source. In some embodiments, the first conductive post may be surrounded on at least three sides by some of the conductive posts coupled to a ground voltage source.

[0034] In some embodiments, the coupling element may have a fan-in configuration.

[0035] According to a further embodiment of the present invention, an RF transistor amplifier is provided, comprising an RF transistor amplifier die having a group III nitride-based semiconductor layer structure and gate and drain fingers extending on the upper surface of the semiconductor layer structure, and a first shielded transmission line structure extending perpendicular to the upper surface of the semiconductor layer structure.

[0036] In some embodiments, the first shielded transmission line structure may be electrically connected to one of the gate finger and the drain finger.

[0037] In some embodiments, the RF transistor amplifier may further include an interconnect structure, wherein a first shielded transmission line structure electrically connects the RF transistor amplifier die to the interconnect structure.

[0038] In some embodiments, the first shielded transmission line structure may include a first conductive post electrically connected to one of the gate fingers or one of the drain fingers, and first and second conductive ground posts on opposite sides of the first conductive post, the first and second conductive ground posts being electrically connected to the source finger of the RF transistor amplifier die. In such embodiments, the first shielded transmission line structure may further include third and fourth conductive ground posts on opposite sides of the first conductive post, the third and fourth conductive ground posts being electrically connected to the source finger.

[0039] In some embodiments, the first conductive post may vertically overlap the active region of the RF transistor amplifier die. In some embodiments, the first conductive ground post may vertically overlap a manifold of the RF transistor amplifier die electrically connected to the gate finger or drain finger. In some embodiments, the second conductive ground post may vertically overlap a portion of the RF transistor amplifier die outside the active region. In some embodiments, both the first conductive post and the first conductive ground post may vertically overlap the gate terminal of the RF transistor amplifier die.

[0040] In some embodiments, the first conductive post and the third conductive post may be electrically connected to the gate manifold of the RF transistor amplifier die, and the first conductive ground post may be located between the first and third conductive posts.

[0041] In some embodiments, the interconnect structure may include a second shielded transmission line structure.

[0042] In some embodiments, the RF transistor amplifier die may further include a gate terminal electrically connected to the gate finger, a drain terminal electrically connected to the drain finger, and a source finger electrically connected to the source finger, wherein the gate terminal, drain terminal, and source terminal are all located above the gate finger, drain finger, and source finger.

[0043] In some embodiments, the first shielded transmission line structure may include a gate post electrically connected to a gate terminal and first and second ground posts on opposite sides of the gate post, the first and second ground posts being electrically connected to the source terminal.

[0044] According to another embodiment of the present invention, an RF transistor amplifier is provided, comprising an RF transistor amplifier die having a group III nitride-based semiconductor layer structure and gate, drain, and source fingers extending on the upper surface of the semiconductor layer structure, and a plurality of conductive pillars extending perpendicular to the upper surface of the semiconductor layer structure, the conductive pillars including a first conductive pillar electrically connected to the gate or drain finger and first and second conductive ground pillars on opposite sides of the first conductive pillar, the first and second conductive ground pillars being electrically connected to the source finger.

[0045] In some embodiments, the RF transistor amplifier may further include an interconnect structure, and conductive pillars may extend between the interconnect structure and the RF transistor amplifier die and electrically connect the interconnect structure to the RF transistor amplifier die.

[0046] In some embodiments, the first and second conductive grounding posts, as well as at least one additional conductive grounding post, may surround the first conductive post.

[0047] In some embodiments, the first conductive post may vertically overlap the active region of the RF transistor amplifier die, and / or the second conductive ground post may vertically overlap a portion of the RF transistor amplifier die outside the active region. In some embodiments, the first conductive ground post may vertically overlap the manifold of the RF transistor amplifier die.

[0048] In some embodiments, the drain pin may extend from the drain manifold across the active region of the RF transistor amplifier die, and the first and third conductive posts may be electrically connected to the drain manifold, and the first conductive ground post may be located between the first and third conductive posts.

[0049] In some embodiments, the semiconductor layer structure may include a group III nitride-based semiconductor layer structure.

[0050] In some embodiments, the conductive post may have a fan-in configuration.

[0051] According to another additional embodiment of the invention, an RF transistor amplifier is provided, comprising an RF transistor amplifier die having a gate terminal, a drain terminal and a source terminal on a first surface of the RF transistor amplifier die, and an interconnection structure that is stacked with the RF transistor amplifier die and electrically connected thereto by a shielded transmission line structure.

[0052] In some embodiments, the shielded transmission line structure may include a first conductive post electrically connected to the gate terminal and first and second conductive ground posts on opposite sides of the first conductive post, the first and second conductive ground posts being electrically connected to the source terminal.

[0053] In some embodiments, the shielded transmission line structure may include a first conductive post electrically connected to the drain terminal and first and second conductive grounding posts on opposite sides of the first conductive post, the first and second conductive grounding posts being electrically connected to the source terminal.

[0054] In some embodiments, the shielded transmission line structure may further include a third conductive grounding post, which, together with the first and second conductive grounding posts, surrounds the first conductive post on at least three sides.

[0055] In some embodiments, the first conductive post may vertically overlap the active region of the RF transistor amplifier die. In some embodiments, the first conductive ground post may vertically overlap the gate manifold electrically connected to the gate terminal. In some embodiments, both the first conductive post and the first conductive ground post may vertically overlap the gate terminal.

[0056] In some embodiments, the first conductive post and the third conductive post may be electrically connected to the gate manifold of the RF transistor amplifier die, and the first conductive ground post may be located between the first and third conductive posts.

[0057] In some embodiments, the interconnect structure may include a second shielded transmission line structure electrically connected to the shielded transmission line structure.

[0058] According to an embodiment of the present invention, an RF transistor amplifier is provided, comprising an RF transistor amplifier die including a gate terminal, a drain terminal, and a source terminal on a first surface of the RF transistor amplifier die, and an interconnect structure stacked with the RF transistor amplifier die, the interconnect structure including a shielded transmission line structure wherein a ground conductor of the shielded transmission line structure is electrically connected to the source terminal and a signal conductor of the shielded transmission line structure is electrically connected to one of the gate terminal and the drain terminal.

[0059] In some embodiments, the shielded transmission line structure may include a stripline transmission line segment, a coplanar waveguide transmission line segment, or a grounded coplanar waveguide transmission line segment.

[0060] In some embodiments, the interconnect structure may include a redistribution layer laminate or a printed circuit board. In some embodiments, multiple circuit elements may be mounted on the interconnect structure. Attached Figure Description

[0061] Figure 1A This is a schematic plan view of a conventional group III nitride-based RF transistor amplifier die.

[0062] Figure 1B It is along Figure 1A A schematic cross-sectional view taken from line 1B-1B.

[0063] Figure 1C It is along Figure 1B A schematic cross-sectional view taken by line 1C-1C illustrates the metallization layer formed directly on the top surface of the semiconductor layer structure.

[0064] Figure 1D It is along Figure 1C A schematic cross-sectional view taken from the line 1D-1D.

[0065] Figure 1E It is packaged in ceramic packaging. Figure 1A-1D A schematic cross-sectional view of a group III nitride-based RF transistor amplifier die.

[0066] Figure 1F It is packaged in overmolded packaging. Figure 1A-1D A schematic cross-sectional view of a group III nitride-based RF transistor amplifier die.

[0067] Figure 2 This is a schematic cross-sectional view illustrating components of various RF transistor amplifiers according to embodiments of the present invention.

[0068] Figure 3AThis is a schematic plan view of a group III nitride-based RF transistor amplifier die according to certain embodiments of the present invention.

[0069] Figure 3B It is along Figure 3A A schematic cross-sectional view taken from line 3B-3B.

[0070] Figure 3C It is along Figure 3B A schematic plan view taken from line 3C-3C illustrates the top-side metallization of the direct contact semiconductor layer structure.

[0071] Figure 3D It is along Figure 3C A schematic cross-sectional view of the line cut in 3D.

[0072] Figure 3E It is along Figure 3C A schematic cross-sectional view taken from line 3E-3E.

[0073] Figure 3F It is along Figure 3C A schematic cross-sectional view taken from line 3F-3F.

[0074] Figure 3G It is along Figure 3C A schematic cross-sectional view taken from line 3G-3G.

[0075] Figure 3H It is along Figure 3B A schematic cross-sectional view taken from line 3H-3H.

[0076] Figure 3I It is installed on the interconnect structure Figures 3A-3H A schematic cross-sectional view of a group III nitride-based RF transistor amplifier.

[0077] Figure 3J It is installed on the alternative interconnect structure Figures 3A-3H A schematic cross-sectional view of a group III nitride-based RF transistor amplifier.

[0078] Figure 3K This is a schematic cross-sectional view of an RF transistor amplifier, which is Figure 3A-3G A modified version of the RF transistor amplifier.

[0079] Figure 3L yes Figures 3A-3H A schematic cross-sectional view of another modified version of a group III nitride-based RF transistor amplifier with a fan-out structure.

[0080] Figure 3M yes Figures 3A-3HA schematic cross-sectional view of yet another modified version of a group III nitride-based RF transistor amplifier.

[0081] Figure 4A and 4B This is a schematic cross-sectional view of an RF transistor amplifier based on group III nitrides. Figure 3A-3I A modified version of a group III nitride-based RF transistor amplifier.

[0082] Figures 5A-5F These are various views of a group III nitride-based RF transistor amplifier die according to another embodiment of the present invention.

[0083] Figure 5G yes Figure 5F A schematic cross-sectional view of a modified version of the RF transistor amplifier.

[0084] Figure 5H and 5I These are schematic cross-sectional views and schematic plan views of an RF transistor amplifier according to another embodiment of the present invention.

[0085] Figure 6A and 6B This is a schematic plan view illustrating an alternative embodiment of the coupling element according to an embodiment of the present invention.

[0086] Figure 7A This is a circuit diagram of an RF transistor amplifier including both impedance matching and harmonic termination circuits according to an embodiment of the present invention.

[0087] Figure 7B Is as Figure 7A A schematic plan view of the interconnect structure of a portion of an RF transistor amplifier according to an embodiment of the present invention.

[0088] Figure 7C It is along Figure 7B A schematic cross-sectional view taken from line 7C-7C.

[0089] Figures 8A-8C This is a schematic diagram illustrating an example coplanar waveguide transmission line segment that can be used to form some of the transmission line segments in an interconnect structure according to an embodiment of the present invention.

[0090] Figure 8D This is an end view of another coplanar waveguide transmission line segment that can be used to form some of the transmission line segments in an interconnect structure, according to an embodiment of the present invention.

[0091] Figures 9A-9CThis is a schematic diagram illustrating an example of a grounded coplanar waveguide transmission line segment that can be used to form some of the transmission line structures in an interconnect structure according to an embodiment of the present invention.

[0092] Figure 10A-10G This is a schematic diagram illustrating a method for forming a packaged RF amplifier according to certain embodiments of the present invention.

[0093] Figure 11A It is included in the ceramic packaging. Figure 3I A schematic cross-sectional view of the packaged RF transistor amplifier.

[0094] Figure 11B It is included in overmolded plastic packaging. Figure 3I A schematic cross-sectional view of the packaged RF transistor amplifier.

[0095] Figure 12 This is a schematic side view of an RF transistor amplifier according to an embodiment of the present invention, which includes two RF transistor amplifier dies coupled to an interconnect structure. Detailed Implementation

[0096] As mentioned above, conventional group III nitride-based packaged RF transistor amplifiers (such as...) Figure 1E and 1FRF transistor amplifiers (1A and 1B) typically implement the gate and drain terminals on the upper side of the semiconductor layer structure and the source terminals on the lower side. Power vias extend through the semiconductor layer structure to electrically connect the source fingers in the upper part of the semiconductor layer structure to the source terminals. These conventional RF transistor amplifiers also typically use bonding wires to connect the RF transistor amplifier die to other components of the device (such as matching circuitry and / or input / output leads). These bonding wires have inherent inductance, which can supply some of the inductance for impedance matching and / or harmonic termination circuitry. The amount of inductance provided by the bonding wire can be varied by changing the length and / or cross-sectional area (e.g., diameter) of the bonding wire, allowing the bonding wire to provide the desired amount of inductance. Unfortunately, as applications move to higher frequencies, the inductance of the bonding wire can exceed the desired inductance for impedance matching and / or harmonic termination circuitry. When this occurs, very short and / or bonding wires with large cross-sectional areas can be used to reduce their inductance. However, very short bonding wires can be difficult to solder in place, which increases manufacturing costs and / or leads to a higher device failure rate. Large junction lines with large cross-sectional areas may require larger gate and drain terminals on the RF transistor amplifier die, leading to an undesirable increase in the overall size of the RF transistor amplifier die. Furthermore, in some higher-frequency applications, even very short junction lines with large cross-sectional areas can have excessive inductance, causing the matching network to fail to properly terminate second or third harmonics, for example. While RF transistor amplifiers can be implemented as monolithic microwave integrated circuit (“MMIC”) devices to avoid the problem of excessive inductance in junction lines, MMIC RF amplifiers are more expensive to manufacture and can only be used within the frequency range of the matching circuit, thus reducing flexibility.

[0097] Furthermore, wire bonding equipment typically used in mass production can have a tolerance of + / - 1 mil, meaning that the length of any given bonding wire can vary by up to 4 mils (i.e., + / - 1 mil at each end of the bonding wire). For high-frequency applications, the variation in inductance associated with a 4-mil bonding wire can be significant, so if the bonding wire is too short or too long by 1-2 mils from the desired nominal length, the performance of the matching circuit will degrade.

[0098] According to embodiments of the present invention, a group III nitride-based RF transistor amplifier is provided, comprising an RF transistor amplifier die having a gate terminal, a drain terminal, and a source terminal all located on the upper side of the RF transistor amplifier die. The RF transistor amplifier may exclude junction wires for gate and / or drain connections, which can reduce the amount of inductance present in the circuit. Since all three gate, drain, and source terminals are on the upper side of the RF transistor amplifier die, the RF transistor amplifier according to embodiments of the present invention can be mounted in a flip-chip arrangement, wherein the RF transistor amplifier die can be mounted on another substrate (such as an interconnect structure) in a stacked arrangement. The interconnect structure may include other circuit elements, such as impedance matching and / or harmonic termination circuitry systems, for example, those of the RF transistor amplifier.

[0099] In some embodiments, the coupling element may be directly connected to the gate, drain, and / or source terminals of the RF transistor amplifier die. In some embodiments, the coupling element may physically and electrically connect the gate, drain, and / or source terminals of the RF transistor amplifier die to an interconnect structure. In other embodiments, the interconnect structure may be omitted, and the coupling element may physically and electrically connect the gate, drain, and / or source terminals of the RF transistor amplifier die to components and / or leads of separately mounted RF transistor amplifiers.

[0100] Furthermore, since source terminals can be provided on the upper side of the RF transistor amplifier die, according to embodiments of the invention, one or more ground connections can exist on the upper side of the RF transistor amplifier. These ground connections can be used to implement RF transmission line connections to the gate and / or drain terminals using a shielded (i.e., ground-signal-ground) transmission line structure. Hereinafter, "transmission line structure" refers to any physical structure comprising at least two conductive elements configured as transmission paths for RF signals. Examples of transmission line structures include microstrip transmission lines, stripline transmission lines, conductive pillars, vias, bumps, pads, sheets, etc. (e.g., a pair of conductive pillars can form a transmission line structure). Hereinafter, "shielded transmission line structure" refers to an RF transmission line structure comprising a signal-carrying conductor and one or more ground conductors adjacent to at least two opposite sides thereof, and a transmission line structure in which three or more ground conductors generally surround the signal-carrying conductor. For example, a shielded transmission line structure can be formed by positioning first and second ground conductors on first and second opposite sides of the signal-carrying conductor or by forming a single conductor wound around the signal-carrying conductor such that it is on the opposite side of the signal-carrying conductor. As another example, a shielded transmission line structure can be formed by positioning first to third ground conductors within a triangle surrounding a signal-carrying conductor. According to embodiments of the invention, the shielded transmission line structure may include any number of separate ground conductors, including one, two, three, four, five, six, or even more. As yet another example, a ring-shaped ground conductor may be formed in a dielectric layer that surrounds (or partially surrounds) a signal-carrying conductor formed in the dielectric layer. Note that, herein, if there exists an axis extending through two different portions of the signal-carrying conductor and the ground conductor, then the ground conductors are considered to be on opposite sides of the signal-carrying conductor. Similarly, if there exists an axis extending through a pair of ground conductors and the signal-carrying conductor, then the pair of ground conductors are located on opposite sides of the signal-carrying conductor. In some embodiments, additional shielded transmission line structures, such as, for example, striplines or coplanar waveguide structures, may be provided in the interconnect structure. Using shielded transmission line structures for connections between and / or within RF transistor amplifier dies and interconnect structures can provide increased signal isolation, reduced insertion loss, and / or improved impedance matching. This can significantly improve the overall performance of the RF transistor amplifier.

[0101] According to some embodiments of the present invention, an RF transistor amplifier is provided, comprising an RF transistor amplifier die having a semiconductor layer structure, a coupling element on the upper surface of the semiconductor layer structure, and an interconnect structure on the upper surface of the coupling element, such that the RF transistor amplifier die and the interconnect structure are arranged in a stacked configuration. The coupling element on these RF transistor amplifiers includes a first shielded transmission line structure. The RF transistor amplifier die may include a gate terminal, a drain terminal, and a source terminal on the upper surface of the semiconductor layer structure. The semiconductor layer structure may be a group III nitride-based semiconductor layer structure.

[0102] In some embodiments, the first shielded transmission line structure may include a first conductive post electrically connected to a first input / output terminal of the RF transistor amplifier die, and first and second conductive ground posts on opposite sides of the first conductive post, the first and second conductive ground posts being electrically connected to a ground terminal of the RF transistor amplifier die. The first shielded transmission line structure may optionally include third and fourth conductive ground posts on opposite sides of the first conductive post, the third and fourth conductive ground posts being electrically connected to the ground terminal of the RF transistor amplifier. The first to fourth conductive ground posts may surround the first conductive post. Furthermore, in some embodiments, the first conductive post may vertically overlap the active region of the RF transistor amplifier die, and the first conductive ground post may vertically overlap a manifold of the RF transistor amplifier die or some other portion of the RF transistor amplifier die outside the active region of the RF transistor amplifier die.

[0103] In some embodiments, the RF transistor amplifier may further include an interconnect structure that can be connected to the RF transistor amplifier die via a coupling element. The interconnect structure may include a second shielded transmission line structure, such as a stripline transmission line segment, a coplanar waveguide transmission line segment, or a grounded coplanar waveguide transmission line segment. The interconnect structure may include, for example, a redistribution layer laminate or a printed circuit board. One or more circuit elements, such as surface-mount capacitors or inductors, may be mounted on the interconnect structure.

[0104] According to another embodiment of the present invention, an RF transistor amplifier is provided, comprising an RF transistor amplifier die having a group III nitride-based semiconductor layer structure, gate and drain fingers extending on the upper surface of the semiconductor layer structure, and a first shielded transmission line structure extending perpendicular to the upper surface of the semiconductor layer structure.

[0105] According to another embodiment of the present invention, an RF transistor amplifier is provided, comprising an RF transistor amplifier die having a group III nitride-based semiconductor layer structure and gate, drain, and source fingers extending on the upper surface of the semiconductor layer structure, and a plurality of conductive pillars extending perpendicular to the upper surface of the semiconductor layer structure. Each conductive pillar includes a first conductive pillar electrically connected to a gate or drain finger, and first and second conductive ground pillars on opposite sides of the first conductive pillar, the first and second conductive ground pillars being electrically connected to the source finger. These RF transistor amplifiers may further include an interconnect structure, wherein the conductive pillars extend between the interconnect structure and the RF transistor amplifier die and electrically connect the interconnect structure to the RF transistor amplifier die. The first and second conductive ground pillars and at least one additional conductive ground pillar surround the first conductive pillar.

[0106] According to another embodiment of the present invention, an RF transistor amplifier is provided, comprising an RF transistor amplifier die and an interconnection structure electrically connected to the RF transistor amplifier die in a stacked arrangement and electrically connected thereto by a shielded transmission line structure, the RF transistor amplifier die including a gate terminal, a drain terminal and a source terminal on a first surface of the RF transistor amplifier die.

[0107] According to another embodiment of the present invention, an RF transistor amplifier is provided, comprising an RF transistor amplifier die and an interconnect structure arranged in a stacked configuration with the RF transistor amplifier die. The RF transistor amplifier die includes a gate terminal, a drain terminal, and a source terminal on a first surface of the RF transistor amplifier die. The interconnect structure includes a shielded transmission line structure, wherein a ground conductor of the shielded transmission line structure is electrically connected to the source terminal and a signal conductor of the shielded transmission line structure is electrically connected to one of the gate terminal and the drain terminal.

[0108] Now refer to Figure 2-12 Embodiments of the invention will be discussed in more detail below.

[0109] Figure 2 This is a schematic cross-sectional view of an RF transistor amplifier 100 according to an embodiment of the present invention. Figure 2As shown, the RF transistor amplifier 100 includes an RF transistor amplifier die 110, a coupling element 120, and an interconnect structure 130. The RF transistor amplifier die 110 may include a group III nitride-based RF transistor amplifier die comprising a plurality of unit cell transistors (not shown). Each unit cell transistor may include a field-effect transistor having a gate, a drain, and a source. The unit cell transistors may be electrically connected in parallel. The RF transistor amplifier die 110 may include a gate terminal 122, a drain terminal 124, and a source terminal 126, which are connected to the gate finger, drain finger, and source finger of the unit cell transistor. The gate terminal 122, drain terminal 124, and source terminal 126 may all be located on the top side of the RF transistor amplifier die 110.

[0110] like Figure 2 As further shown, coupling element 120 is provided on the upper surface of RF transistor amplifier die 110, and interconnect structure 130 is provided on the upper surface of coupling element 120. Therefore, coupling element 120 can be inserted between RF transistor amplifier die 110 and interconnect structure 130. In some embodiments, coupling element may include conductive structures (e.g., metal pillars and pads) formed during wafer-level processing using conventional semiconductor processing techniques and / or other methods (i.e., before a semiconductor wafer comprising multiple RF transistor amplifier dies 110 is diced into individual RF transistor amplifier dies 110). In such embodiments, an underfill material, such as capillary underfill material, may be injected to fill the spaces between the conductive structures of coupling element 120. It should be noted that even though coupling element is formed as part of wafer-level processing, for ease of description, it is described herein as a separate element from RF transistor amplifier die 110. In other embodiments, coupling element 120 may be a discrete structure, such as, for example, a redistribution layer (“RDL”) laminate and / or an interposer, which may be formed separately from the RF transistor amplifier die and may be attached to the RF transistor amplifier die 110 during wafer-level processing steps (i.e., before the wafer is diced into individual RF transistor amplifier dies 110), or may be applied to individual RF transistor amplifier dies 110. It should also be noted that interconnect structure 130 may be omitted in some embodiments of the invention, which will be described in more detail below.

[0111] Figure 3A-3I An RF transistor amplifier 200 based on group III nitrides according to certain embodiments of the present invention is depicted. In particular, Figure 3A This is a schematic plan view of an RF transistor amplifier 200 based on group III nitrides. Figure 3B yes Figure 3A RF transistor amplifier 200 along Figure 3A A schematic cross-sectional view taken from line 3B-3B. Figure 3C It is along Figure 3B A schematic plan view taken by line 3C-3C illustrates the top-side metallized portion of the semiconductor layer structure that directly contacts the RF transistor amplifier die 210 included in the RF transistor amplifier 200. Figure 3D to 3G They are along Figure 3C A schematic cross-sectional view of the RF transistor amplifier 200 taken from the 3D-3D to 3G-3G line. Figure 3H It is along Figure 3B A schematic cross-sectional view taken from line 3H-3H. Figure 3I It is mounted on an interconnect structure 300 such as a printed circuit board. Figures 3A-3H A cross-sectional view of the RF transistor amplifier 200. Depending on the specific application, the RF transistor amplifier 200 may or may not include the interconnect structure 300.

[0112] refer to Figure 3A and 3B The group III nitride-based RF transistor amplifier 200 may include an RF transistor amplifier die 210 and a coupling element 270 mounted on the upper surface of the RF transistor amplifier die 210. (See reference...) Figure 3I Further discussion suggests that the RF transistor amplifier 200 may also include an interconnect structure 300. A coupling element 270 may be located between the RF transistor amplifier die 210 and the interconnect structure 300 and may electrically connect the RF transistor amplifier die 210 to the interconnect structure 300. The RF transistor amplifier die 210, the coupling element 270, and the interconnect structure 300 may be in a stacked relationship or arrangement.

[0113] The RF transistor amplifier die 210 includes a semiconductor layer structure 230 having a top side 212 and a back side 214. A top-side metallization structure 220 is formed on the top side 212 of the semiconductor layer structure 230, and a bottom-side thermal layer 240 is formed on the bottom side 214 of the semiconductor layer structure 230. The top-side metallization structure 220 includes a gate terminal 222, a drain terminal 224, and a source terminal 226, as well as other metallizations that will be discussed in further detail below. It should be noted that although the gate, drain, and source terminals 222, 224, 226 are described herein as each being a single terminal, any of these terminals may alternatively include a plurality of separate terminals electrically connected to each other. The RF transistor amplifier die 210 may be a HEMT-based RF transistor amplifier die, in which case the semiconductor layer structure 230 may include at least a channel layer and a barrier layer, as will be discussed in more detail below.

[0114] Gate terminal 222 can receive the RF signal input to the RF transistor amplifier die 210 from the first external circuit, and drain terminal 224 can output the RF signal amplified by the RF transistor amplifier die 210 to the second external circuit. Gate and drain terminals 222 and 224 can be collectively referred to as input / output terminals herein.

[0115] Coupling element 270 is formed on top of the top-side metallization structure 220 of the RF transistor amplifier die 210. Coupling element 270 can be used to connect the RF transistor amplifier die 210 to another structure (such as an interconnect structure) (see...). Figure 3I As described above, in some embodiments, the coupling element 270 may be formed during wafer-level processing using semiconductor and / or non-semiconductor processing technologies. In other embodiments, the coupling element 270 may include discrete structures, such as, for example, RDL laminates or interposers. An RDL laminate refers to a substrate having a conductive layer pattern and / or conductive vias. As will be discussed in detail below, according to embodiments of the invention, the coupling element 270 may include a shielded ground-signal-ground transmission line structure, which may exhibit increased signal isolation, reduced insertion loss, and / or improved impedance matching.

[0116] The coupling element 270 can be used to connect the RF transistor amplifier die 210 to another structure (such as an interconnect structure). Figure 3I The illustration shows how coupling element 270 can be used to connect RF transistor amplifier die 210 to interconnect structure 300 in the form of a printed circuit board.

[0117] like Figures 3A-3B As shown, coupling element 270 includes a gate connection pad 272, a drain connection pad 274, and a source connection pad 276. Each of these connection pads 272, 274, and 276 may include, for example, an exposed copper pad, but the invention is not limited thereto. The gate connection pad 272 can be electrically coupled to the gate terminal 222 via one or more conductive gate posts 273. Similarly, the drain connection pad 274 can be electrically coupled to the drain terminal 224 via one or more conductive drain posts 275, and the source connection pad 276 can be electrically coupled to one or more source terminals 226 via one or more conductive power posts 277. Additional conductive power posts 279 may also be provided, which will be discussed in further detail below.

[0118] In some embodiments, the combination of the RF transistor amplifier die 210 and the coupling element 270 may have a fan-in configuration. A fan-in configuration may be used to position the gate connection pad 272 inward relative to the gate terminal 222 (i.e., closer to the center of the coupling element when viewed in a plan view) and / or to position the drain connection pad 274 inward relative to the drain terminal 224. However, the invention is not limited to devices having such a fan-in configuration. For example, reference will be made below. Figures 5A-5F In other embodiments discussed, the connection may be neither fan-in nor fan-out, and it will be appreciated that fan-out connections are also possible.

[0119] In some embodiments, the coupling element 270 may be formed as part of a wafer-level processing operation. For example, the coupling element 270 may be formed by forming a conductive gate pillar 273 on the gate terminal 222, a conductive drain pillar 275 on the drain terminal 224, and a conductive power pillar 277 on the source terminal 226. In some embodiments, the conductive pillars 273, 275, and 277 may comprise copper pillars. For example, the conductive pillars may be formed by electroplating a copper seed layer on the gate, drain, and source terminals 222, 224, and 226 and forming the conductive pillars 273, 275, and 277 thereon using one or more masks. Gate connection pad 272, drain connection pad 274, and source connection pad 276 may then be formed on the corresponding gate, drain, and source pillars 273, 275, and 277. Conductive posts 273, 275, 277 and connection pads 272, 274, 276 may be at least partially deployed within a package structure 278, which may include a dielectric material. A variety of dielectric materials may be used, including, for example, silicon oxide, silicon nitride, polymers, molding compounds, and / or combinations thereof. The dielectric material may be processed (e.g., planarized) to expose the gate connection pad 272, drain connection pad 274, and / or source connection pad 276. When the coupling element 270 is formed using a wafer-level process, multiple coupling elements 270 may be formed (one on top of each RF transistor amplifier die 210 included in the wafer), and the RF transistor amplifier die 210 may then be monolithized with the individual coupling elements 270 formed thereon.

[0120] In some embodiments, the coupling element 270 can be formed in a chip-first or chip-last process. In a chip-first process, the coupling element 270 can be formed directly on the RF transistor amplifier die 210 (or on a wafer including the RF transistor amplifier die 210). For example, a seed layer can be deposited (e.g., on one or more of the gate terminal 222, drain terminal 224, and source terminal(s) 226). The seed can then be patterned and electroplated to form a conductive material layer. This process can be repeated multiple times to form conductive pillars 273, 275, 277 and connection pads 272, 274, 276. The conductive pillars 273, 275, 277 and connection pads 272, 274, 276 can then be encapsulated in a package structure 278 to form the coupling element 270.

[0121] In the post-chip process, coupling element 270 can be formed on a temporary carrier layer (not shown). Conductive pillars 273, 275, 277 and connection pads 272, 274, 276 can be formed on the temporary carrier layer in a manner similar to the pre-chip process. When complete, coupling element 270 can be decoupled from the temporary carrier layer and then coupled to the RF transistor amplifier die 210 (either as a wafer-level process or as a chip-level process). For example, coupling element 270 can be coupled (e.g., via solder) to one or more of the gate terminal 222, drain terminal 224, and source terminal 226.

[0122] Other coupling elements 270 may be used alternatively, such as printed circuit boards (e.g., multilayer printed circuit boards), RDL laminates, ceramic substrates including conductive vias and / or pads, or any coupling that can be appropriately electrically connected to the RF transistor amplifier die 210. In some configurations, as will be discussed further herein, coupling element 270 may be omitted.

[0123] Figures 3A-3B The arrangement of conductive posts 273, 275, 277 and connecting pads 272, 274, 276 shown is merely an example, and other arrangements are possible without departing from the invention.

[0124] In embodiments where the semiconductor layer structure 230 of the RF transistor amplifier die 210 has high thermal conductivity, the back side of the RF transistor amplifier die 210 may be mounted on a thermally conductive carrier substrate or base (such as a slug, lead frame, or flange) to provide improved heat dissipation from the amplifier package and the heat generated by the RF transistor amplifier chip. A thermal layer 240 may be formed on the back side 214 of the semiconductor layer structure 230. The thermal layer 240 may be configured to facilitate heat transfer between the RF transistor amplifier die 210 and the carrier substrate or base. In some embodiments, the thermal layer 240 may be omitted. In some embodiments, the thermal layer 240 may be a die attachment layer, such as a eutectic layer. The thermal layer 240 may be a metal layer to form a eutectic or other metal bond. In some embodiments, the thermal layer 240 may be a thermally conductive adhesive.

[0125] Figure 3C It is along Figure 3B A schematic plan view of the RF transistor amplifier die 210, taken along line 3C-3C, shows a portion of the top-side metallization structure 220 of the contact semiconductor layer structure 230. The RF transistor amplifier die 210 may include a group III nitride-based HEMT RF transistor amplifier comprising a plurality of unit cell transistors 216 electrically connected in parallel with each other.

[0126] like Figure 3C As shown, the RF transistor amplifier die 210 includes a gate manifold 242 and a drain manifold 244, a plurality of gate fingers 252, a plurality of drain fingers 254, and a plurality of source fingers 246, all of which can be formed on the upper surface of the semiconductor layer structure 230. The gate manifold 242 and the gate fingers 252 are part of the gate electrode of the RF transistor amplifier die 210. The gate manifold 242 and the gate fingers 252 can be implemented as a first monolithic metal pattern, but the invention is not limited thereto. The drain manifold 244 and the drain fingers 254 are part of the drain electrode of the RF transistor amplifier die 210 and can be implemented as a second monolithic metal pattern, but the invention is not limited thereto. The region between the gate manifold 242 and the drain manifold 242, which includes the unit cell transistor 216, is referred to as the active region 218 of the RF transistor amplifier die 210.

[0127] Gate finger 252 may be formed of a material capable of forming a Schottky contact with a group III nitride-based semiconductor material, such as Ni, Pt, Cu, Pd, Cr, W, and / or WSiN. Drain finger 254 and source finger 246 may comprise a metal capable of forming an ohmic contact with a group III nitride-based material, such as TiAlN. A dielectric layer (or series of dielectric layers) that helps isolate the gate manifolds / fingers 242, 252, drain manifolds / fingers 244, 254, and source finger 246 from each other is not present. Figure 3CThe components of the RF transistor amplifier die 210 are shown in the figure for better illustration.

[0128] One of the unit cell transistors 216 in Figure 3C As shown in the diagram, the unit cell transistor 216 includes gate fingers 252, drain fingers 254, and source fingers 246, as well as a lower portion of the semiconductor layer structure 230. Since all gate fingers 252 are electrically connected to a common gate manifold 242, all drain fingers 254 are electrically connected to a common drain manifold 244, and all source fingers 246 are electrically connected together via source terminals 226 (discussed below), it can be seen that all unit cell transistors 216 are electrically connected together in parallel.

[0129] The unit transistor 216 can be a HEMT device. Suitable structures of group III nitride-based HEMT devices according to embodiments of the present invention can be found in, for example, commonly assigned U.S. Patent Publication No. 2002 / 0066908A1, published June 6, 2002, entitled "Aluminum Gallium Nitride / Gallium Nitride High Electron Mobility Transistors Having A Gate Contact On A Gallium Nitride Based Cap Segment And Methods Of Fabricating Same"; U.S. Patent Publication No. 2002 / 0167023A1, published November 14, 2002, entitled "Group-III Nitride Based High Electron Mobility Transistor (HEMT) With Barrier / Spacer Layer"; and U.S. Patent Publication No. 2002 / 0167023A1, published April 1, 2004, entitled "Nitride-Based Transistors And Methods Of Fabrication Thereof Using Non-Etched The disclosures of these U.S. patents are described in U.S. Patent Publication No. 2004 / 0061129 entitled “ContactRecesses”, U.S. Patent No. 7,906,799 entitled “Nitride-Based Transistors With A Protective Layer And A Low-Damage Recess” published on March 15, 2011, and U.S. Patent No. 6,316,793 entitled “Nitride Based Transistors On Semi-Insulating Silicon Carbide Substrates” published on November 13, 2001. The entire contents of these U.S. patents are incorporated herein by reference.

[0130] refer to Figure 3D-3GThe semiconductor layer structure 230 includes a growth substrate 232 and a plurality of semiconductor layers formed thereon. In the depicted embodiment, a total of two semiconductor layers are shown on the growth substrate 232: a channel layer 234 and a barrier layer 236 on the top side of the channel layer 234. The semiconductor layer structure 230 may include additional semiconductor and / or non-semiconductor layers, such as optional buffer layers, nucleation layers, and / or transition layers (not shown), which may be provided on the growth substrate 232 below the channel layer 234. For example, an AlN buffer layer may be included to provide a suitable crystal structure transition between the SiC growth substrate 232 and the remainder of the semiconductor layer structure 230. In addition, one or more strain-balanced transition layers may be provided, for example, as described in commonly assigned U.S. Patent Publication 2003 / 0102482A1, published June 5, 2003, entitled “Strain Balanced Nitride Heterojunction Transistors and Methods Of Fabricating Strain Balanced Nitride Heterojunction Transistors,” the disclosure of which is incorporated herein by reference as if fully set forth herein. The growth substrate 232 may include, for example, a 4H-SiC or 6H-SiC substrate. In other embodiments, the growth substrate may be or include various semiconductor materials (e.g., group III nitride-based materials, Si, GaAs, ZnO, InP) or non-semiconductor materials (e.g., sapphire).

[0131] Compared to sapphire (Al₂O₃) or silicon, SiC has a closer lattice match to group III nitrides, which are very common substrate materials for group III nitride devices. This closer lattice match in SiC can result in higher quality group III nitride films than are typically achievable on sapphire or silicon. SiC also has very high thermal conductivity, so the total output power of group III nitride devices on silicon carbide is generally not as limited by substrate heat dissipation as the same devices formed on sapphire. Furthermore, the availability of semi-insulating SiC substrates can provide device isolation and reduced parasitic capacitance.

[0132] In some embodiments, the channel layer 234 is a group III nitride material, such as Al. x Ga 1-xN, where 0≤x<1, with the condition that the energy at the conduction band edge of the channel layer 234 is less than the energy at the conduction band edge of the barrier layer 236 at the interface between the channel and barrier layers 234, 236. In certain embodiments of the present invention, x=0, indicating that the channel layer 234 is gallium nitride ("GaN"). The channel layer 234 may also be other Group III nitrides, such as InGaN, AlInGaN, etc. The channel layer 234 may be undoped or unintentionally doped, and may be grown to a thickness of, for example, greater than about 2 nm. The channel layer 234 may also be a multilayer structure, such as a superlattice or a combination of GaN, AlGaN, etc.

[0133] The channel layer 234 may have a bandgap that is smaller than the bandgap of at least a portion of the barrier layer 236, and the channel layer 234 may also have a greater electron affinity than the barrier layer 236. In certain embodiments, the barrier layer 236 is AlN, AlInN, AlGaN or AlInGaN or a combination of layers thereof, with a thickness ranging between about 0.1 nm and about 30 nm or more. In a particular embodiment, the barrier layer 236 is sufficiently thick and has a sufficiently high Al composition and doping to induce a significant carrier concentration at the interface between the channel layer 234 and the barrier layer 236.

[0134] The barrier layer 236 may be a Group III nitride and may have a larger bandgap and a smaller electron affinity than the channel layer 234. In certain embodiments, the barrier layer 236 is undoped or doped with an n-type dopant to less than about 10 19 cm -3 concentration. In some embodiments of the present invention, the barrier layer 236 is Al x Ga 1-x N, where 0<x<1. In a particular embodiment, the aluminum concentration is approximately 25%. However, in other embodiments of the present invention, the barrier layer 236 comprises AlGaN with an aluminum concentration ranging between about 5% and about 100%. In specific embodiments of the present invention, the aluminum concentration is greater than about 10%. In some embodiments, the barrier layer 236 may be implemented as a graded layer and / or multiple layers.

[0135] Due to the bandgap difference between the barrier layer 236 and the channel layer 234 and the piezoelectric effect at the interface between the barrier layer 236 and the channel layer 234, a two-dimensional electron gas (2DEG) is induced in the channel layer 234 at the junction between the channel layer 234 and the barrier layer 236. The 2DEG acts as a highly conductive layer that allows conduction between the source region and its associated drain region of each unit cell transistor 216, where the source region is the portion of the semiconductor layer structure 230 directly under the source finger 246 and the drain region is the portion of the semiconductor layer structure 230 directly under the corresponding drain finger 254.

[0136] An interlayer insulating layer (not shown) may be formed over the gate finger 252, drain finger 254, and source finger 246. The interlayer insulating layer 238 may include a dielectric material such as SiN or SiO2.

[0137] For example in Figure 3D As shown, gate terminal 222 is physically and electrically connected to gate manifold 242 via conductive via 243, drain terminal 224 is physically and electrically connected to drain manifold 244 via conductive via 245, and source terminal 226 is physically and electrically connected to source finger 246 via conductive via 247. While the respective terminals 222, 224, 226 are shown as being directly connected to gate / drain manifolds 242, 244 and / or source finger 246, it will be understood that intermediate elements may be present in some embodiments. For example, in some embodiments, capacitors, inductors, resistors, etc., may be coupled between the terminals and the corresponding manifolds and / or fingers. As an example, a capacitor may be formed on the surface of RF transistor amplifier die 210, coupled to drain manifold 244, and drain terminal 224 may be coupled to the capacitor.

[0138] Since all terminals 222, 224, and 226 are located on the top side of the RF transistor amplifier die 210, there is no requirement for conductive vias extending through the semiconductor layer structure 230 to the back side of the RF transistor amplifier die 210. The absence of vias on the back side of the RF transistor amplifier die 210 to connect the source to a grounded conductive base makes it possible to completely omit the base or use a non-conductive base. Furthermore, the back side of the RF transistor amplifier die 210 can be coupled to a thermally conductive base or layer 240 (such as a heat sink) to provide improved heat dissipation. In some embodiments, the thermal layer 240 can facilitate this thermal coupling. When SiC is used as the substrate material (for substrate 232), the thermal properties of the package can be further improved due to the improved thermal conductivity of SiC.

[0139] Furthermore, placing all terminals 222, 224, and 226 on the top side of the RF transistor amplifier die 210 allows the use of coupling element 270, which brings all transistor connections to their respective connection pads. This allows the RF transistor amplifier die 210 to be further coupled to other components of the circuit (e.g., other routing elements, grounding elements, harmonic and / or input / output impedance matching elements) using connection methods that avoid bonding wires (such as solder). As will be discussed in detail below, positioning all terminals on the top side of the RF transistor amplifier die 210 also allows the use of shielded transmission line structures within the coupling element 270, which can provide various advantages, including increased signal isolation, reduced insertion loss, and / or improved impedance matching.

[0140] Figure 3EThis is a cross-section taken through the gate post 273. As shown in the figure, each gate post 273 extends between the gate terminal 222 and the gate connection pad 272. Figure 3E Multiple source posts 281 are also shown. Each source post 281 extends upward from the source terminal 226. However, the source post 281 is shorter than the aforementioned source post 277, allowing the gate connection pad 272 to extend over and be electrically isolated from the source post 281. In the depicted embodiment, the gate post 273 is located above the gate and drain fingers 252, 254, but embodiments of the invention are not limited thereto. Figure 3C The diagram also shows cross-sectional lines 3E'-3E'. Except that gate terminal 222 will be drain terminal 224, gate post 273 will be drain post 275, and gate connection pad 272 will be drain connection pad 274, the cross-section taken along this line looks similar to... Figure 3E Exactly the same.

[0141] Figure 3F An example of metallization formed above gate manifold 242 is illustrated. As shown, a separate gate terminal 222 is provided above gate manifold 242 and electrically connected to it via gate via 243. Although multiple separate gate terminals 222 are shown, it will be appreciated that a single, larger gate terminal 222 can be used alternatively. Figure 3B and 3H As shown, gate terminal 222 extends in the x-direction, allowing gate post 273 to be laterally offset (in the x-direction) from gate via 243. This allows source post 279 to be formed above gate manifold 242 (and gate terminal 222). The length of source post 279 formed above gate terminal 222 can be shorter than the length of source post 277 formed above source terminal 226, providing a gap 283 between each source post 279 and the corresponding gate terminal 222 to prevent electrical short circuits therebetween. Figure 3F As shown, the source terminal 279 is connected to the source connection pad 276.

[0142] Figure 3G An example of metallization formed above drain manifold 244 is illustrated. As shown, a separate drain terminal 224 is provided above drain manifold 244 and electrically connected to it via drain via 245. Although multiple separate drain terminals 224 are shown, it will be appreciated that a single, larger drain terminal 224 can be used alternatively. Figure 3B and 3HAs shown, the drain terminal 224 extends in the x-direction, allowing the drain post 275 to be laterally offset from the drain via 245. This allows the source post 279 to be formed above the drain manifold 244 (and the drain terminal 224). The length of the source post 279 formed above the drain terminal 224 can be shorter than the length of the source post 277 formed above the source terminal 226, providing a gap 283 between each source post 279 and the corresponding drain terminal 224 to prevent electrical short circuits therebetween. Figure 3G As shown, the source terminal 279 is connected to the source connection pad 276.

[0143] As mentioned above, Figure 3H It is along Figure 3B A cross-sectional view taken along line 3H-3H shows the arrangement of columns 273, 275, 277, 279, and 281 included in coupling element 270. (As shown from...) Figure 3H As seen on the left, three conductive gate pillars 273 extend upward from the gate terminal 222 to connect to the gate connection pad 272 (see [reference]). Figures 3A-3B (and 3E). The RF signal to be input to the RF transistor amplifier die 210 is transmitted from the external structure to the gate connection pad 272, and then through the gate post 273 to the gate terminal 222. The gate terminal 222 feeds the gate signal to the gate finger 252 through the gate via 243 and the gate manifold 242. Therefore, the gate post 273 is part of the transmission line for inputting the RF signal to the RF transistor amplifier die 210. As from Figure 3H As can be seen, source vias 277, 279, and two source vias 281 surround each gate pillar 273. Each set of the four source vias 277, 279, and 281 defines a circle surrounding a corresponding one of the gate pillars 273, with the source vias 277, 279, and 281 spaced approximately 90 degrees apart from each other. Since the source of the RF transistor amplifier die 210 is maintained at ground voltage during operation, each gate pillar 273 and the surrounding source vias 277, 279, and 281 form a shielded transmission line segment 285. The shielded transmission line structure can extend vertically to the upper surface of the semiconductor layer structure 230. The source vias 277, 279, and 281 are used to reduce the emission of RF energy transmitted along the transmission line segment 285 and also shield the gate pillars 273 to protect them from RF energy from other sources. The drain posts 275 have an identical design, each surrounded by four source vias 277, 279, and 281 to form another set of shielded transmission line segments 285, which are used to carry the RF signal output from the RF transistor amplifier die 210 to external circuit elements. Two of the shielded transmission line segments 285 are located in... Figure 3HThe transmission line segment 285 is shown in a dashed circle. By forming the transmission line segment 285 as a shielded transmission line segment, the transmission line segment can be better isolated from external RF interference and / or noise, exhibiting reduced insertion loss, and / or exhibiting improved impedance matching (thereby reducing return loss).

[0144] exist Figures 3A-3H In this embodiment, four source terminals 277, 279, and 281 surround each gate terminal 273 and each drain terminal 275. Source terminals 277, 279, and 281 may also be referred to herein as ground terminals because source terminal 226 (which is electrically connected to source terminals 277, 279, and 281) is typically coupled to electrical ground during device operation. Figure 3B and 3H As shown in the best embodiment, in order to provide a source terminal 279 on the outside of each gate terminal 273 and each drain terminal 275, the source and drain terminals 222, 224 are each designed to have a fan-in configuration so as to leave space for the source terminal 277 on the outside of each gate terminal 273 and drain terminal 275.

[0145] As from Figure 3H It can also be seen that each gate pillar 273 and each drain pillar 275 vertically overlaps the active region 218 of the RF transistor amplifier die 210. In this document, one element of the RF transistor amplifier is "vertically overlapped" with its other element if an axis perpendicular to the main surface of the semiconductor layer structure 230 passes through both elements. (As seen from...) Figure 3H It can also be seen that the source post 279 on the left side of coupling element 270 vertically overlaps the gate manifold 242, and the source post 279 on the right side of coupling element 270 vertically overlaps the drain manifold 244. All source posts 279 can be vertically overlapped with the corresponding portions of the RF transistor amplifier die 210 outside the active region 218. Figure 3H It can also be seen that one of the gate pillars 273 and one of the source pillars 279 vertically overlap each gate terminal 222, and one of the drain pillars 275 and one of the source pillars 279 vertically overlap each drain terminal 224.

[0146] Similarly, Figure 3H As shown, in some embodiments, the source terminal 226 can be implemented as a large monolithic structure. This source terminal 226 can be connected to the source finger 246 via a source via 247, which is located in... Figure 3HThey are not visible in the view because they are covered by source terminal 226, but their location below source terminal 226 is shown with dashed circles. It will also be appreciated that in other embodiments, multiple smaller source terminals 226 may be provided (e.g., source terminals 226 may be provided above each source finger 246), and source connection pads 276 may electrically connect the source terminals 226 and source fingers 246 together. Note that in Figure 3H In the diagram, the source terminals 277 and 281 that connect source terminal 226 to source connection pad 276 are visible, but the source connection pad 276 itself is not visible because its cross-section is cut through the terminals. (Used for...) Figure 3A-3I The shape of the source connection pad in the embodiment is Figure 3A As shown in the plan view.

[0147] Figure 3I This is a schematic cross-sectional view of an RF transistor amplifier 200, which additionally includes an interconnect structure 300 mounted to a coupling element 270. The coupling element 270 can be used to connect an RF transistor amplifier die 210 to the interconnect structure 300. Since the RF transistor amplifier die 210 and the coupling element 270 have already been referenced above... Figures 3A-3H A detailed discussion has been conducted, so the following discussion will focus on interconnect structure 300.

[0148] Interconnection structure 300 can be used to connect RF transistor amplifier die 210 to other circuit elements. For example, interconnection structure 300 may include an RF input terminal 301 for receiving an RF signal to be coupled to the input terminal of RF transistor amplifier die 210, an RF output terminal 308 for receiving an RF signal output from RF transistor amplifier die 210, and one or more ground input terminals 309 for receiving voltages respectively. Interconnection structure 300 may also include a first interconnect pad 372 that can be configured to couple to gate connection pad 272, a second interconnect pad 374 that can be configured to couple to drain connection pad 274, and a third interconnect pad 376 that can be configured to couple to source connection pad 276 of coupling element 270.

[0149] In some embodiments, bonding elements 360 (e.g., solder balls and / or bumps, conductive die attachment material, etc.) may be used to couple the first, second, and third interconnect pads 372, 374, 376 to the gate connection pad 272, drain connection pad 274, and source connection pad 276, respectively. Although illustrated as a single pad, in some embodiments, one or more of the first, second, and / or third interconnect pads 372, 374, 376 may include multiple pads.

[0150] Each of the first, second, and third interconnect pads 372, 374, and 376 can be coupled to one or more conductive patterns 329 within the interconnect structure 300. The conductive patterns 329 can provide various wiring and / or circuitry within the interconnect structure 300. For example, the conductive pattern 329 can connect the first interconnect pad 372 to one or more first surface mount pads 312-1, 312-2 and to an RF input terminal 301. The conductive pattern 329 can also connect the second interconnect pad 374 to one or more second surface mount pads 322-1, 322-2 and to an RF output terminal 308. The conductive pattern 329 can also connect the third interconnect pad 376 to one or more third surface mount pads 332 and to one or more ground pads 309. Therefore, the interconnect structure 300 may have a surface (e.g., a top surface) with a plurality of first surface connection pads 312, a plurality of second surface connection pads 322 and a plurality of third surface connection pads 332, wherein the corresponding first surface connection pads are coupled to the gate connection pads 272 of the coupling element 270, the corresponding second surface connection pads are coupled to the drain connection pads 274 of the coupling element 270, and the corresponding third surface connection pads are coupled to the source connection pads 276 of the coupling element 270.

[0151] The conductive pattern 329 may be encased in an insulating material 315. In some embodiments, the insulating material 315 may include, for example, silicon oxide, silicon nitride, a polymer, a molding compound, a dielectric substrate, or a combination thereof. In some embodiments, the interconnect structure 300 may be formed as a printed circuit board (PCB). In a PCB embodiment, the insulating material 315 may be the substrate of the PCB, and the conductive pattern 329 may be traces formed within the substrate and electroplated or metal-filled vias.

[0152] Circuit element 350 may also be formed on and / or within interconnect structure 300. For example, circuit element 350 may be coupled between two or more of the first, second, and third surface connection pads 312, 322, 332 (e.g., via solder or other bonding). Circuit element 350 may provide various electronic capabilities to RF transistor amplifier 200. For example, circuit element 350 may include impedances (e.g., including resistive, inductive, and capacitive elements) that can be used for impedance matching and / or harmonic termination. Conductive pattern 329 allows circuit element 350 to be coupled along input or output paths in various different configurations.

[0153] Although illustrated on the surface of interconnect structure 300, it will be understood that additional circuit elements 350 may be provided within interconnect structure 300. For example, parallel plate capacitors, interdigitated capacitors, and / or capacitors formed between conductive vias may be implemented within interconnect structure 300. Similarly, spiral inductors or other inductive elements may be implemented within interconnect structure 300. Resistive elements may be formed on or within interconnect structure 300 by forming trace segments or conductive vias, for example, using a conductive material with higher resistance. In some embodiments, circuit elements 350 and / or conductive patterns 329 may be configured to provide at least a portion of a harmonic termination circuit system, a matching circuit system, a separation circuit system, a combination circuit system, and / or a bias circuit system. Other configurations of other types of circuit elements 350 and / or conductive patterns 329 may be used without departing from the scope of the invention.

[0154] One or more ground planes and / or traces 342 may be formed within the interconnect structure 300. These ground planes can be used to form a stripline transmission line structure 344 within the interconnect structure 300. One such stripline transmission line structure... Figure 3I The signal-carrying vias 310 and / or 320 may also have grounding vias 318 on their opposite sides to form a vertical shielded RF transmission line structure 344 within the interconnect structure 300. It will also be appreciated that... Figure 3I The configuration of the conductive pattern 329 and circuit element 350 shown is merely an example and is not intended to limit the embodiments of the invention.

[0155] The following will be a reference Figure 10A-10G As discussed, in some embodiments, the interconnect structure 300 and circuit element 350 may optionally be encapsulated within a packaging material (not shown). The packaging material may include, for example, silicon oxide, silicon nitride, polymer, molding compound, or a combination thereof.

[0156] like Figure 3IAs shown, the interconnect structure 300, together with the top-side contacts of the RF transistor amplifier die 210, allows additional functionality (such as impedance matching and / or harmonic termination) to be conveniently added to the RF transistor amplifier 200 without the need for extensive wire bonding. Therefore, different functionalities and / or capabilities can be easily coupled to the RF transistor amplifier 200 by using different interconnect structures 300. Reducing or eliminating the need for wire bonding also allows for a smaller die size in some applications (where the size of the wire bonding pads drives the die size), thus the RF transistor amplifier die according to embodiments of the invention can also exhibit increased integration density. Therefore, the RF transistor amplifier die according to embodiments of the invention can exhibit improved product assembly consistency, higher yield, increased product integration, reduced cost, and improved RF performance, especially for products operating at high frequencies such as millimeter-wave frequencies.

[0157] Figure 3J It is similar to Figure 3I A schematic cross-sectional view of RF transistor amplifier 200A and RF transistor amplifier 200A. The difference between RF transistor amplifier 200 and 200A is that RF transistor amplifier 200A includes an interconnect structure 300A, wherein circuit elements 350 are mounted on the same side of the interconnect structure 350 as the RF transistor amplifier die 210. It will be appreciated that, in other embodiments, circuit elements 350 may be provided on both main surfaces of interconnect structures 300 and 300A. It will also be appreciated that RF input 301, RF output 308 receiving the RF signal output from RF transistor amplifier die 210, and one or more ground inputs 309 each receiving a ground reference voltage may be provided on any main surface of the interconnect structure (and inputs 301, 308, and 309 need not all be on the same main surface). These different arrangements can facilitate different packaging schemes.

[0158] The techniques disclosed herein can be particularly advantageous in high-frequency applications because the inductance required in the matching circuit can be much lower in such applications, thus avoiding excessive inductance injection when using conventional bonding wires. Furthermore, the tolerance for bonding wire length has a greater impact at higher frequencies, and the size of the bonding pads can drive the chip size in high-frequency applications (especially at lower power). In some embodiments, any RF transistor amplifier die disclosed herein can be configured to operate at frequencies greater than 1 GHz. In other embodiments, these RF transistor amplifier dies can be configured to operate at frequencies greater than 2.5 GHz. In still other embodiments, these RF transistor amplifier dies can be configured to operate at frequencies greater than 3.1 GHz. In additional embodiments, these RF transistor amplifier dies can be configured to operate at frequencies greater than 5 GHz. In some embodiments, these RF transistor amplifier dies can be configured to operate in at least one of the following frequency bands or sub-regions: 2.5–2.7 GHz, 3.4–4.2 GHz, 5.1–5.8 GHz, 12–18 GHz, 18–27 GHz, 27–40 GHz, or 40–75 GHz.

[0159] In the above embodiments, the gate manifold 242 and the gate terminal 222 are separate elements, and the drain gate manifold 244 and the drain terminal 224 are separate elements (e.g., connected via vias 243 and 245, respectively). The invention is not limited thereto. For example, the gate manifold 242 and the gate terminal 222 can be formed as a single monolithic structure and / or the drain manifold 244 and the drain terminal 224 can similarly be formed as a single monolithic structure.

[0160] Although Figure 3A-3I The illustration shows a semiconductor layer structure 230 including a HEMT, but it will be understood that other types of semiconductor devices can be formed in the semiconductor layer structure 230 without departing from the invention. For example, the semiconductor layer structure 230 may include a MOSFET, a DMOS transistor, a MESFET, and / or an LDMOS transistor. Those skilled in the art will recognize that the arrangement of all source / drain / gate contacts on one side of the semiconductor layer structure 230, including the use of coupling elements 270, can allow for improved connectivity and better thermal performance.

[0161] By placing the gate, drain, and source contacts on the same side of the RF transistor amplifier die 210, previously impossible connection options are provided. These connection options also allow for embodiments that can more strongly utilize the improved thermal conductivity of the SiC material.

[0162] Figure 3K Is as Figure 3A-3IA schematic cross-sectional view of the modified RF transistor amplifier 200A, also known as the RF transistor amplifier 200. Figure 3K As shown, RF transistor amplifier 200A is very similar to RF transistor amplifier 200. However, the source terminal 226 is raised higher than the gate terminal 222 and the drain terminal 224 and extends further outward in the X direction. Since the source terminal 226 can extend above the gate terminal 222 and the drain terminal 224 while maintaining electrical isolation from them, this modified arrangement allows the lower surface of each source post 279 to be connected to the source terminal 226. The gate post 273 and the drain post 275 can extend through openings in the source terminal 226. The openings in the source terminal 226 can be similar to... Figure 5I The opening in the source extremum 226G shown (see discussion below).

[0163] Figure 3L This is a schematic cross-sectional view of the RF transistor amplifier 200B. The RF transistor amplifier 200B is... Figures 3A-3H This is another modified version of the group III nitride-based RF transistor amplifier 200. The main difference between RF transistor amplifier 200B and 200 is that RF transistor amplifier 200 has a fan-in configuration for gate and drain connection pads 272, 274, while RF transistor amplifier 200B has a fan-out configuration for gate and drain connection pads 272, 274. Due to the fan-out configuration, the coupling element 270B of RF transistor amplifier 200B can extend further in the X direction than RF transistor amplifier die 210. By making the coupling element 270B wider than RF transistor amplifier die 210, it becomes possible to fan out the gate and drain connection pads 272, 274 and include a ground post 277 outside each gate post 273 and drain post 275. In the example embodiment, the gate connection pad 272 and drain connection pad 274 may each include a plurality of discrete pads formed in an opening within a large source connection pad (and will be similar to those discussed below). Figure 5I Pads 272, 274, and 276 are shown in the diagram.

[0164] It should also be understood that the RF transistor amplifier die can have a variety of different configurations. For example, while the RF transistor amplifier die 210 has top-side gate, drain, and source terminals 222, 224, 226, in some embodiments, it may also have one or more of the back-side gate, drain, and source terminals 222', 224', 226'. This configuration in Figure 3M The diagram illustrates that, Figure 3M This is a schematic cross-sectional view of the RF transistor amplifier 200C, corresponding to the cross-section of 3B. (See diagram.) Figure 3MAs shown, gate via 211, drain via 213, and / or source via 215 can be formed through semiconductor layer structure 230, which is connected to the corresponding gate, drain, and source terminals 222', 224', 226'. For example, as explained in U.S. Provisional Patent Application Serial No. 63 / 004,985 (“985 application”), filed April 3, 2020, including gate and drain terminals on the back side of an RF transistor amplifier die can have various advantages, such as allowing for more flexible impedance matching circuit implementations. The entire contents of the '985 application are incorporated herein by reference. It will be appreciated that back-side gate, drain, and source terminals 222', 224', 226' and / or corresponding gate, drain, and source vias 211, 213, 215 can be included in any RF transistor amplifier die disclosed herein.

[0165] Figure 4A and 4B This is a schematic cross-sectional view of an RF transistor amplifier 200D based on group III nitrides. The RF transistor amplifier 200D is... Figures 3A-3H A modified version of the group III nitride-based RF transistor amplifier 200. (e.g.) Figures 4A-4B As shown, the RF transistor amplifier 200D and Figures 3A-3H The difference between the RF transistor amplifier 200 and the RF transistor amplifier 200D is that in the RF transistor amplifier 200D, the source terminal 226 and source posts 277, 281 are replaced by a thicker source connector 226D and a much shorter source post 277. The source connection pad 276 can be connected to... Figure 3A-3I The source connection pad 276 of the RF transistor amplifier 200 is identical. The thick metal source connector 226D eliminates the need for source pillar 281 and provides an efficient heat dissipation path to remove heat from the active region of the transistor amplifier die 210D. Source pillar 279 is still included in the RF transistor amplifier 200D and is connected to the source connector 226D via source connection pad 276. The RF transistor amplifier 200D can exhibit improved thermal performance. Figure 4B As shown, each gate and drain post 273, 275 is surrounded by source post 277, source post 279 and source plug 226D to form a shielded transmission line segment 285D.

[0166] Figures 5A-5F The illustration shows a group III nitride-based RF transistor amplifier 200E according to another embodiment of the present invention. Specifically, Figure 5A This is a schematic plan view of the RF transistor amplifier 200E, and Figure 5B It is along Figure 5A A schematic cross-sectional view of the RF transistor amplifier 200E taken from line 5B-5B. Figure 5CIt is one of the source fingers along the RF transistor amplifier 200E (with Figure 3C A schematic plan view of the line (3D-3D correspondence). Figure 5D It is along the longitudinal axis of the gate manifold (and) Figure 3C A schematic cross-sectional view of the RF transistor amplifier 200E (corresponding to line 3F-3F). Figure 5E It is along Figure 5B A cross-sectional view taken from line 5E-5E. Finally, Figure 5F This is a schematic cross-sectional view of an RF transistor amplifier 200E, which also includes an interconnect structure 300E. Figures 5A-5F The RF transistor amplifier 200E is similar to Figure 3A-3I The RF transistor amplifier 200. Therefore, the following discussion will focus on the differences between these two RF transistor amplifiers.

[0167] Figure 3A-3I One complicating aspect of the RF transistor amplifier 200 is that the source post 279 is provided "outside" the gate post 273 and "outside" the drain post 275 (in other words, refer to...). Figure 3C and 3H When viewed in a plan view, each gate post 273 is located between the source post 279 and the active region 218 of the RF transistor amplifier die 210, and each drain post 275 is located between the source post 279 and the active region 218. Typically, the gate and drain manifolds 242, 244 are positioned very close to the edge of the RF transistor amplifier die 210 to maximize the area of ​​the active region 218. Therefore, there may not be enough space to place the source post 279 outside the gate post 273 or the drain post 275. Figure 3A-3I The RF transistor amplifier die 210 addresses this issue using a fan-in configuration for the gate connection pad 272 and the drain connection pad 274. Specifically, in the RF transistor amplifier 200, the gate post 273 is laterally offset from the gate manifold 242 and the drain post 275 is laterally offset from the drain manifold 244 to make room for placing the source post 279 outside the gate post 273 and the drain post 275. However, this repositioning complicates the design of the coupling element 270.

[0168] Figures 5A-5E The RF transistor amplifier die 210E avoids the complexity of having a source terminal 279 located outside the gate terminal 273 and drain terminal 275 by simply omitting the source terminal 279. This simplifies the design of the coupling element 270E included in (or mounted on) the RF transistor amplifier chip 210E. Because the source terminal 279 is omitted, the RF transmission line structure in the coupling element 270E is not as... Figure 3A-3IWhile the corresponding RF transmission line structure in the RF transistor amplifier die 210 is completely shielded, they are still shielded on three sides, which should provide a significant performance improvement compared to more conventional transmission line connections to the RF transistor amplifier die.

[0169] The semiconductor layer structure 230 and the metallization of the direct contact semiconductor layer structure 230 (e.g., gate manifold 242, drain manifold 244, gate finger 252, drain finger 254, and source finger 246) in the RF transistor amplifier die 210E and Figure 3A-3I The RF transistor amplifier die 210 can be exactly the same. Therefore, Figure 3C The metallization of the direct-contact semiconductor layer structure for both RF transistor amplifier dies 210 and 210E is schematically illustrated.

[0170] refer to Figures 5A-5D The RF transistor amplifier die 210E provides a longer gate pillar 273E that directly connects the gate manifold 242 to the gate connection pad 272E, and a longer drain pillar 275E that directly connects the drain manifold 244 to the drain connection pad 274E. The gate terminal 222 and drain terminal 224 provided in the RF transistor amplifier 200E can be omitted, resulting in a simpler design. Furthermore, in the RF transistor amplifier 200E, the gate pillar 273E is positioned directly above the gate manifold 242, and the drain pillar 275 is positioned directly above the drain manifold 244. Additionally, the positions of the gate and drain connection pads 272E and 274E can be changed, and the size and shape of the source connection pad 276E are modified so that, compared to the general E-shaped source connection pad 276 included in the RF transistor amplifier 200, the source connection pad 276E comprises a simpler strip (comparative). Figure 3A and 5A In the RF transistor amplifier 200E, the source terminal 279 is omitted, and an additional source terminal 277 is provided. Note that the gate and drain interconnect pads 272E and 274E of the RF transistor amplifier 200E do not have a fan-in configuration.

[0171] Figure 5E The diagram shows a cross-section taken through the gate, drain, and source posts 273E, 275E, and 277, illustrating how these posts are implemented as a shielded transmission line structure. As can be seen, the three source posts 277 partially surround each gate post 273E. Specifically, in... Figure 5EIn the view, source terminals 277 are provided above, below, and to the right of each gate terminal 273E. Similarly, three source terminals 277 partially surround each drain terminal 275E; source terminals 277 are provided above, below, and to the left of each drain terminal 275E. No additional shielding is provided to the left of each gate terminal 273E or to the right of each drain terminal 275E. Note that the source terminal 281 of the RF transistor amplifier 200 can be replaced by the source terminal 277 in the RF transistor amplifier 200E, since the gate and drain terminals 222, 224 are omitted in the RF transistor amplifier 200E.

[0172] Figure 5F This is a schematic cross-sectional view of the RF transistor amplifier 200E when the amplifier also includes the interconnect structure 300E. Coupling element 270E is used to connect the RF transistor amplifier die 210B to the interconnect structure 300E. (As shown) Figure 5F As shown, bonding elements (e.g., solder balls and / or bumps) 360 can be used to couple interconnect structure 300E to coupling element 270E, respectively. Interconnect structure 300E can be almost identical to interconnect structure 300 described above, so further description of it will be omitted.

[0173] Figure 5G This is a schematic cross-sectional view of the RF transistor amplifier 200F, which is compared with... Figure 5F The RF transistor amplifier 200F is identical to the RF transistor amplifier 200E, except that the RF transistor amplifier 200F includes an interconnect structure 300F in which circuit elements 350 are mounted on the same side of the interconnect structure 350 as the RF transistor amplifier die 210. It will be appreciated that, in other embodiments, circuit elements 350 may be provided on both main surfaces of the interconnect structures 300E and 300F. It will also be appreciated that an RF input terminal 301, an RF output terminal 308, and / or a ground input terminal 309 may be provided on either main surface of the interconnect structures 300E and 300F.

[0174] Figure 5H and 5I These are schematic cross-sectional views and schematic plan views of an RF transistor amplifier 200G according to another embodiment of the present invention. In addition to including additional source pillars 277 outside each gate pillar 273E and drain pillar 275E, such that a total of four source pillars 277 surround each gate and drain pillar 272E, 274E, the RF transistor amplifier 200G is similar to... Figures 5A-5E The RF transistor amplifier 200E is very similar. Similar to the one discussed above. Figure 3LIn one embodiment, this can be achieved by forming a coupling element 270G that is wider than the RF transistor amplifier die 210.

[0175] Figure 3A The illustration shows the included Figure 3A-3I and Figures 5A-5F Gate, drain, and source connection pads 272, 274, and 276 in RF transistor amplifiers 200 and 200E; and two example implementations of 272E, 274E, and 276E. Figure 6A and 6B It is a schematic floor plan, illustrating, for example, that one can... Figure 3A-3I Two alternative implementations of the gate, drain, and source connection pads used in the RF transistor amplifier 200. Figures 6A-6B The cross-sections are horizontal cross-sections taken through the gate, drain, and source connection pads 272, 274, and 276 (i.e., they are along...). Figure 3A (The equivalent intercept of line 6-6). Figures 6A-6B The dashed circles in the diagram illustrate the locations of the gate, drain, and source terminals 273, 275, 277, 279, and 281. The dielectric underfill material provided between the gate, drain, and source terminals 273, 275, 277, 279, and 281... Figure 6A and 6B The diagram shows the underlying structures (such as gate, drain, and source terminals 222, 224, 226), thus obscuring the view.

[0176] First refer to Figure 6A As can be seen, multiple source connection pads 276H are provided in contrast to the monolithic source connection pad 276 included in the RF transistor amplifier 200. Figure 6A In this configuration, each source connection pad 276H is implemented as a strip of conductive material. It is noteworthy that the source connection pads 276H are not electrically connected to each other within the RF transistor amplifier die 210 or coupling element 270. Therefore, each source connection pad 276H can have its own separate ground connection. The source connection pads 276H can be electrically connected to each other, for example, via a common source connection attached to the interconnect structure 300 of the coupling element 270.

[0177] like Figure 6B As shown, in another alternative embodiment, the gate, drain, and source connection pads 272, 274, and 276 can be completely omitted. In this embodiment, the gate, drain, and source posts 273, 275, 277, and 279 can be directly connected to the corresponding pads on the interconnect structure using bonding materials such as conductive bumps arranged in a ball grid array or conductive die attachment material. Moreover, since the gate and drain connection pads 272 and 274 are omitted, therefore... Figure 3A-3IIn some embodiments, the source post 281 may be replaced by a source post 277 that extends all the way to the upper surface of the coupling element.

[0178] Although Figure 6A and 6B The description above shows Figure 3A-3I The embodiments described herein include two alternative implementations of the gate, drain, and source connection pads 272, 274, and 276, but it will be appreciated that any other embodiments disclosed herein (such as, for example) may be adapted to these embodiments. Figure 3J-3M Implementation examples Figure 5A-5I Implementation examples Figures 7A-7C Implementation examples and Figure 10A-10G The same modifications were made to the embodiments.

[0179] Figures 7A-7C The illustration shows an example of a matching circuit, such as an impedance matching circuit or a harmonic termination circuit, that can be implemented in an RF transistor amplifier according to an embodiment of the invention. Specifically, Figure 7A This is a circuit diagram of the RF transistor amplifier 200I, which includes impedance matching circuitry and harmonic termination circuitry. Figure 7B This is a schematic plan view of the interconnect structure 300I according to an embodiment of the present invention, which is part of the RF transistor amplifier 200I. Figure 7C This is a schematic cross-sectional view (along the RF transistor amplifier 200I and the coupling element 270I included in the RF transistor amplifier 200I) Figure 7B (Cut off line 7C-7C).

[0180] refer to Figure 7A As can be seen, the RF transistor amplifier 200I includes an input impedance matching circuit 202, an input harmonic termination circuit 204, an RF transistor amplifier die 210, and an output impedance matching circuit 206. The input impedance matching circuit 202 is coupled in series between the RF input terminal 201 of the RF transistor amplifier 200I and the gate terminal 222 of the RF transistor amplifier die 210, and includes an inductor L1. The input harmonic termination circuit 204 is coupled between the gate terminal 222 of the RF transistor amplifier die 210 and ground, and includes a series LC circuit, which includes an inductor L2 and a capacitor C1. The output impedance matching circuit 206 is coupled in series between the drain terminal 224 of the RF transistor amplifier die 210 and the RF output terminal 208 of the RF transistor amplifier 200I, and includes a series LC circuit, which includes an inductor L3 and a capacitor C2.

[0181] Next reference Figure 7B and 7CIt can be seen that inductors L1-L3 and capacitors C1 and C2 can be implemented using surface-mount circuit elements mounted on the upper surface of interconnect structure 300I. RF input terminal 201 and RF output terminal 208 can be implemented as pads on the bottom surface of interconnect structure 300I.

[0182] First and second conductive gate vias 310-1 and 310-2 can extend through the interconnect structure 300I. A horizontal gate segment 314 is also provided so that the RF input terminal 201 has a fan-out configuration, thereby making it easier to electrically connect the RF input terminal 201 to external circuitry. Similarly, first and second conductive drain vias 320-1 and 320-2 also extend through the interconnect structure 300I. A horizontal drain segment 324 is provided so that the RF output terminal 208 also has a fan-out configuration, thereby making it easier to electrically connect the RF output terminal 208 to external circuitry. A conductive pad 312-1 is formed on top of the first conductive gate via 310-1, and a conductive pad 312-2 is formed on top of the second conductive gate via 310-2. Surface mount circuit element L1 is mounted above and electrically connected to conductive pads 312-1 and 312-2 to realize an inductor L1 connected in series between the RF input terminal 201 and the gate terminal 222 of the RF transistor amplifier die 210. Conductive pad 322 is formed on top of both the first conductive drain via 320-1 and the second conductive drain via 320-2.

[0183] like Figure 7B As shown, conductive traces 330, 332, 334, and 336 are provided on the upper surface of the interconnect structure 300I. Conductive trace 330 electrically connects conductive pad 312-1 to the input pad of surface mount circuit element L2, conductive trace 332 electrically connects the output pad of surface mount circuit element L2 to the input pad of surface mount circuit element C1, and the output pad of surface mount circuit element C1 is mounted on and electrically connected to the ground pad 340. Conductive traces 330, 332, and surface mount circuit elements L2 and C1 implement the input harmonic termination circuit 204. Conductive trace 334 electrically connects conductive pad 322 to the input pad of surface mount circuit element L3, conductive trace 336 electrically connects the output pad of surface mount circuit element L3 to the input pad of surface mount circuit element C2, and mounts and electrically connects the output pad of surface mount circuit element C2 to the ground pad 340. Conductive traces 334 and 336 and surface mount circuit elements L3 and C2 realize the output impedance matching circuit 206.

[0184] like Figure 7CAs shown, the shielded transmission line structure can be implemented within the interconnect structure 300I. For example, conductive ground vias 318 are formed on opposite sides of each conductive gate via 310-1, 310-2 and each conductive drain via 320-1, 320-2. Although in Figure 7C Two conductive grounding vias 318 are shown on opposite sides of each conductive gate and drain via 310, 320 in the cross-section, but it will be appreciated that additional conductive grounding vias 318 may (optionally) also be present. Figure 7C The cross-sectional view externally surrounds each conductive gate and drain via 310, 320. Furthermore, conductive ground traces 342 are formed above and below the horizontal gate segment 314, and above and below the horizontal drain segment 324. The conductive ground traces 342 convert the horizontal gate segment 314 and the horizontal drain segment 324 into shielded transmission line segments in the form of corresponding stripline transmission line segments 344.

[0185] Positioning the source terminal 226 on the top side of the RF transistor amplifier die 210 (i.e., the same side as the gate terminal 222 and the drain terminal 224) facilitates the use of the shielded transmission line segment 344 discussed above, as ground voltage connections are readily accessible in the vicinity of the transmission line structure connected to the gate and drain terminals of the RF transistor amplifier die 210. Furthermore, the signal-carrying vias 310 and / or 320 may also have ground vias 318 on their opposite sides to form a vertical shielded RF transmission line structure 344 within the interconnect structure 300I.

[0186] Although Figures 7B-7C The embodiments described herein implement circuit elements L1-L3 and C1-C2 on the main surface of interconnect structure 300I opposite to RF transistor amplifier die 210, but it will be appreciated that the embodiments of the invention are not limited thereto. For example, in other embodiments, some or all of circuit elements L1-L3 and C1-C2 may be mounted on the same main surface on which RF transistor amplifier die 210 is mounted in interconnect structure 300I, or may be implemented within a conductive pattern in or above interconnect structure 300I.

[0187] Although Figure 7C Examples include stripline transmission line segments implemented within interconnect structure 300I, but it will be appreciated that embodiments of the invention are not limited thereto. For example, coplanar waveguide transmission line segments and / or grounded coplanar waveguide transmission line segments may be used to form some or all of the shielded transmission line structures in the interconnect structure according to embodiments of the invention. Figures 8A-8D The illustration shows two example coplanar waveguide transmission line segments that can be used to form some of the components in a shielded transmission line structure. Figures 9A-9CThis is a schematic diagram illustrating an example grounded coplanar waveguide transmission line segment that can be used to form some of the components in a shielded transmission line structure.

[0188] In particular, Figure 8A This is a planar view of segment 400 of the coplanar waveguide transmission line. Figure 8B yes Figure 8A Side view of coplanar waveguide transmission line segment 400 (along) Figure 8A (8B-8B cut off in the middle), and Figure 8C yes Figure 8A Side front view of coplanar waveguide transmission line segment 400 (along...) Figure 8A (The line 8C-8C is cut off).

[0189] like Figures 8A-8C As shown, the coplanar waveguide transmission line segment 400 includes a conductive trace 402 and first and second ground conductive traces 404. The conductive trace 402 and the first and second ground conductive traces 404 extend parallel to each other, with the first and second ground conductive traces 404 on opposite sides of the conductive trace 402. The conductive trace 402 and the first and second ground conductive traces 404 may include, for example, metal traces of a printed circuit board, formed on a dielectric layer of the printed circuit board. A ground metal layer 406 is disposed below the conductive trace 402 and the first and second ground conductive traces 404. This ground metal layer 406 extends parallel to the conductive trace 402 and the first and second ground conductive traces 404 (and may alternatively be disposed above the conductive trace 402). Figure 8B As shown, conductive via 412 can be connected to conductive trace 402. Conductive via 412 can be used to transmit RF signals between conductive trace 402 and another component (e.g., another RF transmission line segment). Similarly, first and second conductive ground vias 414 can be connected to corresponding first and second conductive ground traces 404 to maintain conductive ground trace 404 at ground potential. Conductive ground trace 414 helps to contain RF energy in the dielectric between ground metal layer 406 and conductive ground trace 414.

[0190] It will also be recognized that other coplanar waveguide transmission line segments can be used. For example, Figure 8D This is a side view of another coplanar waveguide structure, 400A (and...). Figure 8B (as shown in the view corresponding to the grounded metal layer 406), wherein the grounded metal layer 406 is deployed above the conductive trace 402 and the grounded conductive trace 404. According to an embodiment of the invention, the coplanar waveguide transmission line segment 400A can also be used in the interconnect structure.

[0191] Figures 9A-9C The illustration shows a grounded coplanar waveguide transmission line segment 400B, which is similar to coplanar waveguide transmission line segment 400. Figures 9A-9C respectively with Figures 8A-8C Corresponding, and shown Figures 8A-8C How can a coplanar waveguide transmission line segment 400 be converted into a grounded coplanar waveguide transmission line segment 400B? For example, by comparison... Figures 8A-8C and Figures 9A-9C As can be seen, the only difference between transmission line segments 400 and 400B is that transmission line segment 400B includes multiple ground vias 408 extending between the ground metal layer 406 and each conductive ground trace 404. The ground vias 408 can extend along a single line, and adjacent ground vias 408 can be spaced sufficiently small to prevent RF energy exceeding a minimum threshold from passing between adjacent ground vias 408. The grounded coplanar waveguide transmission line segment 400B can exhibit a high level of RF shielding. Other grounded coplanar waveguide transmission line segments can be used, as discussed above (e.g., those where the ground metal layer 406 is deployed above the conductive trace 402 and the grounded conductive trace 404).

[0192] Figure 10A-10G This is a schematic diagram illustrating a method for forming a packaged RF transistor amplifier according to certain embodiments of the present invention. Figure 10A As shown, RF transistor amplifier dies, such as RF transistor amplifier die 210, can be manufactured. Typically, multiple RF transistor amplifier dies 210 can be formed on a single semiconductor wafer, which is then diced into individual RF transistor amplifier dies 210.

[0193] refer to Figure 10B Next, a coupling element, such as a coupling element 270, is formed on the upper surface of the RF transistor amplifier die 210. In some cases, the coupling element can be formed using semiconductor processing techniques before the wafer is diced; in this case, the coupling element 270 can be considered part of the RF transistor amplifier die 210. In other cases, the coupling element 270 can be formed separately (e.g., as an RDL laminate) and placed on the semiconductor wafer, or formed separately and placed on a separately diced RF transistor amplifier die 210. Next, as... Figure 10C As shown, an interconnect structure (e.g., interconnect structure 300) can be coupled to a coupling element 270 to attach an RF transistor amplifier die 210 to the interconnect structure 300.

[0194] like Figure 10D As shown, the capillary bottom filling process can be used to inject dielectric material between the conductive structures of coupling element 270. The dielectric material helps prevent short circuits, enhances the structural integrity of the coupling element, and provides proper impedance matching. Figure 10EAs shown, in other cases, a molded underfill process can be used to inject underfill material between the conductive structures of coupling element 270 and also to encapsulate the RF transistor amplifier die 210 in a protective underfill material. Figure 10F and 10G As shown, Figure 10D The equipment can be packaged in overmolded plastic. Figure 10F In this embodiment, only the RF transistor amplifier die 210 and the coupling element 270 are encapsulated within an overmolded plastic material, while... Figure 10G In this embodiment, the RF transistor amplifier die 210, coupling element 270, and interconnect structure 300 are all encapsulated. Openings can be formed within the encapsulation material to provide access to various terminals of the device (e.g., RF input terminals, RF output terminals, ground terminals, bias voltage terminals, etc.).

[0195] Figure 11A and 11B It is an RF transistor amplifier according to an embodiment of the present invention (e.g., Figure 3A-3I Schematic cross-sectional views of the additional packaging options 500A and 500B for the RF transistor amplifier 200. Since the RF transistor amplifier 200 has already been discussed in detail, Figure 11A-11B The discussion will focus on the outer packaging.

[0196] First refer to Figure 11A Package option 500A encapsulates the RF transistor amplifier 200 in a ceramic package. Package 500A is a so-called open cavity package, which includes a carrier substrate 510, sidewalls 520, and a cover 530, which together define an open cavity 540. The RF transistor amplifier 200 (including interconnect structures 300) is deployed on the carrier substrate 510 within the open cavity 540.

[0197] The carrier substrate 510 may include materials configured to facilitate thermal management of the package 500A. For example, the carrier substrate 510 may include copper and / or molybdenum. In some embodiments, the carrier substrate 510 may consist of multiple layers and / or include vias / interconnects. In an example embodiment, the carrier substrate 510 may be a multilayer copper / molybdenum / copper metal flange comprising a core molybdenum layer having a copper cladding layer on any of its main surfaces. The examples of materials for the provided carrier substrate 510 are not intended to limit the invention.

[0198] In some embodiments, the sidewall 520 and / or the cover 530 may be formed of or comprise an insulating material. For example, the sidewall 530 and / or the cover 530 may be formed of or comprise a ceramic material. In some embodiments, the sidewall 530 and / or the cover 530 may be formed of, for example, Al2O3. The cover 530 may be adhered to the sidewall 520 using epoxy resin adhesive. The sidewall 520 may be attached to the carrier substrate 510 via, for example, braising. Leads 515-1, 515-2 may be configured to extend through the sidewall 520, but embodiments of the invention are not limited thereto.

[0199] In some embodiments, the RF transistor amplifier 200 may be deployed on a carrier substrate 510 and leads 515-1, 515-2 may be attached to the underside of the interconnect structure 300. Leads 515-1, 515-2 may be coupled to the interconnect structure 300 using, for example, a conductive die attachment material. As shown, in some embodiments, wire bonding to connect the RF transistor amplifier 200 to leads 515-1, 515-2 may be avoided.

[0200] refer to Figure 11B Packaging option 500B encapsulates the RF transistor amplifier 200 in an overmolded plastic package. Package 500B includes a carrier substrate 510, leads 515-1, 515-2, and overmolded plastic material 550. The RF transistor amplifier 200 (including interconnect structure 300) is deployed on the carrier substrate 510. Leads 515-1, 515-2 are connected to the interconnect structure (e.g., to reference above). Figure 11A (In the same manner as described above). An overmolding material 550, which may be a plastic or a plastic polymer compound, is injection molded around the RF transistor amplifier 200 (including the interconnect structure 300) to provide protection against external environmental influences.

[0201] A method for manufacturing an overmolded plastic package is described in U.S. Patent No. 9,515,011 to Wood et al., entitled “Over-mold plastic packaged wideband-gap power transistors and MMICS,” issued December 6, 2016. The disclosure of this U.S. Patent is incorporated herein by reference as if fully set forth herein. In package 500B, leads 515-1, 515-2 may extend through the overmolded plastic material 550 to directly connect to an interconnect structure. Therefore, in some embodiments, wire bonding to connect the RF transistor amplifier 200 to leads 515-1, 515-2 can be avoided.

[0202] The carrier substrate 510 of the package 500B may include materials configured to assist in thermal management. For example, the carrier substrate 510 may include copper and / or molybdenum. In some embodiments, the carrier substrate 510 may consist of multiple layers and / or include through-holes / interconnects. In some embodiments, the carrier substrate 510 may include a metal heat sink as part of a lead frame or metal block at least partially surrounded by a plastic-overmolded plastic 550.

[0203] Although Figure 11A and 11B Figure C illustrates the use of an RF transistor amplifier 200 with coupling element 270, but the invention is not limited thereto. In other embodiments, the RF transistor amplifier die 210 can be directly coupled to an interconnect structure (as shown above). Figures 5A-5F (In the middle) and the resulting RF transistor amplifier can be packaged using package 500A or 500B.

[0204] It will be appreciated that any RF transistor amplifier according to the embodiments of the invention discussed herein can be installed in, for example, Figure 10D-10G and Figure 11A and 11B The packaged RF transistor amplifier may be in a package such as the one shown. Depending on the embodiment, the packaged RF transistor amplifier may include a monolithic microwave integrated circuit (MMIC) as the RF transistor amplifier die, wherein the RF transistor amplifier die integrates multiple discrete circuits in a single integrated die. Additionally and / or alternatively, the package may include multiple RF transistor amplifier dies connected in series in the paths to form a multi-stage RF transistor amplifier, and / or may include (e.g., in parallel) multiple RF transistor amplifier dies arranged in multiple paths to form an RF transistor amplifier with multiple transistor amplifier dies and multiple paths, such as in a Doherty amplifier configuration. In some embodiments, the packaged RF transistor amplifier may include an RF transistor amplifier die according to embodiments of the present invention and a conventional RF transistor amplifier die, the RF transistor amplifier die according to embodiments of the present invention having conductive gate and / or conductive drain vias providing electrical connections to a back-side interconnect structure, and a conventional RF transistor amplifier die having gate and drain terminals connected to other structures via wire bonding.

[0205] It will also be recognized that multiple RF transistor amplifier dies can be coupled to a single interconnect structure. This arrangement is in Figure 12 It is illustrated schematically. For example... Figure 12As shown, the first and second RF transistor amplifier dies 210-1, 210-2 are coupled to the interconnect structure 300J via corresponding coupling elements 270-1, 270-2. Conductive patterns (e.g., conductive vias and traces) within the interconnect structure 300J can be used to electrically connect each RF transistor amplifier die 210-1, 210-2 to a matching circuit system and to each other (if desired), the matching circuit system being mounted on and / or implemented in the interconnect structure 300J, for example.

[0206] Interconnection structure 300J can, for example, be used to provide interconnections to RF transistor amplifier dies 210-1, 210-2 to implement multi-stage and / or multi-path amplifier circuits, such as Doherty amplifiers. The conductive patterns within interconnection structure 300J can provide electrical connections for multi-stage and / or multi-path amplifier circuits. Therefore, interconnection structure 300J can be configured to provide modular interconnections that can be easily coupled to multiple RF transistor amplifiers without the use of bonding wires.

[0207] The shielded transmission line structure disclosed herein can be used in a variety of RF transistor amplifiers. For example, U.S. Provisional Patent Application Serial No. 63 / 004,765, filed April 3, 2020 (“765 application”) discloses a variety of RF transistor amplifiers that may include an RF transistor amplifier chip, coupling elements, and optional interconnect structures. The shielded transmission line structure disclosed herein can be incorporated into any RF transistor amplifier disclosed in the 765 application. The entire contents of the 765 application are incorporated herein by reference.

[0208] Compared to conventional RF transistor amplifiers, the RF transistor amplifier according to embodiments of the present invention can have many advantages. The provision of a shielded transmission line structure can improve the performance of the RF transistor amplifier. Furthermore, reducing (or completely eliminating) the bonding wires can reduce costs and simplify manufacturing, and can improve the RF performance of the device because the amount of inductance in the impedance matching network can be precisely controlled, and the problem of excessive inductance in the matching network can be avoided. Moreover, by utilizing the RF transistor amplifier according to embodiments of the present invention, wafer-level packaging becomes possible, which can further simplify manufacturing and / or reduce production costs.

[0209] Embodiments of this disclosure can be used, for example, in RF power products for 5G and base station and / or telephone applications, as well as in radar applications.

[0210] Embodiments of the inventive concept have been described above with reference to the accompanying drawings, which illustrate embodiments of the invention. However, the inventive concept can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. The same reference numerals always refer to the same elements.

[0211] It will be understood that while the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the invention. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0212] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the terms “comprising” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0213] It will be understood that when a component, such as a layer, region, or substrate, is referred to as "on another component" or "extending to another component," it can be directly on or directly extended to another component, or intermediate components may exist. Conversely, when a component is referred to as "directly on another component" or "directly extending to another component," no intermediate components exist. It will also be understood that when a component is referred to as "connected" or "coupled" to another component, it can be directly connected or coupled to another component, or intermediate components may exist. Conversely, when a component is referred to as "directly connected" or "directly coupled" to another component, no intermediate components exist.

[0214] Relative terms such as “below” or “above” or “up” or “down” or “horizontal” or “lateral” or “vertical” may be used herein to describe the relationship between one element, layer, or region and another element, layer, or region as shown in the figures. It will be understood that these terms are intended to cover different orientations of the device in addition to those depicted in the figures.

[0215] Typical embodiments of the invention have been disclosed in the accompanying drawings and description, and although specific terminology has been used, it is for general and descriptive purposes only and not for limiting purposes. The scope of the invention is set forth in the following claims.

Claims

1. A radio frequency (RF) transistor amplifier, comprising: An RF transistor amplifier die having a semiconductor layer structure and a gate terminal and a drain terminal on the upper surface of the semiconductor layer structure; Coupled element, which is located on the upper surface of the semiconductor layer structure; as well as The interconnect structure, located on the upper surface of the coupling element, allows the RF transistor amplifier die and the interconnect structure to be arranged in a stacked configuration. The coupling element includes a first shielded transmission line structure extending between the RF transistor amplifier die and the interconnect structure. The first shielded transmission line structure includes a first conductive post and a first conductive ground post. The first conductive post is electrically connected to the gate terminal of the RF transistor amplifier die. The first conductive ground post has a first end electrically connected to the source terminal of the RF transistor amplifier die and a second end not connected to the conductive element.

2. The RF transistor amplifier of claim 1, wherein the first conductive post is electrically connected to a first input / output terminal of the RF transistor amplifier die, and the first shielded transmission line structure further includes a second conductive ground post electrically connected to the source terminal of the RF transistor amplifier die, the first conductive ground post and the second conductive ground post being on opposite sides of the first conductive post.

3. The RF transistor amplifier of claim 2, wherein the first shielded transmission line structure further includes a third conductive ground post and a fourth conductive ground post electrically connected to the source terminal of the RF transistor amplifier, the first ground post to the fourth ground post being arranged radially around the first conductive post.

4. The RF transistor amplifier of claim 3, wherein the first conductive ground post to the fourth conductive ground post surround the first conductive post.

5. The RF transistor amplifier according to any one of claims 1-4, wherein the first conductive post vertically overlaps the active region of the RF transistor amplifier die.

6. The RF transistor amplifier according to any one of claims 1-4, wherein the first conductive ground post and the second conductive ground post vertically overlap the gate manifold of the RF transistor amplifier die, wherein the gate manifold is connected to a plurality of conductive fingers extending across the active region of the RF transistor amplifier die.

7. The RF transistor amplifier according to any one of claims 2-4, wherein the second conductive ground post vertically overlaps a portion of the RF transistor amplifier die outside the active region.

8. The RF transistor amplifier according to any one of claims 2-4, wherein the first conductive post and the first conductive ground post are both perpendicularly overlapped with the first input / output terminal.

9. The RF transistor amplifier according to any one of claims 2-4, wherein the first input / output terminal includes a gate terminal and the ground terminal includes a source terminal, wherein the coupling element further includes a second shielded transmission line structure including a second conductive post electrically connected to the drain terminal of the RF transistor amplifier die and a fifth conductive ground post and a sixth conductive ground post on opposite sides of the second conductive post, the fifth conductive ground post and the sixth conductive ground post being electrically connected to the source terminal.

10. The RF transistor amplifier according to any one of claims 2-4, wherein the first input / output terminal includes a gate terminal and the ground terminal includes a source terminal, the RF transistor amplifier die further includes a drain terminal, and wherein the source terminal is on the opposite side of the gate terminal and on the opposite side of the drain terminal.

11. The RF transistor amplifier according to any one of claims 2-4, wherein the first conductive post and the third conductive post are electrically connected to the gate manifold of the RF transistor amplifier die, and wherein the first conductive ground post is located between the first conductive post and the third conductive post.

12. The RF transistor amplifier according to any one of claims 2-4, wherein the second conductive ground post comprises a metal block having a cross-sectional area in a first plane parallel to the main surface of the RF transistor amplifier die that is at least five times the cross-sectional area of ​​the first conductive post in the first plane.

13. The RF transistor amplifier of any one of claims 2-4, wherein the coupling element further comprises an injectable underfill material surrounding the first conductive post and the first conductive ground post and the second conductive ground post.

14. The RF transistor amplifier according to any one of claims 1-4, wherein the interconnect structure includes a second shielded transmission line structure.

15. The RF transistor amplifier of claim 14, wherein the second shielded transmission line structure comprises a stripline transmission line segment.

16. The RF transistor amplifier of claim 14, wherein the second shielded transmission line structure comprises a coplanar waveguide transmission line segment.

17. The RF transistor amplifier of claim 14, wherein the second shielded transmission line structure comprises a grounded coplanar waveguide transmission line segment.

18. The RF transistor amplifier according to any one of claims 1-4, wherein the semiconductor layer structure comprises a group III nitride-based semiconductor layer structure.

19. The RF transistor amplifier according to any one of claims 1-4, wherein the interconnect structure comprises a redistribution layer laminate structure.

20. The RF transistor amplifier according to any one of claims 1-4, wherein the interconnect structure includes a printed circuit board.

21. The RF transistor amplifier according to any one of claims 1-4, wherein a plurality of circuit elements are mounted on an interconnect structure.

22. The RF transistor amplifier of claim 21, wherein the circuit elements include at least one of a surface-mount capacitor and a surface-mount inductor.

23. The RF transistor amplifier of claim 21, wherein the side of the RF transistor amplifier die not connected to the interconnect structure is packaged.

24. The RF transistor amplifier of claim 1, wherein the RF transistor amplifier die further includes a gate terminal, a drain terminal, and a source terminal on the upper surface of the semiconductor layer structure.

25. The RF transistor amplifier of claim 24, wherein the first shielded transmission line structure includes a gate post electrically connected to the gate terminal and a first ground post and a second ground post on opposite sides of the gate post, the first ground post and the second ground post being electrically connected to the source terminal.

26. The RF transistor amplifier of claim 1, wherein the first shielded transmission line structure includes a plurality of conductive pillars, the plurality of conductive pillars being arranged such that a first conductive pillar is a signal-carrying pillar, the signal-carrying pillar being surrounded at least on both sides by some additional conductive pillars among the conductive pillars coupled to a ground voltage source.

27. The RF transistor amplifier of claim 26, wherein the first conductive pillar is surrounded on at least three sides by some of the conductive pillars coupled to a ground voltage source.

28. The RF transistor amplifier of claim 1, wherein the coupling element has a fan-in configuration.

29. A radio frequency (RF) transistor amplifier, comprising: RF transistor amplifier die having a semiconductor layer structure based on group III nitrides and gate and drain fingers extending on the upper surface of the semiconductor layer structure; as well as The first shielded transmission line structure extends perpendicularly to the upper surface of the semiconductor layer structure. An interconnect structure, wherein the first shielded transmission line structure electrically connects the RF transistor amplifier die to the interconnect structure. The first shielded transmission line structure includes a first conductive post, a first conductive ground post, and a second conductive ground post. The first conductive post is electrically connected to one of the gate fingers or one of the drain fingers. The first conductive ground post and the second conductive ground post are located on a first opposite side and a second opposite side of the first conductive post, respectively. The first conductive ground post and the second conductive ground post are electrically connected to the source finger of the RF transistor amplifier die. The first shielded transmission line structure further includes a third conductive grounding post and a fourth conductive grounding post on the third and fourth opposite sides of the first conductive post, respectively, and the third conductive grounding post and the fourth conductive grounding post are electrically connected to the source finger.

30. The RF transistor amplifier of claim 29, wherein the first shielded transmission line structure is electrically connected to one of the gate finger and the drain finger.

31. The RF transistor amplifier of claim 29, further comprising an interconnect structure, wherein a first shielded transmission line structure electrically connects the RF transistor amplifier die to the interconnect structure.

32. The RF transistor amplifier of claim 29, wherein the first conductive post vertically overlaps the active region of the RF transistor amplifier die.

33. The RF transistor amplifier of claim 29, wherein the first conductive ground post is vertically overlapped and electrically connected to the manifold of the RF transistor amplifier die of the gate finger or drain finger.

34. The RF transistor amplifier of claim 29, wherein the second conductive ground post vertically overlaps a portion of the RF transistor amplifier die outside the active region.

35. The RF transistor amplifier of claim 29, wherein the first conductive post and the first conductive ground post both vertically overlap the gate terminal of the RF transistor amplifier die.

36. The RF transistor amplifier of claim 29, wherein the first conductive post and the third conductive post are electrically connected to the gate manifold of the RF transistor amplifier die, and wherein the first conductive ground post is located between the first conductive post and the third conductive post.

37. The RF transistor amplifier of claim 31, wherein the interconnect structure includes a second shielded transmission line structure.

38. The RF transistor amplifier of claim 29, wherein the RF transistor amplifier die further includes a gate terminal electrically connected to a gate finger, a drain terminal electrically connected to a drain finger, and a source terminal electrically connected to a source finger, wherein the gate terminal, drain terminal, and source terminal are all located above the semiconductor layer structure at a greater distance than the gate finger, drain finger, and source finger.

39. The RF transistor amplifier of claim 38, wherein the first shielded transmission line structure includes a gate post electrically connected to the gate terminal and a first ground post and a second ground post on opposite sides of the gate post, the first ground post and the second ground post being electrically connected to the source terminal.

40. A radio frequency (RF) transistor amplifier, comprising: RF transistor amplifier die having a semiconductor layer structure based on group III nitrides and gate fingers, drain fingers and source fingers extending on the upper surface of the semiconductor layer structure; as well as Multiple conductive pillars extend perpendicularly to the upper surface of the semiconductor layer structure. The multiple conductive pillars include a first conductive pillar electrically connected to a gate finger or a drain finger, and a first conductive ground pillar and a second conductive ground pillar on the opposite side of the first conductive pillar. The first conductive ground pillar and the second conductive ground pillar are electrically connected to a source finger, wherein the first conductive pillar vertically overlaps the active region of the RF transistor amplifier die.

41. The RF transistor amplifier of claim 40, further comprising an interconnect structure, wherein the plurality of conductive pillars extend between the interconnect structure and the RF transistor amplifier die and electrically connect the interconnect structure to the RF transistor amplifier die.

42. The RF transistor amplifier of claim 40 or 41, wherein the first conductive ground post, the second conductive ground post, and at least one additional conductive ground post surround the first conductive post.

43. The RF transistor amplifier of claim 42, wherein the second conductive ground post vertically overlaps a portion outside the active region of the RF transistor amplifier die.

44. The RF transistor amplifier of claim 40, wherein the first conductive ground post vertically overlaps the manifold of the RF transistor amplifier die.

45. The RF transistor amplifier of any one of claims 40 or 41, wherein the drain refers to the active region of the RF transistor amplifier die extending from the drain manifold, and wherein the first conductive post and the third conductive post are positioned directly above the drain manifold and electrically connected to the drain manifold, and wherein the first conductive ground post is located between the first conductive post and the third conductive post.

46. ​​The RF transistor amplifier of any one of claims 40 or 41, wherein the semiconductor layer structure comprises a group III nitride-based semiconductor layer structure.

47. The RF transistor amplifier of claim 40 or 41, wherein the conductive pillars have a fan-in configuration.

48. A radio frequency (RF) transistor amplifier, comprising: An RF transistor amplifier die includes a gate terminal, a drain terminal, and a source terminal on a first outer surface of the RF transistor amplifier die; as well as An interconnect structure is arranged in a stacked configuration with an RF transistor amplifier die and electrically connected to the RF transistor amplifier die via a first shielded transmission line structure, wherein the first shielded transmission line structure is located between the first outer surface of the RF transistor amplifier die and the interconnect structure. The interconnection structure includes a second shielded transmission line structure electrically connected to the first shielded transmission line structure, and The first shielded transmission line structure includes a first conductive post electrically connected to one of the gate terminal and the drain terminal, and a first conductive ground post and a second conductive ground post on the opposite side of the first conductive post, the first conductive ground post and the second conductive ground post being electrically connected to the source terminal.

49. The RF transistor amplifier of claim 48, wherein the first shielded transmission line structure further includes a third conductive ground post, which, together with the first conductive ground post and the second conductive ground post, surrounds the first conductive post on at least three sides.

50. The RF transistor amplifier of claim 48, wherein the first conductive post vertically overlaps the active region of the RF transistor amplifier die.

51. The RF transistor amplifier of claim 48, wherein the first conductive ground post is vertically overlapped and electrically connected to the gate manifold of the gate terminal.

52. The RF transistor amplifier of claim 48, wherein the first conductive post and the first conductive ground post are both vertically overlapped with the gate terminal.

53. The RF transistor amplifier of claim 48, wherein the first conductive post and the third conductive post are electrically connected to the gate manifold of the RF transistor amplifier die, and wherein the first conductive ground post is located between the first conductive post and the third conductive post.

54. A radio frequency (RF) transistor amplifier, comprising: An RF transistor amplifier die, comprising a gate terminal, a drain terminal, and a source terminal on a first surface of the RF transistor amplifier die; as well as An interconnect structure, which is stacked with an RF transistor amplifier die, includes a shielded transmission line structure in which a plurality of ground conductors of the shielded transmission line structure are electrically connected to a source terminal, and a signal conductor of the shielded transmission line structure is electrically connected to one of a gate terminal and a drain terminal, wherein the plurality of ground conductors surround the signal conductor on at least three sides.

55. The RF transistor amplifier of claim 54, wherein the shielded transmission line structure includes a stripline transmission line segment.

56. The RF transistor amplifier of claim 54, wherein the shielded transmission line structure comprises a coplanar waveguide transmission line segment.

57. The RF transistor amplifier of claim 54, wherein the shielded transmission line structure includes a grounded coplanar waveguide transmission line segment.

58. The RF transistor amplifier according to any one of claims 54-57, wherein the interconnect structure comprises a redistribution layer laminate structure.

59. The RF transistor amplifier according to any one of claims 54-57, wherein the interconnect structure includes a printed circuit board.

60. The RF transistor amplifier according to any one of claims 54-57, wherein a plurality of circuit elements are mounted on an interconnect structure.

61. The RF transistor amplifier of claim 60, wherein the circuit elements include at least one of a surface-mount capacitor and a surface-mount inductor.

62. The RF transistor amplifier of any one of claims 54-57, further comprising a coupling element electrically connecting the RF transistor amplifier die to the interconnect structure.

63. The RF transistor amplifier of claim 62, wherein the coupling element has a fan-in configuration.

64. The RF transistor amplifier of claim 62, wherein the coupling element comprises a plurality of conductive pillars.

65. The RF transistor amplifier of claim 64, wherein the conductive pillars are arranged to form a second shielded transmission line structure.

Images