Reference pre-charge system

Abstract

The pre-charge circuit (500) includes a gain amplifier (510), a comparator (530), a reservoir capacitor (550), a switch (545), a current source (540), and a switch network. The gain amplifier has a gain G1 and receives an input voltage Vrefp (505). The gain amplifier outputs an amplified voltage G1Vrefp to the comparator, which compares G1Vrefp to a voltage across the reservoir capacitor. The comparator outputs a control signal (φ2SW) for the switch based on the comparison. The switch couples the current source to the reservoir capacitor. A current from the current source charges the reservoir capacitor. The switch network couples the reservoir capacitor to an output of the pre-charge circuit during a first mode of operation and provides the input voltage Vrefp to the output during a second mode of operation.

Description

Background Technology

[0001] In many high-performance systems, the bandgap reference voltage generator that provides the reference voltage to the analog-to-digital converter (ADC) is filtered to meet desired noise performance. A buffer integrated into the ADC, located between the external pin and the ADC reference input, reduces the load on the reference input pin. Some ADCs use a precharge buffer to reduce the switching load on the reference voltage generator. However, the operational amplifier in the precharge buffer consumes a significant amount of power, and the output of the precharge buffer (i.e., the reference voltage) may drop in response to the feedback capacitor coupling to it. For Δ-Σ (delta-sigma) ADCs, this drop in reference voltage can introduce errors into the integration operation performed by the ADC, which assumes a fixed reference voltage. Some precharge buffers include reservoir capacitors to reduce the drop in response to the feedback capacitor coupling to it, but this consumes a significant amount of power and may be inaccurate when precharging the feedback digital-to-analog converter (DAC) capacitor. Precharge accuracy can be improved by adding gain to the precharge buffer, but at the cost of even more power consumption. Summary of the Invention

[0002] A device includes a gain amplifier, a comparator, a reservoir capacitor, logic circuitry, a current source, a common-mode feedback (CMFB) loop, a current sink, and a switching network. The gain amplifier is coupled to the comparator and a first voltage terminal. The cathode of the reservoir capacitor is coupled to the comparator. The logic circuitry is coupled to the comparator and generates a first control signal for a first switch and a second switch. The first switch couples the current source to the cathode, and the second switch couples the anode of the reservoir capacitor to the current sink. The CMFB loop is coupled to the anode, cathode, and common-mode voltage terminal and generates a second control signal for the current sink. The switching network couples the cathode to a first output of the device and the anode to a second output of the device based on a third control signal. The switching network couples the first voltage terminal to the first output and the second voltage terminal to the second output based on a fourth control signal.

[0003] In some examples, the switching network includes a third switch, a fourth switch, a fifth switch, and a sixth switch. The third switch couples the cathode to the first output. The fourth switch couples the anode to the second output. The fifth switch couples a first voltage terminal to the first output. The sixth switch couples a second voltage terminal to the second output. In some examples, the first and second outputs are coupled to an ADC, and a third control signal causes the third and fourth switches to close during the coarse charging portion of the integration operation performed by the ADC. A fourth control signal causes the fifth and sixth switches to close during the fine charging portion of the integration operation performed by the ADC. In some examples, a first control signal causes the first and second switches to close during the sampling operation performed by the ADC.

[0004] In some examples, the CMFB loop generates a second control signal to adjust the amount of current passing through the current sink such that the voltage at the common-mode voltage terminal is substantially equal to half the voltage across the reservoir capacitor. In some examples, the gain amplifier includes an amplifier and two resistors. The amplifier has a first input coupled to a first voltage terminal. The first resistor is coupled to a second input and a second voltage terminal of the amplifier. The second resistor is coupled to a second input and the amplifier output. In some examples, the second resistor is a variable resistor, and its resistance is selected to adjust for comparator variations with process and temperature. Attached Figure Description

[0005] For a detailed description of the various examples, please now refer to the accompanying drawings, in which:

[0006] Figure 1 The diagram illustrates a positive reference voltage generator used for an ADC.

[0007] Figure 2 The diagram illustrates a differential reference voltage generator used for an ADC.

[0008] Figures 3A-3B The illustration shows an example precharge system integrated into the ADC and a timing diagram of the control signals within the example precharge system.

[0009] Figures 4A-4B The illustration shows another example precharge system with a reservoir capacitor integrated into the ADC, and a timing diagram of the control signals within this example precharge system.

[0010] Figure 5 The illustration shows an example reference precharge system for integration into an ADC.

[0011] Figure 6 The diagram shows... Figure 5 The timing diagram of the reference precharge system is shown.

[0012] Figure 7 The diagram shows... Figure 5 The graph shows the voltage of the inter-reservoir capacitor in the reference precharge system over time.

[0013] Figure 8 The illustration shows an example differential reference precharge system for integration into an ADC.

[0014] Figure 9 The diagram illustrates the use of Figure 8 The example common-mode feedback loop of the differential reference precharge system shown is illustrated.

[0015] Figure 10 The diagram illustrates the use of Figure 8The differential reference system shown here has another example of a common-mode feedback loop with differential integration. Detailed Implementation

[0016] The described reference precharge circuit includes a current source and a comparator to charge the reservoir capacitor, consuming less power than operational amplifier-based precharge circuits. The comparator compares an amplified reference voltage with the voltage across the reservoir capacitor, and when the amplified reference voltage is substantially equal to the voltage across the reservoir capacitor, logic coupled to the comparator generates a control signal to decouple the current source from the reservoir capacitor. A gain amplifier can be used to generate the amplified reference voltage, and a variable resistor in the gain amplifier can be trimmed to improve precharge accuracy across process and temperature variations.

[0017] The desired overall system gain G can be implemented using a first gain G1 and a second gain of the amplified reference voltage. This second gain is caused by the comparator time delay between the time it takes for the voltage across the reservoir capacitor to become substantially equal to the amplified reference voltage and the time it takes for the current source to decouple from the reservoir capacitor. Using this time delay to implement a portion of the overall system gain relaxes the desired comparator speed and corresponding power consumption. To provide a differential reference voltage, a current sink is coupled to the reservoir capacitor. A common-mode feedback loop generates a control signal to adjust the amount of current through the current sink such that the common-mode voltage across the reservoir capacitor is substantially the same as the reference common-mode voltage.

[0018] During the coarse charging phase of the integration operation performed by the ADC, the switching network couples the cathode of the reservoir capacitor to the positive reference input of the ADC and the anode of the reservoir capacitor to the negative reference input of the ADC. During the fine charging phase of the integration operation, the switching network decouples the reservoir capacitor from the output, couples the positive reference voltage source to the positive reference input, and couples the negative reference voltage source to the negative reference input.

[0019] Figure 1 The diagram illustrates a positive reference voltage generator 100 for an ADC 170. The positive reference voltage generator 100 includes a bandgap reference voltage generator 110, a filter 120, a buffer 150, and a capacitor 160. The filter 120 includes a resistor 130 and a capacitor 140. For high-performance ADCs, the bandgap reference voltage can be filtered to reduce noise. In the voltage generator 100, the filter 120 filters the output voltage from the bandgap reference voltage generator 110. The buffer 150 is placed between the resistor 130 and the ADC 170, and the capacitor 160 is coupled to the output of the buffer 150 and the ADC 170.

[0020] Buffer 150 reduces the load on bandgap 110 and reduces the error caused by resistor 130 connected in series between bandgap reference voltage generator 110 and ADC 170. Buffer 150 can be a pre-charge buffer because noise from the pre-charge buffer does not affect the noise performance of ADC 170. Positive reference voltage generator 100 can be incorporated into an integrated circuit separate from the integrated circuit including ADC 170 to simplify overall system design, since buffer 150 does not need to be added to the system separately.

[0021] Figure 2 The illustration shows an ADC260 configured to measure temperature using a ratiometric resistor temperature detector (RTD). Instead of using an absolute voltage, it reduces errors in temperature measurement by measuring the ratio of the RTD's resistance to a reference resistance. The ADC260 generates a reference current IDAC1 and supplies it to a reference resistor Rref 230, which is coupled across a positive reference voltage input 210 and a negative reference voltage input 220. An RTD resistor Rrtd 240 is coupled to Rref 230 and a bias resistor Rbias 250. To ensure that the voltage across Rref 230 is not loaded by the current drawn from the ADC 260, both the positive and negative reference voltages need to be buffered.

[0022] Figure 3A An example precharge system 300 for an ADC (such as an ADC 170 or ADC 260) is illustrated. The precharge system 300 includes a precharge amplifier 310 and switches 315-330. The precharge amplifier 310 may be an operational amplifier. Switch 325 is configured to couple the output of the precharge amplifier 310 to a feedback DAC capacitor Cdac 340 during integration operation φ2. Switch 330 is configured to couple a reference common-mode voltage Vrefcm 335 to Cdac 340 during sampling operation φ1. The positive input of the precharge amplifier 310 is configured to receive a positive reference voltage Vrefp 305, and the negative input of the precharge amplifier 310 is coupled to its output. Switch 320 is configured to couple the output of the precharge amplifier 310 to Cdac 340 via the closed switch 325 during the coarse charge portion φ2PRE of integration operation φ2. Switch 315 is configured to couple Vrefp 305 to the output of precharge amplifier 310 and Cdac 340 via closed switch 325 during the fine charging portion φ2F of integral operation φ2.

[0023] The precharge amplifier 310 rapidly charges Cdac 340 to approximately Vrefp 305 during the coarse charge portion φ2PRE, and provides an external reference voltage generator for Vrefp 305 to charge Cdac 340 to Vrefp 305 more accurately during the fine charge portion φ2F. However, the output of the precharge amplifier 310 may decrease in response to coupling to Cdac 340, which could introduce errors into the integral operation φ2 assuming a fixed reference voltage. Because the precharge amplifier 310 must settle in less than a quarter of a clock cycle, it consumes a significant amount of current.

[0024] Figure 3B The diagram illustrates the timing of an example precharge system 300. At time t0, the ADC is performing sampling operation φ1. Control signal φ1 350 closes switch 330, thereby coupling the reference common-mode voltage Vrefcm 335 to Cdac 340. Control signal φ2 360 opens switch 325, thereby disconnecting the precharge amplifier 310 and the positive reference voltage Vrefp 305 from Cdac 340. Control signal φ2PRE 365 opens switch 320, and control signal φ2F 370 opens switch 315. At time t1, the ADC stops performing sampling operation φ1. Control signal φ1 350 opens switch 330, thereby disconnecting Vrefcm 335 from Cdac 340. Switches 315-325 remain open.

[0025] At time t2, the ADC performs integration operation φ2. Control signal φ2 360 closes switch 325, thereby connecting Cdac 340 to switches 315 and 320. Switches 315 and 330 remain open. Integration operation φ2 includes a coarse charge portion φ2PRE and a fine charge portion φ2F. At t2, the coarse charge portion φ2PRE begins, and control signal φ2PRE 365 closes switch 320, thereby connecting the output of precharge amplifier 310 to Cdac 340. Precharge amplifier 310 rapidly charges Cdac 340 to approximately Vrefp 305. At time t3, the coarse charge portion φ2PRE ends. Control signal φ2PRE 365 opens switch 320, thereby disconnecting the output of amplifier 310 from Cdac 340. Switches 315 and 330 remain open, and switch 325 remains closed.

[0026] At time t4, the fine charging phase φ2F begins. Control signal φ2F 370 closes switch 315, thereby connecting the positive reference voltage Vrefp 305 from the external voltage generator to Cdac 340. Switches 320 and 330 remain open, and switch 325 remains closed. The external reference voltage generator providing Vrefp 305 charges Cdac 340 to Vrefp 305 more precisely during the fine charging phase φ2F. At time t5, the ADC completes integration operation φ2, and the fine charging phase φ2F ends. Control signal φ2F 370 opens switch 315, thereby disconnecting the external reference voltage provider from Cdac 340. Control signal φ2 360 opens switch 325, thereby disconnecting Cdac 340 from switches 315 and 320. Switches 320 and 330 remain open.

[0027] Figure 4A Another example precharge system 400 with a reservoir capacitor 450 for an ADC is illustrated. The precharge system 400 is similar to the precharge system 300 shown in Figure 3 and includes an additional switch 445 and a reservoir capacitor 450. Switch 445 is configured to couple the output of the precharge amplifier 410 to the reservoir capacitor Cres 450 when the precharge system 400 is not in the coarse charge portion φ2PRE of the integration operation φ2 (such as during the fine charge portion φ2F of the sampling operation φ1 or the integration operation φ2). Cres 450 has a much larger capacitance than that of Cdac 440.

[0028] When the pre-charge system is not in the coarse charge section φ2PRE, switch 445 is closed, and the output of pre-charge amplifier 410 charges Cres 450 to approximately Vrefp 405. During the coarse charge section φ2PRE of the integration operation φ2, switch 445 is open, thereby disconnecting Cres 450 from the output of pre-charge amplifier 410, and switch 420 is closed, thereby connecting Cres 450 to Cdac 440 through the closed switch 425. Through charge sharing, Cdac 440 is charged to approximately:

[0029]

[0030] Where Vrefp represents the positive reference voltage Vrefp 405, Cres represents the capacitance of the reservoir capacitor Cres 450, and Cdac represents the capacitance of the DAC capacitor Cdac 440.

[0031] Because the precharge amplifier 410 is disconnected from Cdac 440 and Cres 450 provides the reference voltage during the coarse charging phase φ2PRE, the reference voltage supplied to the DAC drops less than the reference voltage supplied to the DAC by the precharge system 300 shown in Figure 3. However, the precharge amplifier 410 consumes a significant amount of power, and the precharge system cannot accurately charge Cdac 440. Introducing gain via the precharge amplifier 410 can improve the charging accuracy of the precharge amplifier 410, but at the cost of even higher power consumption.

[0032] Figure 4B The timing diagram of the example precharge system 400 is shown. At time t0, the ADC is performing sampling operation φ1. Control signal φ1 460 closes switch 430, thereby connecting the common-mode reference voltage Vrefcm 435 to Cdac 440. Control signal φ2 470 opens switch 425, thereby disconnecting Cdac 440 from switches 415 and 420. Control signal φ2PRE 475 opens switch 420. Since φ2PRE 475 indicates that the example precharge system 400 is not in the coarse charging portion φ2PRE of the integration operation φ2, the control signal... 485 closes switch 445. Cres 450 is charged by the output of precharge amplifier 410. Control signal φ2F 480 opens switch 415.

[0033] At time t1, the ADC stops performing sampling operation φ1. Control signal φ1 460 opens switch 430, thereby disconnecting Vrefcm 435 from Cdac 440. Switches 415-425 remain open, and switch 445 remains closed. At time t2, the ADC performs integration operation φ2. Control signal φ2 470 closes switch 425, thereby connecting Cdac 440 to switches 415 and 420. Switches 415, 420, and 430 remain open. Integration operation φ2 includes a coarse charge portion φ2PRE and a fine charge portion φ2F.

[0034] At t2, the coarse charging section φ2PRE begins. Control signal φ2PRE 475 closes switch 420, thereby connecting Cres 450 to Cdac 440 via the closed switch 425. Control signal 485 causes switch 445 to open, thereby disconnecting the output of precharge amplifier 410 from Cres 450. Through charge sharing, Cres 450 charges Cdac 440 to approximately:

[0035]

[0036] At time t3, the coarse charging phase φ2PRE ends. Control signal φ2PRE 475 causes switch 420 to open, thereby disconnecting Cres 450 from Cdac 440. Switches 415 and 430 remain open, and switch 425 remains closed.

[0037] At time t4, the fine charging section φ2F begins. Control signal φ2F 480 closes switch 415, thereby connecting the positive reference voltage Vrefp 405 from the external voltage generator to Cdac 440. Switches 420 and 430 remain open, and switch 425 remains closed. Since the coarse charging section φ2PRE has ended, the control signal... 485 closes switch 445, and the output of pre-charge amplifier 410 recharges Cres 450. An external reference voltage generator providing Vrefp 405 charges Cdac 440 to Vrefp 405 more precisely during the fine charging phase φ2F. At time t5, the ADC completes integration operation φ2, and the fine charging phase φ2F ends. Control signal φ2F 480 opens switch 415, thereby disconnecting the external reference voltage provider from Cdac 440. Control signal φ2 470 opens switch 425, thereby disconnecting Cdac 440 from switches 415 and 420. Switches 420 and 430 remain open.

[0038] Figure 5 An example reference precharge system 500 for an ADC is illustrated. The reference precharge system 500 includes a gain amplifier 510, a comparator 530, logic circuitry 535, a current source 540, a reservoir capacitor 550, and switches 545, 560, and 565. The gain amplifier has a gain G1 and includes an amplifier 520, a variable resistor 514, and a resistor 518. The positive input of amplifier 520 is configured to draw voltage from an external voltage generator (such as...). Figure 1 The bandgap reference voltage generator 110 shown receives a positive reference voltage Vrefp 505. A variable resistor 514 is coupled between the negative input and output of the amplifier 520. A resistor 518 is coupled between the negative input of the amplifier 520 and a terminal configured to receive a negative reference voltage Vrefn 525 from an external voltage generator (such as the bandgap reference voltage generator 110).

[0039] The output of amplifier 520 is coupled to the positive input of comparator 530. The negative input of comparator 530 is coupled to node 555. The output of comparator 530 is coupled to logic circuit 535, which generates a control signal for switch 545. When switch 545 is closed, current source 540 is coupled to node 555 and generates a current Icharge, which can be expressed as:

[0040]

[0041] Where R represents the internal resistance of current source 540. The reservoir capacitor Cres 550 is connected to node 555 and ground, and has a much larger capacitance than Cdac 585.

[0042] Comparator 530 compares the output of gain amplifier 510 (approximately G1 multiplied by Vrefp 505) with the voltage across Cres 550 at node 555. When the voltage across Cres 550 is less than the output of gain amplifier 510, logic circuit 535 closes switch 545, thereby connecting current source 540 to Cres 550. In response to the voltage across Cres 550 being substantially equal to the output of gain amplifier 510, logic circuit 535 opens switch 545, thereby disconnecting current source 540 from Cres 550. The delay between the voltage across Cres 550 approximately reaching the output of gain amplifier 510 and the opening of switch 545 allows Cres 550 to continue charging for a period of time, thereby implementing additional gain G2.

[0043] Overall, current source 540 charges Cres 550, such that the voltage Vpre across Cres 550 can be expressed as:

[0044] Vpre=(G1+G2)*(Vrefp505-Vrefn525)

[0045]

[0046] Gain amplifier 510 provides a portion of the gain G1, and the remaining portion of the gain G2 can be implemented using the delay in comparator 530, as referenced herein. Figure 7 Further description. By employing a comparator 530 and a current source 540 instead of an operational amplifier to charge the Cres 550 and the extended Cdac 585, the reference precharge system 500 uses a method described in Figure 3 and... Figure 4A The operational amplifier-based buffer systems 300 and 400 described herein have low power consumption.

[0047] During the coarse charging portion φ2PRE of integration operation φ2, switch 545 disconnects current source 540 from Cres 550, and switch 560 closes, thereby connecting Cres 550 to Cdac 585 via closed switch 572. In the fine charging portion φ2F of integration operation φ2, switch 560 opens, disconnecting Cres 550 from Cdac 585, and switch 565 closes, thereby connecting the external voltage generator providing Vrefp 505 to Cdac 585 via closed switch 572. During integration operation φ2, Cdac 585 also receives the negative reference voltage Vrefn 525 via switch 576. In sampling operation φ1, switches 572 and 576 open, thereby disconnecting Cdac 585 from both the positive and negative reference voltages. Switch 574 closes, thereby connecting the reference common-mode voltage Vrefcm 580 to Cdac 585.

[0048] Figure 6 The diagram shows... Figure 5 The timing diagram of the reference precharge system is shown. At time t0, the ADC is performing sampling operation φ1. Control signal φ1 610 closes switch 574, thereby connecting the common-mode reference voltage Vrefcm 580 to Cdac 585. Control signal φ2 620 opens switches 572 and 576, thereby disconnecting Cdac 585 from switches 560 and 565, as well as the positive reference voltage Vrefp 505 and the negative reference voltage Vrefn 525. Control signal φ2PRE 625 opens switch 560, thereby disconnecting Cres 550 from the open switch 572. Control signal φ2F 630 opens switch 565, thereby disconnecting the external voltage generator providing Vrefp 505 from the open switch 572. Control signal φ2_SW 635 closes switch 545, thereby connecting current source 540 to Cres 550. Current source 540 charges Cres 550, giving Cres 550 a voltage Vpre across it, as previously described herein.

[0049] At time t1, the ADC completes sampling operation φ1. Control signal φ1 610 opens switch 574, thereby disconnecting Vrefcm 580 from Cdac 585. Switches 572, 576, 560, and 565 remain open. Control signal φ2_SW 635 opens switch 545, thereby disconnecting current source 540 and Cres 550. At time t2, the ADC performs integration operation φ2. Control signal φ2 620 closes switches 572 and 576, thereby connecting Cdac 585 to switches 560 and 565, and to the negative reference voltage Vrefn 525. Switches 574, 565, and 545 remain open. At t2, the coarse charge portion φ2PRE begins. Control signal φ2PRE 625 closes switch 560, thereby connecting Cres 550 to Cdac 585 through the closed switch 572. Through charge sharing, Cres 550 charges Cdac 585 to Vrefp_coarse. At time t3, the coarse charge portion φ2PRE ends. Control signal φ2PRE 625 causes switch 560 to open, thereby disconnecting Cres 550 from Cdac 585. Switches 574, 565, and 545 remain open.

[0050] At time t4, the fine charging phase φ2F begins. Control signal φ2F 630 closes switch 565, connecting the positive reference voltage Vrefp 505 from the external voltage generator to Cdac 585. Switches 574 and 560 remain open. Control signal φ2_SW closes switch 545, connecting current source 540 to Cres 550. The external reference voltage generator providing Vrefp 505 charges Vrefp 505 to Cdac 585 more precisely during the fine charging phase φ2F. At time t5, the fine charging phase φ2F ends. Control signal φ2F 630 opens switch 565, disconnecting the external reference voltage provider from Cdac 585. At time t6, the ADC completes integration operation φ2. Control signal φ2 620 disconnects switches 572 and 576, thereby disconnecting Cdac 585 from switches 560 and 565, as well as the positive and negative reference voltages.

[0051] Figure 7The figure illustrates the voltage V(Cres) 710 across the reservoir capacitor 550 over time. Between t0 and t1, current source 540 charges Cres 550, and voltage V(Cres) 710 increases, crossing the positive reference voltage 505. At t1, V(Cres) 710 reaches the threshold voltage Vth 730 output from gain amplifier 510, which is G1 multiplied by Vrefp 505. Between t1 and t2, comparator 530 and logic circuit 535 determine that V(Cres) 710 is approximately the same as Vth 730 and turn off switch 545. At time t2, switch 545 turns off and disconnects current source 540 from Cres 550. During the delay 750 between t1 and t2 from comparator 540 and logic circuit 535, current source 540 continues to charge Cres 550. V(Cres)710 increases from Vth 730 to Vpre 740, which can be expressed as:

[0052]

[0053]

[0054]

[0055] Where tdelay represents the delay of 750 between t1 and t2.

[0056] By utilizing comparator delay 750 to implement gain, the comparator speed can be reduced, thereby reducing the power consumption of the reference precharge system 500. The gain G1 of gain amplifier 510 can be trimmed using variable resistor 514 to compensate for variations in comparator delay 750 with process and temperature. At time t3, switch 560 closes, connecting Cres 550 to Cdac 585 via closed switch 572. Cres 550 charges Cdac 585 through charge sharing, thereby reducing V(Cres) 710 below the positive reference voltage 505. At time t4, switch 560 opens, disconnecting Cres 550 from Cdac 585. Switch 545 closes, connecting current source 540 and Cres 550. Current source 540 begins recharging Cres 550.

[0057] Figure 8 An example differential reference precharge system 800 for an ADC is illustrated. For ease of illustration, the reference precharge system 800 is referred to herein with reference to... Figure 5The reference precharge system 500 shown is described and includes a common-mode feedback (CMFB) loop 810, a current sink 820, and switches 825, 835, and 840. Cres 550 is coupled to node 830 instead of grounding. The CMFB loop 810 is coupled to nodes 555 and 830 and is configured to receive a common-mode reference voltage Vrefcm 580. The CMFB loop 810 outputs a control signal Vctrl 815 for the current sink 820, which is connected to node 830 via switch 825 in the return path of the charging current Icharge from current source 540. During the coarse charge portion φ2PRE of the integration operation φ2, switch 835 couples node 830 to switch 576. During the fine charge portion φ2F of the integration operation φ2, switch 840 couples an external reference voltage generator providing a negative reference voltage Vrefn 805 to switch 576.

[0058] The voltage at node 555 is Vrefp_coarse, and the voltage at node 830 is Vrefn_coarse. Considering the finite capacitance of Cres 550 during charge sharing with Cdac 585, Vrefp_coarse is greater than Vrefp 505, and Vrefn_coarse is less than Vrefn 805. CMFB loop 810 compares Vrefcm 580 with half the sum of Vrefp_coarse and Vrefn_coarse and generates a control signal Vctrl 815 to adjust the current sink 820. CMFB loop 810 balances the current source 540 and the current sink 820, similar to a differential amplifier. As described above, refer to... Figure 5 The comparator 530 and current source 540 consume less power than the operational amplifier-based precharge system. The current sink 820 and CMFB loop 810 consume less power than the reference precharge system 500.

[0059] Figure 9 The diagram illustrates the use of Figure 8The differential reference precharge system 800 shown is an example common-mode feedback loop 900. The CMFB loop 900 includes an amplifier 950, sampling capacitors Cs 935 and 940, an integrating capacitor Cint 955, and switches 910, 915A, 920B, 925A, 930B, and 945B. During sampling operation φ1, switch 915A couples node 555 with voltage Vrefp_coarse to Cs 935. During integration operation φ2, switch 920B couples the common-mode reference voltage Vrefcm 580 to Cs 935. During sampling operation φ1, switch 925A couples node 830 with voltage Vrefn_coarse to Cs 940. During integration operation φ2, switch 930B couples Vrefcm 580 to Cs 940.

[0060] Cs 935 and 940 are coupled together and to switches 910 and 945B. Switch 910 provides the input common-mode voltage INCM 905. Switch 945B couples Cs 935 and 940, as well as INCM 905, to the negative input of amplifier 950. The positive input of amplifier 950 is configured to receive INCM 905. Integrating capacitor Cint 955 is coupled between the negative input and output of amplifier 950. The ratio of the capacitance of integrating capacitor 955 to the capacitance of sampling capacitor 935 or 940 determines the stability and responsiveness of CMFB loop 900. The output of amplifier 950 is the control signal Vctrl 815 for current sink 820. CMFB loop 900 samples the common-mode voltage across Cres 550 and compares it to Vrefcm 580.

[0061] Figure 10 The diagram illustrates the use of Figure 8Another example of a common-mode feedback loop 1000 with differential integration is shown in the differential reference precharge system 800. The CMFB loop 1000 includes switches 1010, 1012A, 1014B, 1016A, 1018B, 1020B, 1022A, 1024B, 1026A, 1040, 1044B, and 1048B; sampling capacitors Cs 1030, 1032, 1034, and 1036; sampling capacitors Cint 1054 and 1058; resistors 1064, 1068, 1070, and 1080; and amplifiers 1050 and 1075. During sampling operation φ1, switch 1012A couples node 555 with Vrefp_coarse to Cs 1030. During integration operation φ2, switch 1014B couples Vrefcm 580 to Cs 1030. During sampling operation φ1, switch 1016A couples node 830 with Vrefn_coarse to Cs 1032. During integration operation φ2, switch 1018B couples Vrefcm 580 to Cs 1032. During integration operation φ2, switch 1020B couples Vrefcm 580 to Cs 1034. During sampling operation φ1, switch 1022A couples Vrefcm 580 to Cs 1034. During integration operation φ2, switch 1024B couples Vrefcm 580 to Cs 1036. During sampling operation φ1, switch 1026A couples Vrefcm 580 to Cs 1036.

[0062] Cs 1030 and 1032 are coupled together and then coupled to switches 1010 and 1044B. Switch 1010 provides the input common-mode voltage INCM 1005. During integration operation φ2, switch 1044B couples Cs 1030 and 1032, along with INCM 1005, to the positive input of amplifier 1050. Cs 1034 and 1036 are coupled together and then coupled to switches 1040 and 1048B. Switch 1040 provides the input common-mode voltage INCM 1005. During integration operation φ2, switch 1048B couples Cs 1034 and 1036, along with INCM 1005, to the negative input of amplifier 1050. Integrating capacitor Cint 1054 is coupled between the positive input and negative output of amplifier 1050. Cint 1058 is coupled between the negative input and positive output of amplifier 1050. The ratio of the capacitance of the integrating capacitor 1054 or 1058 to the capacitance of the sampling capacitor 1030, 1032, 1034 or 1036 determines the stability and responsiveness of the CMFB loop 1000.

[0063] Resistor 1064 is coupled between the negative output of amplifier 1050 and the positive input of amplifier 1075. Resistor 1068 is coupled between the positive output of amplifier 1050 and the negative input of amplifier 1075. Resistor 1070 is coupled between the positive input of amplifier 1075 and the terminal providing the input common-mode voltage INCM 1005. Resistor 1080 is coupled between the negative input and output of amplifier 1075. Amplifier 1050 acts as a differential integrator. Amplifier 1075 acts as a differential-to-single-ended converter and outputs the control signal Vctrl815.

[0064] The term "coupled" is used throughout this specification. This term can encompass connection, communication, or signaling paths that bring the functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then in the first example, device A is coupled to device B; or in the second example, if intermediate component C does not substantially alter the functional relationship between device A and device B, then device A is coupled to device B via intermediate component C such that control signals generated via device A control device B.

[0065] Within the scope of the claims, modifications are possible in the described embodiments, and other embodiments are also possible.

Claims

1. An apparatus comprising: A gain amplifier coupled to a comparator and a first voltage terminal; A reservoir capacitor includes a cathode and an anode, wherein the comparator is further coupled to the cathode; A logic circuit coupled to the comparator and configured to generate a first control signal for a first switch and a second switch, wherein the first switch is configured to couple a current source to the cathode, and wherein the second switch is configured to couple a current sink to the anode; The common-mode feedback loop, or CMFB loop, is coupled to the anode, the cathode, and the common-mode voltage terminal. The CMFB loop is configured to generate a second control signal for the current sink. as well as A switching network configured to couple the cathode to a first output and the anode to a second output based on a third control signal, and configured to couple the first voltage terminal to the first output and the second voltage terminal to the second output based on a fourth control signal.

2. The apparatus of claim 1, wherein the switching network comprises: A third switch is configured to couple the cathode to the first output; A fourth switch is configured to couple the anode to the second output; A fifth switch is configured to couple the first voltage terminal to the first output; as well as A sixth switch is configured to couple the second voltage terminal to the second output.

3. The apparatus of claim 2, wherein the first output and the second output are coupled to an analog-to-digital converter (ADC), wherein the third control signal causes the third switch and the fourth switch to close during a coarse charging portion of an integration operation performed by the ADC, and wherein the fourth control signal causes the fifth switch and the sixth switch to close during a fine charging portion of the integration operation performed by the ADC.

4. The apparatus of claim 1, wherein the gain amplifier comprises: An amplifier having a first input, a second input, and an amplifier output, wherein the first input is coupled to the first voltage terminal; A first resistor is coupled to the second voltage terminal and the second input; as well as A second resistor is coupled to the second input and the amplifier output.

5. The apparatus of claim 1, wherein the first output and the second output are coupled to an analog-to-digital converter (ADC), wherein the first control signal causes the first switch and the second switch to close during a sampling operation performed by the ADC.

6. The apparatus of claim 1, wherein the CMFB loop generates the second control signal to adjust the amount of current passing through the current sink such that the voltage at the common-mode voltage terminal is substantially equal to half the voltage across the reservoir capacitor.

7. The apparatus of claim 1, wherein the first output and the second output are coupled to a feedback capacitor in the analog-to-digital converter (ADC), wherein the current source is configured to charge the reservoir capacitor such that the voltage across the reservoir capacitor is approximately equal to: Where G represents the overall gain, Cdac represents the capacitance of the feedback capacitor, Cres represents the capacitance of the reservoir capacitor, Vrefp represents the voltage at the first voltage terminal, and Vrefn represents the voltage at the second voltage terminal.

8. The apparatus of claim 7, wherein the gain amplifier has a gain G1, and wherein the current source is configured to generate a charging current approximately equal to: Where R represents the internal resistance of the current source, and the overall gain G is essentially equal to: Where tdelay represents the time when the output of the gain amplifier is substantially equal to the voltage across the reservoir capacitor and the time when the first switch and the second switch disconnect the current source and the current sink from the reservoir capacitor.

9. A pre-charging circuit, comprising: A gain amplifier having a gain G1, the gain amplifier being configured to receive an input voltage Vrefp and output an amplified voltage G1Vrefp; A comparator is configured to compare the amplified voltage G1Vrefp with the voltage across the reservoir capacitor, and is further configured to generate a control signal based on the comparison result. A switch configured to couple a current source to the reservoir capacitor based on the control signal, wherein the current source is configured to generate a charging current for the reservoir capacitor; as well as A switching network is configured to couple the reservoir capacitor to an output during the coarse charging portion of an integration operation performed by an analog-to-digital converter (ADC), wherein the output is configured to be coupled to a feedback capacitor in the ADC, wherein the switching network is further configured to provide the input voltage Vrefp to the feedback capacitor during the fine charging portion of the integration operation.

10. The pre-charge circuit of claim 9, wherein the input voltage Vrefp is a first input voltage, and wherein the gain amplifier comprises: An amplifier having a first input, a second input, and an amplifier output, wherein the first input is configured to receive the first input voltage Vrefp; A first resistor is coupled to the second input and configured to receive the second input voltage Vrefn; as well as A second resistor is coupled to the second input and the amplifier output.

11. The pre-charge circuit of claim 10, wherein the second resistor is a variable resistor, and wherein the resistance of the second resistor is selected to adjust for changes in the comparator with process and temperature.

12. The pre-charge circuit of claim 9, wherein the comparator is coupled to a logic circuit, wherein the logic circuit is configured to generate the control signal.

13. The pre-charge circuit according to claim 9, wherein the input voltage Vrefp is a first input voltage, and wherein the charging current is approximately: Where Vrefn represents the second input voltage, and R represents the internal resistance of the current source, wherein the control signal causes the current source to charge the reservoir capacitor such that the voltage across the reservoir capacitor is approximately: Where Cres represents the capacitance of the reservoir capacitor, and tdelay represents the delay between the amplified voltage G1Vrefp and the voltage across the reservoir capacitor becoming substantially equal and the control signal causing the switch to disconnect the current source from the reservoir capacitor.

14. The pre-charge circuit of claim 9, wherein the input voltage Vrefp is a first input voltage, wherein the control signal is a first control signal, wherein the switch is a first switch, wherein the output is a first output, wherein the reservoir capacitor includes a cathode and an anode, wherein the comparator is coupled to the cathode, wherein the first switch is configured to couple the current source to the cathode, and wherein the pre-charge circuit further includes: A second switch is configured to couple a current sink to the anode based on the first control signal; as well as The common-mode feedback loop, or CMFB loop, is configured as follows: Determine the common-mode voltage of the reservoir capacitor; The common-mode voltage of the reservoir capacitor is compared with a reference common-mode voltage; and A second control signal is generated to adjust the amount of current passing through the current sink, such that the common-mode voltage of the reservoir capacitor is substantially equal to the reference common-mode voltage. The switching network is further configured to couple the anode to a second output during the coarse charging portion, wherein the second output is configured to couple to the feedback capacitor, and wherein the switching network is further configured to provide a second input voltage Vrefn to the second output during the fine charging portion.

15. The pre-charge circuit of claim 14, wherein the CMFB loop comprises: An amplifier having a first input, a second input, and an output for the second control signal, wherein the first input is configured to receive an input common-mode voltage; as well as A switched capacitor circuit coupled to the first input and the second input, the cathode and the anode, wherein the switched capacitor circuit is configured to receive the reference common-mode voltage.

16. The pre-charge circuit of claim 14, wherein the CMFB comprises: A differential switched capacitor integrator coupled to the cathode and the anode, the differential switched capacitor integrator being configured to receive the reference common-mode voltage and the input common-mode voltage; as well as A differential-to-single-ended amplifier is coupled to the differential switched capacitor integrator and has an output for the second control signal.

17. An apparatus comprising: A first pre-charge circuit, comprising: A gain amplifier coupled to a first voltage terminal; A comparator coupled to the gain amplifier and the capacitor cathode, the comparator having an output for a first control signal, wherein the reservoir capacitor includes the capacitor cathode and the capacitor anode; A first switch is configured to couple a current source to the cathode of the capacitor based on the first control signal; A second switch is configured to couple the capacitor cathode to a first output during a first operating mode; A third switch, configured to couple the first voltage terminal to the first output during a second operating mode; and The second pre-charge circuit includes: A feedback loop coupled to the capacitor cathode, the capacitor anode, and a second voltage terminal is configured to generate a second control signal for current sinking. A fourth switch is configured to couple the current sink to the anode of the capacitor based on the first control signal; A fifth switch, configured to couple the capacitor anode to a second output during the first operating mode; and A sixth switch is configured to couple a third voltage terminal to the second output during the second operating mode.

18. The apparatus of claim 17, wherein the first pre-charge circuit further comprises logic circuitry coupled to the comparator and configured to generate the first control signal.

19. The apparatus of claim 17, wherein the first output and the second output are configured to be coupled to a feedback capacitor in an analog-to-digital converter (ADC), wherein the first operating mode corresponds to a coarse charging portion of an integration operation performed by the ADC, and wherein the second operating mode corresponds to a fine charging portion of the integration operation.

20. The apparatus of claim 17, wherein the feedback loop is configured as follows: Determine the common-mode voltage of the reservoir capacitor; The common-mode voltage of the reservoir capacitor is compared with the voltage at the second voltage terminal; and The second control signal is generated to adjust the amount of current passing through the current sink such that the common-mode voltage of the reservoir capacitor is substantially equal to the voltage at the second voltage terminal.

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