Systems, methods, and storage media for swapping and encoding double words in a memory subsystem

Abstract

A processing device in a memory system identifies a first set of bits associated with a translation unit of a memory device, where the first set of bits corresponds to a page field. The processing device identifies a second set of bits associated with the translation unit of the memory device, where the second set of bits corresponds to a block field. The processing device determines that a value representing a page number stored in the page field satisfies a threshold criterion. In response to determining that the value representing the page number satisfies the threshold criterion, the processing device determines a difference between the value representing the page number and a threshold value associated with the threshold criterion. The processing device stores a value representing the difference as a plurality of bits in the second set of bits. The processing device stores a value representing a block number stored in the block field as a plurality of bits in the first set of bits.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically, to intelligent swapping and efficient encoding of double words in memory subsystems. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, this disclosure relates to a memory subsystem comprising: a memory device; and a processing means operatively coupled to the memory device to perform operations including: identifying a first set of bits associated with a translation unit of the memory device, wherein the first set of bits corresponds to a page field; identifying a second set of bits associated with the translation unit of the memory device, wherein the second set of bits corresponds to a block field; determining that a value representing a page number stored in the page field satisfies a threshold criterion; and in response to determining that the value representing the page number satisfies the threshold criterion: determining a difference between the value representing the page number and a threshold associated with the threshold criterion; storing a value representing the difference as a plurality of bits in the second set of bits; and storing a value representing a block number stored in the block field as a plurality of bits in the first set of bits.

[0004] In another aspect, this disclosure relates to a method for exchanging and encoding double words in a memory subsystem, comprising: identifying a first set of bits associated with a translation unit of a memory device, wherein the first set of bits corresponds to a page field; identifying a second set of bits associated with the translation unit of the memory device, wherein the second set of bits corresponds to a block field; determining that a value representing a page number stored in the page field satisfies a threshold criterion; and in response to determining that the value representing the page number satisfies the threshold criterion: determining a difference between the value representing the page number and a threshold associated with the threshold criterion; storing the value representing the difference as a plurality of bits in the second set of bits; and storing a value representing a block number stored in the block field as a plurality of bits in the first set of bits.

[0005] In another aspect, this disclosure relates to a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means, cause the processing means to perform operations including: identifying a first set of bits associated with a translation unit of a memory means, wherein the first set of bits corresponds to a page field; identifying a second set of bits associated with the translation unit of the memory means, wherein the second set of bits corresponds to a block field; determining a fixed value stored as the first and second bits of the second set of bits; in response to determining that the fixed value is stored as the first and second bits of the second set of bits, calculating a calculated value based on a value stored in the block field and a threshold associated with a threshold criterion; determining a page number based on the calculated value; and determining a block number based on the value stored in the page field. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0007] Figure 1 Examples of computing systems including a memory subsystem are shown according to some embodiments of the present disclosure.

[0008] Figure 2 An example block diagram is shown illustrating an initial double word according to some embodiments of the present disclosure and the resulting double word after intelligent swapping and effective encoding.

[0009] Figure 3 This is a flowchart of an example method for intelligent swapping and efficient encoding of two words in a memory subsystem according to some embodiments of the present disclosure.

[0010] Figure 4 This is a flowchart of an example method for intelligent swapping and efficient encoding of two words in a memory subsystem according to some embodiments of the present disclosure.

[0011] Figure 5 This is a flowchart of an example method for intelligent swapping and efficient encoding of two words in a memory subsystem according to some embodiments of the present disclosure.

[0012] Figure 6 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0013] This disclosure relates to intelligent switching and efficient encoding of double words in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. The following describes... Figure 1Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem comprising one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0014] The memory subsystem may include high-density non-volatile memory devices, where data retention is required when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. (The following section combines...) Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states related to the number of bits being stored. Logic states may be represented by binary values ​​(e.g., “0” and “1”) or combinations of these values.

[0015] The die is also referred to below as a logical unit identified by a Logical Unit Number (LUN). In some conventional memory subsystems, a LUN can be 64 GB in size. The data stored within each LUN can be represented as one or more data blocks. In some instances, each data block can be one or more logical pages. A logical page is an abstraction of a physical page. The size of the data in a data block can be 512 bytes, 4096 bytes (4KB), etc., depending on the memory device configuration. Each data block can also be referred to as a Translation Unit (TU). For some types of memory devices (e.g., NAND), a TU is the basic data granularity managed by the memory device. A TU can contain a predefined number of logical units (e.g., logical pages, logical blocks, etc.). In some instances, a TU is predefined to contain a single logical block, so the size of the TU is equal to the size of the logical block. In some instances, a TU is predefined to contain multiple logical blocks. In this case, the size of the TU is a multiple of the size of the logical blocks. In one instance, a TU can be predefined to contain a 512-byte logical block, so the size of the TU is 512 bytes. In another instance, a TU can be predefined as containing a 4KB logical block (which can contain multiple logical pages), therefore the size of the TU is 4KB. In yet another instance, a TU can be predefined as containing eight 512-byte logical blocks, totaling (8... The size is 512 bytes, or 4096 bytes (4KB).

[0016] When the host system of the memory subsystem requests access to data (e.g., read data, write data), the host system can send a data access request to the memory device for a TU location within the LUN. For example, the host system can provide a logical address (e.g., a logical block address (LBA), an LBA with an offset, etc.) that identifies the location from which data is to be stored or read. Because the data from the host system will ultimately be stored at a physical address within the memory device, the memory subsystem maintains a logic-to-physical (L2P) translation map or table to identify the physical location where data corresponding to each logical address resides. The L2P map can contain several L2P entries. Each entry in the L2P map identifies the physical location corresponding to a specific TU. The L2P map tracks each TU segment that has been written to the memory subsystem by maintaining its physical address. For example, an L2P entry can contain an index of the TU (e.g., TU 0, TU 1, etc.), the corresponding physical address, some metadata, such as a flag indicating whether the data at an address is valid or invalid, etc. An L2P entry can also be called a double word. Each double word can contain 32 bits.

[0017] In a conventional memory subsystem, the 32 bits in each double word can represent different fields, such as LUN number, block number, page number, plane number, and TU offset. Traditionally, memory devices require the same number of bits to represent certain fields, including TU offset and plane number, but use different numbers of bits to represent other fields such as page count and block count. For example, the number of bits required for the page count and block count fields can depend on the drive density and parameters of the memory device. For instance, in a memory device with a page count of 5184 KB and a block count of 236 KB, the page number field would need to be represented in the double word as (2 13 () or 13 bits, the block number field will need to be represented in a double word as (2 8 ) or 8 bits, for a total of 21 bits. In another memory device, the page count could be 2112 KB and the block count could be 556 KB. In this case, the page number field would need to be represented in a double word as (2 12 ) bits, and the block number field will need to be represented as (2) bits in the double word. 10 There are 22 bits in total. Therefore, depending on the parameters of the memory device, a double word may require additional bits or more to represent a field.

[0018] Because each double word is 32 bits in size, sacrificing each bit is costly. For example, some conventional memory subsystems might use one bit of the double word (e.g., bit 31) as a parity bit. The parity bit is used to detect errors in the data and is therefore important for data integrity. To maintain a double word in a memory device where the page number and block number fields, as in the example described above, require 22 bits, a conventional memory subsystem might use the bit required for the parity bit. However, this would disable the protection provided by the parity bit, potentially leading to undetectable errors in the data and poor memory subsystem performance. In other instances, a conventional memory subsystem might obtain an extra bit from another field (e.g., the LUN field). However, even removing just one bit used to represent the LUN field results in a reduction in drive density. Drive density is the amount of data a memory device can hold. For example, if the LUN field is reduced from 6 bits to 5 bits and the LUN size is 64 GB, the drive density will be halved (i.e., 64 GB). 2 6 =4 TB compared to 64 GB 2 5 =2 TB). This can lead to a decrease in memory device performance. To avoid the problems discussed above, some conventional memory subsystems may use larger double words (with a size greater than 32 bits). However, increasing the double word size may require additional DRAM space for the extra bits, which is expensive.

[0019] The aspects of this disclosure address the above and other deficiencies by employing a memory subsystem with intelligent exchange and efficient encoding using page number and block number fields in double words. To support memory subsystems with memory devices requiring more bits to represent page counts and / or block counts, additional bits are not derived from other fields (such as parity fields or LUN fields). Instead, the memory subsystem identifies a set of page field bits associated with the TU and a set of block field bits associated with the TU. For example, the set of page field bits may be 12 bits, and the set of block field bits may be 10 bits. The memory subsystem allocates 11 bits instead of 12 bits to the set of page field bits. The memory subsystem determines that the value representing the page number stored in the page field bits satisfies a certain threshold (e.g., 2047 KB). If the value representing the page number satisfies the threshold, the memory subsystem calculates the difference between the value representing the page number and the threshold. The memory subsystem stores the value representing the calculated difference as a set of block field bits. The memory subsystem also stores the value representing the block number stored in the block field bits within the set of page field bits. Therefore, the memory subsystem swaps the page field and the block field, saving an extra bit. The memory subsystem can further indicate that the page field and the block field have been swapped using a set of conditions, which may include storing a fixed value as the first two bits of the block field. If it is determined that the fixed value is stored as the first two bits of the block field, then the memory subsystem knows that the set of conditions has been met, and therefore the page field and the block field have been swapped, and can be decoded if necessary.

[0020] The advantages of this disclosure include, but are not limited to, saving at least one bit in a double word. This bit can be used to represent a parity bit, which can be used to verify data in the event of any errors, as described above. This saved bit can also be used to represent a LUN field. The extra bits in the LUN field can support a greater drive density, as described above. Therefore, saving at least one bit can improve the performance of the memory device and increase its efficiency with minimal changes.

[0021] Figure 1 Example computing system 100 including memory subsystem 110 according to some embodiments of the present disclosure is shown. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or combinations of such devices.

[0022] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0023] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0024] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to…” or “coupled with…” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0025] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and to read data from the memory subsystem 110.

[0026] Host system 120 can be coupled to memory system 110 via a physical host interface. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or combinations of communication connections.

[0027] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0028] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. Crosspoint arrays of non-volatile memory cells can perform bit storage based on changes in volume resistance in conjunction with stackable cross-grid data access arrays. Furthermore, compared to many flash-based memories, crosspoint non-volatile memories can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0029] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages that may refer to logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0030] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND flash memory (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0031] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0032] The memory subsystem controller 115 may include a processing means comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0033] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is shown to include a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0034] Typically, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may translate these commands or operations into instructions or appropriate commands to enable desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block address (LBA) namespace) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry may translate commands received from the host system into command instructions to access the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0035] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0036] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0037] The memory subsystem 110 includes a field-switching component 113 that performs intelligent switching and efficient encoding of two words of a memory device. In some embodiments, the memory subsystem controller 115 includes at least a portion of the field-switching component 113. In some embodiments, the field-switching component 113 is part of the host system 110, an application, or an operating system. In other embodiments, the local media controller 135 includes at least a portion of the field-switching component 113 and is configured to perform the functions described herein.

[0038] Field switching component 113 can identify a set of page field bits associated with a TU of the memory device. Field switching component 113 can further identify a set of block field bits associated with the TU. Field switching component 113 can determine the size of the set of page field bits and the size of the set of block field bits based on parameters of the memory device (e.g., page count and block count). Field switching component 113 can allocate a specific number of bits to the set of page field bits. For example, field switching can determine that the size of the set of page field bits is 12 bits and the size of the set of block field bits is 10 bits. Field switching component 113 can allocate one less bit to the set of page field bits, i.e., 11 bits instead of 12 bits. Field switching component 113 can determine that the value representing the page number stored in the page field bits meets a certain threshold (e.g., 2047 KB). If the value representing the page number meets the threshold, then field switching component 113 can calculate the difference between the value representing the page number and the threshold. Field switching component 113 can store the value representing the calculated difference as a set of block field bits. The field exchange component 113 may store a value in the set of page field bits indicating the presence of a block number in the block field bits. The field exchange component 113 may further indicate that the page field and block field have been exchanged using a set of conditions, which may include storing a fixed value as the first two bits of the block field bits. If the field exchange component 113 determines that a fixed value is stored as the first two bits of the block field bits, then the field exchange component 113 knows that the set of conditions has been met, and therefore the page field and block field have been exchanged. Further details regarding the operation of the field exchange component 113 are described below.

[0039] Figure 2 The diagram illustrates an example block diagram of an initial double word and the resulting double word after intelligent switching and effective encoding, according to some embodiments of the present disclosure. As described above, in order for the memory subsystem to identify the physical address of the location where data is stored on the memory device, the memory subsystem maintains an L2P table to identify the physical page address of the data. The table may contain several double words, each double word containing different fields for identifying the physical page address. In some embodiments, each double word may have a size of 32 bits. For example, the memory subsystem may have a double word 260, such as... Figure 2 As shown, it contains 32 bits numbered from bit 0 to bit 31. In some embodiments, the double word 260 may contain five different fields (fields 201, 202, 203, 204, and 205), each requiring a specific number of bits to represent. For example, field 201 may represent a TU offset; field 202 may represent a plane number; field 203 may represent a LUN number; field 204 may represent a page number; and field 205 may represent a block number. Figure 2In this context, field 204 (i.e., the page field) requires 12 bits to represent, and field 205 (i.e., the block field) requires 10 bits. As described above, in memory devices where certain fields, such as the page field and the block field, require a total of 22 bits to represent, performance issues may arise due to the need to steal bits from other fields, such as the LUN field or the parity field. In these cases, aspects of this disclosure, for example... Figure 1 The field exchange component 113 described herein can perform intelligent exchange and efficient encoding of certain fields within double word 260, thereby eliminating the need to steal bits from another field. For example, field exchange component 113 can identify field 204 (i.e., the page field) and field 205 (i.e., the block field). Field exchange component 113 can determine that the value representing the page number stored in field 204 meets a certain threshold criterion. In response to determining that the value representing the page number meets the threshold criterion, field exchange component 113 can determine the difference between the value representing the page number and the threshold criterion value. Field exchange component 113 can store a value representing said difference in field 205. For example, Figure 2 Step 210 is shown, where the value representing the difference is moved from field 204 to field 205. The field exchange component 113 may also store in field 204 the value representing the block number stored in field 205. For example, Figure 2 Step 230 is shown, where the value indicating the block number moves from field 205 to field 204. Field exchange component 113 can also be configured with specific conditions to indicate that an exchange has occurred between field 204 and field 205. For example, Figure 2 Step 220 is shown, where the first two digits of field 205 are set to a fixed value (“XX”) indicating that the specific condition has been met.

[0040] Figure 2 Double word 270 is further illustrated, which is the double word obtained after the field switching component 113 performs intelligent swapping and efficient encoding of fields 204 and 205. Double word 270 contains fields corresponding to double word 260 (i.e., field 206 corresponds to field 201, field 207 corresponds to field 202, field 208 corresponds to field 203, field 209 corresponds to field 204, and field 210 corresponds to field 205). However, double word 270 shows that after intelligent swapping and efficient encoding, field 209 can be represented by 11 bits instead of 12 bits, while the bits required to represent the other fields remain unchanged. As described above, the ability to save a bit reduces cost and improves the performance of the memory device. Further details regarding field switching component 113 are described below.

[0041] Figure 3This is a flowchart of an example method 300 for intelligent swapping and efficient encoding of two words in a memory subsystem according to some embodiments of the present disclosure. Method 300 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 300 is performed by… Figure 1 The field exchange component 113 is executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0042] At operation 302, the processing logic identifies a first set of bits in the memory device. In some embodiments, the first set of bits corresponds to a translation unit of the memory device. A translation unit of the memory device may include a set of fields, such as a page field, a block field, a plane number field, and an offset field. These fields can be used to identify the physical page address of the translation unit. These fields may be stored as portions of entries (i.e., double words) in a data structure such as an L2P table. In some embodiments, each double word may contain 32 bits. In some embodiments, each field may require a predetermined number of bits to represent. For example, a page field may require 12 bits, a block field may require 10 bits, a plane number field may require 2 bits, and an offset field may require 2 bits. In some embodiments, the number of bits required for each field depends on parameters set for the memory device, such as the total page count and total block count of the memory device. The first set of bits may correspond to a page field. In another embodiment, the first set of bits may correspond to another field, such as a block field. In some embodiments, the processing logic allocates the first set of bits based on a bit count. For example, the processing logic may determine the bit count of the first set of bits. In response to determining the bit count of the first group of bits, the processing logic may allocate a different number of bits to the first group of bits, for example, allocating one less bit. For example, in some embodiments, the processing logic may determine that the bit count of the first group of bits is 12 bits. Then, the processing logic may allocate 11 bits to the first group of bits instead of 12 bits.

[0043] At operation 304, the processing logic identifies a second set of bits for the memory device. In some embodiments, the second set of bits corresponds to a translation unit of the memory device. The translation unit of the memory device may include a set of fields, such as a page field, a block field, a plane number field, and an offset field. This set of fields can be used to identify the physical page address of the translation unit. The set of fields may be stored as portions of entries (i.e., double words) in a data structure such as an L2P table. In some embodiments, each double word may contain 32 bits. In some embodiments, each field may require a predetermined number of bits to represent. For example, the page field may require 12 bits, the block field may require 10 bits, the plane number field may require 2 bits, and the offset field may require 2 bits. In some embodiments, the number of bits required for each field depends on parameters set for the memory device, such as the total page count and total block count of the memory device. The second set of bits may correspond to a block field. In another embodiment, the set of bits may correspond to another field, such as a page field.

[0044] At operation 306, the processing logic determines that the value representing the page number meets a threshold criterion. In some embodiments, the page number may be stored as a first set of bits, for example, in a page field. In some embodiments, the page number stored as the first set of bits is stored in a portion of an entry in the L2P table corresponding to the translation unit. In some embodiments, determining that the value representing the page number meets the threshold criterion includes comparing the value representing the page number with a threshold associated with the threshold criterion and determining that the value representing the page number is greater than the threshold. In some embodiments, the threshold is a fixed value (e.g., 2047). The threshold may be set according to parameters of the memory device, or it may be set by the host system of the memory subsystem. In some embodiments, the threshold is a modifiable value. In some embodiments, the processing logic determines that the value representing the page number does not meet the threshold criterion. In response to determining that the value representing the page number does not meet the threshold criterion, the processing logic may store the value representing the page number as a set of bits in the first set of bits. In some embodiments, storing the value representing the page number as the first set of bits includes updating a portion of an entry in the L2P table corresponding to the translation unit with the page number value. In response to determining that the value representing the page number does not meet the threshold criterion, the processing logic may store the value representing the block number as a set of bits in the second set of bits. In some embodiments, storing the value representing the block number as a second set of bits includes updating a portion of the entry in the L2P table corresponding to the translation unit with the value of the block number. In some embodiments, determining that the value representing the page number does not meet a threshold criterion includes comparing the value representing the page number with a threshold associated with the threshold criterion, and determining that the value representing the page number is equal to, equivalent to, or less than the threshold.

[0045] At operation 308, in response to determining that the value representing the page number meets a threshold criterion, the processing logic determines the difference between the value representing the page number and a threshold associated with the threshold criterion. In some embodiments, determining the difference includes subtracting the threshold from the value representing the page number.

[0046] At operation 310, in response to determining that the value representing the page number meets a threshold criterion, the processing logic stores the value representing the difference as a set of bits in a second set of bits. In some embodiments, storing the value representing the difference as a set of bits in the second set of bits includes updating a portion of the entry in the L2P table corresponding to the translation unit with the value representing the difference.

[0047] At operation 312, in response to determining that the value representing the page number meets a threshold criterion, the processing logic stores the value representing the block number as a set of bits in a first set of bits. In some embodiments, the block number may be stored, for example, as a second set of bits in a block field. In some embodiments, storing the value representing the block number as the first set of bits includes updating a portion of the entry in the L2P table corresponding to the translation unit with the value of the block number. In some embodiments, the processing logic stores a fixed value as two bits in the second set of bits. In some embodiments, storing the value representing the fixed value as two bits in the second set of bits includes updating a portion of the entry in the L2P table corresponding to the translation unit with the fixed value. In some embodiments, the processing logic stores the fixed value as the last two consecutive bits in the second set of bits. In some embodiments, the fixed value is an integer value, such as 1. In some embodiments, storing the fixed value as two bits in the second set of bits indicates to the processing logic that a specific condition has been met. In some embodiments, the specific condition includes an exchange between the page field and the block field.

[0048] Figure 4 This is a flowchart of an example method 400 for intelligent swapping and efficient encoding of two words in a memory subsystem according to some embodiments of the present disclosure. Method 400 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1 The field exchange component 113 is executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0049] At operation 402, the processing logic identifies a first set of bits for the memory device. In some embodiments, the first set of bits corresponds to a translation unit of the memory device. The translation unit of the memory device may include a set of fields, such as a page field, a block field, a plane number field, and an offset field. This set of fields can be used to identify the physical page address of the translation unit. The set of fields may be stored as portions of entries (i.e., double words) in a data structure such as an L2P table. In some embodiments, each double word may contain 32 bits. In some embodiments, each field may require a predetermined number of bits to represent. For example, the page field may require 12 bits, the block field may require 10 bits, the plane number field may require 2 bits, and the offset field may require 2 bits. In some embodiments, the number of bits required for each field depends on parameters set for the memory device, such as the total page count and total block count of the memory device. The first set of bits may correspond to a page field. In another embodiment, the first set of bits may correspond to another field, such as a block field.

[0050] At operation 404, the processing logic identifies a second set of bits for the memory device. In some embodiments, the second set of bits corresponds to a translation unit of the memory device. The translation unit of the memory device may include a set of fields, such as a page field, a block field, a plane number field, and an offset field. This set of fields can be used to identify the physical page address of the translation unit. The set of fields may be stored as entries (i.e., double words) in a data structure such as an L2P table. In some embodiments, each double word may contain 32 bits. In some embodiments, each field may require a predetermined number of bits to represent. For example, the page field may require 12 bits, the block field may require 10 bits, the plane number field may require 2 bits, and the offset field may require 2 bits. In some embodiments, the number of bits required for each field depends on parameters set for the memory device, such as the total page count and total block count of the memory device. The second set of bits may correspond to the block field. In another embodiment, the set of bits may correspond to another field, such as the page field.

[0051] At operation 406, the processing logic allocates the first group of bits based on the bit count. For example, the processing logic may determine the bit count of the first group of bits. In response to determining the bit count of the first group of bits, the processing logic may allocate a different number of bits to the first group of bits, such as allocating one less bit. For example, in some embodiments, the processing logic may determine that the bit count of the first group of bits is 12 bits. Then, the processing logic may allocate 11 bits to the first group of bits instead of 12 bits.

[0052] At operation 408, the processing logic determines that the value representing the page number meets a threshold criterion. In some embodiments, the page number may be stored as a first set of bits in a page field, for example. In some embodiments, the page number stored as the first set of bits is stored in a portion of an entry in the L2P table corresponding to the translation unit. In some embodiments, determining that the value representing the page number meets the threshold criterion involves comparing the value representing the page number with a threshold associated with the threshold criterion and determining that the value representing the page number is greater than the threshold. In some embodiments, the threshold is a fixed value (e.g., 2047). The threshold may be set according to parameters of the memory device, or it may be set by the host system of the memory subsystem. In some embodiments, the threshold is a modifiable value.

[0053] At operation 410, in response to determining that the value representing the page number meets a threshold criterion, the processing logic determines the difference between the value representing the page number and a threshold associated with the threshold criterion. In some embodiments, determining the difference includes subtracting the threshold from the value representing the page number.

[0054] At operation 412, in response to determining that the value representing the page number meets a threshold criterion, the processing logic stores the value representing the difference as a set of bits in a second set of bits. In some embodiments, storing the value representing the difference as a set of bits in the second set of bits includes updating a portion of the entry in the L2P table corresponding to the translation unit with the value representing the difference.

[0055] At operation 414, in response to determining that the value representing the page number meets a threshold criterion, the processing logic stores the value representing the difference as a set of bits in a second set of bits. In some embodiments, storing the value representing the difference as a set of bits in the second set of bits includes updating a portion of the entry in the L2P table corresponding to the translation unit with the value representing the difference.

[0056] At operation 416, the processing logic stores the fixed value as two bits in the second set of bits. In some embodiments, storing the value representing the fixed value as two bits in the second set of bits includes updating a portion of the entry in the L2P table corresponding to the translation unit with the fixed value. In some embodiments, the processing logic stores the fixed value as the last two consecutive bits in the second set of bits. In some embodiments, the fixed value is an integer value, such as 1. In some embodiments, storing the fixed value as two bits in the second set of bits indicates to the processing logic that a specific condition has been met. In some embodiments, the specific condition includes an exchange between the page field and the block field.

[0057] At operation 418, in response to determining that the value representing the page number does not meet a threshold criterion, the processing logic may store the value representing the page number as a set of bits in a first set of bits. In some embodiments, storing the value representing the page number as the first set of bits includes updating a portion of the entry in the L2P table corresponding to the translation unit with the page number value. In some embodiments, determining that the value representing the page number does not meet a threshold criterion includes comparing the value representing the page number with a threshold associated with the threshold criterion and determining that the value representing the page number is equal to, equal to, or less than the threshold.

[0058] At operation 420, in response to determining that the value of the indicated page number does not meet a threshold criterion, the processing logic may store the value of the indicated block number as a set of bits in a second set of bits. In some embodiments, storing the value of the indicated block number as said set of bits in the second set of bits includes updating a portion of the entry in the L2P table corresponding to the translation unit with the value of the block number. In some embodiments, determining that the value of the indicated page number does not meet a threshold criterion includes comparing the value of the indicated page number with a threshold associated with the threshold criterion, and determining that the value of the indicated page number is equal to, equal to, or less than the threshold.

[0059] Figure 5 This is a flowchart of an example method 500 for intelligent swapping and efficient encoding of two words in a memory subsystem according to some embodiments of the present disclosure. Method 500 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1 The field exchange component 113 is executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0060] At operation 502, the processing logic identifies a first set of bits for the memory device. In some embodiments, the first set of bits corresponds to a translation unit of the memory device. A translation unit of the memory device may include a set of fields, such as a page field, a block field, a plane number field, and an offset field. These fields can be used to identify the physical page address of the translation unit. These fields may be stored as portions of entries (i.e., double words) in a data structure such as an L2P table. In some embodiments, each double word may contain 32 bits. In some embodiments, each field may require a predetermined number of bits to represent. For example, a page field may require 12 bits, a block field may require 10 bits, a plane number field may require 2 bits, and an offset field may require 2 bits. In some embodiments, the number of bits required for each field depends on parameters set for the memory device, such as the total page count and total block count of the memory device. The first set of bits may correspond to a page field. In another embodiment, the first set of bits may correspond to another field, such as a block field. In some embodiments, the processing logic allocates the first set of bits based on a bit count. For example, the processing logic may determine the bit count of the first set of bits. In response to determining the bit count of the first group of bits, the processing logic may allocate a different number of bits to the first group of bits, for example, allocating one less bit. For example, in some embodiments, the processing logic may determine that the bit count of the first group of bits is 12 bits. Then, the processing logic may allocate 11 bits to the first group of bits instead of 12 bits.

[0061] At operation 504, the processing logic identifies a second set of bits for the memory device. In some embodiments, the second set of bits corresponds to a translation unit of the memory device. The translation unit of the memory device may include a set of fields, such as a page field, a block field, a plane number field, and an offset field. This set of fields can be used to identify the physical page address of the translation unit. The set of fields may be stored as portions of entries (i.e., double words) in a data structure such as an L2P table. In some embodiments, each double word may contain 32 bits. In some embodiments, each field may require a predetermined number of bits to represent. For example, the page field may require 12 bits, the block field may require 10 bits, the plane number field may require 2 bits, and the offset field may require 2 bits. In some embodiments, the number of bits required for each field depends on parameters set for the memory device, such as the total page count and total block count of the memory device. The second set of bits may correspond to a block field. In another embodiment, the set of bits may correspond to another field, such as a page field.

[0062] At operation 506, the processing logic determines that a fixed value is stored as the first and second bits of a second set of bits. In some embodiments, determining that a fixed value is stored as the first and second bits of a second set of bits may include identifying a first value stored as the first bit of a second set of bits in a portion of an entry corresponding to the translation unit's L2P table. The processing logic may identify a second value stored as the second bit of a second set of bits in a portion of an entry corresponding to the translation unit's L2P table. The processing logic may compare the first value with the second value. The processing logic may determine that the first value and the second value are equal to the fixed value. In some embodiments, the fixed value is an integer value, such as 1. In some embodiments, the processing logic determines that the fixed value is stored as the last two consecutive bits of a second set of bits. In some embodiments, determining that a fixed value is stored as the first and second bits of a second set of bits includes determining that a specific condition has been met. In some embodiments, the specific condition includes that an exchange has occurred between the page field and the block field. In some embodiments, if the processing logic determines that the fixed value is not stored as the first and second bits of a second set of bits, then the processing logic determines a page number based on the value stored in the page field. In some embodiments, determining a page number based on the value stored in the page field includes setting the value representing the page number to be equal to the value stored in the page field. In some embodiments, setting the value representing the page number equal to the value stored in the page field involves updating a portion of the entry in the L2P table corresponding to the translation unit with the value representing the page number. In some embodiments, if the processing logic determines that the fixed value is not stored as the first and second bits of the second set of bits, then the processing logic determines the block number based on the value stored in the block field. In some embodiments, determining the block number based on the value stored in the block field involves setting the value representing the block number equal to the value stored in the block field. In some embodiments, setting the value representing the block number equal to the value stored in the block field involves updating a portion of the entry in the L2P table corresponding to the translation unit with the value representing the block number.

[0063] At operation 508, the processing logic calculates the calculated value. In some embodiments, calculating the calculated value involves adding the value stored in the block field to a threshold associated with a threshold criterion. In some embodiments, the processing logic may identify the value stored in the block field using a portion of an entry in the L2P table corresponding to the translation unit. In some embodiments, the threshold is a fixed value (e.g., 2047). The threshold may be set according to parameters of the memory device, or it may be set by the host system of the memory subsystem. In some embodiments, the threshold is a modifiable value.

[0064] At operation 510, the processing logic determines the page number based on the calculated value. In some embodiments, determining the page number based on the calculated value includes setting the value representing the page number to be equal to the calculated value. In some embodiments, setting the value representing the page number to be equal to the calculated value includes updating a portion of the entry in the L2P table corresponding to the translation unit with the value representing the page number.

[0065] At operation 512, the processing logic determines the block number based on the value stored in the page field. In some embodiments, determining the block number based on the value stored in the page field includes setting the value representing the block number to be equal to the value stored in the page field. In some embodiments, setting the value representing the block number to be equal to the value stored in the page field includes updating a portion of the entry in the L2P table corresponding to the translation unit with the value representing the block number.

[0066] Figure 6 An example machine of computer system 600 is shown, within which an instruction set is executable to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of field exchange component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment within the capacity of a server or client machine in a client-server network environment.

[0067] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although shown as a single machine, the term "machine" should also be considered to include any set of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein.

[0068] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0069] Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 602 is configured to execute instructions 626 to perform the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communication on network 620.

[0070] Data storage device 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) storing one or more sets of instructions 626 or software embodying any one or more methods or functions described herein. The instructions 626 may also reside wholly or at least partially within main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0071] In one embodiment, instruction 626 includes instructions for implementing a component corresponding to a field exchange (e.g., Figure 1 The field exchange component 113) contains functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing the one or more instruction sets. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding instruction sets executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" should be accordingly understood to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0072] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and are generally considered, a self-consistent sequence of operations that produce the desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for reasons of common use, it has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc.

[0073] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities within the registers and memories of a computer system into other data representing physical quantities similarly represented within the memory or registers of a computer system or other such information storage systems.

[0074] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for a particular purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0075] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the teachings and procedures herein, or it may prove convenient to construct more specialized devices to implement the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure described herein can be implemented using various programming languages.

[0076] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable for programming a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0077] In the foregoing description, embodiments of this disclosure have been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications can be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory subsystem comprising: Memory devices; as well as A processing device operatively coupled to the memory device to perform operations including: Identify a first set of bits associated with a translation unit of the memory device, wherein the first set of bits corresponds to a page field; Identify a second set of bits associated with the translation unit of the memory device, wherein the second set of bits corresponds to a block field; Determine that the value representing the page number stored in the page field meets the threshold criterion; and In response to determining that the value representing the page number meets the threshold criterion: Determine the difference between the value representing the page number and the threshold associated with the threshold criterion; Store the value representing the difference as multiple bits in the second group of bits; as well as The value representing the block number stored in the block field is stored as multiple bits in the first group of bits.

2. The memory subsystem according to claim 1, further comprising: The fixed value is stored as the first bit and the second bit of the second group of bits.

3. The memory subsystem according to claim 1, wherein the translation unit includes a plurality of fields, wherein the plurality of fields include the page field, the block field, the plane number field, and the offset field.

4. The memory subsystem of claim 1, wherein the processing means is configured to perform operations further comprising: The first group of bits is allocated according to the bit count.

5. The memory subsystem of claim 1, wherein the processing means is configured to perform operations further comprising: Determine that the value of the page number does not meet the threshold criterion; and In response to determining that the value representing the page number does not meet the threshold criterion, the value representing the page number is stored as the plurality of bits in the first group of bits.

6. The memory subsystem of claim 1, wherein the processing means is configured to perform operations further comprising: Determine that the value of the page number does not meet the threshold criterion; and In response to determining that the value representing the page number does not meet the threshold criterion, the value representing the block number is stored as multiple bits in the second set of bits.

7. The memory subsystem of claim 1, wherein determining that the value representing the page number stored in the page field satisfies the threshold criterion comprises: The value of the page number is compared with the threshold associated with the threshold criterion; as well as It is determined that the value of the page number is greater than the threshold.

8. A method for exchanging and encoding double words in a memory subsystem, comprising: Identify a first set of bits associated with a translation unit of the memory device, wherein the first set of bits corresponds to a page field; Identify a second set of bits associated with the translation unit of the memory device, wherein the second set of bits corresponds to a block field; Determine that the value representing the page number stored in the page field meets the threshold criterion; and In response to determining that the value representing the page number meets the threshold criterion: Determine the difference between the value representing the page number and the threshold associated with the threshold criterion; Store the value representing the difference as multiple bits in the second group of bits; as well as The value representing the block number stored in the block field is stored as multiple bits in the first group of bits.

9. The method of claim 8, further comprising: Store the fixed value as the first and second bits of the second group of bits.

10. The method of claim 8, wherein the translation unit comprises a plurality of fields, wherein the plurality of fields include the page field, the block field, the plane number field, and the offset field.

11. The method of claim 8, further comprising: The first group of bits is allocated according to the bit count.

12. The method of claim 8, further comprising: This indicates that the value of the page number does not meet the threshold standard; as well as In response to determining that the value representing the page number does not meet the threshold criterion, the value representing the page number is stored as the plurality of bits in the first group of bits.

13. The method of claim 8, further comprising: This indicates that the value of the page number does not meet the threshold standard; as well as In response to determining that the value representing the page number does not meet the threshold criterion, the value representing the block number is stored as multiple bits in the second set of bits.

14. The method of claim 8, wherein determining that the value representing the page number stored in the page field satisfies the threshold criterion comprises: The value of the page number is compared with the threshold associated with the threshold criterion; as well as It is determined that the value of the page number is greater than the threshold.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means, cause the processing means to perform operations including: Identify a first set of bits associated with a translation unit of the memory device, wherein the first set of bits corresponds to a page field; Identify a second set of bits associated with the translation unit of the memory device, wherein the second set of bits corresponds to a block field; The fixed value is determined to be stored as the first and second bits in the second group of bits; In response to determining that the fixed value is stored as the first bit and the second bit in the second set of bits, the calculated value is calculated based on the value stored in the block field and the threshold associated with the threshold criterion; The page number is determined based on the calculated value; as well as The block number is determined based on the value stored in the page field.

16. The non-transitory computer-readable storage medium of claim 15, wherein the translation unit comprises a plurality of fields, wherein the plurality of fields include the page field, the block field, the plane number field, and the offset field.

17. The non-transitory computer-readable storage medium of claim 15, wherein the processing means is configured to perform further operations including: In response to determining that the fixed value is not stored as the first and second bits in the second set of bits: The page number is determined based on the value stored in the page field; and The block number is determined based on the value stored in the block field.

18. The non-transitory computer-readable storage medium of claim 15, wherein determining the page number based on the calculated value comprises: Set the value representing the page number to be equal to the calculated value.

19. The non-transitory computer-readable storage medium of claim 15, wherein determining the block number based on a value stored in the page field comprises: Set the value representing the block number to be equal to the value stored in the page field.

20. The non-transitory computer-readable storage medium of claim 15, wherein determining that the fixed value is stored as the first bit and the second bit in the second set of bits comprises: The first value of the first bit in the second group of bits is identified and stored. Identify and store the second value of the second bit in the second group of bits; Compare the first value with the second value; and The first value and the second value are determined to be equal to the fixed value.

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