Techniques for retiring blocks of a memory system

Abstract

This application is directed to techniques for retiring a block of a memory system. In some examples, aspects of a memory system or memory device can be configured to determine an error of a block of memory cells. Upon determining that the error occurred, the memory system can identify one or more operating conditions associated with the block. For example, the memory system can determine a temperature of the block, a cycle count of the block, a number of times the block experienced an error, a bit error rate of the block, and / or a number of available blocks in a related system. Depending on whether criteria associated with the respective operating condition is satisfied, the block can be enabled or retired.

Description

[0001] Cross-referencing

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 648,396, filed January 19, 2022, entitled "Techniques for Retiring Blocks of a Memory System," and U.S. Provisional Patent Application No. 63 / 233,065, filed August 13, 2021, entitled "Techniques for Managing Temporarily Retired Blocks of an Memory System," each of which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to technologies for blocks used in decommissioned memory systems. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless periodically updated by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods even in the absence of an external power supply. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include a memory device comprising a memory cell block; and a controller coupled to the memory device and configured to cause the apparatus to: determine that at least one error has occurred in the memory cell block; identify one or more operating conditions associated with the memory cell block, at least in part based on the determination of the occurrence of the at least one error; determine whether to terminate the memory cell block, at least in part based on the determination of the occurrence of the at least one error and the identification of the one or more operating conditions associated with the memory cell block; and terminate the memory cell block, at least in part based on the memory cell block containing the at least one error and the one or more operating conditions associated with the memory cell block satisfying a criterion.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: determine that at least one error has occurred in a memory cell block of a memory system; identify one or more operating conditions associated with the memory cell block of the memory system, at least in part based on the determination of the occurrence of the at least one error; determine whether to terminate the memory cell block, at least in part based on the determination of the occurrence of the at least one error and the identification of the one or more operating conditions associated with the memory cell block of the memory system; and terminate the memory cell block, at least in part based on the memory cell block containing the at least one error and the satisfaction of a criterion by the one or more operating conditions associated with the memory cell block of the memory system.

[0008] A method is described. The method may include determining that at least one error has occurred in a memory cell block of the memory system; identifying one or more operating conditions associated with the memory cell block of the memory system, based at least in part on determining that at least one error has occurred; determining whether to terminate the memory cell block, based at least in part on determining that at least one error has occurred and identifying the one or more operating conditions associated with the memory cell block of the memory system; and terminating the memory cell block, based at least in part on the memory cell block containing the at least one error and the one or more operating conditions associated with the memory cell block of the memory system satisfying a criterion. Attached Figure Description

[0009] Figure 1 This document describes examples of systems that support techniques for decommissioning memory systems, based on the examples disclosed herein.

[0010] Figure 2 A block diagram illustrating a circuit that supports a technique for retiring memory systems, based on the examples disclosed herein.

[0011] Figure 3 Examples of process flowcharts illustrating the techniques for supporting the decommissioning of memory systems based on the examples disclosed herein.

[0012] Figure 4 A block diagram of a memory system is shown, illustrating a technique for using blocks in a decommissioned memory system, based on examples disclosed herein.

[0013] Figure 5 The flowchart illustrates one or more methods for supporting techniques for decommissioning memory systems, based on examples disclosed herein. Detailed Implementation

[0014] A memory system may include one or more memory devices, which comprise arrays of memory cells and circuitry operable to perform access operations on memory cells. Various structures of the memory devices (e.g., memory dies) may wear out or degrade over time, potentially leading to operational failures or other unreliable operations. Some memory systems or memory devices are configured to detect indications of unreliable or failed access operations and, in response to such detection, deactivate portions of the memory array. However, some techniques used to detect unreliable or failed access operations may be overly conservative and result in excessive waste of the memory array.

[0015] According to the examples disclosed herein, aspects of a memory system or memory device can be configured to determine that an error has occurred in a memory cell block. Upon detection of an error, the block can be immediately deactivated based on one or more operating conditions that meet certain criteria. In some cases, the determination to deactivate a block can be based on operating conditions that can be associated with the detection of one or more errors (e.g., simultaneous occurrence). Examples of operating conditions may include block temperature, block cycle count, number of errors experienced by the block, bit error rate of the block, and / or the number of available blocks in the associated system. Each operating condition can be associated with a corresponding criterion for deactivating the block. Thus, the associated memory system can deactivate blocks relatively more aggressively or less aggressively based on whether the operating conditions meet (or fail to meet) the corresponding criteria. Compared to other techniques for array deactivation, by implementing one or more aspects of temporarily deactivating blocks according to the examples disclosed herein, the memory device can be configured with greater capacity, less oversupply, or a longer lifetime, as well as other benefits or combinations thereof.

[0016] As per reference Figure 1 and 2 Features of this disclosure are described in the context of the systems, apparatus, and circuits described herein. (See references...) Figure 3 The features of this disclosure are described in the context of the process flowchart. References are also included. Figure 4 and 5 These and other features of this disclosure are further illustrated and described in the context of device diagrams and flowcharts of the technology for retiring memory systems.

[0017] Figure 1 This document describes an example of a system 100 that supports techniques for retiring blocks from a memory system, based on the examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0018] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0019] System 100 may be contained in a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capability, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or any other computing device containing memory and processing means.

[0020] System 100 may include a host system 105 that can be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations as described herein. The host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed via the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to the host system 105 or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0021] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise convey control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more of these interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110 or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0022] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, then the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0023] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations generally referred to as access operations at the memory device 130, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute these commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to implement the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses associated with the memory device 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0024] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0025] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0026] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed herein to the memory system controller 115.

[0027] Although Figure 1 The example of memory system 110 described herein includes memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, each located within memory device 130, to perform the functions attributed herein to memory system controller 115. Generally, one or more functions attributed herein to memory system controller 115 may, in some cases, be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130, at least partially managed by memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0028] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0029] In some instances, memory device 130 may (e.g., on the same die or within the same package) include a local controller 135, which can perform operations on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. For example, such as Figure 1 As described, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0030] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0031] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information; if configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity for supporting circuitry.

[0032] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, concurrent operations may occur within different planes 165. For example, memory cells within different blocks 170 can be operated on in parallel, as long as the different blocks 170 are located in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and virtual blocks 180 may refer to a group of blocks 170 within which parallel operations can occur. For example, blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d may be operated on in parallel, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual blocks 180. In some cases, a virtual block may contain blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory devices 130-a and 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be “block 0” of plane 165-a, block 170-b may be “block 0” of plane 165-b, etc.). In some cases, parallel operations in different planes 165 may be subject to one or more restrictions, such as parallel operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0033] In some cases, block 170 may contain memory cells organized in rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be referred to as a bit line) (e.g., coupled thereto).

[0034] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 may be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single programming or reading operation), and block 170 may be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Furthermore, in some cases, NAND memory cells may be erased before they can be rewritten with new data. Therefore, for example, in some cases, the used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0035] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, cleanup, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in block 170 to have invalid data in order to erase and reuse block 170, an algorithm called “garbage collection” may be invoked to allow block 170 to be erased and freed up as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting block 170 containing valid and invalid data, selecting pages 175 in the block containing valid data, copying the valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected pages 175 as invalid, and erasing the selected block 170. Therefore, the number of erased blocks 170 can be increased, allowing more blocks 170 to be used to store subsequent data (e.g., data subsequently received from the host system 105).

[0036] System 100 may include any number of non-transitory computer-readable media that support techniques for managing temporarily retired blocks of the memory system. For example, host system 105, memory system controller 115, or memory device 130 may include, or otherwise access, storage instructions (e.g., firmware) to perform one or more of the functions described herein that pertain to host system 105, memory system controller 115, or memory device 130. For example, such instructions, when executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0037] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0038] The memory system controller 115 can be configured to determine that an error has occurred on one or more blocks 170 of the memory cells. After determining an error on block 170, the memory system controller 115 can immediately identify one or more operating conditions associated with block 170. For example, the memory system controller 115 can determine the temperature of block 170 (or other components of the memory system), the cycle count of block 170, the number of times block 170 has experienced an error, the bit error rate of block 170, and / or the number of available blocks 170 in the memory system 110. Depending on whether criteria associated with the corresponding operating conditions are met, block 170 can be enabled or deactivated. Therefore, by determining whether corresponding criteria associated with one or more operating conditions are met, the memory system controller 115 can deactivate blocks 170 relatively more aggressively or less aggressively than deactivating blocks using only errors in the data. Thus, the memory system 110 can be configured with greater capacity, less oversupply, or a longer lifetime, among other benefits.

[0039] Figure 2 This document illustrates a block diagram of circuitry 200 supporting techniques for decommissioning blocks in a memory system, based on examples disclosed herein. Circuitry 200 may be included in memory system 110 and may include one or more components of memory device 130. For example, circuitry 200 illustrates an example of block 170-a comprising an array of memory cells 205. Each of the memory cells 205 may be located or otherwise accessed based on the intersection of word line 225 (e.g., WL) and bit line 235 (e.g., BL), which may each be referred to as an access line of block 170-a. Memory cells 205 along word line 225 may be examples of pages 175. Word line 225 and bit line 235 may be coupled to row decoder 220 and column decoder 230, respectively, for controlling various biasing or activation of the respective access lines. In some instances, row decoder 220 and column decoder 230 may be components of local controller 135, which may support access operations such as writing logical state to memory cell 205 or sensing logical state stored in memory cell 205, as well as other operations and their signaling. Row decoder 220 and column decoder 230 may be coupled to controller 240, which is configured to perform various techniques for topology-based decommissioning as disclosed herein. In various instances, controller 240 may be included in memory system controller 115, included in local controller 135, or distributed between memory system controller 115 and local controller 135, as well as other configurations.

[0040] Memory cell 205 may be arranged physically or electrically according to sub-blocks 210 (e.g., first sub-block 210-a and second sub-block 210-b). In some instances, each of the sub-blocks 210 may contain or refer to a subset of the word lines 225 of block 170 (e.g., sub-block 210-a contains or is associated with word lines WLa1 to WLam, and sub-block 210-b contains or is associated with word lines WLb1 to WLbm). Although block 170-a is shown as containing two sub-blocks 210, block 170 may contain any number of sub-blocks 210 according to the described technology (e.g., two, three, four, five, six, seven, eight, etc.). Alternatively, although sub-block 210 is described as each containing a corresponding subset of word lines 225 of block 170-a and all bit lines 235 of block 170-a, in some instances, sub-block 210 may each contain a corresponding subset of bit lines 235 of block 170 (e.g., and some or all of word lines 225 of block 170).

[0041] In some instances, one or more structures of circuit 200 (e.g., the structure of die 160) may wear out or degrade over time, which can lead to one or more physical defects. For example, circuit 200 illustrates an instance of defect 250-a, which may be associated at least with word line WLai and defect 250-b, which may be associated at least with bit line BLj. Defect 250 may refer to various forms of degradation or failure of one or more physical elements of circuit 200. For example, defect 250 may refer to short-circuit defects or other dielectric breakdowns (e.g., leakage paths), such as short circuits between access lines and the chassis or ground structure of die 160, short circuits between access lines and voltage sources (e.g., positive voltage sources, negative voltage sources), short circuits between first access lines and second access lines (e.g., between first word line 225 and second word line 225, between first bit line 235 and second bit line 235, between word line 225 and bit line 235), or short circuits between other structures of circuit 200. In some instances, defect 250 may refer to an open-circuit defect or other reduction or suppression of conductivity, such as an interruption of conductivity or a break in the conductive path of an access line or other reduction in cross-section. Examples of defects 250-a and 250-b are for illustrative purposes, and the circuit may produce any number of one or more defects 250 at various locations in the circuitry of the memory device 130, and defect 150 may affect any number of one or more access lines.

[0042] In some instances, defect 250 may cause an error in response to accessing memory cell 205 of block 170-a, and the error may include uncorrectable errors (e.g., if the number of errors exceeds the error correction capability of memory system 110 or memory device 130 including circuitry 200, if the errors are not due to a temporary condition). For example, if defect 250-a is an open-circuit defect, then defect 250-a may cause an error in response to accessing memory cell 205 along word line WLai downstream of defect 250-a (e.g., downstream of the line decoder, farther from line decoder 220 than defect 250-a), because the signal has not been transmitted through defect 250-a. Similarly, if defect 250-b is an open-circuit defect, then defect 250-b can cause an error in response to accessing memory cell 205 along bit line BLj downstream of defect 250-b (e.g., further from column decoder 230 than defect 250-b, relative to downstream of column decoder 230), because the signal is not transmitted through defect 250-b. In instances where defect 250 is a short circuit, dielectric breakdown, or leakage defect associated with the access line, such defect 250 can cause an error in response to accessing both memory cell 205 downstream of defect 250 and memory cell 205 upstream of defect 250 (e.g., causing voltage instability or charge leakage that typically affects signaling transmission on the access line).

[0043] In some instances, controller 240 may manage one or more mappings for tracking enabled blocks 170 and deactivated blocks 170 (e.g., permanently deactivated blocks 170). As used herein, an enabled block 170 may refer to any block 170 actively configured to store data. For example, data may be read from or written to an active block 170. A deactivated block 170 may refer to a block that is no longer configured to be accessed. For example, a block 170 may have experienced one or more errors (e.g., uncorrectable errors, uncorrectable error control code (ECC) errors) and may therefore no longer be able to reliably store data. These blocks 170 may be deactivated so that data may no longer be read from or written to them.

[0044] In other instances, controller 240 may manage any number of mappings used to track the state of block 170. For example, controller 240 may manage mappings for blocks 170 that have experienced different types of errors (e.g., uncorrectable errors, performance errors (e.g., relatively slow-performing blocks 170)), or mappings for blocks designated as having errors during factory testing.

[0045] Whether to retire block 170 can be based on the occurrence of an error and whether criteria associated with operating conditions are met. For example, some blocks 170 may experience errors that are transient in nature. Block 170 storing relatively old data may experience data retention problems that might not otherwise occur but may occur for data being stored in block 170 over a relatively long period of time. Similarly, some blocks 170 may experience temperature changes (e.g., as measured or detected by temperature sensor 245) or voltage changes (e.g., as measured or detected by voltage sensor 246), which may cause temporary (e.g., transient) errors that may not affect the long-term reliability of block 170. Therefore, if block 170 experiences an error, one or more operating conditions associated with block 170 can be identified and compared with corresponding criteria. If the criteria are met, then block 170 can be retired (e.g., the index associated with the block can be stored in a mapping used to track retired blocks 170). Conversely, if one or more of the criteria are not met, then block 170 may remain enabled (e.g., the index associated with the block may be stored or kept stored in a mapping used to track the enabled block 170).

[0046] In some instances, controller 240 may determine that an error has occurred in block 170-a (e.g., enabled block 170). Upon determining an error, controller 240 may immediately identify one or more operating conditions associated with block 170-a. As described herein, operating conditions for block 170-a may involve the temperature of block 170-a, the cycle count of block 170-a, the number of errors experienced by block 170-a, the bit error rate of block 170-a, and / or the number of available blocks 170 in memory system 110. Furthermore, each operating condition may be associated with a corresponding criterion for determining whether to deactivate block 170-a, and multiple operating conditions may be used to determine whether to deactivate block 170-a. For example, block 170-a may be deactivated if both the operating temperature and the cycle count meet a cycle count threshold, but remain enabled if neither of the two criteria is met.

[0047] By utilizing one or more operating conditions to determine whether to terminate block 170-a, memory system 110 may be able to terminate block 170 more aggressively or less aggressively. For example, block 170-a may undergo testing in which it is exposed to relatively high or low temperatures. Therefore, block 170-a may experience errors, but these errors, attributable to altered operating conditions (e.g., high or low temperature, to give an example), may be transient in nature. In some cases, a temperature threshold may be set such that if the operating temperature of block 170-a exceeds the temperature threshold, then the block may remain enabled. Alternatively, if the temperature threshold is not exceeded (e.g., if the operating temperature of block 170-a is relatively high but does not reach the threshold), then the error may be unexpected and may require terminating block 170-a.

[0048] Criteria for other operating conditions can be similarly configured to allow for more aggressive or less aggressive termination of block 170 based on various criteria. For example, criteria associated with the cycle count of block 170, the number of errors the block experiences, or the bit error rate of block 170 can be configured such that relatively low values ​​(e.g., relatively few accesses, relatively few errors, relatively low bit error rate) may not trigger the termination of block 170. Furthermore, block 170 may be terminated if the memory system 110 contains a relatively large number of available blocks, and may remain enabled if the memory system 110 contains a relatively small number of available blocks. Therefore, by determining whether appropriate criteria associated with one or more operating conditions are met, controller 240 can terminate block 170 relatively more aggressively or less aggressively. Thus, memory system 110 can be configured with larger capacity, less oversupply, or a longer lifetime, among other benefits.

[0049] Figure 3 This document illustrates an example of a process flowchart for a method 300 supporting a technique for retiring a block of a memory system, based on the examples disclosed herein. Aspects of method 300 may be implemented by a controller (e.g., memory system controller 115, local controller 135, controller 240) and other components. Alternatively, aspects of method 300 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to memory system 110 or memory device 130). For example, instructions may cause the controller to perform the operations of method 300 if executed by the controller.

[0050] In some instances, method 300 may begin (e.g., initiate) at 305 based on the determination of an error in block 170-a. For example, method 300 may begin in response to controller 240 determining an error condition, such as a read error (e.g., in block 170-a) determined during a process of normal operation (e.g., during a read operation performed in response to a read command from host system 105), media management operation (e.g., garbage collection operation, wear leveling operation), or other operation.

[0051] At 310, one or more operating conditions may be identified. As described herein, these operating conditions may include the temperature of block 170-a, the cycle count of block 170-a, the number of errors experienced by block 170-a, the bit error rate of block 170-a, or the number of available blocks 170-a in memory system 110. In some cases, multiple operating conditions may be used to determine whether to retire block 170-a. Therefore, at 310, controller 240 may identify each of the operating conditions used to determine whether to retire block 170-a. In other instances, controller 240 may identify additional operating conditions, although some operating conditions may be used to determine whether to retire block 170-a.

[0052] At 315, controller 240 can assign a score to block 170-a. In some instances, the score can be assigned based on a comparison of the identified operating conditions with corresponding thresholds. The score can be based on a comparison of the operating temperature of block 170-a, the cycle count of block 170-a, the number of errors experienced by block 170-a, the bit error rate of block 170-a, or the number of available blocks 170-a in the memory system with corresponding thresholds. In some cases, a weighted score can be assigned based on a different weighting value associated with each of the operating conditions.

[0053] For example, a relatively low operating temperature, a relatively high cycle count, a relatively large number of errors induced, a relatively high bit error rate, and a relatively low number of available blocks 170 in memory system 110 can result in a relatively high score. Conversely, a relatively high operating temperature, a relatively low cycle count, a relatively low number of errors induced, a relatively low bit error rate, and a relatively high number of available blocks 170 in memory system 110 can result in a relatively low score. This score can be used to determine whether to decommission block 170-a.

[0054] In some cases, the operating temperature of block 170 can be used to determine whether to terminate the block. For example, temperature sensor 245 can be used to determine the temperature of the block after an error has occurred. If the temperature of block 170 is relatively high (e.g., above a temperature threshold), then block 170 may not be terminated; however, if the temperature of block 170 is relatively low (e.g., below a temperature threshold), then block 170 may be terminated. In some instances, block 170 may not be terminated due to a relatively high (or relatively low) operating temperature, because said temperature may have caused the error. That is, the error may be transient in nature due to a relatively high or relatively low temperature. In some instances, the temperature threshold used to determine whether to terminate block 170 may be a configurable threshold. In some cases, the operating temperature of block 170 can be estimated by measuring the temperature in other locations of the memory system. For example, one or more temperature sensors in any location of the memory system can be used to determine the operating temperature.

[0055] Alternatively or concurrently, the cycle count of block 170 can be used to determine whether to retire the block. As described herein, a “cycle count” can refer to a single program-erase (P / E) operation performed on block 170. In some instances, the memory system’s controller 240 or another component (e.g., a counter) can track each P / E operation performed on the corresponding block 170. If the cycle count of block 170 is relatively high (e.g., above a cycle count threshold), then block 170 can be retired; however, if the cycle count of block 170 is relatively low (e.g., below a cycle count threshold), then block 170 may not be retired. In some instances, retiring block 170 may be attributable to a relatively high cycle count because block 170 tends to degrade after performing a relatively high number of P / E operations, thus making it more likely that the detected error is not transient in nature. In some instances, the cycle count threshold used to determine whether to retire block 170 can be a configurable threshold.

[0056] In other instances, the number of errors in block 170 can be used to determine whether to retire the block. In some instances, the memory system's controller 240 or another component (e.g., a counter) can track each time an error is detected in a corresponding block 170. If the number of errors in block 170 is relatively high (e.g., above an error threshold), then block 170 can be retired; however, if the number of errors in block 170 is relatively low (e.g., below the error threshold), then block 170 may not be retired. In some instances, the probability that errors are not transient in nature when a high number of errors occurs can lead to the retirement of block 170 due to the relatively high number of errors. In some instances, the error threshold used to determine whether to retire block 170 can be a configurable threshold.

[0057] In another instance, the bit error rate of block 170 can be used to determine whether to retire the block. In some instances, the memory system's controller 240 or another component (e.g., a counter) can track each time an error is detected in the corresponding block 170 over a duration. The controller 240 or the other component can calculate the bit error rate as the number of bit errors during said duration divided by the total number of bits transmitted. If the bit error rate of block 170 is relatively high (e.g., above an error rate threshold), then block 170 can be retired; however, if the bit error rate of block 170 is relatively low (e.g., below the error rate threshold), then block 170 may not be retired. In some instances, the probability that the error is not transient in nature when a high bit error rate occurs can lead to the retirement of block 170 due to the relatively high bit error rate. In some instances, the error threshold used to determine whether to retire block 170 can be a configurable threshold.

[0058] Alternatively, the number of available blocks 170 can be used to determine whether to retire a block. In some instances, the memory system's controller 240 or another component (e.g., a counter) may track the number of available blocks 170 at any given time. To meet certain performance benchmarks, the memory system may maintain a number of blocks available for performing operations requested by the host system. If the number of blocks falls below a threshold, the memory system may perform one or more memory management operations (e.g., garbage collection operations) to make more blocks available for host system operations. As described herein, some blocks may be retired and therefore unavailable, while other blocks may be (e.g., temporarily) unavailable due to the ongoing garbage collection operation on block 170. If the number of available blocks 170 is relatively high (e.g., above a threshold number of available blocks 170), then block 170 may be retired; however, if the number of available blocks 170 is relatively low (e.g., below a threshold number of available blocks 170), then block 170 may not be retired. In some instances, block 170 may be retired due to a relatively high number of available blocks, because the memory system may contain the necessary number of available blocks for subsequent operations (e.g., access operations). In some instances, the threshold number of available blocks 170 used to determine whether to retire block 170 may be a configurable threshold.

[0059] At 320, controller 240 may determine whether to terminate block 170-a based on whether the score meets a threshold. Controller 240 may compare the score with a threshold (e.g., a threshold score) to determine whether to terminate block 170-a. At 325, controller 240 may terminate block 170-a based on the score. In some instances, block 170-a may be terminated based on whether the score meets or fails to meet the threshold, which can be a design choice issue. At 330, controller 240 may determine not to terminate block 170-a based on the score (e.g., block 170-a may remain enabled). In such instances, block 170-a may remain enabled based on whether the score meets or fails to meet the threshold, which can be a design choice issue.

[0060] At 330, controller 240 may determine one or more criteria associated with the identified operating conditions. Controller 240 may determine criteria in cases where the score does not meet a threshold (e.g., at 320), or when the score is not used to determine whether to terminate block 170-a. By way of example, at 310, the controller may have identified the operating temperature of block 170-a. Therefore, at 330, controller 240 may determine that if the operating temperature of block 170-a is less than a threshold temperature value, then block 170-a is terminated, and if the operating temperature of block 170-a is greater than the threshold temperature value, then block 170-a is not terminated.

[0061] In some cases, other criteria associated with the operating conditions of block 170-a may be as follows.

[0062] If the number of access operations performed on block 170-a is greater than the threshold number of access operations, then block 170-a is terminated; if the number of access operations performed on block 170-a is less than the threshold number of access operations, then block 170-a is not terminated.

[0063] If block 170-a experiences the number of errors greater than the threshold number for a duration, then block 170-a is terminated; if block 170-a experiences the number of errors less than the threshold number for a duration, then block 170-a is not terminated.

[0064] If block 170-a is associated with a bit error rate greater than the threshold error rate, then block 170-a is deprecated; if block 170-a is associated with a bit error rate less than the threshold error rate, then block 170-a is not deprecated.

[0065] If the number of available blocks 170 in memory system 110 is greater than the threshold number of available blocks 170, then block 170-a is retired; and if the number of available blocks 170 in memory system 110 is less than the threshold number of available blocks 170, then block 170-a is not retired.

[0066] At 335, controller 240 may determine whether to terminate block 170-a based on whether determined criteria are met. Controller 240 may compare the identified operating conditions (e.g., metrics or values ​​associated with the operating conditions) with the determined corresponding criteria. At 340, controller 240 may terminate block 170-a based on the satisfaction of the criteria. In some cases, if multiple operating conditions are identified and multiple criteria are determined, each criterion may be satisfied to terminate the block. Using the example described herein, controller 240 may terminate block 170-a based on the operating temperature of block 170-a being less than a threshold temperature value.

[0067] At 345, controller 240 may not terminate block 170-a based on the failure to meet a criterion. For example, controller 240 may not terminate block 170-a based on its operating temperature being greater than a threshold temperature value. In this example, the error, attributed to the relatively high operating temperature of block 170-a, may be transient in nature, thus keeping block 170-a in the enabled state may be desirable. In some cases, if multiple operating conditions are identified and multiple criteria are determined, block 170-a may not be terminated if one or more of the criteria are not met.

[0068] At 350, controller 240 can determine a second error, a second operating condition, and a second criterion for block 170-a. For example, controller 240 can identify the second operating condition and determine the criterion associated with the second operating condition based on a second error experienced by block 170-a (e.g., a second error). The operating condition identified at 350 can be identified from the same set of operating conditions described above at 310, and the determined criterion can be the same as or different from the criterion described above at 330. In some cases, the second criterion can be different from the criterion described above at 330. For example, as described above: if the operating temperature of block 170-a is less than a threshold temperature value, then block 170-a is deactivated, and if the operating temperature of block 170-a is greater than the threshold temperature value, then block 170-a is not deactivated. However, at 350, the criterion can be changed to: if the operating temperature of block 170-a is greater than the threshold temperature value, then block 170-a is deactivated; and if the operating temperature of block 170-a is less than the threshold temperature value, then block 170-a is not deactivated. This criterion can be changed because in some cases, the reproduced error may be less likely to be transient in nature.

[0069] At 355, controller 240 may determine whether to terminate block 170-a based on whether the determined second criterion is met. Controller 240 may compare the identified operating conditions (e.g., metrics or values ​​associated with the operating conditions) with the determined corresponding second criterion. At 360, controller 240 may terminate block 170-a based on the satisfaction of the second criterion. In some cases, if multiple operating conditions are identified and multiple criteria are determined, then each criterion may be satisfied to terminate the block.

[0070] At 365, controller 240 may not terminate block 170-a based on the failure to meet criteria. In some cases, if multiple operating conditions are identified and multiple criteria are determined, block 170-a may not be terminated if one or more of the criteria are not met. Furthermore, controller 240 may continue to determine errors in block 170-a and may continue to determine whether to keep block 170-a enabled or terminate block 170-a, as described herein.

[0071] As described herein, multiple operating conditions and associated criteria can be used to determine whether to terminate block 170, which has caused an error. For example, block 170 may be terminated based on the satisfaction of a first criterion and a second criterion, while block 170 may not be terminated if either the first criterion or the second criterion is not satisfied.

[0072] In some cases, the operating temperature of block 170 can be a primary operating condition used in conjunction with other operating conditions to determine whether to terminate block 170. For example, the temperature of block 170 and the cycle count of block 170 can be used to determine whether to terminate block 170. Therefore, if the temperature of block 170 meets a temperature threshold and the number of access operations performed on block 170 meets a cycle count threshold, then block 170 can be terminated. If the temperature of block 170 does not meet the temperature threshold, if the number of access operations performed on the block does not meet the cycle count threshold, or both, then block 170 can not be terminated.

[0073] In another instance, the temperature of block 170 and the number of errors triggered by block 170 can be used to determine whether to decommission block 170. Therefore, if the temperature of block 170 meets a temperature threshold, and the number of errors during a duration (e.g., a configurable duration) meets an error threshold, then block 170 can be decommissioned. In some cases, controller 240 can track (e.g., count) the number of errors triggered by block 170. If the temperature of block 170 does not meet a temperature threshold, if the number of errors during the said duration does not meet an error threshold, or both, then block 170 may not be decommissioned.

[0074] In yet another instance, the temperature of block 170 and the bit error rate of block 170 can be used to determine whether to retire block 170. Therefore, if the temperature of block 170 meets a temperature threshold and the bit error rate of block 170 meets an error rate threshold, then block 170 can be retired. If the temperature of block 170 does not meet the temperature threshold, if the bit error rate does not meet the error rate threshold, or both, then block 170 can not be retired.

[0075] In yet another instance, the temperature of block 170 and the number of available blocks in memory system 110 can be used to determine whether to retire block 170. Therefore, if the temperature of block 170 meets a temperature threshold and the number of available blocks 170 in memory system 110 meets a threshold number of available blocks 170, then block 170 can be retired. If the temperature of block 170 does not meet the temperature threshold, or if the number of available blocks 170 in memory system 110 does not meet the threshold number of available blocks 170, or both, then block 170 may not be retired.

[0076] Alternatively, the number of available blocks in memory system 110 may be a primary operating condition used in conjunction with other operating conditions to determine whether to retire block 170. For example, the number of available blocks in memory system 110 and the cycle count of block 170 may be used to determine whether to retire block 170. Therefore, if the number of available blocks 170 in memory system 110 meets a threshold number of available blocks 170 and the number of access operations performed on block 170 meets a cycle count threshold, then block 170 may be retired. If the number of available blocks 170 in memory system 110 does not meet the threshold number of available blocks 170, if the number of access operations performed on block 170 does not meet the cycle count threshold, or both, then block 170 may not be retired.

[0077] In another example, the number of available blocks in memory system 110 and the number of errors triggered by block 170 can be used to determine whether block 170 should be retired. Therefore, if the number of available blocks 170 in memory system 110 meets a threshold number of available blocks 170 and the number of errors during a duration (e.g., a configurable duration) meets an error threshold, then block 170 can be retired. If the number of available blocks 170 in memory system 110 does not meet the threshold number of available blocks 170, if the number of errors during the duration does not meet an error threshold, or both, then block 170 may not be retired.

[0078] In another example, the number of available blocks in memory system 110 and the bit error rate of block 170 can be used to determine whether to retire block 170. Therefore, if the number of available blocks 170 in memory system 110 meets a threshold number of available blocks 170 and the bit error rate of block 170 meets an error rate threshold, then block 170 can be retired. If the number of available blocks 170 in memory system 110 does not meet the threshold number of available blocks 170, if the bit error rate does not meet the error rate threshold, or both, then block 170 may not be retired.

[0079] The aforementioned arrangement of the operating conditions and associated criteria used to determine whether to deactivate block 170 is for illustrative purposes only. Therefore, any combination or number of operating conditions and associated criteria can be used to keep block 170 enabled or deactivate it. The combination or number of operating conditions and associated criteria can be a design choice issue and can be selected based on the desired aggressiveness of deactivating block 170 and other criteria. Thus, by determining whether the corresponding criteria associated with one or more operating conditions are met, controller 240 can deactivate block 170 relatively more aggressively or less aggressively. Therefore, memory system 110 can be configured with larger capacity, less oversupply, or longer lifetime, and other benefits.

[0080] Figure 4A block diagram 400 illustrates a memory system 420 supporting techniques for retiring memory systems, according to examples disclosed herein. The memory system 420 may be as described in reference... Figures 1 to 3 Examples of aspects of the described memory system. Memory system 420 or its various components may be examples of means for performing various aspects of the techniques described herein for performing block decommissioning of a memory system. For example, memory system 420 may include a determining component 425, an identifying component 430, a block decommissioning component 435, a comparing component 440, a scoring and assigning component 445, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0081] The determining component 425 may be configured or otherwise support means for determining the occurrence of at least one error in a memory cell block of the memory system. In some instances, the determining component 425 may be configured or otherwise support means for determining the occurrence of at least one error in a second memory cell block of the memory system.

[0082] In some instances, to support the determination of whether to retire a memory cell block, the determining component 425 may be configured or otherwise supported to support means for determining whether the temperature of the memory cell block meets a temperature threshold. In some instances, to support the determination of whether to retire a memory cell block, the determining component 425 may be configured or otherwise supported to support means for determining whether the number of access operations performed on the memory cell block meets a cycle count threshold.

[0083] In some instances, to support the determination of whether to retire a memory cell block, the determining component 425 may be configured or otherwise supported to provide means for determining whether the number of errors in the memory cell block meets an error threshold over a given period of time. In some instances, to support the determination of whether to retire a memory cell block, the determining component 425 may be configured or otherwise supported to provide means for determining whether the bit error rate of the memory cell block meets an error rate threshold.

[0084] In some instances, determining component 425 may be configured or otherwise supported for means of determining whether to terminate a memory cell block, based at least in part on determining the occurrence of the at least one error and identifying one or more operating conditions associated with the memory cell block of the memory system. In some instances, to support the determination of whether to terminate a memory cell block, determining component 425 may be configured or otherwise supported for means of determining whether the number of available blocks of memory cells in the memory system meets a threshold number of available blocks.

[0085] In some instances, determining component 425 may be configured or otherwise supported as means for determining a second occurrence of at least one error in the second memory block of the memory system after preventing the termination of the second memory block. In some instances, determining component 425 may be configured or otherwise supported as means for determining the criterion based at least in part on identifying one or more operating conditions associated with the memory block of the memory system. In some instances, determining component 425 may be configured or otherwise supported as means for determining a third occurrence of at least one error in the memory block of the memory system.

[0086] The identification component 430 may be configured or otherwise supported to provide means for identifying one or more operating conditions associated with the memory cell block of the memory system, based at least in part on determining the occurrence of the at least one error. In some instances, the identification component 430 may be configured or otherwise supported to provide means for identifying a second set of operating conditions associated with the second memory cell block of the memory system, based at least in part on determining the occurrence of the at least one error in the second memory cell block. In some instances, the identification component 430 may be configured or otherwise supported to provide means for identifying a third operating condition associated with the memory cell block of the memory system, based at least in part on determining the occurrence of the at least one error.

[0087] Block termination component 435 may be configured or otherwise support means for terminating the memory cell block at least in part based on the memory cell block containing the at least one error and the satisfaction of one or more operating condition criteria associated with the memory cell block of the memory system. In some instances, block termination component 435 may be configured or otherwise support means for preventing the termination of the second memory cell block at least in part based on the failure of the second set of operating conditions associated with the memory cell block of the memory system to satisfy the second criterion.

[0088] In some instances, block retirement component 435 may be configured or otherwise support means for retiring the second memory cell block at least in part based on the occurrence of the second occurrence of the at least one error in the second memory cell block and the second set of operating conditions associated with the second memory cell block of the memory system satisfying the second criterion. In some instances, block retirement component 435 may be configured or otherwise support means for retiring the memory cell block at least in part based on the satisfaction of the criterion by one or more operating conditions associated with the memory cell block of the memory system and the satisfaction of the third operating condition by the third criterion.

[0089] In some instances, the block retirement component 435 may be configured or otherwise supported to prevent the retirement of the memory cell block based at least in part on the failure of one or more operating conditions associated with the memory cell block of the memory system to meet the criteria or the failure of the third operating condition to meet the criteria. In some instances, the block retirement component 435 may be configured or otherwise supported to retire the memory cell block based at least in part on the score assigned to the memory cell block of the memory system meeting a corresponding threshold.

[0090] In some instances, the comparison component 440 may be configured or otherwise supported as means for comparing the one or more operating conditions associated with the memory cell block of the memory system with the criteria, wherein determining whether to retire the memory cell block is based at least in part on comparing the one or more operating conditions associated with the memory cell block of the memory system with corresponding thresholds.

[0091] In some instances, the scoring assignment component 445 may be configured or otherwise support means for assigning scores to the memory cell blocks of the memory system based at least in part on identifying one or more operating conditions associated with the memory cell blocks of the memory system.

[0092] In some instances, the at least one error in the memory cell block of the memory system is a correctable error. In some instances, the one or more operating conditions associated with the memory cell block of the memory system include the temperature of the memory cell block, the cycle count of the memory cell block, the number of times the memory cell block has failed, the bit error rate of the memory cell block, or the number of available blocks in the memory system. In some instances, determining whether to retire the memory cell block is based at least in part on the one or more operating conditions of the memory cell block near the duration associated with identifying the at least one error.

[0093] Figure 5 A flowchart illustrating a method 500 for supporting techniques for retiring blocks of a memory system according to examples disclosed herein is shown. The operation of method 500 may be implemented by a memory system or its components as described herein. For example, the operation of method 500 may be implemented by reference to... Figures 1 to 4 The memory system described herein performs the functions described. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the functions described below. Alternatively, the memory system may use dedicated hardware to perform aspects of the functions described below.

[0094] At point 505, the method may include determining that at least one error has occurred in a memory cell block of the memory system. The operation at point 505 can be performed according to the examples disclosed herein. In some instances, it may be performed by reference... Figure 4 The described aspect is the determination of the component 425 performing the operation of 505.

[0095] At 510, the method may include identifying one or more operating conditions associated with a memory cell block of the memory system, based at least in part on determining that at least one error has occurred. The operation at 510 may be performed according to the examples disclosed herein. In some instances, it may be provided by reference... Figure 4 The described identification component 430 performs the operation of 510.

[0096] At 515, the method may include determining whether to terminate a memory cell block based at least in part on determining that at least one error has occurred and identifying one or more operating conditions associated with the memory cell block of the memory system. The operation at 515 may be performed according to the examples disclosed herein. In some instances, it may be performed by reference to... Figure 4 The described aspect is the determination of the component 425 performing the operation of 515.

[0097] At 520, the method may include retiring the memory cell block at least in part based on the memory cell block containing at least one error and one or more operating conditions associated with the memory cell block of the memory system satisfying criteria. The operation at 520 may be performed according to the examples disclosed herein. In some examples, it may be performed by reference to... Figure 4 The described block retirement component 435 performs the operation of 520.

[0098] In some instances, the device as described herein may perform one or more methods, such as method 500. The device may include features, circuitry, logic, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: determining that at least one error has occurred in a memory block of the memory system; identifying one or more operating conditions associated with the memory block of the memory system, at least in part based on determining that at least one error has occurred; determining whether to terminate the memory block, at least in part based on determining that at least one error has occurred and identifying the one or more operating conditions associated with the memory block of the memory system; and terminating the memory block, at least in part based on the memory block containing the at least one error and the one or more operating conditions associated with the memory block of the memory system satisfying a criterion.

[0099] Some examples of the methods 500 and apparatus described herein may additionally include operations, features, circuit systems, logic, means, or instructions for: determining the occurrence of at least one error in the second memory cell block of the memory system; identifying a second set of operating conditions associated with the second memory cell block of the memory system, based at least in part on the determination of the occurrence of the at least one error in the second memory cell block; and preventing the termination of the second memory cell block, based at least in part on the failure of the second set of operating conditions associated with the memory cell block of the memory system to meet a second criterion.

[0100] Some examples of the methods 500 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for: determining a second occurrence of at least one error in the second memory block of the memory system after preventing the termination of the second memory block; and terminating the second memory block at least in part based on the second occurrence of the second memory block containing the at least one error and the second set of operating conditions associated with the second memory block of the memory system satisfying the second criterion.

[0101] Some examples of the methods 500 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for: determining the criteria based at least in part on identifying one or more operating conditions associated with the memory cell block of the memory system; and comparing the one or more operating conditions associated with the memory cell block of the memory system with the criteria, wherein determining whether to deactivate the memory cell block may be based at least in part on comparing the one or more operating conditions associated with the memory cell block of the memory system with corresponding thresholds.

[0102] Some examples of the methods 500 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for: identifying a third operating condition associated with the memory cell block of the memory system, at least in part based on determining the occurrence of the at least one error; and deactivating the memory cell block, at least in part based on the one or more operating conditions associated with the memory cell block of the memory system satisfying the criterion and the third operating condition satisfying the third criterion.

[0103] Some examples of the methods 500 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for: determining a third occurrence of at least one error in the memory cell block of the memory system; and preventing the termination of the memory cell block based at least in part on the failure of one or more operating conditions associated with the memory cell block of the memory system to meet the criteria or the failure of the third operating condition to meet the criteria.

[0104] Some examples of the methods 500 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for: assigning a score to a memory cell block of the memory system based at least in part on identifying one or more operating conditions associated with the memory cell block of the memory system; and deactivating the memory cell block based at least in part on the score assigned to the memory cell block of the memory system satisfying a corresponding threshold.

[0105] In some instances of the method 500 and apparatus described herein, the at least one error in the memory cell block of the memory system may be a correctable error.

[0106] In some instances of the method 500 and apparatus described herein, the one or more operating conditions associated with the memory cell block of the memory system include the temperature of the memory cell block, the cycle count of the memory cell block, the number of times the memory cell block may have failed, the bit error rate of the memory cell block, or the number of available blocks in the memory system.

[0107] In some instances of the method 500 and apparatus described herein, determining whether to deactivate the memory cell block may include operations, features, circuitry, logic, means, or instructions for determining whether the temperature of the memory cell block meets a temperature threshold.

[0108] In some instances of the method 500 and apparatus described herein, determining whether to retire the memory cell block may include operations, features, circuitry, logic, means, or instructions for determining whether the number of access operations performed on the memory cell block satisfies a cycle count threshold.

[0109] In some instances of the method 500 and apparatus described herein, determining whether to deactivate the memory cell block may include operations, features, circuitry, logic, means, or instructions for determining whether the number of errors in the memory cell block meets an error threshold over a given period of time.

[0110] In some instances of the method 500 and apparatus described herein, determining whether to retire the memory cell block may include operations, features, circuitry, logic, means, or instructions for determining whether the bit error rate of the memory cell block meets an error rate threshold.

[0111] In some instances of the method 500 and apparatus described herein, determining whether to retire the memory cell block may include operations, features, circuitry, logic, means, or instructions for determining whether the number of available blocks of memory cells in the memory system meets a threshold number of available blocks.

[0112] Some examples of the methods 500 and devices described herein may additionally include operations, features, circuit systems, logic, means, or instructions for determining whether to terminate a memory cell block may be based at least in part on the one or more operating conditions of the memory cell block near the duration associated with identifying the at least one error.

[0113] It should be noted that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0114] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, a signal may represent a bus of signals, which may have various bit widths.

[0115] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled) if any conductive path exists between them that can support the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0116] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. If a component, such as a controller, couples other components together, then the component initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0117] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. If a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0118] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0119] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a preceding condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the preceding condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0120] Additionally, the terms "directly in response to" or "directly responding to" can refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) "directly in response to" or "directly responding to" such other condition or action.

[0121] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0122] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped, for example, degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or a channel. If the channel is n-type (i.e., the majority of charge carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "off" or "deactivated."

[0123] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0124] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral used to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0125] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions may also be physically located in various locations, including distributed configurations such that portions of the functions are implemented in different physical locations.

[0126] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0127] As used herein, the word "or," as used in the claims, such as in a list of items (e.g., a list followed by phrases such as "at least one of..." or "one or more of..."), indicates a list containing endpoints such that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0128] Computer-readable media includes both non-transitory computer-readable storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital video discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0129] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: A memory device comprising a block of memory cells; and A controller, coupled to the memory device and configured to cause the device to: Determine the occurrence of at least one error in the memory cell block; Based at least in part on determining the occurrence of the at least one error, multiple operating conditions associated with the memory cell block are identified; Weighted scores are assigned to the memory cell block based at least in part on different weighted values ​​associated with each of the plurality of operating conditions associated with the memory cell block; Whether to retire the memory cell block is determined at least in part based on the failure of the weighted score to meet the threshold; The memory cell block is prevented from being decommissioned, at least in part, based on the fact that the weighted score assigned to the memory cell block fails to meet the threshold. Whether to retire the memory cell block is determined at least in part based on the criteria for satisfying the plurality of operating conditions associated with the memory cell block; The memory cell block is decommissioned at least in part based on the fact that the weighted score assigned to the memory cell block fails to meet the threshold and that the plurality of operating conditions associated with the memory cell block meet the criteria.

2. The device according to claim 1, further comprising: A second memory cell block, distinct from the memory cell block, wherein the controller is configured to cause the device to: Determine the occurrence of at least one error in the second memory cell block; A second set of operating conditions associated with the second memory cell block is identified, at least in part, based on the determination of the occurrence of the at least one error in the second memory cell block; The second memory cell block is prevented from being decommissioned, at least in part, because the second set of operating conditions associated with the second memory cell block fails to meet the second criterion.

3. The device of claim 2, wherein the controller is configured to cause the device to: After preventing the termination of the second memory cell block, a second occurrence of at least one error in the second memory cell block is determined; and The second memory cell block is decommissioned at least in part based on the second occurrence of the at least one error contained in the second memory cell block and the second set of operating conditions associated with the second memory cell block satisfying the second criterion.

4. The device of claim 1, wherein the controller is configured to cause the device to: The criteria are determined at least in part based on identifying the plurality of operating conditions associated with the memory cell block; and The plurality of operating conditions associated with the memory cell block are compared with the criteria, wherein determining whether to retire the memory cell block is based at least in part on comparing the plurality of operating conditions associated with the memory cell block with corresponding thresholds.

5. The device of claim 1, wherein the controller is configured to cause the device to: Based at least in part on determining the occurrence of the at least one error, a third operating condition associated with the memory cell block is identified, the third operating condition being different from the plurality of operating conditions; and The memory cell block is deactivated at least in part based on the fact that the plurality of operating conditions associated with the memory cell block satisfy the criteria and the fact that the third operating condition satisfies the third criterion.

6. The device of claim 5, wherein the controller is configured to cause the device to: A third occurrence of at least one error in the memory cell block is determined; The memory cell block is prevented from being decommissioned, at least in part, based on the failure of the plurality of operating conditions associated with the memory cell block to meet the criteria or the failure of the third operating condition to meet the criteria.

7. The device of claim 1, wherein the at least one error in the memory cell block is a correctable error.

8. The device of claim 1, wherein the plurality of operating conditions associated with the memory cell block include the temperature of the memory cell block, the cycle count of the memory cell block, the number of times the memory cell block has failed, the bit error rate of the memory cell block, or the number of available blocks.

9. The device of claim 1, wherein determining whether to retire the memory cell block comprises: Determine whether the temperature of the memory cell block meets the temperature threshold.

10. The device of claim 1, wherein determining whether to retire the memory cell block comprises: Determine whether the number of access operations performed on the memory cell block meets the cycle count threshold.

11. The device of claim 1, wherein determining whether to retire the memory cell block comprises: Determine whether the number of errors in the memory cell block during a given period of time meets an error threshold.

12. The device of claim 1, wherein determining whether to retire the memory cell block comprises: Determine whether the bit error rate of the memory cell block meets the error rate threshold.

13. The device of claim 1, wherein determining whether to retire the memory cell block comprises: Determine whether the number of available blocks in the memory cell meets the threshold number of available blocks.

14. The device of claim 1, wherein determining whether to retire the memory cell block is based at least in part on the plurality of operating conditions of the memory cell block in the vicinity of the duration associated with identifying the at least one error.

15. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: Determine the occurrence of at least one error in a memory cell block of the memory system; Based at least in part on determining the occurrence of the at least one error, multiple operating conditions associated with the memory cell block of the memory system are identified; Weighted scores are assigned to the memory cell block based at least in part on different weighted values ​​associated with each of the plurality of operating conditions associated with the memory cell block; Whether to retire the memory cell block is determined at least in part based on the failure of the weighted score to meet the threshold; The memory cell block is prevented from being decommissioned, at least in part, based on the fact that the weighted score assigned to the memory cell block fails to meet the threshold. Whether to retire the memory cell block is determined at least in part based on the criteria for satisfying the plurality of operating conditions associated with the memory cell block; and The memory cell block is decommissioned at least in part based on the fact that the weighted score assigned to the memory cell block fails to meet the threshold and that the plurality of operating conditions associated with the memory cell block of the memory system meet the criteria.

16. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the electronic device, cause the electronic device to: Determine the occurrence of at least one error in a second memory cell block of the memory system, the second memory cell block being different from the memory cell block; A second set of operating conditions associated with the second memory cell block of the memory system is identified, at least in part, based on the determination of the occurrence of the at least one error in the second memory cell block; The second memory cell block is prevented from being decommissioned, at least in part, based on the fact that the second set of operating conditions associated with the second memory cell block of the memory system fails to meet the second criterion.

17. The non-transitory computer-readable medium of claim 16, wherein the instructions, when executed by the processor of the electronic device, cause the electronic device to: After preventing the termination of the second memory cell block, a second occurrence of at least one error in the second memory cell block of the memory system is determined; and The second memory cell block is decommissioned at least in part based on the second occurrence of the at least one error contained in the second memory cell block and the second set of operating conditions associated with the second memory cell block of the memory system satisfying the second criterion.

18. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the electronic device, cause the electronic device to: The criteria are determined at least in part based on identifying the plurality of operating conditions associated with the memory cell blocks of the memory system; and The plurality of operating conditions associated with the memory cell block of the memory system are compared with the criteria, wherein determining whether to retire the memory cell block is based at least in part on comparing the plurality of operating conditions associated with the memory cell block of the memory system with corresponding thresholds.

19. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the electronic device, cause the electronic device to: Based at least in part on determining the occurrence of the at least one error, a third operating condition associated with the memory cell block of the memory system is identified, the third operating condition being different from the plurality of operating conditions; and The memory cell block is deactivated at least in part based on the fact that the plurality of operating conditions associated with the memory cell block of the memory system satisfy the criteria and the fact that the third operating condition satisfies the third criterion.

20. The non-transitory computer-readable medium of claim 19, wherein the instructions, when executed by the processor of the electronic device, cause the electronic device to: A third occurrence of at least one error in the memory cell block of the memory system is determined; The memory cell block is prevented from being decommissioned, at least in part, based on the failure of the plurality of operating conditions associated with the memory cell block of the memory system to meet the criteria or the failure of the third operating condition to meet the criteria.

21. The non-transitory computer-readable medium of claim 15, wherein the at least one error in the memory cell block of the memory system is a correctable error.

22. The non-transitory computer-readable medium of claim 15, wherein the plurality of operating conditions associated with the memory cell block of the memory system include the temperature of the memory cell block, the cycle count of the memory cell block, the number of times the memory cell block has failed, the bit error rate of the memory cell block, or the number of available blocks in the memory system.

23. A method executed by a memory system, the method comprising: Determine the occurrence of at least one error in a memory cell block of the memory system; Based at least in part on determining the occurrence of the at least one error, multiple operating conditions associated with the memory cell block of the memory system are identified; Weighted scores are assigned to the memory cell block based at least in part on different weighted values ​​associated with each of the plurality of operating conditions associated with the memory cell block; Whether to retire the memory cell block is determined at least in part based on the failure of the weighted score to meet the threshold; The memory cell block is prevented from being decommissioned, at least in part, based on the fact that the weighted score assigned to the memory cell block fails to meet the threshold. Whether to retire the memory cell block is determined at least in part based on the criteria for satisfying the plurality of operating conditions associated with the memory cell block; and The memory cell block is decommissioned at least in part based on the fact that the weighted score assigned to the memory cell block fails to meet the threshold and that the plurality of operating conditions associated with the memory cell block of the memory system meet the criteria.

24. The method of claim 23, further comprising: Determine the occurrence of at least one error in a second memory cell block of the memory system, the second memory cell block being different from the memory cell block; A second set of operating conditions associated with the second memory cell block of the memory system is identified, at least in part, based on the determination of the occurrence of the at least one error in the second memory cell block; The second memory cell block is prevented from being decommissioned, at least in part, based on the fact that the second set of operating conditions associated with the second memory cell block of the memory system fails to meet the second criterion.

25. The method of claim 23, further comprising: The criteria are determined at least in part based on identifying the plurality of operating conditions associated with the memory cell blocks of the memory system; and The plurality of operating conditions associated with the memory cell block of the memory system are compared with the criteria, wherein determining whether to retire the memory cell block is based at least in part on comparing the plurality of operating conditions associated with the memory cell block of the memory system with corresponding thresholds.

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