Optimization method for color image mean preprocessing

Abstract

The application provides an optimization method for color image mean value preprocessing, aiming at RGB color images, 64*3 image data are loaded each time, 16 8-bit data are loaded in a register, 12 variable registers are used; then the loaded register data are converted into 16 bits, 6 intermediate conversion registers are added to convert 3 variable registers, 3 registers are used for 16-bit data accumulation, after accumulation, the rest of the variable register data are converted and accumulated; when the 3 registers are accumulated to 256 times, the data is right shifted by 8 bits, which is equivalent to dividing by 256, then 3 new registers are used to accumulate the 3 registers after shifting, the 3 registers are initialized to 0 and then re-accumulate the new data; then the 3 new registers are used to accumulate the 3 registers after shifting, when accumulated to 256 times, the result is saved to three arrays; the array data is accumulated again, and the mean value of each channel of RGB is calculated. The speed is improved.

Description

Technical Field

[0001] This invention relates to the field of image processing technology, and in particular to an optimized method for preprocessing the mean of color images. Background Technology

[0002] In existing image processing technologies, images are processed in two ways: grayscale and color. Because color images differ from grayscale images, methods used for grayscale images cannot be used for color images. Similarly, the processing methods for color images differ from those for grayscale images. Accumulation and averaging are frequently used in processing, but ordinary summation and averaging are very slow. For example, with chips like the Beijing Junzheng T30 and T31, the speed of averaging calculations slows down the overall processing speed. This increased time leads to a greater overall processing time. Using ordinary one-by-one accumulation can be understood as a C implementation, but generally, SIMD instructions cannot achieve continuous accumulation, and there is no corresponding SIMD implementation method. For color image accumulation, data from the same channel is usually accumulated, skipping steps. SIMD implementation is more difficult and lacks the ability to perform skipped accumulation.

[0003] In addition, the following are commonly used terms in the prior art:

[0004] 1. Mean: The mean generally refers to the average. The mean, a statistical term, is a measure of central tendency in a set of data. It is calculated by summing all the data points in a set and dividing by the number of data points. It is an indicator reflecting the central tendency of data. The key to solving word problems involving the mean is determining the "total quantity" and the total number of parts corresponding to that total quantity.

[0005] 2. RGB color image: An image with three channels, where the three pixels are stored in RGB order.

[0006] 3. SIMD (Single Instruction Multiple Data) instructions are a type of instruction that performs calculations using a vector-based approach. This means that a single instruction can execute multiple data streams, which can significantly improve program speed. A SIMD instruction can be understood as executing one instruction to perform an operation on an array of a specified size. In a 128-bit SIMD instruction, the array size is defined in 128 bits, storing 16 eight-bit data elements, 4 three-bit data elements, or 8 sixteen-bit data elements. For example, adding two arrays can be done directly with a single SIMD instruction. Summary of the Invention

[0007] To address the problems in the prior art, the purpose of this application is to improve the speed of averaging calculations, achieving a 40-fold improvement.

[0008] Specifically, this invention provides an optimized method for color image mean preprocessing. For RGB color images, the method loads 64*3 image data points each time, with one register loading 16 8-bit data points. It uses 12 variable registers: vrdr0, vrdg0, vrdb0, vrdr1, vrdg1, vrdb1, vrdr2, vrdg2, vrdb2, vrdr3, vrdg3, and vrdb3. The loaded register data is then converted to 16 bits, with 6 intermediate conversion registers added: vrd_r0, vrd_r1, vrd_g0, vrdg3, vrdb3. rd_g1, vrd_b0, vrd_b1, convert vrdr0, vrdg0, vrdb0 to vrd_r0, vrd_r1, vrd_g0, vrd_g1, vrd_b0, vrd_b1, using three registers sum_hr0, sum_hg0, sum_hb0 for 16-bit data accumulation. After accumulation, vrdr1, vrdg1, vrdb1, vrdr2, vrdg2, vrdb2, vrdr3, vrdg3, vrdb3 are converted and accumulated again; when sum_hr0, sum_hg0 When sum_hb0 accumulates 256 times, the data is right-shifted by 8 bits (equivalent to dividing by 256). Then, the shifted sum_hr0, sum_hg0, and sum_hb0 are accumulated using the three registers sum_hr1, sum_hg1, and sum_hb1, while sum_hr0, sum_hg0, and sum_hb0 are initialized to 0 before the newly loaded data is re-accumulated. The shifted sum_hr0, sum_hg1, and sum_hb0 are accumulated using sum_hr1, sum_hg1, and sum_hb1. When sum_hr1, sum_hg1, and sum_hb1 accumulate 256 times, the results of sum_hr1, sum_hg1, and sum_hb1 are saved into three arrays. Finally, the data in the three arrays are accumulated again, and the average value of each RGB channel is calculated.

[0009] The method further includes:

[0010] S1, Initialization and Register Declarations for Used Variables:

[0011] Let vri0 be the select register that converts the first 8 data in the 8-bit register into a 16-bit select register, and vri1 be the select register that converts the last 8 data in the 8-bit register into a 16-bit select register.

[0012] The preprocessed data is indata, with width and height, and the total number of data is piel_count = width * height;

[0013] Let a dataset be vsave[3][8], a regular temporary variable sum_intr, sum_intg, sum_intb with mean values ​​of avgr, avgg, avgb, and a calculator count to count the cumulative sums of sum_hr1, sum_hg1, and sum_hb1, initially set to 0;

[0014] S2, load 64*3 image data into vrdr0,vrdg0,vrdb0,vrdr1,vrdg1,vrdb1,vrdr2,vrdg2,vrdb2,vrdr3,vrdg3,vrdb3, and then change the indata pointer, i.e., indata = indata + 64*3.

[0015] S3. Using a pre-defined selection order, the data is converted from 8 bits to 16 bits. This involves setting two selection registers, vri0 and vri1, with the specific selection order pre-designed. The registers for converting to 16 bits are vrd_r1, vrd_r0, vrd_g1, vrd_g0, vrd_b1, and vrd_b0. Three registers, sum_hr0, sum_hg0, and sum_hb0, are used to accumulate the 16-bit data vrd_r1, vrd_r0, vrd_g1, vrd_g0, vrd_b1, and vrd_b0. After accumulation, vrdr1, vrdg1, vrdb1, vrdr2, vrdg2, vrdb2, vrdr3, vrdg3, and vrdb3 are converted to 16 bits again and accumulated. During the first accumulation and initialization, the data in sum_hr0, sum_hg0, and sum_hb0 are 0.

[0016] S4. Repeat steps S2 and S3 until the loop count reaches 256. Then, shift the values ​​of sum_hr0, sum_hg0, and sum_hb0, and add the processed results to sum_hr1, sum_hg1, and sum_hb1. Finally, set the values ​​of sum_hr0, sum_hg0, and sum_hb0 to 0, and increment count by 1.

[0017] S5. Repeat steps S2, S3, and S4 until the loop reaches 256 times. Save sum_hr1, sum_hg1, and sum_hb1 to vsave[0][8], vsave[1][8], and vsave[2][8]. Sum the data in vsave to sum_intr, sum_intg, and sum_intb. Set the data in sum_hr1, sum_hg1, and sum_hb1 to 0. Repeat steps S2, S3, and S4 until all data has been calculated.

[0018] S6, save sum_hr1, sum_hg1, sum_hb1 to vsave[0][8], vsave[1][8], vsave[2][8], and sum the data in vsave to sum_intr, sum_intg, sum_intb. The number of times the sum is accumulated is count;

[0019] S7, Calculate the mean: sum by the number of times the sum is accumulated.

[0020] The method is applied to chips with SIMD instructions, and optimizes the corresponding instruction set. The target image to be processed is a multiple of 2048 in length and width. The image mean preprocessing requires a precision error of less than 1. The corresponding instruction set used includes addition instructions, shift instructions, arbitrary value extraction instructions, division instructions, data loading instructions, and data saving instructions.

[0021] The overall method or core idea of ​​this application can be implemented on a chip with SIMD instructions, but there will be some differences in details. Some instructions may be missing, or some instructions that require two implementations can be implemented on other chips using a single instruction. The instructions will differ from chip to chip. Normal addition, subtraction, multiplication, and shifting are generally the same, but specific chips will have instructions with unique functions. Therefore, the specific chip for the application will be specified.

[0022] The method is applied to Beijing Junzheng T30 and T31 chips.

[0023] The addition instruction, shift instruction, arbitrary value fetching instruction, division instruction, data loading instruction, and data saving instruction are as follows:

[0024] a) Addition instruction:

[0025] vrd=ingenic_add_h(vrs,vrt);

[0026] The input variables are vrs and vrt, and the output variable is vrd; vrd stores 8 int16_t data, and vrs and vrt store 8 int16_t data.

[0027] Equivalent operations:

[0028] vrd0:=vrs0+vrt0;

[0029] vrd1:=vrs1+vrt1;

[0030] ...

[0031] vrd7:=vrs7+vrt7;

[0032] b) Shift instruction: Shifts each element in the variable by i bits;

[0033] Left shift instruction

[0034] vrd=ingenic_shift_left(vrs,i)

[0035] Right shift instruction

[0036] vrd=ingenic_shift_right(vrs,i);

[0037] c) Arbitrary value selection instruction: Selects 4, 8, or 16 data points from variables vrs and vrt according to the numbers set by vri. When using this instruction, a permanent register vri is required to select the data at a specific location.

[0038] vrd=ingenic_choise_h(vrs,vrt,vri);

[0039] d) Division instruction:

[0040] vrd=ingenic_div_d(vrs,vrt);

[0041] The input variables are vrs and vrt, and the output variable is the vrd register; vrd stores 16 int8_t data, and vrs and vrt store 16 int8_t data; the result is rounded.

[0042] Equivalent operations:

[0043] vrd0:=vrs0 / vrt0;

[0044] vrd1:=vrs1 / vrt1;

[0045] ...

[0046] vrd7:=vrs7 / vrt7;

[0047] ...

[0048] Vrd15: = vrs15 / vrt15;

[0049] e) Load Data Instruction: The input is the data to be loaded, currently a pointer to the data, indata. Starting from the memory location m pointed to by indata, 128 bits of data are loaded. If the data is 8 bits, 16 bits are loaded; if it's 16 bits, 8 bits are loaded; if it's 32 bits, 4 bits are loaded. The data is loaded into the variable vrd register; where m is calculated in bytes, i.e., 8 bits per unit.

[0050] vrd=ingenic_load(indata,m);

[0051] f) Save data instruction: The register variable vrd contains the data to be saved, and the pointer savedata stores the data. The data in the register is stored starting from the pointer position. The 128 bits of data in vrd are stored into savedata.

[0052] ingenic_save(vrd,savedata,m).

[0053] In step S2, the indata pointer is modified, further including a data loading instruction: the data to be loaded is the data pointed to by the indata pointer. Starting from positions 0, 16, ..., 160, 176 pointed to by the indata pointer, 128 bits of data are loaded sequentially. If it is 8 bits of data, 16 bits are loaded; if it is 16 bits of data, 8 bits are loaded; if it is 32 bits, 4 bits are loaded. The data is loaded into the variable vrdri, vrdgi, vrdbi registers, where i = 0, 1, 2, 3, represented as:

[0054] vrdr0=ingenic_load(indata, 0)

[0055] vrdg0=ingenic_load(indata, 16)

[0056] vrdb0=ingenic_load(indata, 32)

[0057] vrdr1=ingenic_load(indata, 48)

[0058] vrdg1=ingenic_load(indata, 64)

[0059] vrdb1=ingenic_load(indata, 80)

[0060] vrdr2=ingenic_load(indata, 96)

[0061] vrdg2=ingenic_load(indata, 112)

[0062] vrdb2=ingenic_load(indata, 128)

[0063] vrdr3=ingenic_load(indata, 144)

[0064] vrdg3=ingenic_load(indata, 160)

[0065] vrdb3=ingenic_load(indata, 176)

[0066] indata = indata + 64 * 3.

[0067] Step S3 further includes an arbitrary value selection instruction: selecting 4, 8, or 16 data points from variables vrdrm and vrdrn, vrdgm and vrdgn, vrdbm and vrdbn according to the numbers set by vrij, and outputting vrd_r1, vrd_r0, vrd_g1, vrd_g0, vrd_b1, and vrd_b0 respectively; it also includes an addition instruction, with input variables sum_hr0, sum_hg0, and sum_hr0, and the output of the arbitrary value selection instruction, with output variables sum_hr0, sum_hg0, and sum_hr0 respectively; where m and n are 0, 1, 2, and 3 respectively, and j is 1 and 0 respectively.

[0068] vrd_r1=ingenic_choise_h(vrdr0,vrdr0,vri1)

[0069] vrd_r0=ingenic_choise_h(vrdr0,vrdr0,vri0)

[0070] vrd_g1=ingenic_choise_h(vrdg0,vrdg0,vri1)

[0071] vrd_g0=ingenic_choise_h(vrdg0,vrdg0,vri0)

[0072] vrd_b1=ingenic_choise_h(vrdb0,vrdb0,vri1)

[0073] vrd_b0=ingenic_choose_h(vrdb0,vrdb0,vri0)

[0074] sum_hr0=ingenic_add_h(sum_hr0,vrd_r0);

[0075] sum_hr0=ingenic_add_h(sum_hr0,vrd_r1);

[0076] sum_hg0=ingenic_add_h(sum_hg0,vgd_g0);

[0077] sum_hg0=ingenic_add_h(sum_hg0,vgd_g1);

[0078] sum_hb0=ingenic_add_h(sum_hb0,vgd_b0);

[0079] sum_hb0=ingenic_add_h(sum_hb0,vgd_b1);

[0080] ……

[0081] vrd_r1=ingenic_choose_h(vrdr3,vrdr3,vri1)

[0082] vrd_r0=ingenic_choose_h(vrdr3,vrdr3,vri0)

[0083] vrd_g1=ingenic_choose_h(vrdg3,vrdg3,vri1)

[0084] vrd_g0=ingenic_choose_h(vrdg3,vrdg3,vri0)

[0085] vrd_b1=ingenic_choose_h(vrdb3,vrdb3,vri1)

[0086] vrd_b0=ingenic_choose_h(vrdb3,vrdb3,vri0)

[0087] sum_hr0=ingenic_add_h(sum_hr0,vrd_r0);

[0088] sum_hr0=ingenic_add_h(sum_hr0,vrd_r1);

[0089] sum_hg0=ingenic_add_h(sum_hg0,vgd_g0);

[0090] sum_hg0=ingenic_add_h(sum_hg0,vgd_g1);

[0091] sum_hb0=ingenic_add_h(sum_hb0,vgd_b0);

[0092] sum_hb0=ingenic_add_h(sum_hb0,vgd_b1).

[0093] Step S4 further includes a right shift instruction, which shifts each element in sum_hr0, sum_hg0, and sum_hb0 to the right by 8 bits, and then increments count by 1.

[0094] sum_hr1=ingenic_shift_right(sum_hr0,8)

[0095] sum_hg1=ingenic_shift_right(sum_hg0,8)

[0096] sum_hb1=ingenic_shift_right(sum_hb0,8)

[0097] count += 1.

[0098] Step S7 further includes:

[0099] avgr = sum_intr / count;

[0100] avgg = sum_intg / count;

[0101] avgb = sum_intb / count.

[0102] Therefore, the advantage of this application lies in providing a method for calculating the average value of RGB color images. When used on Beijing Junzheng T30 and T31 chips, the method optimizes the processing using the corresponding instruction sets of the T30 and T31 chips, achieving a 40-fold speed improvement. The target image is a multiple of 2048 pixels in length and width, and the required precision error for image averaging preprocessing is within 1, meeting the requirements of practical applications. Attached Figure Description

[0103] The accompanying drawings, which are provided to further illustrate the invention and form part of this application, are not intended to limit the scope of the invention.

[0104] Figure 1 This is a flowchart of the method of the present invention. Detailed Implementation

[0105] To better understand the technical content and advantages of the present invention, the present invention will now be described in further detail with reference to the accompanying drawings.

[0106] The specific implementation is carried out on the Beijing Junzheng T30 / T31 chip, and the method of this application is reproduced on this chip. The idea of ​​the processing method can be used on any chip with SIMD instructions.

[0107] Because color images use an RGBBRGBRGBRGB... storage format, calculating the mean involves calculating the individual mean values ​​of r, g, and b. Direct summation is not feasible in this case; therefore, grayscale image processing methods cannot be used to process color images. The number of registers used for color image processing must be a multiple of 3 due to RGB values. Therefore, 12 registers are used to load data. Since there are only 32 registers available, registers are needed for intermediate processing, result storage, and there are also permanently occupied registers. Therefore, the design aims to utilize all registers to the maximum extent possible. Since the initial load requires at least 12 registers, any further increases must be multiples of 12. Even when using 24 registers, some registers must be reserved for other uses, exceeding 32. Therefore, 12 registers were chosen for the initial data loading. Furthermore, the initial load cannot be reduced; at least 12 registers are required. Therefore, 12 registers were selected.

[0108] like Figure 1 As shown, this invention relates to an optimization method for color image mean preprocessing, the method comprising:

[0109] S1, Initialization and Register Declarations for Used Variables:

[0110] Let vri0 be the select register that converts the first 8 data in the 8-bit register into a 16-bit select register, and vri1 be the select register that converts the last 8 data in the 8-bit register into a 16-bit select register.

[0111] The preprocessed data is indata, with width and height, and the total number of data is piel_count = width * height;

[0112] Let a dataset be vsave[3][8], a regular temporary variable sum_intr, sum_intg, sum_intb with mean values ​​of avgr, avgg, avgb, and a calculator count to count the cumulative sums of sum_hr1, sum_hg1, and sum_hb1, initially set to 0;

[0113] S2, load 64*3 image data into vrdr0,vrdg0,vrdb0,vrdr1,vrdg1,vrdb1,vrdr2,vrdg2,vrdb2,vrdr3,vrdg3,vrdb3, and then change the indata pointer, i.e., indata = indata + 64*3.

[0114] S3. Using a pre-defined selection order, the data is converted from 8 bits to 16 bits. This involves setting two selection registers, vri0 and vri1, with the specific selection order pre-designed. The registers for converting to 16 bits are vrd_r1, vrd_r0, vrd_g1, vrd_g0, vrd_b1, and vrd_b0. Three registers, sum_hr0, sum_hg0, and sum_hb0, are used to accumulate the 16-bit data vrd_r1, vrd_r0, vrd_g1, vrd_g0, vrd_b1, and vrd_b0. After accumulation, vrdr1, vrdg1, vrdb1, vrdr2, vrdg2, vrdb2, vrdr3, vrdg3, and vrdb3 are converted to 16 bits again and accumulated. During the first accumulation and initialization, the data in sum_hr0, sum_hg0, and sum_hb0 are 0.

[0115] S4. Repeat steps S2 and S3 until the loop count reaches 256. Then, shift the values ​​of sum_hr0, sum_hg0, and sum_hb0, and add the processed results to sum_hr1, sum_hg1, and sum_hb1. Finally, set the values ​​of sum_hr0, sum_hg0, and sum_hb0 to 0, and increment count by 1.

[0116] S5. Repeat steps S2, S3, and S4 until the loop reaches 256 times. Save sum_hr1, sum_hg1, and sum_hb1 to vsave[0][8], vsave[1][8], and vsave[2][8]. Sum the data in vsave to sum_intr, sum_intg, and sum_intb. Set the data in sum_hr1, sum_hg1, and sum_hb1 to 0. Repeat steps S2, S3, and S4 until all data has been calculated.

[0117] S6, save sum_hr1, sum_hg1, sum_hb1 to vsave[0][8], vsave[1][8], vsave[2][8], sum_intr, sum_intg, sum_intb, and the number of sums is count;

[0118] S7, Calculate the mean: sum by the number of times the sum is accumulated.

[0119] Specifically, this embodiment can also be described as follows:

[0120] 1. Usage Requirements. The method described uses Beijing Junzheng T30 and T31 chips. Using standard averaging calculations is very slow, severely impacting overall performance. Optimization using the corresponding instruction sets of the T30 and T31 chips achieves a 40-fold speed improvement. The target image being processed is a multiple of 2048 pixels in length and width. The image averaging preprocessing requires an accuracy error within 1%, meeting practical application requirements. The corresponding instruction sets used on the T30 and T31 chips include addition, shift, arbitrary value retrieval, division, and data loading instructions. The instructions are as follows:

[0121] a) Addition instruction:

[0122] vrd=ingenic_add_h(vrs,vrt);

[0123] The input variables are vrs and vrt, and the output variable is vrd. vrd stores 8 int16_t data, and vrs and vrt store 8 int16_t data.

[0124] Equivalent operations:

[0125] vrd0:=vrs0+vrt0;

[0126] vrd1:=vrs1+vrt1;

[0127] ...

[0128] vrd7:=vrs7+vrt7;

[0129] b) Shift instruction: Shifts each element in the variable by i bits.

[0130] Left shift instruction

[0131] vrd=ingenic_shift_left(vrs,i)

[0132] Right shift instruction

[0133] vrd=ingenic_shift_right(vrs,i)

[0134] c) Arbitrary value selection instruction: Selects 4, 8, or 16 data points from variables vrs and vrt according to the numbers set by vri. When using this instruction, a permanent register vri is required to select the data at a specific location.

[0135] vrd=ingenic_choise_h(vrs,vrt,vri);

[0136] The input variables are vrs, vrt, and vri, and the output variable is the vrd register. Based on the location specified by vri, this instruction writes the data from the destination registers vrs and vrt to another register, vrd. This instruction uses the registers vri (for storing location), vrs and vrt (for storing the destination), and vrd (for storing the result).

[0137] d) Division instruction:

[0138] vrd=ingenic_div_d(vrs,vrt);

[0139] The input variables are vrs and vrt, and the output variable is the vrd register. vrd stores 16 int8_t values, and vrs and vrt also store 16 int8_t values. The result is rounded.

[0140] Equivalent operations:

[0141] vrd0:=vrs0 / vrt0;

[0142] vrd1:=vrs1 / vrt1;

[0143] ...

[0144] vrd7:=vrs7 / vrt7;

[0145] ...

[0146] Vrd15: = vrs15 / vrt15;

[0147] e) Load Data Instruction: The input is the data to be loaded, currently a pointer to the data, `indata`. Starting from the memory location `m` pointed to by `indata`, load 128 bits of data. If the data is 8 bits, load 16 bits; if it's 16 bits, load 8 bits; if it's 32 bits, load 4 bits. The data is loaded into the variable `vrd` register. Here, `m` is calculated in bytes, i.e., 8 bits per unit.

[0148] vrd = ingenic_load(indata,m)

[0149] f) Save data instruction: The register variable vrd contains the data to be saved, and the pointer savedata stores the data. The data in the register is stored starting from the pointer position. 128 bits of data from vrd are stored in savedata.

[0150] ingenic_save(vrd,savedata,m).

[0151] 2. Calculate the mean.

[0152] For RGB color images, we load 64*3 image data points at a time. One register can load 16 8-bit data points, using 12 variable registers: vrdr0, vrdg0, vrdb0, vrdr1, vrdg1, vrdb1, vrdr2, vrdg2, vrdb2, vrdr3, vrdg3, and vrdb3. Then, we convert the loaded register data to 16 bits, adding six intermediate conversion registers: vrd_r0, vrd_r1, vrd_g0, vrd_g1, and vrd_b0. vrd_b1 converts vrdr0, vrdg0, and vrdb0 into vrd_r0, vrd_r1, vrd_g0, vrd_g1, vrd_b0, and vrd_b1, respectively. Then, it uses three registers sum_hr0, sum_hg0, and sum_hb0 to accumulate 16 bits of data. After accumulation, it performs conversion and accumulation on vrdr1, vrdg1, vrdb1, vrdr2, vrdg2, vrdb2, vrdr3, vrdg3, and vrdb3. When sum_hr0 and sum_hg0... When `sum_hb0` accumulates 256 times, the data is right-shifted by 8 bits (equivalent to dividing by 256). Then, the shifted `sum_hr0`, `sum_hg0`, and `sum_hb0` are accumulated using the three registers `sum_hr1`, `sum_hg1`, and `sum_hb1`. `sum_hr0`, `sum_hg0`, and `sum_hb1` are initialized to 0 before the newly loaded data is re-accumulated. Similarly, `sum_hr1`, `sum_hg1`, and `sum_hb1` are used to accumulate the shifted `sum_hr0`, `sum_hg0`, and `sum_hb0`. When `sum_hr1`, `sum_hg1`, and `sum_hb1` accumulate 256 times, the results are saved to three arrays. Finally, the data in the three arrays are summed again, and the average value of each RGB channel is calculated. The specific implementation is as follows.

[0153] The variable registers used are declared as follows: vrdr0, vrdg0, vrdb0, vrdr1, vrdg1, vrdb1, vrdr2, vrdg2, vrdb2, vrdr3, vrdg3, vrdb3; sum_hr0, sum_hg0, sum_hb0; sum_hr1, sum_hg1, sum_hb1. Let vri0 be the selection register that converts the first 8 data bits in the 8-bit register to a 16-bit register, and vri1 be the selection register that converts the last 8 data bits in the 8-bit register to a 16-bit register. The preprocessed data is named indata, with a width of width and a height of height. The total number of data bits is piel_count = width * height. Let a data set be vsave[3][8], a regular temporary variable sum_intr, sum_intg, sum_intb with mean values ​​of avgr, avgg, avgb, and a calculator count to count the cumulative sums of sum_hr1, sum_hg1, and sum_hb1, initially set to 0.

[0154] Due to the characteristics of the three-channel color system, the number of registers used for loading data must be a multiple of 3, and the total number of registers is 32. The number of registers used cannot exceed 32; otherwise, repeated loading and storage of data will result in extremely low efficiency. Therefore, in the algorithm optimization design below, a set of 16-bit data needs to be converted and accumulated once. During data loading, the process from DDR to cache is slow, but the process from cache to register is very fast. Cached data that is not used promptly will be overwritten by other data. Therefore, we used the maximum number of registers for loading data to load all cached data and avoid waste.

[0155] a) Load 64*3 image data points into vrdr0, vrdg0, vrdb0, vrdr1, vrdg1, vrdb1, vrdr2, vrdg2, vrdb2, vrdr3, vrdg3, vrdb3. Then modify the indata pointer, i.e., indata = indata + 64*3

[0156] vrdr0=ingenic_load(indata, 0)

[0157] vrdg0=ingenic_load(indata, 16)

[0158] vrdb0=ingenic_load(indata, 32)

[0159] vrdr1=ingenic_load(indata, 48)

[0160] vrdg1=ingenic_load(indata, 64)

[0161] vrdb1=ingenic_load(indata, 80)

[0162] vrdr2=ingenic_load(indata, 96)

[0163] vrdg2=ingenic_load(indata, 112)

[0164] vrdb2=ingenic_load(indata, 128)

[0165] vrdr3=ingenic_load(indata, 144)

[0166] vrdg3=ingenic_load(indata, 160)

[0167] vrdb3=ingenic_load(indata, 176)

[0168] indata = indata + 64 * 3

[0169] (b) Use a pre-defined selection order to convert data from 8 bits to 16 bits. Since there is no direct instruction in the instruction set to convert 8 bits to 16 bits, an arbitrary value fetching instruction is needed. This involves setting two selection registers, vri0 and vri1, and pre-designing the specific selection order within them. The registers for converting to 16 bits are vrd_r1, vrd_r0, vrd_g1, vrd_g0, vrd_b1, and vrd_b0. The three registers sum_hr0, sum_hg0, and sum_hb0 are used to accumulate the 16-bit data vrd_r1, vrd_r0, vrd_g1, vrd_g0, vrd_b1, and vrd_b0. After accumulation, vrdr1, vrdg1, vrdb1, vrdr2, vrdg2, vrdb2, vrdr3, vrdg3, and vrdb3 are converted to 16 bits before accumulation. During the first accumulation and initialization, the data in sum_hr0, sum_hg0, and sum_hb0 are 0.

[0170] vrd_r1=ingenic_choise_h(vrdr0,vrdr0,vri1)

[0171] vrd_r0=ingenic_choose_h(vrdr0,vrdr0,vri0)

[0172] vrd_g1=ingenic_choose_h(vrdg0,vrdg0,vri1)

[0173] vrd_g0=ingenic_choose_h(vrdg0,vrdg0,vri0)

[0174] vrd_b1=ingenic_choose_h(vrdb0,vrdb0,vri1)

[0175] vrd_b0=ingenic_choose_h(vrdb0,vrdb0,vri0)

[0176] sum_hr0=ingenic_add_h(sum_hr0,vrd_r0);

[0177] sum_hr0=ingenic_add_h(sum_hr0,vrd_r1);

[0178] sum_hg0=ingenic_add_h(sum_hg0,vgd_g0);

[0179] sum_hg0=ingenic_add_h(sum_hg0,vgd_g1);

[0180] sum_hb0=ingenic_add_h(sum_hb0,vgd_b0);

[0181] sum_hb0=ingenic_add_h(sum_hb0,vgd_b1);

[0182] ……

[0183] vrd_r1=ingenic_choose_h(vrdr3,vrdr3,vri1)

[0184] vrd_r0=ingenic_choose_h(vrdr3,vrdr3,vri0)

[0185] vrd_g1=ingenic_choose_h(vrdg3,vrdg3,vri1)

[0186] vrd_g0=ingenic_choose_h(vrdg3,vrdg3,vri0)

[0187] vrd_b1=ingenic_choise_h(vrdb3,vrdb3,vri1)

[0188] vrd_b0=ingenic_choise_h(vrdb3,vrdb3,vri0)

[0189] sum_hr0=ingenic_add_h(sum_hr0,vrd_r0);

[0190] sum_hr0=ingenic_add_h(sum_hr0,vrd_r1);

[0191] sum_hg0=ingenic_add_h(sum_hg0,vgd_g0);

[0192] sum_hg0=ingenic_add_h(sum_hg0,vgd_g1);

[0193] sum_hb0=ingenic_add_h(sum_hb0,vgd_b0);

[0194] sum_hb0=ingenic_add_h(sum_hb0,vgd_b1);

[0195] c) Repeat steps a) and b) until the loop reaches 256 times. Then, shift the values ​​in sum_hr0, sum_hg0, and sum_hb0, and add the processed results to sum_hr1, sum_hg1, and sum_hb1. Finally, set the values ​​in sum_hr0, sum_hg0, and sum_hb0 to 0, and increment the count by one.

[0196] sum_hr1=ingenic_shift_right(sum_hr0,8)

[0197] sum_hg1=ingenic_shift_right(sum_hg0,8)

[0198] sum_hb1=ingenic_shift_right(sum_hb0,8)

[0199] count+=1

[0200] d) Repeat steps a), b), and c) until the loop reaches 256 times. Then, save sum_hr1, sum_hg1, and sum_hb1 to vsave[0][8], vsave[1][8], and vsave[2][8]. Sum the data in vsave to sum_intr, sum_intg, and sum_intb. Set the data in sum_hr1, sum_hg1, and sum_hb1 to 0. Repeat steps a), b), and c) until all data has been calculated.

[0201] e) Save sum_hr1, sum_hg1, sum_hb1 to vsave[0][8], vsave[1][8], vsave[2][8], and sum the data in vsave to sum_intr, sum_intg, sum_intb. The number of times the sum is accumulated is count.

[0202] avgr = sum_intr / count;

[0203] avgg = sum_intg / count;

[0204] avgb = sum_intb / count.

[0205] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the embodiments of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An optimized method for color image mean preprocessing, characterized in that, The method is designed for RGB color images. It loads 64*3 image data points at a time, using 16 8-bit data points in one register and 12 variable registers: vrdr0, vrdg0, vrdb0, vrdr1, vrdg1, vrdb1, vrdr2, vrdg2, vrdb2, vrdr3, vrdg3, and vrdb3. The loaded register data is then converted to 16 bits using 6 intermediate conversion registers: vrd_r0, vrd_r1, vrd_g0, vrd_g1, vrd_b0, and vrd_b1. vrdr0, vrdg0, and vrdb0 are converted to vrd_r0, vrd_r1, vrd_g0, vrd_g1, vrd_b0, and vrd_b1. Three registers, sum_hr0, sum_hg0, and sum_hb0, are used to accumulate the 16-bit data. After accumulation, vrdr1, vrdg1, and vrdg2 are then processed. vrdb1,vrdr2,vrdg2, vrdb2,vrdr3, vrdg3 and vrdb3 are used for conversion and accumulation. When sum_hr0, sum_hg0, and sum_hb0 are accumulated 256 times, the data is right-shifted by 8 bits, which is equivalent to dividing by 256. Then, the shifted sum_hr0, sum_hg0, and sum_hb0 are accumulated using the three registers sum_hr1, sum_hg1, and sum_hb1. sum_hr0, sum_hg0, and sum_hb0 are initialized to 0 and then the newly loaded data is accumulated again. The shifted sum_hr0, sum_hg0, and sum_hb0 are accumulated using sum_hr1, sum_hg1, and sum_hb1. When sum_hr1, sum_hg1, and sum_hb1 are accumulated 256 times, the results of sum_hr1, sum_hg1, and sum_hb1 are saved to three arrays. Finally, the data in the three arrays are accumulated again, and the average value of each RGB channel is calculated.

2. The optimization method for color image mean preprocessing according to claim 1, characterized in that, The method further includes: S1, Initialization and Register Declarations for Used Variables: Let vri0 be a selection register that converts the first 8 data in the register used to load 16 8-bit data into 16-bit data, and vri1 be a selection register that converts the last 8 data in the register into 16-bit data. The preprocessed data is indata, with width and height, and the total number of data is piel_count = width * height; Let a data set be vsave[3][8], a regular temporary variable sum_intr, sum_intg, sum_intb with mean values ​​of avgr, avgg, avgb, and a calculator count to count the cumulative sums of sum_hr1, sum_hg1, and sum_hb1, with an initial value of 0; S2, load 64*3 image data into vrdr0,vrdg0,vrdb0,vrdr1,vrdg1, vrdb1,vrdr2,vrdg2,vrdb2,vrdr3, vrdg3,vrdb3, and then change the indata pointer, i.e., indata=indata+64*3. S3. Using a pre-defined selection order, the data is converted from 8 bits to 16 bits. This involves setting two selection registers, vri0 and vri1, with the specific selection order pre-designed. The registers for converting to 16 bits are vrd_r1, vrd_r0, vrd_g1, vrd_g0, vrd_b1, and vrd_b0. Three registers, sum_hr0, sum_hg0, and sum_hb0, are used to accumulate the 16-bit data vrd_r1, vrd_r0, vrd_g1, vrd_g0, vrd_b1, and vrd_b0. After accumulation, vrdr1, vrdg1, vrdb1, vrdr2, vrdg2, vrdb2, vrdr3, vrdg3, and vrdb3 are converted to 16 bits again and accumulated. During the first accumulation and initialization, the data in sum_hr0, sum_hg0, and sum_hb0 are 0. S4. Repeat steps S2 and S3 until the loop count reaches 256. Then, shift the values ​​in sum_hr0, sum_hg0, and sum_hb0, and add the processed results to sum_hr1, sum_hg1, and sum_hb1. Finally, set the values ​​in sum_hr0, sum_hg0, and sum_hb0 to 0, and increment count by 1. S5. Repeat steps S2, S3, and S4 until the loop reaches 256 times. Save sum_hr1, sum_hg1, and sum_hb1 to vsave[0][8], vsave[1][8], and vsave[2][8]. Sum the data in vsave to sum_intr, sum_intg, and sum_intb. Set the data in sum_hr1, sum_hg1, and sum_hb1 to 0. Repeat steps S2, S3, and S4 until all data has been calculated. S6, save sum_hr1, sum_hg1, sum_hb1 to vsave[0][8], vsave[1][8], vsave[2][8], sum_intr, sum_intg, sum_intb, and the number of sums is count; S7, Calculate the mean: sum by the number of times the sum is accumulated.

3. The optimization method for color image mean preprocessing according to claim 2, characterized in that, The method is applied to chips with SIMD instructions, and optimizes the corresponding instruction set. The target image to be processed is a multiple of 2048 in length and width. The image mean preprocessing requires a precision error of less than 1. The corresponding instruction set used includes addition instructions, shift instructions, arbitrary value extraction instructions, division instructions, data loading instructions, and data saving instructions.

4. The optimization method for color image mean preprocessing according to claim 3, characterized in that, The method is applied to Beijing Junzheng T30 and T31 chips.

5. The optimization method for color image mean preprocessing according to claim 3, characterized in that, The addition instruction, shift instruction, arbitrary value fetching instruction, division instruction, data loading instruction, and data saving instruction are as follows: a) The addition instruction is represented as: vrd = ingenic_add_h (vrs, vrt); The input variables are vrs and vrt, and the output variable is vrd; vrd stores 8 int16_t data, and vrs and vrt store 8 int16_t data. Equivalent operations: vrd0 := vrs0 + vrt0; vrd1 := vrs1 + vrt1; …… vrd7 := vrs7 + vrt7; b) Shift instruction: Shifts each element in the variable by i bits; The left shift instruction is represented as: vrd = ingenic_shift_left (vrs, i) The right shift instruction is represented as: vrd = ingenic_shift_right (vrs, i); c) Arbitrary value selection instruction: Selects 4, 8, or 16 data points from variables vrs and vrt according to the numbers set in vri. This instruction requires a permanent register vri to be used for selecting the specific data location; it is represented as: vrd = ingenic_choise_h (vrs, vrt, vri); d) Division instruction: represented as: vrd = ingenic_ div_d (vrs, vrt); The input variables are vrs and vrt, and the output variable is the vrd register; vrd stores 16 int8_t data, and vrs and vrt store 16 int8_t data; the result is rounded. Equivalent operations: vrd0 := vrs0 / vrt0; vrd1 := vrs1 / vrt1; …… vrd7 := vrs7 / vrt7; …… Vrd15 := vrs15 / vrt15; e) Load Data Instruction: The input is the data to be loaded, currently a pointer to the data, indata. Starting from the memory location m pointed to by indata, 128 bits of data are loaded. If it's 8-bit data, 16 bits are loaded; if it's 16-bit data, 8 bits are loaded; if it's 32-bit data, 4 bits are loaded. The data is loaded into the variable vrd register. Here, m is calculated in bytes, i.e., 8 bits per unit, represented as: vrd = ingenic_load (indata,m); f) Save data instruction: The register variable vrd contains the data to be saved, and the pointer savedata stores the data. The data in the register is stored starting from the pointer position. Storing 128 bits of data from vrd into savedata is represented as follows: ingenic_save (vrd, savedata, m).

6. The optimization method for color image mean preprocessing according to claim 5, characterized in that, In step S2, the indata pointer is modified, further including a data loading instruction: the data to be loaded is the data pointed to by the indata pointer. Starting from positions 0, 16, ..., 160, 176 pointed to by the indata pointer, 128 bits of data are loaded sequentially. If it is 8 bits of data, 16 bits are loaded; if it is 16 bits of data, 8 bits are loaded; if it is 32 bits, 4 bits are loaded. The data is loaded into the variable vrdri, vrdgi, vrdbi registers, where i = 0, 1, 2, 3, represented as: vrdr0 = ingenic_load (indata, 0) vrdg0 = ingenic_load (indata, 16) vrdb0 = ingenic_load (indata, 32) vrdr1 = ingenic_load (indata, 48) vrdg1 = ingenic_load (indata, 64) vrdb1 = ingenic_load (indata, 80) vrdr2 = ingenic_load (indata, 96) vrdg2 = ingenic_load (indata, 112) vrdb2 = ingenic_load (indata, 128) vrdr3 = ingenic_load (indata, 144) vrdg3 = ingenic_load (indata, 160) vrdb3 = ingenic_load (indata, 176) indata = indata + 64 * 3.

7. The optimization method for color image mean preprocessing according to claim 6, characterized in that, Step S3 further includes an arbitrary value selection instruction: selecting 4, 8, or 16 data points from variables vrdrm and vrdrn, vrdgm and vrdgn, vrdbm and vrdbn according to the numbers set by vrij, and outputting vrd_r1, vrd_r0, vrd_g1, vrd_g0, vrd_b1, and vrd_b0 respectively; it also includes an addition instruction, with input variables sum_hr0, sum_hg0, and sum_hr0, and the output of the arbitrary value selection instruction, with output variables sum_hr0, sum_hg0, and sum_hr0 respectively; where m and n are 0, 1, 2, and 3 respectively, and j is 1 and 0, represented as: vrd_r1 = ingenic_choice_h (vrdr0, vrdr0,vri1) vrd_r0 = ingenic_choice_h (vrdr0, vrdr0,vri0) vrd_g1 = ingenic_choose_h (vrdg0, vrdg0,vri1) vrd_g0 = ingenic_choose_h (vrdg0, vrdg0,vri0) vrd_b1 = ingenic_choose_h (vrdb0, vrdb0,vri1) vrd_b0 = ingenic_choose_h (vrdb0, vrdb0,vri0) sum_hr0 = ingenic_add_h (sum_hr0, vrd_r0); sum_hr0 = ingenic_add_h (sum_hr0, vrd_r1); sum_hg0 = ingenic_add_h (sum_hg0, vgd_g0); sum_hg0 = ingenic_add_h (sum_hg0, vgd_g1); sum_hb0 = ingenic_add_h (sum_hb0, vgd_b0); sum_hb0 = ingenic_add_h (sum_hb0, vgd_b1); …… vrd_r1 = ingenic_choose_h (vrdr3, vrdr3,vri1) vrd_r0 = ingenic_choice_h (vrdr3, vrdr3,vri0) vrd_g1 = ingenic_choose_h (vrdg3, vrdg3,vri1) vrd_g0 = ingenic_choose_h (vrdg3, vrdg3,vri0) vrd_b1 = ingenic_choose_h (vrdb3, vrdb3,vri1) vrd_b0 = ingenic_choose_h (vrdb3, vrdb3,vri0) sum_hr0 = ingenic_add_h (sum_hr0, vrd_r0); sum_hr0 = ingenic_add_h (sum_hr0, vrd_r1); sum_hg0 = ingenic_add_h (sum_hg0, vgd_g0); sum_hg0 = ingenic_add_h (sum_hg0, vgd_g1); sum_hb0 = ingenic_add_h (sum_hb0, vgd_b0); sum_hb0 = ingenic_add_h (sum_hb0, vgd_b1).

8. The optimization method for color image mean preprocessing according to claim 7, characterized in that, Step S4 further includes a right shift instruction, which shifts each element in sum_hr0, sum_hg0, and sum_hb0 to the right by 8 bits, and then increments count by 1, as follows: sum_hr0 = ingenic_shift_right (sum_hr0, 8) sum_hg0 = ingenic_shift_right (sum_hg0, 8) sum_hb0 = ingenic_shift_right (sum_hb0, 8) count += 1.

9. The optimization method for color image mean preprocessing according to claim 8, characterized in that, Step S7 further includes: avgr=sum_intr / count; avgg = sum_intg / count; avgb=sum_intb / count.

Images