Phase correction circuit, clock buffer including the same, and semiconductor device

Abstract

Disclosed are a phase correction circuit, a clock buffer including the same, and a semiconductor device. The phase correction circuit includes a plurality of signal paths configured to transmit a multi-phase signal. The phase correction circuit further includes a ring circuit coupled to the plurality of signal paths, the ring circuit being configured to correct a phase skew in the multi-phase signal by averaging phases of two signals obtained by combining a signal of each signal path with another signal of another signal path different from the corresponding signal path.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Application No. 10-2021-0108093, filed with the Korean Intellectual Property Office on August 17, 2021, the entirety of which is incorporated herein by reference. Technical Field

[0003] The various embodiments generally relate to semiconductor circuits, and more specifically to phase correction circuits and clock buffers and semiconductor devices including therein. Background Technology

[0004] Semiconductor circuits (e.g., semiconductor memories) use clock signals as reference signals for read or write operations. Semiconductor memories use multi-phase clock signals (e.g., four-phase clock signals). The clock buffer of a semiconductor memory receives a clock signal provided externally to the semiconductor memory and generates a multi-phase clock signal. The multi-phase clock signal itself may be skewed, or it may contain skew due to differences in the signal transmission paths used to transmit the individual multi-phase clock signals. When the multi-phase clock signal contains skew, the operational performance of the circuitry used to process data degrades. As a result, data reliability decreases. Summary of the Invention

[0005] Various embodiments relate to a phase correction circuit capable of automatically correcting phase skew in a multi-phase signal, and a clock buffer and semiconductor device including the circuit.

[0006] In an embodiment, the phase correction circuit may include: a plurality of signal paths configured to transmit multi-phase signals; and a ring circuit coupled to the plurality of signal paths, the ring circuit being configured to correct phase skew in the multi-phase signals by averaging the phases of two signals obtained by combining a signal in each signal path with another signal from a different signal path.

[0007] The loop circuit can be disabled when the operating frequency is less than a preset value, and has a driving force that varies according to the value of the operating frequency when the operating frequency is equal to or greater than the preset value.

[0008] Multiple signal paths may include a first signal path, a second signal path, a third signal path, and a fourth signal path. The ring circuit may include: a first signal transmission unit configured to invert a signal at a first node of a first signal path and transmit the inverted signal to a second node of a third signal path; a first programmable buffer configured to buffer a signal at a second node of the first signal path and transmit the buffered signal to a first node of the second signal path; a second signal transmission unit configured to invert a signal at a first node of the second signal path and transmit the inverted signal to a second node of a fourth signal path; a second programmable buffer configured to buffer a signal at a second node of the second signal path and transmit the buffered signal to a first node of the third signal path; a third signal transmission unit configured to invert a signal at a first node of the third signal path and transmit the inverted signal to a second node of the first signal path; a third programmable buffer configured to buffer a signal at a second node of the third signal path and transmit the buffered signal to a first node of the fourth signal path; a fourth signal transmission unit configured to invert a signal at a first node of the fourth signal path and transmit the inverted signal to a second node of the second signal path; and a fourth programmable buffer configured to buffer a signal at a second node of the fourth signal path and transmit the buffered signal to a first node of the first signal path.

[0009] In an embodiment, the phase correction circuit may include: a plurality of signal paths configured to transmit multi-phase signals; a first correction loop configured to synthesize two adjacent signals based on the plurality of signal paths in the multi-phase signal; and a second correction loop configured to synthesize complementary signals in the multi-phase signal.

[0010] In an embodiment, the clock buffer may include: a phase separator configured to receive an external clock signal and generate a multi-phase clock signal; and a phase correction circuit coupled to a plurality of signal paths for transmitting the multi-phase clock signal, the phase correction circuit being configured to correct phase skew in the multi-phase clock signal by averaging the phases of two signals, the two signals being obtained by combining a signal in each signal path with another signal from a different signal path.

[0011] In an embodiment, the semiconductor device may include: a memory region; a data output circuit configured to output data from the memory region to the outside of the semiconductor device according to a phase-corrected clock signal; and a clock buffer configured to receive an external clock signal, generate a multi-phase clock signal, and generate a phase-corrected clock signal by performing a phase averaging operation on the signal of each of a plurality of signal paths used to transmit the multi-phase clock signal and the signal of another signal path.

[0012] In an embodiment, the phase correction circuit may include: a ring circuit coupled to a plurality of signal paths configured to transmit a multi-phase clock signal and configured to perform at least one of synthesizing two adjacent signals based on the plurality of signal paths and synthesizing complementary signals in the multi-phase clock signal; a plurality of programmable buffers coupled to the plurality of signal paths, the plurality of programmable buffers being configured to operate in response to a control code; and a code control circuit configured to generate a control code in response to operating frequency information. The phase correction circuit can correct phase skew in the multi-phase clock signal by controlling the driving force of the programmable buffers and the phase averaging of the two signals synthesized by the ring circuit according to the control code.

[0013] The programmable buffer can be disabled when the operating frequency defined in the operating frequency information is less than a preset value, according to the control code, and each programmable buffer has a driving force that varies according to the value of the operating frequency when the operating frequency is equal to or greater than the preset value. Attached Figure Description

[0014] Figure 1 This is a diagram illustrating the structure of a semiconductor system according to an embodiment.

[0015] Figure 2 This is a diagram illustrating the structure of a semiconductor device according to an embodiment.

[0016] Figure 3 It is shown Figure 2 A diagram of the structure of a phase separator.

[0017] Figure 4 It is shown Figure 2 A diagram showing the structure of the first signal path.

[0018] Figure 5 It is shown Figure 2 A diagram showing the structure of the code control circuit.

[0019] Figure 6 It is shown Figure 2 A diagram showing the structure of the phase correction circuit.

[0020] Figure 7 It is shown Figure 6 A diagram showing the structure of the first programmable buffer.

[0021] Figure 8 This illustrates an embodiment. Figure 6 A diagram showing the structure of the first correction loop in the phase correction circuit.

[0022] Figure 9 This illustrates an embodiment. Figure 6 The diagram shows the structure of the second correction loop of the phase correction circuit.

[0023] Figure 10 This is a diagram illustrating the structure of a semiconductor device according to another embodiment. Detailed Implementation

[0024] The embodiments will now be described in more detail with reference to the accompanying drawings.

[0025] Figure 1 This is a diagram illustrating the structure of a semiconductor system 1 according to an embodiment.

[0026] refer to Figure 1 Semiconductor system 1 may include controller 2 and semiconductor device 3.

[0027] Controller 2 can be a GPU (Graphics Processing Unit) or a CPU (Central Processing Unit). Controller 2 can provide external clock signals to semiconductor device 3, such as data clock signals WCK / WCKB, system clock signals HCK / HCKB, and command signals CMD. The data clock signals WCK / WCKB can have a period and / or frequency different from the system clock signals HCK / HCKB. When writing data DATA, controller 2 can provide the data clock signals WCK / WCKB to semiconductor device 3. Controller 2 can receive data DATA output from semiconductor device 3 according to a read command.

[0028] Semiconductor device 3 can use a multi-phase clock signal as a reference signal for read or write operations. Semiconductor device 3 can generate the multi-phase clock signal using an external clock signal (e.g., a data clock signal WCK / WCKB). Semiconductor device 3 can be a volatile memory device, a non-volatile memory device, or a memory device that combines both volatile and non-volatile memory.

[0029] Figure 2 This is a diagram illustrating the structure of a semiconductor device 10 according to an embodiment.

[0030] refer to Figure 2 The semiconductor device 10 may include a clock buffer 11, a memory region 30, and a data output circuit 40. The semiconductor device 10 may also include an MRS (mode register setting) 50 and a code control circuit 60.

[0031] Clock buffer 11 can receive data clock signals WCK and WCKB and generate multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB. Clock buffer 11 can be configured to perform a phase correction operation by compensating for skew in the multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB by combining a signal from at least one of the multiple signal paths 31 to 34 with another signal from another signal path, thereby generating phase-corrected clock signals ICLKC, QCLKC, ICLKBC, and QCLKBC. Clock buffer 11 can be configured to determine whether to perform the phase correction operation based on the operating frequency of the semiconductor device 10. Clock buffer 11 can be configured to change the driving force during the phase correction operation based on the operating frequency of the semiconductor device 10.

[0032] The clock buffer 11 may include a phase separator 12, a phase correction circuit 100, and multiple signal paths 31 to 34.

[0033] Phase splitter 12 can receive data clock signals WCK and WCKB and generate multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB. Phase splitter 12 can separate the phases of data clock signals WCK and WCKB and simultaneously divide the frequencies of data clock signals WCK and WCKB, so that each multi-phase clock signal ICLK, QCLK, ICLKB, and QCLKB has a frequency that is 2 or 4 times that of data clock signals WCK and WCKB.

[0034] exist Figure 6 The phase correction circuit 100, shown in more detail below, may include a ring circuit 101, multiple programmable buffers, and a code control circuit. The ring circuit 101 may be coupled to multiple signal paths 31 to 34 configured to transmit multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB, respectively, and configured to perform one or more operations of synthesizing two adjacent signals based on the multiple signal paths 31 to 34 and synthesizing complementary signals in the multi-phase clock signals. The multiple programmable buffers may be coupled to the multiple signal paths 31 to 34 and configured to operate in response to drive force control codes STCODE<0:N> and STCODEB<0:N>. The code control circuit may be configured to generate control codes in response to operating frequency information FINF. The phase correction circuit 100 can be configured to correct phase skew in multi-phase clock signals ICLK, QCLK, ICLKB and QCLKB by controlling the driving force of the programmable buffer and the phase averaging of the two signals synthesized by the ring circuit 101 according to the driving force control codes STCODE<0:N> and STCODEB<0:N>.

[0035] In the current embodiment, when the operating frequency defined in the operating frequency information FINF is less than a preset value, the programmable buffer can be disabled according to the drive force control codes STCODE<0:N> and STCODEB<0:N>. When the operating frequency is equal to or greater than the preset value, the drive force of the programmable buffer can be changed.

[0036] Phase correction circuit 100 may include multiple signal paths 31 to 34. Phase correction circuit 100 can perform a phase correction operation to compensate for skew in multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB by combining a signal from at least one of the multiple signal paths 31 to 34 with another signal from another signal path. Phase correction circuit 100 can interrupt the phase correction operation in response to drive force control codes STCODE<0:N> and STCODEB<0:N>. Drive force control codes STCODE<0:N> and STCODEB<0:N> each may include multiple signal bits and have a complementary relationship. Phase correction circuit 100 can change the drive force of the phase correction operation in response to drive force control codes STCODE<0:N> and STCODEB<0:N>.

[0037] Multiple signal paths 31 to 34 can delay multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB and output delayed signals. Multiple signal paths 31 to 34 can transmit the multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB, which have passed through the phase correction circuit 100, as phase-corrected clock signals ICLKC, QCLKC, ICLKBC, and QCLKBC to the data output circuit 40. Multiple signal paths 31 to 34 may include a first signal path 31, a second signal path 32, a third signal path 33, and a fourth signal path 34. The first signal path 31 can output the phase clock signal ICLK, which has passed through the phase correction circuit 100, as the phase-corrected clock signal ICLKC. The second signal path 32 can output the phase clock signal QCLK, which has passed through the phase correction circuit 100, as the phase-corrected clock signal QCLKC. The third signal path 33 can output the phase clock signal ICLKB, which has passed through the phase correction circuit 100, as the phase-corrected clock signal ICLKBC. The fourth signal path 34 can output the phase clock signal QCLKB, which has passed through the phase correction circuit 100, as the phase correction clock signal QCLKBC.

[0038] Memory region 30 may include at least one of volatile memory and non-volatile memory. Examples of volatile memory include SRAM (Static RAM), DRAM (Dynamic RAM), and SDRAM (Synchronous DRAM), and examples of non-volatile memory may include ROM (Read-Only Memory), PROM (Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), EPROM (Electrically Programmable ROM), flash memory, PRAM (Phase-Change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), and FRAM (Ferroelectric RAM), etc. Memory region 30 may output data stored therein during a read operation of semiconductor device 10 and store data input from outside semiconductor device 10 during a write operation of semiconductor device 10.

[0039] The data output circuit 40 can output the data from the memory region 30 to the outside of the semiconductor device 10 according to the phase correction clock signals ICLKC, QCLKC, ICLKBC and QCLKBC.

[0040] MRS 50 can store and output the operating frequency information FINF of the semiconductor device 10. The operating frequency information FINF can be set during the manufacturing process of the semiconductor device 10, or received from an external device (e.g., controller 2) and stored in MRS 50.

[0041] The code control circuit 60 can generate drive force control codes STCODE<0:N> and STCODEB<0:N> in response to the operating frequency information FINF. The code control circuit 60 can change the values ​​of drive force control codes STCODE<0:N> and STCODEB<0:N> according to the value of the operating frequency information FINF.

[0042] Figure 3 It is shown Figure 2 A diagram showing the structure of the phase separator 12.

[0043] refer to Figure 3The phase separator 12 may include a first buffer 12-1, a frequency divider 12-2, and a second buffer 12-3. The first buffer 12-1 buffers the data clock signals WCK and WCKB and outputs the buffered signal. The frequency divider 12-2 separates the phase of the output signal from the first buffer 12-1, divides the frequency of the output signal, and outputs the divided signal. In this case, the frequency divider 12-2 can divide the frequency of the output signal by 2. The second buffer 12-3 buffers the output signal from the frequency divider 12-2 and outputs the buffered signal as the multi-phase clock signals ICK / QCK / ICKB / QCKB. Ideally, the multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB need to have a predetermined phase difference from each other. However, due to variations in PVT (power, voltage, temperature), as the phase difference between the multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB becomes different from the target value, the multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB may exhibit skew.

[0044] Figure 4 It is shown Figure 2 The diagram shows the structure of the first signal path 31.

[0045] refer to Figure 4 The first signal path 31 may include a plurality of inverters 31-1 to 31-N. Although described below, the phase correction circuit 100 may be coupled between the output port of any one of the inverters 31-1 to 31-N and the input port of the other one of the inverters 31-1 to 31-N.

[0046] Figure 5 It is shown Figure 2 The diagram shows the structure of the code control circuit 60.

[0047] refer to Figure 5 The code control circuit 60 can select one of the precodes PRECODE0 to PRECODEEn based on the operating frequency information FINF, and output the selected precode as the drive force control codes STCODE<0:N> and STCODEB<0:N>. Each of the precodes PRECODE0 to PRECODEEn can include signal bits corresponding to the drive force control codes STCODE<0:N> and STCODEB<0:N>. The values ​​of the precodes PRECODE0 to PRECODEEn can be set to different values. The code control circuit 60 can include a code storage circuit 61 and a multiplexer 62.

[0048] The code storage circuit 61 may include storage circuitry for storing precodes PRECODE0 to PRECODEEn, for example, multiple registers 61-1 to 61-N. The precodes PRECODE0 to PRECODEEn may be stored separately in multiple registers 61-1 to 61-N.

[0049] The multiplexer 62 can select a precode stored in any one of the multiple registers 61-1 to 61-N according to the operating frequency information FINF, and output the selected precode as the drive force control codes STCODE<0:N> and STCODEB<0:N>.

[0050] The operating frequency information FINF can define the operating frequency of the semiconductor device 10, i.e., the operating speed. For example, when the frequency range in which the semiconductor device 10 can operate is divided into four parts A, B, C, and D, part 'A' can be defined as 'low speed', part 'B' can be defined as 'high speed-1', part 'C' can be defined as 'high speed-2', and part 'D' can be defined as 'high speed-3'. Since the operating speed can be divided into four stages, the operating frequency information FINF can be configured with two bits to limit the operating speed. For low speed, high speed-1, high speed-2, and high speed-3, the values ​​of the operating frequency information FINF can be set to '00', '01', '10', and '11', respectively. At this time, assuming N is 3 (N=3), the first precode PRECODE0 can have the value '0000' (as the value corresponding to the drive force control code STCODE<0:3>) and the value '1111' (as the value corresponding to the drive force control code STCODEB<0:3>). The second precode PRECODE1 can have the value '1000' (as the value corresponding to the drive force control code STCODE<0:3>) and the value '0111' (as the value corresponding to the drive force control code STCODEB<0:3>). The third precode PRECODE2 can have the value '1100' (as the value corresponding to the drive force control code STCODE<0:3>) and the value '0011' (as the value corresponding to the drive force control code STCODEB<0:3>). The fourth precode PRECODE3 can have the value '1110' (as the value corresponding to the drive force control code STCODE<0:3>) and the value '0001' (as the value corresponding to the drive force control code STCODEB<0:3>).

[0051] When the value of the operating frequency information FINF is '00', the multiplexer 62 can output the first precode PRECODE0 as the drive force control codes STCODE<0:3> and STCODEB<0:3>. When the value of the operating frequency information FINF is '01', the multiplexer 62 can output the second precode PRECODE1 as the drive force control codes STCODE<0:3> and STCODEB<0:3>. When the value of the operating frequency information FINF is '10', the multiplexer 62 can output the third precode PRECODE2 as the drive force control codes STCODE<0:3> and STCODEB<0:3>. When the value of the operating frequency information FINF is '11', the multiplexer 62 can output the fourth precode PRECODE3 as the drive force control codes STCODE<0:3> and STCODEB<0:3>.

[0052] Figure 6 It is shown Figure 2 A diagram showing the structure of the phase correction circuit 100.

[0053] refer to Figure 6 The phase correction circuit 100 may include a first signal path 31 to a fourth signal path 34 and a ring circuit 101.

[0054] The ring circuit 101 can perform phase averaging by combining the signals from the first signal path 31 to the fourth signal path 34 with the signals from the other paths, thereby compensating for skew in the multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB. The ring circuit 101 may include a first correction loop and a second correction loop, which will be referred to below. Figure 8 and Figure 9The ring circuit 101 may include multiple signal transmission units 131-1, 132-1, 133-1, and 134-1, and multiple programmable buffers 131-2, 132-2, 133-2, and 134-2. Each of the multiple signal transmission units 131-1, 132-1, 133-1, and 134-1 may be configured as an inverter. The driving force of the multiple programmable buffers 131-2, 132-2, 133-2, and 134-2 may be changed according to the driving force control codes STCODE<0:N> and STCODEB<0:N>. The first signal transmission unit 131-1 may invert the signal at node N11 of the first signal path 31 and transmit the inverted signal to node N32 of the third signal path 33. The first programmable buffer 131-2 may buffer the signal at node N12 of the first signal path 31 and transmit the buffered signal to node N21 of the second signal path 32. The second signal transmission unit 132-1 can invert the signal at node N21 of the second signal path 32 and transmit the inverted signal to node N42 of the fourth signal path 34. The second programmable buffer 132-2 can buffer the signal at node N22 of the second signal path 32 and transmit the buffered signal to node N31 of the third signal path 33. The third signal transmission unit 133-1 can invert the signal at node N31 of the third signal path 33 and transmit the inverted signal to node N12 of the first signal path 31. The third programmable buffer 133-2 can buffer the signal at node N32 of the third signal path 33 and transmit the buffered signal to node N41 of the fourth signal path 34. The fourth signal transmission unit 134-1 can invert the signal at node N41 of the fourth signal path 34 and transmit the inverted signal to node N22 of the second signal path 32. The fourth programmable buffer 134-2 can buffer the signal at node N42 of the fourth signal path 34 and transmit the buffered signal to node N11 of the first signal path 31.

[0055] Figure 7 It is shown Figure 6 A diagram of the structure of the first programmable buffer 131-2.

[0056] refer to Figure 7 The first programmable buffer 131-2 may include a basic drive unit 140 and a variable drive unit 150.

[0057] The basic driving unit 140 can drive and output the input signal IN. The basic driving unit 140 may include a first transistor 141 and a second transistor 142. The first transistor 141 can drive the output node to the ground terminal level according to the level of the input signal IN. The second transistor 142 can drive the output node to the power supply terminal level according to the level of the input signal IN.

[0058] The variable drive unit 150 can drive the output signal of the basic drive unit 140 using a drive force that varies according to the drive force control codes STCODE<0:N> and STCODEB<0:N>, and output a drive signal. The variable drive unit 150 may include a first transistor 151, a second transistor 152, a first drive force adjustment circuit 160, and a second drive force adjustment circuit 170. The first drive force adjustment circuit 160 may have a resistance value that varies according to the drive force control code STCODE<0:N>. The first drive force adjustment circuit 160 may include a plurality of transistors 160-1 to 160-N, which are commonly coupled to a ground terminal and configured to receive corresponding bits of the drive force control code STCODE<0:N> through their gate terminals. The first transistor 151 can drive the output node to the ground terminal level according to the output signal of the basic drive unit 140 and has a drive time that is changed by the first drive force adjustment circuit 160. The second drive force adjustment circuit 170 may include a plurality of transistors 170-1 to 170-N, which are commonly coupled to a power supply terminal and configured to receive corresponding bits of the drive force control code STCODEB<0:N> through their gate terminals. The second transistor 152 can drive the output node to the power supply terminal level according to the output signal of the basic drive unit 140, and has a drive time that is changed by the second drive force adjustment circuit 170.

[0059] For reference Figure 5 As described, when the operating speed of semiconductor device 10 is set to low, the first pre-encoded PRECODE0 can be provided to the first through fourth programmable buffers 131-2, 132-2, 133-2, and 134-2 as drive force control codes STCODE<0:3> and STCODEB<0:3>. Since drive force control code STCODE<0:3> is '0000' and drive force control code STCODEB<0:3> is '1111', all transistors in the first drive force adjustment circuit 160 and the second drive force adjustment circuit 170 can be turned off, thereby stopping the operation of the first through fourth programmable buffers 131-2, 132-2, 133-2, and 134-2. Because the operation of the first through fourth programmable buffers 131-2, 132-2, 133-2, and 134-2 has stopped, the first and second correction loops of the ring circuit 101 may also stop. When the semiconductor device 10 operates at a low speed, the skew in the multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB can be minimized. Therefore, the operation of the ring circuit 101 can be stopped to reduce current consumption.

[0060] When the operating speed of the semiconductor device 10 is set to high speed-1, the second precode PRECODE1 can be provided to the first to fourth programmable buffers 131-2, 132-2, 133-2, and 134-2 as drive force control codes STCODE<0:3> and STCODEB<0:3>. The drive force control code STCODE<0:3> has a code value '1000' that is increased compared to the first precode PRECODE0, and the drive force control code STCODEB<0:3> has a code value '0111' that is decreased compared to the first precode PRECODE0. Therefore, the first to fourth programmable buffers 131-2, 132-2, 133-2, and 134-2 can operate to generate the output signal OUT by delaying the input signal IN by a first time and driving the delayed signal. Through the operation of the first to fourth programmable buffers 131-2, 132-2, 133-2 and 134-2, the first correction loop and the second correction loop of the ring circuit 101 can be operated to correct the skew in the multi-phase clock signals ICLK, QCLK, ICLKB and QCLKB.

[0061] When the operating speed of semiconductor device 10 is set to high speed-2, the third precode PRECODE2 can be provided to the first to fourth programmable buffers 131-2, 132-2, 133-2, and 134-2 as drive force control codes STCODE<0:3> and STCODEB<0:3>. The drive force control code STCODE<0:3> has an increased code value '1100' compared to the second precode PRECODE1, and the drive force control code STCODEB<0:3> has a decreased code value '0011' compared to the second precode PRECODE1. Therefore, the first to fourth programmable buffers 131-2, 132-2, 133-2, and 134-2 can operate to generate an output signal OUT by delaying the input signal IN by a second time and driving the delayed signal. The second time can be shorter than the first time. Through the operation of the first to fourth programmable buffers 131-2, 132-2, 133-2 and 134-2, the first correction loop and the second correction loop of the ring circuit 101 can be operated to correct the skew in the multi-phase clock signals ICLK, QCLK, ICLKB and QCLKB.

[0062] When the operating speed of semiconductor device 10 is set to high speed -3, the fourth precode PRECODE3 can be provided to the first to fourth programmable buffers 131-2, 132-2, 133-2, and 134-2 as drive force control codes STCODE<0:3> and STCODEB<0:3>. The drive force control code STCODE<0:3> has an increased code value '1110' compared to the third precode PRECODE2, and the drive force control code STCODEB<0:3> has a decreased code value '0001' compared to the third precode PRECODE2. Therefore, the first to fourth programmable buffers 131-2, 132-2, 133-2, and 134-2 can operate to generate the output signal OUT by delaying the input signal IN by a third time and driving the delayed signal. The third time can be shorter than the second time. Through the operation of the first to fourth programmable buffers 131-2, 132-2, 133-2 and 134-2, the first correction loop and the second correction loop of the ring circuit 101 can be operated to correct the skew in the multi-phase clock signals ICLK, QCLK, ICLKB and QCLKB.

[0063] When the operating speed of the semiconductor device 10 is set to low, the first to fourth programmable buffers 131-2, 132-2, 133-2, and 134-2 of the ring circuit 101 can be disabled. Because the first to fourth programmable buffers 131-2, 132-2, 133-2, and 134-2 are disabled, the operation of the first correction circuit may cease, and the operation of the second correction circuit may partially cease.

[0064] When the operating speed of the semiconductor device 10 is set to high speed-1, high speed-2, or high speed-3, the first to fourth programmable buffers 131-2, 132-2, 133-2, and 134-2 can be enabled, and the first and second correction circuits can operate to correct the skew in the multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB. The semiconductor device 10 can reduce the signal processing delay time of the first to fourth programmable buffers 131-2, 132-2, 133-2, and 134-2 according to the drive force control codes STCODE<0:3> and STCODEB<0:3>, thereby making the signal processing delay time suitable for the operating speed, i.e., suitable for high speed-1, high speed-2, or high speed-3.

[0065] The following will be referenced Figure 8 and Figure 9 The operation of the ring circuit 101 will be described below. The ring circuit 101 of the semiconductor device 10 according to the present embodiment may include a plurality of correction loops, and the skew correction operations of the plurality of correction loops may be performed simultaneously.

[0066] Figure 8 This is a diagram showing the structure of the first correction loop 101-1 of the phase correction circuit according to the present embodiment.

[0067] refer to Figure 8 The first correction circuit 101-1 can perform skew correction by averaging the phases of two adjacent signals based on the first to fourth signal paths 31 to 34 in the multi-phase clock signals ICLK, QCLK, ICLKB and QCLKB.

[0068] The first correction circuit 101-1 can be configured by the first to fourth programmable buffers 131-2, 132-2, 133-2 and 134-2.

[0069] The first programmable buffer 131-2 can mix the signal from the first signal path 31 into the second signal path 32, the second programmable buffer 132-2 can mix the signal from the second signal path 32 into the third signal path 33, the third programmable buffer 133-2 can mix the signal from the third signal path 33 into the fourth signal path 34, and the fourth programmable buffer 134-2 can mix the signal from the fourth signal path 34 into the first signal path 31. The loop configured by the first to fourth programmable buffers 131-2, 132-2, 133-2 and 134-2 can be repeatedly operated to average the phases of the multi-phase clock signals ICLK, QCLK, ICLKB and QCLKB, thereby correcting the phase skew of the signal among the multi-phase clock signals ICLK, QCLK, ICLKB and QCLKB that has experienced phase skew.

[0070] The phase skew correction operation for the QCLK_O signal will be described below, assuming the phase skew occurs in the QCLK_O signal of the second signal path 32. The signal PGM BUF_OUT can be generated after the delay time of the first signal path 31 and the time Δt caused by the drive delay of the first programmable buffer 131-2. Since the signal PGM BUF_OUT is mixed into the node of the signal QCLK_O, the phase of the signal QCLK_O can be corrected to a phase corresponding to the average of the phases of the signals PGM BUF_OUT and QCLK_O. Figure 8 Only an example of the phase skew correction process for clock signals ICLK and QCLK in the multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB is shown. The phase skew correction process for clock signals QCLK and ICLKB, clock signals ICLKB and QCLKB, and clock signals QCLKB and ICLK can also be performed in the same manner.

[0071] Figure 9This is a diagram showing the structure of the second correction loop 101-2 of the phase correction circuit according to an embodiment.

[0072] refer to Figure 9 The second correction circuit 101-2 can perform skew correction by averaging the phases of the complementary signals in the multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB. The second correction circuit 101-2 can perform skew correction by averaging the phases of clock signals ICLK and ICLKB, and clock signals QCLK and QCLKB.

[0073] The second correction circuit 101-2 can be configured with first to fourth programmable buffers 131-2, 132-2, 133-2 and 134-2 and first to fourth signal transmission units 131-1, 132-1, 133-1 and 134-1.

[0074] The second correction circuit 101-2 can correct the phase skew of the multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB by repeatedly performing a cyclic operation that combines the mixing operation with the operation of the first to fourth programmable buffers 131-2, 132-2, 133-2, and 134-2. The mixing operation refers to mixing the signal of the first signal path 31 into the third signal path 33, mixing the signal of the second signal path 32 into the fourth signal path 34, mixing the signal of the third signal path 33 into the first signal path 31, and mixing the signal of the fourth signal path 34 into the second signal path 32.

[0075] The phase skew correction operation for signal ICLKB_O will be described below, assuming the phase skew occurs at signal ICLKB_O in the third signal path 33. Signal ICLK_O, which is complementary to signal ICLKB_O, can be generated as signal ICLKB_OOa by the first signal transmission unit 131-1. As ICLKB_O passes through the inverter in the third signal path 33, signal ICLKB_OOb is generated. Since signals ICLKB_OOa and ICLKB_OOb are mixed at the same node, signal ICLKB_OO, obtained by averaging the phases of the two signals, can be output as the phase correction clock signal ICLKBC. In this way, the phase of signal ICLKB_O can be corrected. Figure 9Only an example of the phase skew correction process for clock signals ICLK and ICLKB out of the multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB is shown. The phase skew correction process for clock signals QCLK and QCLKB can also be performed in the same manner.

[0076] Figure 10 This is a diagram illustrating the structure of a semiconductor device 20 according to another embodiment.

[0077] refer to Figure 10 The semiconductor device 20 may include a clock buffer 21, a memory region 30, and a data output circuit 40. The semiconductor device 20 may also include an MRS 50 and a code control circuit 60.

[0078] Clock buffer 21 can receive data clock signals WCK and WCKB and generate multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB. Clock buffer 21 can perform phase correction operations by combining a signal from at least one of the multiple signal paths 31 to 34 with another signal from another signal path to compensate for skew in the multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB, thereby generating phase-corrected clock signals ICLKC, QCLKC, ICLKBC, and QCLKBC. Clock buffer 21 can determine whether to perform the phase correction operation based on the operating frequency of the semiconductor device 20. Clock buffer 11 can change the driving force according to the operating frequency of the semiconductor device 20 during the phase correction operation.

[0079] The clock buffer 21 may include a phase separator 22, multiple phase correction circuits 200-1 to 200-N, and multiple signal paths 31 to 34.

[0080] Phase splitter 22 can receive data clock signals WCK and WCKB and generate multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB. Phase splitter 22 can separate the phases of data clock signals WCK and WCKB and simultaneously divide the frequencies of data clock signals WCK and WCKB, so that each multi-phase clock signal ICLK, QCLK, ICLKB, and QCLKB has a frequency that is 2 or 4 times that of the external clock signals WCK and WCKB.

[0081] Multiple phase correction circuits 200-1 to 200-N may each include multiple signal paths 31 to 34. Each phase correction circuit 200-1 to 200-N can perform a phase correction operation to compensate for skew in multi-phase clock signals ICLK, QCLK, ICLKB, and QCLKB by combining a signal from at least one of the multiple signal paths 31 to 34 with another signal from another signal path. The multiple phase correction circuits 200-1 to 200-N can interrupt the phase correction operation in response to drive force control codes STCODE<0:N> and STCODEB<0:N>. The multiple phase correction circuits 200-1 to 200-N can change the drive force of the phase correction operation in response to drive force control codes STCODE<0:N> and STCODEB<0:N>. The multiple phase correction circuits 200-1 to 200-N can be used with a reference... Figures 2 to 6 The phase correction circuit 100 described is configured in the same manner.

[0082] The memory area 30, data output circuit 40, MRS 50, and code control circuit 60 can be connected with... Figure 2 Configure in the same way.

[0083] According to another embodiment, the clock buffer 21 of the semiconductor device 20 may include a plurality of phase correction circuits 200-1 to 200-N coupled to a plurality of signal paths 31 to 34. Therefore, the plurality of phase correction circuits 200-1 to 200-N can repeatedly perform phase correction operations on the output of a previous phase correction circuit, which makes it possible to... Figure 2 Compared to the semiconductor device 10, the phase correction performance can be further improved.

[0084] Although various embodiments have been described above, those skilled in the art will understand that the described embodiments are merely examples. Therefore, the phase correction circuits, clock buffers, and semiconductor devices described herein should not be limited to the described embodiments.

Claims

1. A phase correction circuit, comprising: Multiple signal paths for transmitting multi-phase signals; as well as A ring circuit that corrects phase skew in the multi-phase signal by performing a phase averaging operation by combining the signal of each of the plurality of signal paths with another signal of another signal path different from the corresponding signal path.

2. The phase correction circuit according to claim 1, wherein, The ring circuit is disabled when the operating frequency is less than a preset value.

3. The phase correction circuit according to claim 1, wherein, The ring circuit is disabled when the operating frequency is less than a preset value; and The ring circuit has a driving force that varies according to the value of the operating frequency when the operating frequency is equal to or greater than the preset value.

4. The phase correction circuit according to claim 1, wherein, The plurality of signal paths includes a first signal path, a second signal path, a third signal path, and a fourth signal path. The ring circuit includes: The first signal transmission unit inverts the signal at the first node of the first signal path and transmits the inverted signal to the second node of the third signal path. A first programmable buffer buffers signals from a second node of the first signal path and transmits the buffered signals to a first node of the second signal path. The second signal transmission unit inverts the signal at the first node of the second signal path and transmits the inverted signal to the second node of the fourth signal path. A second programmable buffer buffers the signal of the second node of the second signal path and transmits the buffered signal to the first node of the third signal path. The third signal transmission unit inverts the signal at the first node of the third signal path and transmits the inverted signal to the second node of the first signal path. A third programmable buffer buffers the signal of the second node of the third signal path and transmits the buffered signal to the first node of the fourth signal path. A fourth signal transmission unit inverts the signal at the first node of the fourth signal path and transmits the inverted signal to the second node of the second signal path; and A fourth programmable buffer buffers the signal of the second node of the fourth signal path and transmits the buffered signal to the first node of the first signal path.

5. A phase correction circuit, comprising: Multiple signal paths for transmitting multi-phase signals; A first correction circuit synthesizes two signals in the multi-phase signal that are transmitted through two adjacent signal paths among the plurality of signal paths; and The second correction circuit synthesizes the complementary signal in the multiphase signal.

6. The phase correction circuit according to claim 5, wherein, The first correction circuit is disabled when the operating frequency is less than a preset value.

7. The phase correction circuit according to claim 5, wherein: The first correction circuit is disabled when the operating frequency is less than a preset value; and The first correction circuit has a driving force that varies according to the value of the operating frequency when the operating frequency is equal to or greater than the preset value.

8. The phase correction circuit according to claim 5, wherein, The plurality of signal paths includes a first signal path, a second signal path, a third signal path, and a fourth signal path, and The first correction circuit includes: A first programmable buffer buffers signals from a second node of the first signal path and transmits the buffered signals to a first node of the second signal path. A second programmable buffer buffers the signal of the second node of the second signal path and transmits the buffered signal to the first node of the third signal path. A third programmable buffer buffers the signal from the second node of the third signal path and transmits the buffered signal to the first node of the fourth signal path; and A fourth programmable buffer buffers the signal of the second node of the fourth signal path and transmits the buffered signal to the first node of the first signal path.

9. The phase correction circuit according to claim 8, wherein, The first correction circuit further includes: A first signal transmission unit inverts the signal at the first node of the first signal path and transmits the inverted signal to the second node of the third signal path. The second signal transmission unit inverts the signal at the first node of the second signal path and transmits the inverted signal to the second node of the fourth signal path. A third signal transmission unit inverts the signal at the first node of the third signal path and transmits the inverted signal to the second node of the first signal path; and A fourth signal transmission unit inverts the signal at the first node of the fourth signal path and transmits the inverted signal to the second node of the second signal path.

10. A clock buffer, comprising: A phase splitter that receives an external clock signal and generates a multi-phase clock signal; as well as A phase correction circuit is coupled to multiple signal paths for transmitting the multi-phase clock signal. The phase correction circuit corrects the phase skew in the multi-phase clock signal by performing a phase averaging operation by combining the signal of each of the multiple signal paths with another signal of another signal path different from the corresponding signal path.

11. The clock buffer of claim 10, wherein, The phase correction circuit includes: A first correction circuit synthesizes two signals in the multi-phase clock signal that are transmitted through two adjacent signal paths among the plurality of signal paths; and The second correction circuit synthesizes the complementary signal in the multi-phase clock signal.

12. The clock buffer according to claim 11, wherein, The first correction circuit includes a plurality of programmable buffers, each of which has an adjustable driving force. The plurality of programmable buffers are disabled when the operating frequency is less than a preset value, and each of the plurality of programmable buffers has a driving force that varies according to the value of the operating frequency when the operating frequency is equal to or greater than the preset value.

13. The clock buffer according to claim 11, wherein, The plurality of signal paths includes a first signal path, a second signal path, a third signal path, and a fourth signal path. The first correction circuit includes: A first programmable buffer buffers signals from a second node of the first signal path and transmits the buffered signals to a first node of the second signal path. A second programmable buffer buffers the signal of the second node of the second signal path and transmits the buffered signal to the first node of the third signal path. A third programmable buffer buffers the signal from the second node of the third signal path and transmits the buffered signal to the first node of the fourth signal path; and A fourth programmable buffer buffers the signal of the second node of the fourth signal path and transmits the buffered signal to the first node of the first signal path.

14. The clock buffer according to claim 13, wherein, The first correction circuit further includes: A first signal transmission unit inverts the signal at the first node of the first signal path and transmits the inverted signal to the second node of the third signal path. The second signal transmission unit inverts the signal at the first node of the second signal path and transmits the inverted signal to the second node of the fourth signal path. A third signal transmission unit inverts the signal at the first node of the third signal path and transmits the inverted signal to the second node of the first signal path; and A fourth signal transmission unit inverts the signal at the first node of the fourth signal path and transmits the inverted signal to the second node of the second signal path.

15. A semiconductor device, comprising: Memory area; A data output circuit that outputs data from the memory region to the outside of the semiconductor device according to a phase-corrected clock signal; as well as A clock buffer receives an external clock signal, generates a multi-phase clock signal, and generates the phase-corrected clock signal by performing a phase averaging operation on the signal of each of the multiple signal paths used to transmit the multi-phase clock signal and the signal of another signal path.

16. The semiconductor device according to claim 15, wherein, The clock buffer includes: A phase separator that receives the external clock signal and generates the multi-phase clock signal; A first correction circuit synthesizes two signals in the multi-phase clock signal that are transmitted through two adjacent signal paths among the plurality of signal paths; and The second correction circuit synthesizes the complementary signal in the multi-phase clock signal.

17. The semiconductor device according to claim 16, wherein, The first correction circuit includes a plurality of programmable buffers, each of which has an adjustable driving force. The plurality of programmable buffers are disabled when the operating frequency of the semiconductor device is less than a preset value, and each of the plurality of programmable buffers has a driving force that varies according to the value of the operating frequency when the operating frequency is equal to or greater than the preset value.

18. The semiconductor device according to claim 16, wherein, The plurality of signal paths includes a first signal path, a second signal path, a third signal path, and a fourth signal path. The first correction circuit includes: A first programmable buffer buffers signals from a second node of the first signal path and transmits the buffered signals to a first node of the second signal path. A second programmable buffer buffers the signal of the second node of the second signal path and transmits the buffered signal to the first node of the third signal path. A third programmable buffer buffers the signal from the second node of the third signal path and transmits the buffered signal to the first node of the fourth signal path; and A fourth programmable buffer buffers the signal of the second node of the fourth signal path and transmits the buffered signal to the first node of the first signal path.

19. The semiconductor device according to claim 18, wherein, The first correction circuit further includes: A first signal transmission unit inverts the signal at the first node of the first signal path and transmits the inverted signal to the second node of the third signal path. The second signal transmission unit inverts the signal at the first node of the second signal path and transmits the inverted signal to the second node of the fourth signal path. A third signal transmission unit inverts the signal at the first node of the third signal path and transmits the inverted signal to the second node of the first signal path; and A fourth signal transmission unit inverts the signal at the first node of the fourth signal path and transmits the inverted signal to the second node of the second signal path.

20. A phase correction circuit, comprising: A ring circuit coupled to multiple signal paths transmitting a multi-phase clock signal, the ring circuit performing at least one of the operations of synthesizing two signals transmitted through two adjacent signal paths in the multi-phase clock signal and synthesizing complementary signals in the multi-phase clock signal; Multiple programmable buffers are coupled to the multiple signal paths, and the multiple programmable buffers operate in response to control codes; as well as A code control circuit that generates the control code in response to operating frequency information. The phase correction circuit corrects the phase skew in the multi-phase clock signal by controlling the driving force of the programmable buffer and the phase averaging of the two signals synthesized by the ring circuit according to the control code.

21. The phase correction circuit according to claim 20, wherein, The ring circuit includes: A first correction circuit, which synthesizes two adjacent signals based on the plurality of signal paths in the multi-phase clock signal; and The second correction circuit synthesizes the complementary signal in the multi-phase clock signal.

22. The phase correction circuit according to claim 20, wherein, The programmable buffer is disabled when the operating frequency defined in the operating frequency information is less than a preset value, according to the control code; and Each of the programmable buffers has a driving force that varies according to the value of the operating frequency when the operating frequency is equal to or greater than the preset value.

23. The phase correction circuit according to claim 20, wherein, The code control circuit includes: Code storage circuit, which stores pre-encoded codes; and A multiplexer that selects one of the precodes based on the operating frequency information and outputs the selected code as the control code.

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