Memory system and method of operating the memory system

Abstract

The present disclosure relates to a memory system and a method of operating the same. A memory device includes a memory block, a peripheral circuit, and control logic. The memory block includes a plurality of string groups respectively connected to corresponding selection lines among a plurality of selection lines. The peripheral circuit performs a program operation of data on the memory block. The control logic controls the program operation of the peripheral circuit. The memory block is connected to a first word line to an n-th word line. The control logic is configured to control the peripheral circuit to perform, among physical pages included in a first string group, a first program operation on a physical page connected to an i-th word line, a second program operation on a physical page connected to an i-1-th word line, and a dummy program operation on a physical page connected to an i+1-th word line. Here, n is a natural number equal to or greater than 3, and i is a natural number greater than 0 and less than n-1.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0102206, filed on August 3, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to electronic devices, and more specifically, to memory systems and methods of operating such memory systems. Background Technology

[0004] Memory devices can be formed in a two-dimensional structure (where strings are arranged horizontally on a semiconductor substrate) or a three-dimensional structure (where strings are stacked vertically on a semiconductor substrate). Three-dimensional memory devices are designed to address the integration limitations of two-dimensional memory devices and can include multiple memory cells stacked vertically on a semiconductor substrate. A memory system may include a memory device and a controller that controls the memory device. Summary of the Invention

[0005] According to one embodiment of this disclosure, a memory device includes a memory block, peripheral circuitry, and control logic. The memory block includes multiple serial groups connected to corresponding select lines among a plurality of select lines. The peripheral circuitry performs data programming operations on the memory block. The control logic controls the programming operations of the peripheral circuitry. The memory block is connected to first word lines through n word lines. The control logic controls the peripheral circuitry to perform a first programming operation on physical pages connected to the i-th word line, a second programming operation on physical pages connected to the (i-1)-th word line, and a dummy programming operation on physical pages connected to the (i+1)-th word line, all within physical pages included in the first serial group. Here, n is a natural number equal to or greater than 3, and i is a natural number greater than 0 and less than n-1.

[0006] According to another embodiment of this disclosure, a method of operating a memory system involves reprogramming a memory block comprising multiple serial groups. The method includes: performing a first programming operation on a physical page connected to an i-th word line among multiple physical pages included in a first serial group, and performing a second programming operation on a physical page connected to an (i-1)-th word line; performing the first programming operation on a physical page connected to an i-th word line among multiple physical pages included in a second serial group, and performing a second programming operation on a physical page connected to an (i-1)-th word line; performing a dummy programming operation on a physical page connected to an (i+1)-th word line among multiple physical pages included in the first serial group, and performing a second programming operation on a physical page connected to an i-th word line; and performing a dummy programming operation on a physical page connected to an (i+1)-th word line among multiple physical pages included in the second serial group, and performing a second programming operation on a physical page connected to an i-th word line. Here, i is a natural number greater than 2.

[0007] According to another embodiment of this disclosure, a method for operating a memory system involves performing a programming operation on a memory block comprising multiple serial groups using a reprogramming method. The method includes: performing a first programming operation on physical pages connected to the i-th word line among multiple physical pages included in a first serial group and a second serial group; performing a second programming operation on physical pages connected to the (i-1)-th word line among multiple physical pages included in the first and second serial groups; performing a dummy programming operation on physical pages connected to the (i+1)-th word line among multiple physical pages included in the first and second serial groups; and performing a second programming operation on physical pages connected to the i-th word line among multiple physical pages included in the first and second serial groups. Here, i is a natural number greater than 2. Attached Figure Description

[0008] Figure 1 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0009] Figure 2 It is a diagram. Figure 1 A diagram of a memory device.

[0010] Figure 3 It is a diagram. Figure 2 A diagram of the memory blocks.

[0011] Figure 4 This is a diagram illustrating one embodiment of a memory block configured in three dimensions.

[0012] Figure 5 This is a diagram illustrating another embodiment of a memory block configured in three dimensions.

[0013] Figure 6 This is a diagram illustrating an example of a serial group of configured memory blocks.

[0014] Figure 7 More detailed illustrations Figure 6 The circuit diagram of the first string group shown.

[0015] Figure 8 This is a circuit diagram illustrating a portion of the unit strings included in the first and second string groups.

[0016] Figure 9A This is a diagram illustrating another example of a serial group of configured memory blocks.

[0017] Figure 9B This is a circuit diagram illustrating a portion of the unit strings included in the first to fourth string groups.

[0018] Figure 10 This is a diagram illustrating the threshold voltage distribution of a memory system during programming operations according to an embodiment of the present disclosure.

[0019] Figures 11A to 11F This is a diagram illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0020] Figures 12A to 12D This is a diagram illustrating a method of operating a memory device according to another embodiment of the present disclosure.

[0021] Figure 13 This is a diagram for reference. Figures 12A to 12D A flowchart describing the method for operating a memory device.

[0022] Figures 14A to 14G This is a diagram illustrating a method of operating a memory device according to another embodiment of the present disclosure.

[0023] Figure 15 This is a diagram for reference. Figures 14A to 14G A flowchart describing the method for operating a memory device.

[0024] Figure 16 The illustration includes Figure 2 A diagram of another embodiment of the memory system of the shown memory device.

[0025] Figure 17 The illustration includes Figure 2 A diagram of another embodiment of the memory system of the shown memory device.

[0026] Figure 18 The illustration includes Figure 2 A diagram of another embodiment of the memory system of the shown memory device.

[0027] Figure 19 The illustration includes Figure 2A diagram of another embodiment of the memory system of the shown memory device. Detailed Implementation

[0028] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this specification or application are provided for the purpose of describing embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0029] Embodiments of this disclosure provide a memory system capable of improving the threshold voltage distribution of memory cells after programming, and a method for operating the memory system.

[0030] This technology can provide a memory system capable of improving the threshold voltage distribution of memory cells after programming, and a method for operating the memory system.

[0031] Figure 1 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0032] refer to Figure 1 The memory system 1000 may include a memory device 1100 in which data is stored, and may include a memory controller 1200 that controls the memory device 1100 based on the host 2000.

[0033] The host 2000 can communicate with the memory system 1000 using an interface protocol, such as Peripheral Component Interconnect-Fast (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or Serial Attached SCSI (SAS). Furthermore, the interface protocol between the host 2000 and the memory system 1000 is not limited to the examples above and can be one of other interface protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Panel Interface (ESDI), or Integrated Drive Electronics (IDE).

[0034] The memory controller 1200 can control the overall operation of the memory system 1000 and can control the data exchange between the host 2000 and the memory device 1100. For example, the memory controller 1200 can control the memory device 1100 to program or read data according to a request from the host 2000. Furthermore, the memory controller 1200 can store information about the main memory blocks and sub-memory blocks included in the memory device 1100, and can select the memory device 1100 to perform programming operations on the main memory blocks or sub-memory blocks based on the amount of data loaded for the programming operation. According to one embodiment, the memory device 1100 may include Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), or Flash memory.

[0035] The memory controller 1200 may include a programming sequence controller 1210. When a write request is received from the host 2000, the programming sequence controller 1210 may set a programming order for multiple strings included in a selected memory block of a plurality of memory blocks included in the memory device 1100, to which programming operations are to be performed. For example, the programming sequence controller 1210 may set a programming order such that the multiple strings included in the selected memory block are programmed sequentially. For example, the programming sequence controller 1210 may set a programming order such that a first programming operation is performed sequentially on the multiple strings included in the selected memory block, and subsequently, a second programming operation is performed sequentially on the multiple strings.

[0036] In one embodiment of this disclosure, the programming sequence controller 1210 is illustrated and described as being included in the memory controller 1200, but this disclosure is not limited thereto, and the programming sequence controller 1210 is configured to be included as a component of the memory device 1100.

[0037] The memory device 1100 can perform programming, reading, or erasing operations based on the memory controller 1200.

[0038] Figure 2 It is a diagram. Figure 1 A diagram of a memory device.

[0039] refer to Figure 2The memory device 1100 may include a memory cell array 100 in which data is stored. The memory device 1100 may include peripheral circuitry 200 configured to perform: programming operations for storing data in the memory cell array 100, read operations for outputting the stored data, and erase operations for erasing the stored data. The memory device 1100 may include control logic 300, which is configured according to... Figure 1 The memory controller 1200 controls the peripheral circuit 200.

[0040] Memory cell array 100 may include multiple memory blocks 110 numbered from MB1 to MBk (k being a positive integer). Local lines LL and bit lines BL1 to BLn (n being a positive integer) may be connected to each memory block 110 numbered from MB1 to MBk. For example, local line LL may include a first select line, a second select line, and multiple word lines arranged between the first select line and the second select line. Furthermore, local line LL may include dummy lines arranged between the first select line and the word line and between the second select line and the word line. Here, the first select line may be a source select line, and the second select line may be a drain select line. For example, local line LL may include word lines, drain select lines, and source select lines, and a source line SL. For example, local line LL may also include dummy lines. For example, local line LL may also include pipe lines. Local lines LL may be individually connected to memory blocks 110 numbered from MB1 to MBk, and bit lines BL1 to BLn may be collectively connected to memory blocks 110 numbered from MB1 to MBk. The memory blocks 110, numbered from MB1 to MBk, can be implemented in a two-dimensional or three-dimensional structure. For example, in a two-dimensional memory block 110, the memory cells can be arranged in a direction parallel to the substrate. For example, in a three-dimensional memory block 110, the memory cells can be stacked in a direction perpendicular to the substrate.

[0041] The peripheral circuitry 200 can be configured to perform programming, reading, and erasing operations on the selected memory block 110 based on the control logic 300. For example, the peripheral circuitry 200 can perform a first programming operation, a second programming operation, or a first programming operation through a third programming operation based on the control logic 300.

[0042] As an example, the peripheral circuit 200 can perform programming operations on the selected memory block 110 in the following ways: multi-level cell (MLC) programming method capable of storing two bits of data, three-level cell (TLC) programming method capable of programming three bits of data, four-level cell (QLC) programming method capable of programming four bits of data, etc.

[0043] When data is stored in the memory cell, the peripheral circuitry 200 can perform a programming operation using a reprogramming method that includes a first programming operation and a second programming operation. The first programming operation can be performed to first program the memory cell to a first target level, and the second programming operation can be performed to subsequently program the memory cell to a second target level. The first target level and the second target level can be the same threshold voltage level, or the first target level can be a threshold voltage level lower than the threshold voltage level of the second target level. The reprogramming method described above can include a first programming operation through a y-th programming operation (y is an integer equal to or greater than 2), and the target level for each programming operation can be the same, or the target level for the first programming operation can be lower than the target level of another programming operation.

[0044] The peripheral circuit 200 can perform a first programming operation to sequentially program a plurality of strings included in the selected memory block 110, perform a second programming operation to sequentially program the plurality of strings, and perform a third programming operation to sequentially program the plurality of strings.

[0045] The peripheral circuitry 200 may include a voltage generation circuitry 210, a row decoder 220, a page buffer group 230, a column decoder 240, an input / output circuitry 250, a pass / fail determiner (pass / fail check circuitry) 260, and a source line driver 270.

[0046] The voltage generation circuit 210 can generate various operating voltages Vop used in programming, reading, and erasing operations in response to the operation signal OP_CMD. Furthermore, the voltage generation circuit 210 can selectively discharge the local line LL in response to the operation signal OP_CMD. For example, the voltage generation circuit 210 can generate programming voltage, verification voltage, pass voltage, read voltage, source line voltage, etc., based on control logic 300.

[0047] The row decoder 220 can transmit the operating voltage Vop to the local line LL connected to the selected memory block 110 in response to the row address RADD.

[0048] Page buffer group 230 may include a plurality of page buffers 231 numbered PB1 to PBn connected to bit lines BL1 to BLn. Page buffers 231 numbered PB1 to PBn may operate in response to a page buffer control signal PBSIGNALS. For example, during programming operations, page buffers 231 numbered PB1 to PBn may temporarily store data received by the column decoder 240 and control the potential levels of the corresponding bit lines BL1 to BLn according to the stored data. Furthermore, during programming operations, page buffers 231 numbered PB1 to PBn may be activated sequentially, and during activation, page buffers 231 numbered PB1 to PBn may control the potential levels of the corresponding bit lines according to the temporarily stored data. At this time, the remaining inactive page buffers apply a programming disable voltage (e.g., power supply voltage) to the corresponding bit lines. For example, during a programming operation, page buffer PB1 is activated, and the potential level of bit line BL1 is controlled according to the data stored in page buffer PB1. After programming the memory cell connected to bit line BL1 is completed, page buffer PB2 is activated, and the potential level of bit line BL2 is controlled according to the data stored in page buffer PB2. As described above, page buffers 231 numbered from PB1 to PBn are activated sequentially.

[0049] The column decoder 240 can transfer data between the input / output circuitry 250 and the page buffer group 230 in response to the column address CADD. For example, the column decoder 240 can exchange data with the page buffer 231 via the data line DL, or with the input / output circuitry 250 via the column line CL.

[0050] The input / output circuit 250 can output from... Figure 1 The memory controller 1200 receives the command CMD and address ADD and transmits them to the control logic 300, or it can exchange data DATA with the column decoder 240.

[0051] During a read or verification operation, the pass / fail determiner 260 can generate a reference current in response to the enable bit VRY_BIT<#>, compare the sensed voltage VPB received from the page buffer group 230 with the reference voltage generated by the reference current, and output a pass signal PASS or a failure signal FAIL.

[0052] The source line driver 270 can be connected to the memory cells included in the memory cell array 100 via the source line SL, and can control the voltage of the source nodes. For example, during a read or verify operation, the source line driver 270 can electrically connect the source node of the memory cell to a ground node. Furthermore, during a programming operation, the source line driver 270 can apply a ground voltage to the source node of the memory cell. During an erase operation, the source line driver 270 can apply an erase voltage to the source node of the memory cell. The source line driver 270 can receive a source line control signal CTRL_SL from the control logic 300, and can control the voltage of the source nodes based on the source line control signal CTRL_SL.

[0053] Control logic 300 can output operation signals OP_CMD, row address RADD, page buffer control signals PBSIGNALS, and enable bit VRY_BIT<#> in response to commands CMD and address ADD, and can control peripheral circuitry 200. Furthermore, control logic 300 can determine whether the verification operation passes or fails in response to pass signals PASS or fail signals FAIL.

[0054] According to the embodiments described above in this disclosure, during a programming operation of a selected memory block among a plurality of memory blocks 110 numbered from MB1 to MBk, the memory device 1100 may sequentially select and program a plurality of strings included in the selected memory block. For example, during the programming operation of the MLC method, a first programming operation may be performed to sequentially program a plurality of strings included in the selected memory block 110, and a second programming operation may be performed to sequentially program a plurality of strings. Furthermore, during the programming operation of the MLC method, a first programming operation may be performed to sequentially program a plurality of strings included in the selected memory block 110, a second programming operation may be performed to sequentially program a plurality of strings, and a third programming operation may be performed to sequentially program a plurality of strings.

[0055] Figure 3 It is a diagram. Figure 2 A diagram of the memory blocks.

[0056] refer to Figure 3The memory block 110 can be connected to a plurality of word lines arranged parallel to each other between a first select line and a second select line. Here, the first select line can be a source select line SSL, and the second select line can be a drain select line DSL. More specifically, the memory block 110 can include a plurality of strings ST connected between bit lines BL1 to BLn and the source line SL. Bit lines BL1 to BLn can be connected to strings ST individually, and the source line SL can be connected together to strings ST. Since strings ST can be configured to be identical to each other, as an example, the strings ST connected to the first bit line BL1 will be specifically described.

[0057] A string ST may include, in series between the source line SL and the first bit line BL1, a source selection transistor SST, a plurality of memory cells F1 to F16, and a drain selection transistor DST. However, the invention is not limited thereto. A string ST may include more than one source selection transistor SST and drain selection transistor DST, and may include more than the number of memory cells (F1 to F16) in this embodiment.

[0058] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells F1 to F16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings ST can be connected to the source select line SSL, the gates of the drain select transistor DST can be connected to the drain select line DSL, and the gates of memory cells F1 to F16 can be connected to multiple word lines WL1 to WL16. A group of memory cells in different strings ST that are connected to the same word line can be referred to as a physical page PPG. Therefore, memory block 110 can include physical pages PPGs corresponding to the number of word lines WL1 to WL16.

[0059] A memory cell can store one bit of data. This is often referred to as a single-level cell (SLC). In this case, a physical page (PPG) can store one logical page (LPG) of data. A logical page (LPG) of data can include the number of data bits contained in the cells within a physical page (PPG). Alternatively, a memory cell can store two or more bits of data. This is often referred to as a multi-level cell (MLC). In this case, a physical page (PPG) can store the data of two or more logical pages (LPGs).

[0060] Figure 4 This is a diagram illustrating one embodiment of a memory block configured in three dimensions.

[0061] refer to Figure 4The memory cell array 100 may include multiple memory blocks 110 numbered from MB1 to MBk. Each memory block 110 may include multiple strings ST11 to ST1m and ST21 to ST2m. As an embodiment, each of the multiple strings ST11 to ST1m and ST21 to ST2m may be formed in a 'U' shape. In the first memory block MB1, m strings may be arranged in the row direction (X direction). Figure 4 In this example, two strings are arranged in the column direction (Y direction), but this is for ease of description, and three or more strings can be arranged in the column direction (Y direction).

[0062] Each of the multiple strings ST11 to ST1m and ST21 to ST2m may include at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0063] The source-select transistor (SST), drain-select transistor (DST), and memory cells MC1 to MCn can have similar structures. For example, each of the source-select transistor (SST), drain-select transistor (DST), and memory cells MC1 to MCn may include a channel film, a tunneling insulating film, a charge-trapping film, and a barrier insulating film. For example, a pillar for providing the channel film may be provided in each string. For example, a pillar may be provided in each string for providing at least one of the channel film, tunneling insulating film, charge-trapping film, and barrier insulating film.

[0064] The source selection transistor SST of each string can be connected between the source line SL and memory cells MC1 to MCp.

[0065] As one embodiment, source-select transistors arranged in strings in the same row can be connected to source-select lines extending in the row direction, and source-select transistors arranged in strings in different rows can be connected to different source-select lines. Figure 4 In the first row, the source select transistors ST11 to ST1m can be connected to the first source select line SSL1. The source select transistors ST21 to ST2m in the second row can be connected to the second source select line SSL2.

[0066] In another embodiment, the source selection transistors in series ST11 to ST1m and ST21 to ST2m can be connected together to a single source selection line.

[0067] The first memory cell MC1 to the nth memory cell MCn of each string can be connected between the source select transistor SST and the drain select transistor DST.

[0068] The first memory cells MC1 to the nth memory cell MCn can be divided into first memory cells MC1 to the pth memory cell MCp and the (p+1)th memory cells MCp+1 to the nth memory cell MCn. The first memory cells MC1 to the pth memory cell MCp can be arranged sequentially in the vertical direction (Z-direction) and connected in series between the source selection transistor SST and the channel transistor PT. The (p+1)th memory cells MCp+1 to the nth memory cell MCn can be arranged sequentially in the vertical direction (Z-direction) and connected in series between the channel transistor PT and the drain selection transistor DST. The first memory cells MC1 to the pth memory cell MCp and the (p+1)th memory cells MCp+1 to the nth memory cell MCn can be connected to each other via the channel transistor PT. The gates of each string of first memory cells MC1 to the nth memory cell MCn can be connected to the first word line WL1 to the nth word line WLn, respectively.

[0069] As an example, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. When a dummy memory cell is provided, the voltage or current of the corresponding string can be stably controlled. The gate of the pipe transistor PT of each string can be connected to the pipe line PL.

[0070] The drain select transistor (DST) of each string can be connected between the bit line and memory cells MCp+1 to MCn. Strings arranged in the row direction can be connected to drain select lines extending in the row direction. The drain select transistors of strings ST11 to ST1m in the first row can be connected to the first drain select line DSL1. The drain select transistors of strings ST21 to ST2m in the second row can be connected to the second drain select line DSL2.

[0071] A string arranged in the column direction can be connected to a bit line extending in the column direction. Figure 4 In the first column, strings ST11 and ST21 can be connected to the first bit line BL1. Strings ST1m and ST2m in the m-th column can be connected to the m-th bit line BLm.

[0072] In a string arranged in a row direction, memory cells connected to the same word line can be configured as a page. For example, memory cells in the first row of strings ST11 to ST1m connected to the first word line WL1 can be configured as a page. Memory cells in the second row of strings ST21 to ST2m connected to the first word line WL1 can be configured as another page. A string arranged in a row direction will be selected by selecting either the drain select line DSL1 or DSL2. A page of the selected string will be selected by selecting any one of the word lines WL1 to WLn.

[0073] Figure 5 This is a diagram illustrating another embodiment of a memory block configured in three dimensions.

[0074] refer to Figure 5 The memory cell array 100 may include multiple memory blocks 110 numbered from MB1 to MBk. Each memory block 110 may include multiple strings ST11' to ST1m' and ST21' to ST2m'. Each of the multiple strings ST11' to ST1m' and ST21' to ST2m' may extend along the vertical direction (Z direction). Within block 110, m strings may be arranged in the row direction (X direction). Figure 5 In this example, two strings are arranged in the column direction (Y direction), but this is for ease of description, and three or more strings can be arranged in the column direction (Y direction).

[0075] Each of the multiple strings ST11' to ST1m' and ST21' to ST2m' may include at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn and at least one drain selection transistor DST.

[0076] The source select transistor SST of each string can be connected between the source line SL and memory cells MC1 to MCn. Source select transistors of strings arranged in the same row can be connected to the same source select line. The source select transistors of strings ST11' to ST1m' arranged in the first row can be connected to the first source select line SSL1. The source select transistors of strings ST21' to ST2m' arranged in the second row can be connected to the second source select line SSL2. As another embodiment, the source select transistors of strings ST11' to ST1m' and ST21' to ST2m' can be connected to a single source select line.

[0077] The first memory cells MC1 to the nth memory cell MCn in each string can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first memory cells MC1 to the nth memory cell MCn can be connected to the first word line WL1 to the nth word line WLn, respectively.

[0078] As one embodiment, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. When a dummy memory cell is provided, the voltage or current of the corresponding string can be stably controlled. Therefore, the reliability of the data stored in memory block 110 can be improved.

[0079] The drain select transistor (DST) of each string can be connected between the bit line and memory cells MC1 to MCn. The drain select transistors (DST) of strings arranged in the row direction can be connected to drain select lines extending in the row direction. The drain select transistors (DST) of strings ST11' to ST1m' can be connected to the first drain select line DSL1. The drain select transistors (DST) of strings ST21' to ST2m' can be connected to the second drain select line DSL2.

[0080] That is, in addition to excluding the pipe transistor PT from each string, Figure 5 The memory block 110 can have the same as Figure 4 The equivalent circuit of memory block 110 is similar to the equivalent circuit.

[0081] Figure 6 This is a diagram illustrating an example of a serial group of configured memory blocks.

[0082] refer to Figure 6 It shows that it includes Figure 4 or Figure 5 The memory blocks shown are string groups STRING GROUP 1 and STRING GROUP 2. See also, for example, a reference. Figure 4 The string groups included in memory block MB1 can be defined as cell strings sharing a drain select line or a source select line. For example, in Figure 4 In this configuration, the unit strings ST11 to ST1m that share the first drain selection line DSL1 and the first source selection line SSL1 can be configured as the first string group STRING GROUP 1. Simultaneously, the unit strings ST21 to ST2m that share the second drain selection line DSL2 and the second source selection line SSL2 can be configured as the second string group STRING GROUP 2.

[0083] As another example, in Figure 5 In this configuration, cell strings ST11' to ST1m' sharing the first drain select line DSL1 and the first source select line SSL1 can be configured as a first string group STRING GROUP 1. Simultaneously, cell strings ST21' to ST2m' sharing the second drain select line DSL2 and the second source select line SSL2 can be configured as a second string group STRING GROUP 2. The memory block may include two string groups, STRING GROUP 1 and STRING GROUP 2, arranged in the +X direction. Each string group in STRING GROUP 1 and STRING GROUP 2 may include cell strings arranged in the row direction (i.e., the +Y direction). Simultaneously, each string group in STRING GROUP 1 and STRING GROUP 2 may include pages arranged in the string direction (i.e., the +Z direction). See later for reference. Figure 7 and Figure 8 A more detailed description of the configuration for each string group is provided.

[0084] Figure 7 More detailed illustrations Figure 6 The circuit diagram of the first string group is shown. Since the second string group can also have the same configuration as the first string group, a detailed circuit diagram of the second string group is omitted.

[0085] refer to Figure 7 The first string group 1 may include unit strings ST11 to ST1m that share a first drain select line DSL1 and a first source select line SSL1. That is, unit strings ST11 to ST1m included in the first string group 1 can be jointly connected to the first drain select line DSL1 and the first source select line SSL1. Unit strings ST11 to ST1m can be arranged in the first string group 1 in the +Y direction. The corresponding unit strings ST11 to ST1m can be connected to the corresponding bit lines BL1 to BLm.

[0086] Meanwhile, the first STRING GROUP 1 may include pages PAGE11 to PAGE1n arranged in the +Z direction. Each page in PAGE11 to PAGE1n may be a collection of memory cells connected to corresponding word lines WL1 to WLn. Therefore, each page in PAGE11 to PAGE1n may be referred to as a "physical page".

[0087] In the case where the memory device includes SLC, one physical page can correspond to one logical page. In the case where the memory device includes MLC, one physical page can correspond to two logical pages. In the case where the memory device includes TLC, one physical page can correspond to three logical pages. In the case where the memory device includes QLC, one physical page can correspond to four logical pages.

[0088] Although Figure 7 Although not shown, the second string group 2 may also include unit strings ST21 to ST2m arranged in the +Y direction. Simultaneously, the second string group 2 may include pages PAGE21 to PAGE2n arranged in the +Z direction.

[0089] Figure 8 This is a circuit diagram illustrating a portion of the unit strings included in the first and second string groups.

[0090] refer to Figure 8The diagram shows the unit string ST11 included in the first string group STRING GROUP 1 and the unit string ST21 included in the second string group STRING GROUP 2. Figure 8 It can be illustrated in the +Y direction. Figure 6 The circuit diagram of the memory block is shown. Therefore, in Figure 8 In the diagram, unit strings ST12 to ST1m included in the first string group STRING GROUP 1 and unit strings ST22 to ST2m included in the second string group STRING GROUP 2 are not shown.

[0091] The first string group STRING GROUP 1's cell string ST11 may include memory cells MC11 to MC1n connected between the first drain select transistor DST1 and the first source select transistor SST1. The second string group STRING GROUP 2's cell string ST21 may include memory cells MC21 to MC2n connected between the second drain select transistor DST2 and the second source select transistor SST2.

[0092] Cell string ST11, included in the first string group STRING GROUP 1, and cell string ST21, included in the second string group STRING GROUP 2, can be connected together to bit line BL1. Simultaneously, page buffer PB1 can also be connected together to bit line BL1. That is, cell string ST11, included in the first string group STRING GROUP 1, and cell string ST21, included in the second string group STRING GROUP 2, can share page buffer PB1.

[0093] Figure 9A This is another example diagram illustrating a serial group of memory blocks. Meanwhile, Figure 9B This is a circuit diagram illustrating a portion of the unit strings included in the first to fourth string groups.

[0094] refer to Figure 9A The memory block may include four string groups STRING GROUP 1 through STRING GROUP 4. As described above, the string groups included in the memory block may be defined as cell strings sharing a drain select line or a source select line. Figure 6 The memory block shown can include two string groups, but as Figure 9A As shown, the memory block can be configured to include four string groups.

[0095] refer to Figure 9BThe diagram shows the unit string ST11 included in the first string group STRING GROUP 1, the unit string ST21 included in the second string group STRING GROUP 2, the unit string ST31 included in the third string group STRING GROUP 3, and the unit string ST41 included in the fourth string group STRING GROUP 4. Figure 9B It can be illustrated in the +Y direction. Figure 9A The circuit diagram of the memory block shown is shown.

[0096] The first string group STRING GROUP 1, string ST11, may include memory cells MC11 to MC1n connected between the first drain select transistor DST1 and the first source select transistor SST1. The second string group STRING GROUP 2, string ST21, may include memory cells MC21 to MC2n connected between the second drain select transistor DST2 and the second source select transistor SST2. The third string group STRING GROUP 3, string ST31, may include memory cells MC31 to MC3n connected between the third drain select transistor DST3 and the third source select transistor SST3. The fourth string group STRING GROUP 4, string ST41, may include memory cells MC41 to MC4n connected between the fourth drain select transistor DST4 and the fourth source select transistor SST4.

[0097] refer to Figures 6 to 8 This describes a memory block with two string groups. However, as... Figure 9A and Figure 9B As shown, a memory block with four serial groups can also be configured.

[0098] Figure 10 This is a threshold voltage distribution diagram illustrating programming operations of a memory system according to an embodiment of the present disclosure. (Reference) Figure 10 According to one embodiment of the present disclosure, the memory system programs the memory cells using a reprogramming method.

[0099] When a write request and data are input from the host 2000, the memory controller 1200 can generate a command CMD in response to the write request to control the write operation of the memory device 1100, and can convert the address received with the write request into the address of the memory device 1100 to generate a converted address ADD.

[0100] In response to a write request, the programming sequence controller 1210 of the memory controller 1200 can set a programming order for multiple strings included in a selected memory block among multiple memory blocks included in the memory device 1100, to which programming operations are to be performed. For example, the programming sequence controller 1210 can set a programming order such that multiple strings included in the selected memory block are selected and programmed sequentially.

[0101] The memory controller 1200 can transfer commands (CMD), data, and addresses (ADD) to the memory device 1100.

[0102] In response to the command CMD and the address ADD, the control logic 300 of the memory device 1100 can output the operation signal OP_CMD, the row address RADD, and the page buffer control signal PBSIGNALS, so that the peripheral circuitry 200 performs a first programming operation on the selected physical page configured by the memory cell connected to the word line WL1 in the selected memory block (e.g., MB1). Subsequently, after performing the first programming operation or the second programming operation on another physical page, a second programming operation can be performed on the selected physical page.

[0103] refer to Figure 10 The first programming operation can either maintain the threshold voltage of the memory cell in the erase state S0 as is, or program the threshold voltage of the memory cell to a state higher than the target levels PV1*, PV2*, and PV3*. In this case, the target levels PV1*, PV2*, and PV3* of the first programming operation can be lower than the target levels PV1, PV2, and PV3 of the second programming operation. Furthermore, as another embodiment, the target levels PV1*, PV2*, and PV3* of the first programming operation and the target levels PV1, PV2, and PV3 of the second programming operation can be set identically. As a result of the first programming operation, the memory cell can be programmed to have one of the programming states S0, S1*, S2*, and S3*. Simultaneously, the second programming operation can be an operation that, after the first programming operation, maintains the threshold voltage of the memory cell in the erase state S0, or programs the threshold voltage of the memory cell to a state higher than the target levels PV1, PV2, and PV3. As a result of the second programming operation, the memory cell can be programmed to have one of the programming states S0, S1, S2, and S3.

[0104] In embodiments of this application, a first programming operation and a second programming operation may be included in the reprogramming operation. However, the invention is not limited thereto. The reprogramming operation may include the first programming operation to the y-th programming operation (y is an integer equal to or greater than 2), and the target level of each programming operation may be equal to each other, or the target level of the first programming operation may be lower than the target level of another programming operation. The reprogramming operation can be used to improve the threshold voltage distribution of memory cells.

[0105] At the same time, as an example reference Figure 10 The reprogramming method is described, but the reprogramming method can also be applied to TLC or QLC.

[0106] Figures 11A to 11F This is a diagram illustrating a method of operating a memory device according to an embodiment of the present disclosure.

[0107] Figures 11A to 11F Multiple pages connected to the first word line WL1 through the nth word line WLn are shown. More specifically, the first string group ST1 may include the first physical page through the nth physical page. The first physical page through the nth physical page can be programmed using a reprogramming method. That is, in order to program a physical page, a first programming operation and a second programming operation can be performed. The verification voltage of the first programming operation may be less than the verification voltage of the second programming operation.

[0108] exist Figures 11A to 11B In this context, a physical page connected to each word line is represented by two connected quadrilaterals to indicate this characteristic. Simultaneously, the numbers written into each quadrilateral indicate the programming order of the data.

[0109] More specifically, see reference Figure 11A The first programming operation (1) can be performed on the physical pages connected to the first word line WL1, which are among the n physical pages included in the first string group ST1. To indicate this, in Figure 11A In the first quadrilateral of the two quadrilaterals connected to the first word line WL1 within the physical page indicating the first string group ST1, the number "1" is written. This means that it is possible to... Figure 11A The first physical page of the first group ST1 in the shown physical pages performs the first programming operation. Meanwhile, in Figure 11A In the diagram, the number "1" is shown in the first quadrilateral of the two quadrilaterals connecting to the first word line WL1 within the physical page of the first string group ST1, and the second quadrilateral is empty. This means that the first programming operation can only be performed on the physical page connected to the first word line WL1 within the physical page of the first string group ST1, and the second programming operation is not performed.

[0110] Refer again Figure 11AAfter performing the first programming operation (1) on the physical pages of the first string group ST1 connected to the first word line WL1, the first programming operation (2) can be performed on the physical pages of the second string group ST2 connected to the first word line WL1. Thereafter, the first programming operation (3) can be performed on the physical pages of the third string group ST3 connected to the first word line WL1, and the first programming operation (4) can be performed on the physical pages of the fourth string group ST4 connected to the first word line WL1.

[0111] refer to Figure 11B In the first quadrilateral of the two quadrilaterals indicating the physical page of the first string group ST1 connected to the second word line WL2, the number "5" is written. Therefore, after performing the first programming operation (4) on the physical page of the fourth string group ST4 connected to the first word line WL1, the first programming operation can be performed on the physical page of the first string group ST1 connected to the second word line WL2. Afterwards, in the second quadrilateral of the two quadrilaterals indicating the physical page of the first string group ST1 connected to the first word line WL1, the number "6" is written. Therefore, after performing the first programming operation (5) on the physical page of the first string group ST1 connected to the second word line WL2, the second programming operation can be performed on the physical page of the first string group ST1 connected to the first word line WL1.

[0112] In a similar manner, after performing a second programming operation (6) on the physical page of the first string group ST1 connected to the first word line WL1, a first programming operation (7) is performed on the physical page of the second string group ST2 connected to the second word line WL2, and a second programming operation (8) can be performed on the physical page of the second string group ST2 connected to the first word line WL1.

[0113] Subsequently, a first programming operation (9) can be performed on the physical page of the third string group ST3 connected to the second word line WL2, and a second programming operation (10) can be performed on the physical page of the third string group ST3 connected to the first word line WL1.

[0114] Finally, a first programming operation (11) can be performed on the physical page of the fourth string group ST4 connected to the second word line WL2, and a second programming operation (12) can be performed on the physical page of the fourth string group ST4 connected to the first word line WL1.

[0115] refer to Figure 11C This can be used as a reference. Figure 11BThe same programming operation is performed continuously. That is, after the second programming operation (12) can be performed on the physical page of the fourth string group ST4 connected to the first word line WL1, the first programming operation (13) can be performed on the physical page of the first string group ST1 connected to the third word line WL3, and the second programming operation (14) can be performed on the physical page of the first string group ST1 connected to the second word line WL2.

[0116] Subsequently, a first programming operation (15) can be performed on the physical page of the second string group ST2 connected to the third word line WL3, and a second programming operation (16) can be performed on the physical page of the second string group ST2 connected to the second word line WL2.

[0117] Subsequently, a first programming operation (17) can be performed on the physical page of the third string group ST3 connected to the third word line WL3, and a second programming operation (18) can be performed on the physical page of the third string group ST3 connected to the second word line WL2.

[0118] Subsequently, a first programming operation (19) can be performed on the physical pages of the fourth string group ST4 connected to the third word line WL3, and a second programming operation (20) can be performed on the physical pages of the fourth string group ST4 connected to the second word line WL2. A memory system according to an embodiment of this disclosure can be used in conjunction with reference to... Figures 11A to 11C The method described is the same method used to program page data.

[0119] refer to Figure 11D The diagram illustrates the operation where programming is stopped after programming a physical page connected to the eighth word line. When it is anticipated that programming will stop after programming a physical page connected to the eighth word line, the memory system can perform a second programming operation (60) on the physical page connected to the seventh word line of the fourth string group ST4, and then perform a second programming operation (61) on the physical page connected to the eighth word line of the first string group ST1, instead of performing a first programming operation on the physical page connected to the ninth word line of the first string group ST1. Subsequently, a second programming operation (62) can be performed on the physical page connected to the eighth word line of the second string group ST2, a second programming operation (63) can be performed on the physical page connected to the eighth word line of the third string group ST3, and a second programming operation (64) can be performed on the physical page connected to the eighth word line of the fourth string group ST4. Data programming can be stopped after completing sixty-four programming operations.

[0120] refer to Figure 11E This shows that, for example, when using Figure 11DThe explanation describes the operation of restarting the programming operation after it has been stopped. In this case, the programming operation can be performed from the physical page connected to the ninth word line. More specifically, after performing the first programming operation (1') on the physical page connected to the ninth word line WL9 of the first string group ST1, the first programming operation (2') can be performed on the physical page connected to the ninth word line WL9 of the second string group ST2. Subsequently, the first programming operation (3') can be performed on the physical page connected to the ninth word line WL9 of the third string group ST3, and the first programming operation (4') can be performed on the physical page connected to the ninth word line WL9 of the fourth string group ST4.

[0121] refer to Figure 11F After performing a first programming operation (4') on the physical page of the fourth string group ST4 connected to the ninth word line WL9, a first programming operation (5') can be performed on the physical page of the first string group ST1 connected to the cross line WL10, and a second programming operation (6') can be performed on the physical page of the first string group ST1 connected to the ninth word line WL9. Subsequently, a first programming operation (7') can be performed on the physical page of the second string group ST2 connected to the cross line WL10, and a second programming operation (8') can be performed on the physical page of the second string group ST2 connected to the ninth word line WL9.

[0122] Subsequently, a first programming operation (9') can be performed on the physical page of the third string group ST3 connected to the cross line WL10, and a second programming operation (10') can be performed on the physical page of the third string group ST3 connected to the ninth word line WL9.

[0123] In addition, a first programming operation (11') can be performed on the physical page of the fourth string group ST4 connected to the cross line WL10, and a second programming operation (12') can be performed on the physical page of the fourth string group ST4 connected to the ninth word line WL9.

[0124] That is, when programming operations are restarted after a programming operation has been stopped, programming operations can be performed on physical pages connected to the ninth and subsequent word lines in a similar order to the programming order performed on physical pages connected to the first through eighth word lines.

[0125] refer to Figure 11FAfter performing a second programming operation (61, 62, 63, and 64) on the page connected to the eighth word line as the programming operation stops, the first and second programming operations (1', 2', 3', 4', 6', 8', 10', and 12') can be performed on the page connected to the ninth word line as the programming operation restarts. This may degrade the threshold voltage distribution of the memory cells included in the page connected to the eighth word line. This increases the likelihood of read failures when data stored in the page connected to the eighth word line is read.

[0126] According to another embodiment of the memory system and method of operating the memory system, when programming operations stop, a dummy programming operation can be performed on the page adjacent to the page in which the last programmed data is to be stored, and thereafter, a second programming operation can be performed on the page in which the last programmed data is to be stored. Therefore, even if programming operations are later restarted, the possibility of degradation of the threshold voltage distribution of memory cells in which data has already been stored can be reduced. Hereinafter, reference is made to… Figures 12A to 12D This describes a method of operating a memory system according to another embodiment of the present disclosure.

[0127] Figures 12A to 12D This is a diagram illustrating a method of operating a memory device according to another embodiment of the present disclosure.

[0128] refer to Figure 12A The following scenario illustrates a situation where a first programming operation (53, 55, 57, 59) can be performed on a physical page connected to the eighth word line WL8, and a second programming operation (54, 56, 58, 60) can be performed on a physical page connected to the seventh word line WL7. The programming order of the physical pages connected to the first word line WL1 through the seventh word line WL7 is generally the same as that in the reference. Figures 11A to 11F The programming order described is the same.

[0129] refer to Figure 12A This illustrates the operation where programming is stopped after programming the physical page connected to the eighth word line. (See reference.) Figure 12B When it is anticipated that programming operations on the physical pages connected to the eighth word line will cease, the memory system may perform a second programming operation (60) on the physical pages of the fourth string group ST4 connected to the seventh word line, and then, dummy data may be programmed into the physical pages of the first string group ST1 connected to the ninth word line (61). Thereafter, the memory system may perform a second programming operation (62) on the physical pages of the first string group ST1 connected to the eighth word line.

[0130] Subsequently, the memory system can program dummy data into the physical page of the second string group ST2 connected to the ninth word line (63), and can perform a second programming operation on the physical page of the second string group ST2 connected to the eighth word line (64).

[0131] Subsequently, the memory system can program the dummy data in the physical page of the third string group ST3 connected to the ninth word line (65), and can perform a second programming operation on the physical page of the third string group ST3 connected to the eighth word line (66).

[0132] Subsequently, the memory system can program the dummy data in the physical page of the fourth string group ST4 connected to the ninth word line (67), and can perform a second programming operation on the physical page of the fourth string group ST4 connected to the eighth word line (68).

[0133] refer to Figure 12C The diagram illustrates the operation in the case where the programming operation is restarted. In this case, the programming operation can be performed from the physical page connected to the crosshair WL10. More specifically, the first programming operation (1') can be performed on the physical page of the first string group ST1 connected to the crosshair WL10, and the first programming operation (2') can be performed on the physical page of the second string group ST2 connected to the crosshair WL10. Subsequently, the first programming operation (3') can be performed on the physical page of the third string group ST3 connected to the crosshair WL10, and the first programming operation (4') can be performed on the physical page of the fourth string group ST4 connected to the crosshair WL10.

[0134] refer to Figure 12D After performing a first programming operation (4') on the physical page of the fourth string group ST4 connected to the first crosshair WL10, a first programming operation (5') can be performed on the physical page of the first string group ST1 connected to the eleventh word line WL11, and a second programming operation (6') can be performed on the physical page of the first string group ST1 connected to the first crosshair WL10. Subsequently, a first programming operation (7') can be performed on the physical page of the second string group ST2 connected to the eleventh word line WL11, and a second programming operation (8') can be performed on the physical page of the second string group ST2 connected to the first crosshair WL10.

[0135] Subsequently, a first programming operation (9') can be performed on the physical page of the third string group ST3 connected to the eleventh word line WL11, and a second programming operation (10') can be performed on the physical page of the third string group ST3 connected to the cross line WL10.

[0136] In addition, a first programming operation (11') can be performed on the physical page of the fourth string group ST4 connected to the eleventh word line WL11, and a second programming operation (12') can be performed on the physical page of the fourth string group ST4 connected to the cross line WL10.

[0137] That is, when programming is restarted after a programming operation has been stopped, programming operations can be performed on physical pages connected to the first and subsequent word lines in a similar order to the programming order performed on physical pages connected to the first through eighth word lines.

[0138] refer to Figure 12B After performing the first programming operation (53, 55, 57, and 59) on the page connected to the eighth word line as the programming operation stops, a dummy programming operation (61, 63, 65, and 67) can be performed on the page connected to the ninth word line, and after each dummy programming operation, a second programming operation (62, 64, 66, and 68) can be performed on the physical page connected to the eighth word line. Therefore, even if the first and second programming operations (1', 2', 3', 4', 6', 8', 10', and 12') are performed on the page connected to the crosshair after programming has resumed, the likelihood of degradation in the threshold voltage distribution of the memory cells included in the page connected to the eighth word line is reduced.

[0139] That is, according to another embodiment of the memory system and method of operating the memory system, when the programming operation stops, a dummy programming operation can be performed on the page adjacent to the page in which the last programming data is to be stored, and thereafter, a second programming operation can be performed on the page in which the last programming data is to be stored. Therefore, even if the programming operation is later restarted, the possibility of degradation of the threshold voltage distribution of the memory cells in which data has already been stored can be reduced.

[0140] Figure 13 This is a diagram for reference. Figures 12A to 12D A flowchart describing a method for operating a memory device. (See below for reference.) Figures 12A to 12D right Figure 13 The method shown is described below. Figures 12A to 12D In this context, when programming operations cease, the physical page storing the last data is the physical page connected to the eighth word line WL8. Therefore, for ease of description, [the following is a simplified description of the process]. Figure 13 The case where i is 8 is described.

[0141] In step S110, among the multiple physical pages included in the first string group ST1, a first programming operation can be performed on the physical page connected to the i-th word line, and a second programming operation can be performed on the physical page connected to the (i-1)-th word line. (See reference) Figures 12A to 12DAmong the multiple physical pages included in the first string group ST1, a first programming operation (53) can be performed on the physical page connected to the eighth word line WL8, and a second programming operation (54) can be performed on the physical page connected to the seventh word line WL7.

[0142] In step S120, among the multiple physical pages included in the second string group ST2, a first programming operation can be performed on the physical page connected to the i-th word line, and a second programming operation can be performed on the physical page connected to the (i-1)-th word line. (See reference...) Figures 12A to 12D Among the multiple physical pages included in the second string group ST2, a first programming operation (55) can be performed on the physical page connected to the eighth word line WL8, and a second programming operation (56) can be performed on the physical page connected to the seventh word line WL7.

[0143] In step S130, among the multiple physical pages included in the third string group ST3, a first programming operation can be performed on the physical page connected to the i-th word line, and a second programming operation can be performed on the physical page connected to the (i-1)-th word line. (See reference) Figures 12A to 12D Among the multiple physical pages included in the third string group ST3, a first programming operation (57) can be performed on the physical page connected to the eighth word line WL8, and a second programming operation (58) can be performed on the physical page connected to the seventh word line WL7.

[0144] In step S140, among the multiple physical pages included in the fourth string group ST4, a first programming operation can be performed on the physical page connected to the i-th word line, and a second programming operation can be performed on the physical page connected to the (i-1)-th word line. (See reference) Figures 12A to 12D Among the multiple physical pages included in the fourth string group ST4, a first programming operation (59) can be performed on the physical page connected to the eighth word line WL8, and a second programming operation (60) can be performed on the physical page connected to the seventh word line WL7.

[0145] Subsequently, in step S150, among the multiple physical pages included in the first string group ST1, dummy data can be programmed into the physical page connected to the (i+1)th word line, and a second programming operation can be performed on the physical page connected to the i-th word line. (See reference) Figures 12A to 12D Among the multiple physical pages included in the first string group ST1, a dummy programming operation (61) can be performed on the physical page connected to the ninth word line WL9, and a second programming operation (62) can be performed on the physical page connected to the eighth word line WL8.

[0146] In step S160, among the multiple physical pages included in the second string group ST2, dummy data can be programmed into the physical page connected to the (i+1)th word line, and a second programming operation can be performed on the physical page connected to the i-th word line. (See reference...) Figures 12A to 12D Among the multiple physical pages included in the second string group ST2, a dummy programming operation (63) can be performed on the physical page connected to the ninth word line WL9, and a second programming operation (64) can be performed on the physical page connected to the eighth word line WL8.

[0147] In step S170, among the multiple physical pages included in the third string group ST3, dummy data can be programmed into the physical page connected to the (i+1)th word line, and a second programming operation can be performed on the physical page connected to the i-th word line. (See reference) Figures 12A to 12D Among the multiple physical pages included in the third string group ST3, a dummy programming operation (65) can be performed on the physical page connected to the ninth word line WL9, and a second programming operation (66) can be performed on the physical page connected to the eighth word line WL8.

[0148] In step S180, among the multiple physical pages included in the fourth string group ST4, dummy data can be programmed into the physical page connected to the (i+1)th word line, and a second programming operation can be performed on the physical page connected to the i-th word line. (See reference) Figures 12A to 12D Among the multiple physical pages included in the fourth string group ST4, a dummy programming operation (67) can be performed on the physical page connected to the ninth word line WL9, and a second programming operation (68) can be performed on the physical page connected to the eighth word line WL8.

[0149] Subsequently, in step S190, among the multiple physical pages included in the first to fourth string groups, a first programming operation can be performed on each physical page connected to the (i+2)th word line. (See reference...) Figures 12A to 12D As the programming operation restarts, the first programming operation (1', 2', 3', and 4') can be performed on the physical page connected to the crosshair WL10.

[0150] Figures 14A to 14G This is a diagram illustrating a method of operating a memory device according to another embodiment of the present disclosure.

[0151] refer to Figure 14AAfter performing the first programming operation (1) on the physical pages of the first string group ST1 connected to the first word line WL1, the first programming operation (2) can be performed on the physical pages of the second string group ST2 connected to the first word line WL1, the first programming operation (3) can be performed on the physical pages of the third string group ST3 connected to the first word line WL1, and the first programming operation (4) can be performed on the physical pages of the fourth string group ST4 connected to the first word line WL1. That is, the first programming operation can be performed sequentially on the physical pages of the first string group ST1 to the fourth string group ST4 connected to the first word line WL1.

[0152] refer to Figure 14B After performing the first programming operation (4) on the physical pages of the fourth string group ST4 connected to the first word line WL1, the first programming operation (5) can be performed on the physical pages of the first string group ST1 connected to the second word line WL2, the first programming operation (6) can be performed on the physical pages of the second string group ST2 connected to the second word line WL2, the first programming operation (7) can be performed on the physical pages of the third string group ST3 connected to the second word line WL2, and the first programming operation (8) can be performed on the physical pages of the fourth string group ST4 connected to the second word line WL2. That is, after performing the first programming operation (1, 2, 3 and 4) sequentially on the physical pages of the first string group ST1 to the fourth string group ST4 connected to the first word line WL1, the first programming operation (5, 6, 7 and 8) can be performed sequentially on the physical pages of the first string group ST1 to the fourth string group ST4 connected to the second word line WL2.

[0153] Refer again Figure 14B After performing the first programming operation (5, 6, 7 and 8) sequentially on the physical pages of the first string group ST1 to the fourth string group ST4 connected to the second word line WL2, the second programming operation (9, 10, 11 and 12) can be performed sequentially on the physical pages of the first string group ST1 to the fourth string group ST4 connected to the first word line WL1.

[0154] refer to Figure 14C After sequentially performing the second programming operations (9, 10, 11, and 12) on the physical pages of the first string groups ST1 to ST4 connected to the first word line WL1, the first programming operations (13, 14, 15, and 16) on the physical pages of the first string groups ST1 to ST4 connected to the third word line WL3 can be sequentially performed, and the second programming operations (17, 18, 19, and 20) on the physical pages of the first string groups ST1 to ST4 connected to the second word line WL2 can be sequentially performed. In this method, the physical pages connected to the first word line WL1 to the seventh word line WL7 can be programmed using a reprogramming method.

[0155] refer to Figure 14DThe diagram illustrates a scenario where a first programming operation (53, 54, 55, and 56) is sequentially performed on the physical pages of the first string group ST1 to the fourth string group ST4 connected to the eighth word line WL8, and a second programming operation (57, 58, 59, and 60) is sequentially performed on the physical pages of the first string group ST1 to the fourth string group ST4 connected to the seventh word line WL7. In this scenario, the programming operation can be stopped after the physical pages connected to the eighth word line WL8 have been programmed.

[0156] refer to Figure 14E When the programming operation is expected to stop after programming of the physical pages connected to the eighth word line WL8, the memory system may sequentially perform a second programming operation (57, 58, 59 and 60) on the physical pages connected to the seventh word line WL7 of the first string group ST1 to the fourth string group ST4, and then program dummy data into the physical pages connected to the ninth word line WL9 of the first string group ST1 to the fourth string group ST4 (61, 62, 63 and 64).

[0157] refer to Figure 14F After performing dummy programming operations (61, 62, 63 and 64) on the physical pages of the first string group ST1 to the fourth string group ST4 connected to the ninth word line WL9, the second programming operations (65, 66, 67 and 68) can be performed sequentially on the physical pages of the first string group ST1 to the fourth string group ST4 connected to the eighth word line WL8.

[0158] refer to Figure 14G As the programming operation restarts, the first programming operation (1', 2', 3' and 4') can be performed sequentially on the physical pages connected to the crosshair WL10 of the first string group ST1 to the fourth string group ST4.

[0159] Figure 15 This is a diagram for reference. Figures 14A to 14G A flowchart describing a method for operating a memory device. (See below for reference.) Figures 14A to 14G right Figure 15 The method shown is described below. Figures 14A to 14G In this context, when programming operations cease, the physical page storing the last data can be the physical page connected to the eighth word line WL8. Therefore, for ease of description, [the following is a simplified description of the process]. Figure 15 The case where i is 8 is described.

[0160] In step S210, among the multiple physical pages included in the first string group ST1 to the fourth string group ST4, a first programming operation can be performed on the physical page connected to the i-th word line. (See reference...) Figures 14A to 14G Among the multiple physical pages included in the first string group ST1 to the fourth string group ST4, the first programming operation (53, 54, 55 and 56) can be performed on the physical page connected to the eighth word line WL8.

[0161] Subsequently, in step S230, among the multiple physical pages included in the first to fourth string groups, a second programming operation can be performed on the physical page connected to the (i-1)th word line. (See reference...) Figures 14A to 14G Among the multiple physical pages included in the first string group ST1 to the fourth string group ST4, a second programming operation (57, 58, 59 and 60) can be performed on the physical page connected to the seventh word line WL7.

[0162] Subsequently, in step S250, among the multiple physical pages included in the first to fourth string groups, dummy data can be programmed into each physical page connected to the (i+1)th word line. (See reference...) Figures 14A to 14G Among the multiple physical pages included in the first string group ST1 to the fourth string group ST4, dummy programming operations (61, 62, 63 and 64) can be performed on the physical page connected to the ninth word line WL9.

[0163] Subsequently, in step S270, among the multiple physical pages included in the first to fourth string groups, a second programming operation can be performed on the physical page connected to the i-th word line. (See reference...) Figures 14A to 14G Among the multiple physical pages included in the first string group ST1 to the fourth string group ST4, a second programming operation (65, 66, 67 and 68) can be performed on the physical page connected to the eighth word line WL8.

[0164] Subsequently, in step S290, among the multiple physical pages included in the first string group ST1 to the fourth string group ST4, a first programming operation can be performed on the physical page connected to the (i+2)th word line. (See reference...) Figures 14A to 14G Among the multiple physical pages included in the first string group ST1 to the fourth string group ST4, the first programming operation (1', 2', 3' and 4') can be performed on the physical page connected to the crosshair WL10.

[0165] Figure 16 The illustration includes Figure 2 A diagram of another embodiment of the memory system of the shown memory device.

[0166] refer to Figure 16 The memory system 30000 can be implemented as a cellular phone, smartphone, tablet PC, personal digital assistant (PDA), or wireless communication device. The memory system 30000 may include a memory device 1100 and a memory controller 1200, which controls the operation of the memory device 1100. Based on the processor 3100, the memory controller 1200 can control data access operations on the memory device 1100, such as programming, erasing, or reading operations.

[0167] Based on the memory controller 1200, data programmed into the memory device 1100 can be output via the display 3200.

[0168] The radio transceiver 3300 can transmit and receive radio signals via the antenna ANT. For example, the radio transceiver 3300 can convert the radio signals received via the antenna ANT into signals that can be processed by the processor 3100. Therefore, the processor 3100 can process the signals output from the radio transceiver 3300 and transmit the processed signals to the memory controller 1200 or the display 3200. The memory controller 1200 can program the signals processed by the processor 3100 into the memory device 1100. Furthermore, the radio transceiver 3300 can convert the signals output from the processor 3100 into radio signals and output the converted radio signals to an external device via the antenna ANT. The input device 3400 can be a device capable of inputting control signals for controlling the operation of the processor 3100 or data to be processed by the processor 3100. The input device 3400 can be implemented as a pointing device such as a touchpad or computer mouse, a keypad, or a keyboard. The processor 3100 can control the operation of the display 3200, so that the display 3200 outputs data from the memory controller 1200, data from the radio transceiver 3300, or data from the input device 3400.

[0169] According to one embodiment, the memory controller 1200, which is capable of controlling the operation of the memory device 1100, can be implemented as part of the processor 3100, or it can be implemented as a chip separate from the processor 3100.

[0170] Figure 17 The illustration includes Figure 2 A diagram of another embodiment of the memory system of the shown memory device.

[0171] refer to Figure 17 The memory system 40000 can be implemented as a personal computer (PC), tablet PC, netbook, e-reader, personal digital assistant (PDA), portable multimedia player (PMP), MP3 player, or MP4 player.

[0172] The memory system 40000 may include a memory device 1100 and a memory controller 1200, the memory controller 1200 being able to control data processing operations on the memory device 1100.

[0173] Based on the data input via input device 4200, processor 4100 can output data stored in memory device 1100 via display 4300. For example, input device 4200 can be implemented as a pointing device such as a touchpad or computer mouse, a keypad, or a keyboard.

[0174] The processor 4100 can control the overall operation of the memory system 40000 and can also control the operation of the memory controller 1200. According to one embodiment, the memory controller 1200, which is capable of controlling the operation of the memory device 1100, can be implemented as part of the processor 4100 or as a separate chip from the processor 4100.

[0175] Figure 18 The illustration includes Figure 2 A diagram of another embodiment of the memory system of the shown memory device.

[0176] refer to Figure 18 The memory system 50000 can be implemented as an image processing device, such as a digital camera, a portable phone equipped with a digital camera, a smartphone equipped with a digital camera, or a tablet PC equipped with a digital camera.

[0177] The memory system 50000 may include a memory device 1100 and a memory controller 1200, the memory controller 1200 being able to control data processing operations on the memory device 1100, such as programming operations, erasing operations, or reading operations.

[0178] The image sensor 5200 of the memory system 50000 can convert optical images into digital signals. The converted digital signals can be transmitted to the processor 5100 or the memory controller 1200. Based on the processor 5100, the converted digital signals can be output through the display 5300 or stored in the memory device 1100 through the memory controller 1200. Furthermore, based on the processor 5100 or the memory controller 1200, data stored in the memory device 1100 can be output through the display 5300.

[0179] According to one embodiment, the memory controller 1200, which is capable of controlling the operation of the memory device 1100, may be implemented as part of the processor 5100 or as a separate chip from the processor 5100.

[0180] Figure 19 The illustration includes Figure 2 A diagram of another embodiment of the memory system of the shown memory device.

[0181] refer to Figure 19The memory system 70000 can be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100, a memory controller 1200, and a card interface 7100.

[0182] The memory controller 1200 can control data exchange between the memory device 1100 and the card interface 7100. According to one embodiment, the card interface 7100 may be a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface, but is not limited thereto.

[0183] Card interface 7100 can exchange data between host 60000 and memory controller 1200 according to the protocol of host 60000. According to one embodiment, card interface 7100 can support Universal Serial Bus (USB) protocol and IC-USB protocol. Here, card interface can refer to: hardware capable of supporting protocols used by host 60000, software installed in that hardware, or signal transmission method.

[0184] When the memory system 70000 is connected to the host interface 6200 of the host 60000 (such as a PC, tablet PC, digital camera, digital audio player, mobile phone, console video game hardware, or digital set-top box), based on the microprocessor 6100, the interface 6200 can perform data communication with the memory device 1100 through the card interface 7100 and the memory controller 1200.

[0185] The embodiments of this disclosure disclosed in this specification and accompanying drawings are provided by way of specific examples only to simply describe the technical content of this disclosure and to aid in understanding it, and are not intended to limit the scope of this disclosure. It will be apparent to those skilled in the art that other modifications based on the technical spirit of this disclosure can be implemented in addition to the embodiments disclosed herein.

Claims

1. A memory device, comprising: The memory block includes multiple serial groups, each of which is connected to a corresponding select line among multiple select lines; The peripheral circuitry is configured to perform a first programming operation and a second programming operation on the memory block. as well as The control logic is configured to control the first programming operation and the second programming operation of the peripheral circuit. The memory block is connected to the first word line to the nth word line. The control logic is configured to control the peripheral circuitry to: perform the first programming operation on a physical page connected to the i-th word line and perform the second programming operation on a physical page connected to the (i-1)-th word line among a plurality of physical pages included in a first string group; perform the first programming operation on a physical page connected to the i-th word line and perform the second programming operation on a physical page connected to the (i-1)-th word line among a plurality of physical pages included in a second string group; perform a dummy programming operation on a physical page connected to the (i+1)-th word line and perform the second programming operation on the physical page connected to the i-th word line among the plurality of physical pages included in the first string group; perform the dummy programming operation on a physical page connected to the (i+1)-th word line and perform the second programming operation on the physical page connected to the i-th word line among the plurality of physical pages included in the second string group; and perform the second programming operation on a physical page connected to the (i+1)-th word line among the plurality of physical pages included in the second string group. Where n is a natural number equal to or greater than 3, and i is a natural number greater than 0 and less than n-1.

2. The memory device of claim 1, wherein the first programming operation is an operation of programming a threshold voltage of a memory cell to a first target level, and The second programming operation is the operation of programming the threshold voltage of the memory cell to a second target level.

3. The memory device of claim 2, wherein the first target level is a level lower than the second target level.

4. The memory device of claim 3, wherein the control logic is configured to control the peripheral circuitry to perform the second programming operation on the physical page connected to the i-th word line after performing the dummy programming operation on the physical page connected to the i+1-th word line.

5. The memory device of claim 4, wherein the control logic is configured to control the peripheral circuitry to perform the first programming operation on a physical page connected to the (i+2)th word line after performing the second programming operation on the physical page connected to the i-th word line.

6. The memory device of claim 1, wherein the control logic controls the peripheral circuitry to sequentially perform the first programming operation on physical pages connected to the i-th word line among the plurality of physical pages included in the first and second string groups after performing the second programming operation on the physical pages connected to the i+2-th word line among the plurality of physical pages included in the second string group.

7. The memory device of claim 1, wherein the control logic controls the peripheral circuitry to sequentially perform the first programming operation on physical pages connected to the i-th word line among a plurality of physical pages included in the first string group and the second string group, sequentially perform the second programming operation on physical pages connected to the (i-1)-th word line among the plurality of physical pages included in the first string group and the second string group, sequentially perform the dummy programming operation on physical pages connected to the (i+1)-th word line among the plurality of physical pages included in the first string group and the second string group, and sequentially perform the second programming operation on physical pages connected to the i-th word line among the plurality of physical pages included in the first string group and the second string group.

8. The memory device of claim 7, wherein the control logic controls the peripheral circuitry to sequentially perform the first programming operation on physical pages connected to the i-th word line among the plurality of physical pages included in the first string group and the second string group, after sequentially performing the second programming operation on physical pages connected to the i+2-th word line among the plurality of physical pages included in the first string group and the second string group.

9. A method of operating a memory system, the memory system performing a first programming operation and a second programming operation on a memory block comprising a plurality of serial groups, the plurality of serial groups being respectively connected to corresponding select lines among a plurality of select lines, and wherein the memory block is connected to a first word line to an nth word line, the method comprising: A first programming operation is performed on the memory cell connected to the i-th word line among the memory cells included in the first string group, and a second programming operation is performed on the memory cell connected to the (i-1)-th word line among the memory cells included in the first string group. The first programming operation is performed on the memory cells connected to the i-th word line among the memory cells included in the second string group, and the second programming operation is performed on the memory cells connected to the (i-1)-th word line among the memory cells included in the second string group. as well as Perform a dummy programming operation on the memory cells connected to the (i+1)th word line among the memory cells included in the first string group. Where i is a natural number greater than 2.

10. The method of claim 9, wherein the first programming operation is an operation of programming a threshold voltage of a memory cell to a first target level, and The second programming operation is the operation of programming the threshold voltage of the memory cell to a second target level.

11. The method of claim 10, wherein the first target level is a level lower than the second target level.

12. The method according to claim 9, further comprising: After performing the dummy programming operation on the memory cells connected to the (i+1)th word line among the memory cells included in the first string group, the dummy programming operation is performed on the memory cells connected to the (i+1)th word line among the memory cells included in the second string group.

13. The method of claim 9, further comprising: The first programming operation is performed sequentially on the physical pages connected to the i-th word line among the multiple physical pages included in the first string group and the second string group; The second programming operation is performed sequentially on the physical pages connected to the (i-1)th word line among the plurality of physical pages included in the first string group and the second string group; The virtual programming operation is performed sequentially on the physical pages connected to the (i+1)th word line among the plurality of physical pages included in the first string group and the second string group; as well as The second programming operation is performed sequentially on the physical pages connected to the i-th word line among the plurality of physical pages included in the first string group and the second string group.

14. The method of claim 13, wherein the first programming operation is an operation of programming a threshold voltage of a memory cell to a first target level, and The second programming operation is the operation of programming the threshold voltage of the memory cell to a second target level.

15. The method of claim 14, wherein the first target level is a level lower than the second target level.

16. The method of claim 13, further comprising: After performing the second programming operation on the physical page connected to the i-th word line among the plurality of physical pages included in the first string group and the second string group, the first programming operation is performed on the physical page connected to the (i+2)-th word line among the plurality of physical pages included in the first string group and the second string group.

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