Antifuse type one-time-programmable memory cell and its related memory cell array structure

Abstract

The application discloses a one-time programming storage unit and a related storage unit array structure. The one-time programming storage unit comprises a first selection element, a first follow element and a first antifuse transistor. A first end of the first selection element is connected to a first bit line. A second end of the first selection element is connected to a first node. A selection end of the first selection element is connected to a first word line. A first end of the first follow element is connected to the first node. A second end of the first follow element is connected to a second node. A first control end of the first follow element is connected to a first follow control line. A first drain / source end of the first antifuse transistor is connected to the second node. A gate end of the first antifuse transistor is connected to a first antifuse control line. A second drain / source end of the first antifuse transistor is floating.

Description

Technical Field

[0001] This invention relates to a non-volatile memory, and more particularly to an antifuse-type one-time programming memory cell and its associated cell array structure. Background Technology

[0002] As is well known, non-volatile memory can retain its data content even after power is turned off. Generally speaking, once non-volatile memory is manufactured and shipped from the factory, users can program it to record data.

[0003] Based on the number of times it can be programmed, non-volatile memory can be further divided into: multi-time programming memory (MTP memory), one-time programming memory (OTP memory), or mask-mode read-only memory (Mask ROM memory).

[0004] Basically, users can program MTP memory multiple times to modify the stored data. OTP memory, on the other hand, can only be programmed once; once programmed, its stored data cannot be modified. Mask ROM memory, however, has all its stored data pre-recorded at the factory; users can only read the data in the Mask ROM, but cannot program it.

[0005] Furthermore, OTP memories can be categorized into fuse-type OTP memories and antifuse-type OTP memories based on their characteristics. In a fuse-type OTP memory, the memory cell has a low resistance value when it is not programmed; however, after programming, the memory cell has a high resistance value.

[0006] Conversely, in antifuse type OTP memory, the memory cell has a high resistance value when it has not been programmed, and a low resistance value when it has been programmed.

[0007] Please refer to Figure 1AThe diagram illustrates a conventional antifuse OTP memory cell. The antifuse OTP memory cell 100 includes a select transistor M. S With an antifuse transistor M AF Select transistor M S The first drain / source terminal is connected to the bit line BL, and the selection transistor M is selected. S The gate terminal is connected to the word line WL, and the selection transistor M is selected. S The second drain / source terminal is connected to the antifuse transistor M. AF The first drain / source terminal, antifuse transistor M AF The gate terminal of the transistor is connected to the antifuse control line AF, and the antifuse transistor M... AF The second drain / source terminal is floating.

[0008] Due to the antifuse transistor M AF The second drain / source terminal is floating, so the antifuse transistor M AF It can be considered as a capacitor. That is to say, the antifuse OTP memory cell 100 is a transistor and a capacitor memory cell (1T1Ccell).

[0009] Please refer to Figure 1B and Figure 1C The diagram illustrates the bias voltage for programming and inhibiting actions in an existing antifuse OTP memory cell.

[0010] like Figure 1B As shown, during programming, the bit line BL receives the ground voltage (0V), and the antifuse control line AF receives the programming voltage (V). PP The word line WL receives the turn-on voltage (V). ON For example, the programming voltage V PP The voltage is 5V, and the turn-on voltage is V. ON It is 2.5V.

[0011] When programming, select transistor M. S When the bit line BL is turned on, the ground voltage (0V) is transferred to the antifuse transistor M. AF The first drain / source terminal enables the antifuse transistor M to... AFThe voltage stress between the gate terminal and the first drain / source terminal is the programming voltage V. PP This causes the antifuse transistor M to... AF The gate oxide layer of the antifuse transistor M ruptures. AF A low resistance value exists between the gate terminal and the first drain / source terminal. That is, the antifuse OTP memory cell 100 is in a low resistance storage state.

[0012] like Figure 1C As shown, during the programming suppression operation, the bit line BL receives the ground voltage (0V), and the antifuse control line AF receives the programming voltage (V). PP The word line WL receives the turn-off voltage (V). OFF For example, the off voltage V OFF It is 0V.

[0013] When programming to suppress actions, select transistor M. S When the circuit is turned off, the ground voltage (0V) of bit line BL cannot be transmitted to the antifuse transistor M. AF The first drain / source terminal enables the antifuse transistor M to... AF The voltage stress between the gate terminal and the first drain / source terminal is very small, and the antifuse transistor M... AF The gate oxide layer is not ruptured, and the antifuse transistor M... AF The gate terminal and the first drain / source terminal maintain a high resistance value. That is, the antifuse OTP memory cell 100 is in a high resistance storage state.

[0014] In addition, such as Figure 1C As shown, when programming to suppress the action, transistor M is selected. S Turn off. At this point, select transistor M. S This will generate leakage current. For example, punch current I. Punch and gate-induced drain leakage current (GIDL) GIDL .

[0015] like Figure 1C As shown, when transistor M is selected S When turned off, select transistor M. S The voltage at the second drain / source terminal is approximately (V) PP -V tAF), where V tAF For antifuse transistor M AF The threshold voltage is approximately 1V, so transistor M is selected. S The voltage at the second drain / source terminal is approximately 4V (5V-1V).

[0016] Furthermore, select transistor M S When shut down, the voltage difference between the first drain / source and the second drain / source will cause an inrush current I. Punch The generation of inrush current I is greater as the voltage difference increases. Punch It is also larger. With Figure 1C For example, select transistor M S The voltage difference between the first drain / source and the second drain / source is approximately 4V, which will generate a large inrush current I. Punch And the impact current I Punch The flow is from the second drain / source terminal of the selection transistor Ms to the first drain / source terminal.

[0017] Additionally, select transistor M S The voltage difference between the second drain / source terminal and the gate terminal will cause the gate-induced drain current I. GIDL The generation of gate-induced drain current I is greater when the voltage difference is larger. GIDL It is also larger. With Figure 1C For example, select transistor M S The voltage difference between the second drain / source terminal and the gate terminal is approximately 4V, which will generate a large gate-induced drain current I. GIDL And the gate induces a drain current I GIDL Select transistor M S The second drain / source flow direction selection transistor M S The body terminal.

[0018] Please refer to Figure 2A The diagram illustrates another existing antifuse OTP memory cell. The antifuse OTP memory cell 200 includes a selection transistor M. S A following transistor M FL With an antifuse transistor M AF Select transistor M S The first drain / source terminal is connected to the bit line BL, and the selection transistor M is selected. S The gate terminal is connected to the word line WL, and the selection transistor M is selected. S The second drain / source terminal is connected to the follow transistor M.FL The first drain / source terminal, followed by transistor M FL The gate of the transistor is connected to the following control line FL, and the follower transistor M... FL The second drain / source terminal is connected to the antifuse transistor M. AF The first drain / source terminal, antifuse transistor M AF The gate terminal of the antifuse transistor M is connected to the antifuse control line AF. AF The second drain / source terminal is floating.

[0019] Due to the antifuse transistor M AF The second drain / source terminal is floating, so the antifuse transistor M AF It can be considered as a capacitor. That is to say, the antifuse OTP memory cell 200 is a two-transistor and one-capacitor memory cell (2T1Ccell).

[0020] Please refer to Figure 2B and Figure 2C The diagram shows the bias voltage for programming and programming suppression operations of an existing anti-fuse OTP memory cell.

[0021] like Figure 2B As shown, during programming, the bit line BL receives the ground voltage (0V), and the antifuse control line AF receives the programming voltage (V). PP The word line WL receives the turn-on voltage (V). ON The control line FL receives a control voltage V. FL For example, the programming voltage V PP The voltage is 5V, and the turn-on voltage is V. ON The voltage is 1.8V, and the control voltage V is... FL It is 1.8V. Basically, the control voltage V... FL Control follower transistor M FL It is in the conducting state.

[0022] Therefore, when selecting transistor M S Turn on and follow transistor M FL When in the ON state, the ground voltage (0V) of bit line BL is transferred to the antifuse transistor M. AF The first drain / source terminal enables the antifuse transistor M to... AF The voltage stress between the gate terminal and the first drain / source terminal is the programming voltage V. PP This causes the antifuse transistor M to...AF The gate oxide layer of the antifuse transistor M ruptures. AF A low resistance value exists between the gate terminal and the first drain / source terminal. That is, the antifuse OTP memory cell 200 is in a low resistance storage state.

[0023] like Figure 2C As shown, during the programming suppression operation, the bit line BL receives the ground voltage (0V), and the antifuse control line AF receives the programming voltage (V). PP The word line WL receives the turn-off voltage (V). OFF The control line FL receives a control voltage V. FL For example, the off voltage V OFF This is the ground voltage (0V).

[0024] Therefore, when selecting transistor M S Turn off and follow transistor M FL When in the ON state, the ground voltage (0V) of bit line BL cannot be transmitted to the antifuse transistor M. AF The first drain / source terminal enables the antifuse transistor M to... AF The voltage stress between the gate terminal and the first drain / source terminal is very small, and the antifuse transistor M... AF The gate oxide layer is not ruptured, and the antifuse transistor M... AF The gate terminal and the first drain / source terminal maintain a high resistance value. That is, the antifuse OTP memory cell 200 is in a high resistance storage state.

[0025] In addition, such as Figure 2C As shown, when programming to suppress the action, transistor M is selected. S Turn off. At this point, select transistor M. S The second drain / source voltage is approximately (V) FL -V tFL Select transistor M) S This will generate leakage current. For example, the inrush current I. Punch and gate-induced drain current I GIDL1 Additionally, following transistor M FL The second drain / source voltage is approximately (V) PP -V tAF ), following transistor M FL This will generate leakage current. For example, the gate induces a drain leakage current I. GIDL2 For example, V tFL To follow transistor MFL The critical voltage, V tAF For antifuse transistor M AF The critical voltage, V tFL Approximately 1V, V tAF It is approximately 0.7V. Therefore, transistor M is selected. S The second drain / source voltage is approximately 1.1V (1.8V-0.7V), following the transistor M. FL The second drain / source voltage is approximately 4V (5V-1V).

[0026] Furthermore, select transistor M S A voltage difference of 1.1V between the second drain / source terminal and the first source terminal will cause an inrush current I. Punch The generation of transistor M. S A voltage difference of 1.1V between the second drain / source terminal and the gate terminal will cause the gate to induce a drain current I. GIDL1 Generation. Additionally, following transistor M... FL The voltage difference of 2.2V (4V-1.8V) between the second drain / source terminal and the gate terminal will cause the gate to induce a drain current I. GIDL2 produce.

[0027] In the existing antifuse OTP memory cell 200, the control voltage V is adjusted. FL The leakage current can be further adjusted. Please refer to [the relevant documentation / reference]. Figure 2D The diagram illustrates the control voltage V of the existing antifuse OTP memory cell 200 during programmed suppression operation. FL The relationship with leakage current. For example, in the antifuse OTP memory cell 200, the selection transistor M... S Follower transistor M FL With antifuse transistor M AF The channel length is 36nm.

[0028] Depend on Figure 2D It can be seen that when the control voltage V FL When decreasing, select transistor M S The resulting surge current I Punch and gate-induced drain current I GIDL1 It will decrease, but it follows transistor M FL The generated gate-induced drain current I GIDL2 It will increase. Conversely, when the control voltage V... FL When the voltage rises, the follower transistor M FL The generated gate-induced drain current I GIDL2 It will decrease, but choosing transistor M... S The generated surge current I Punchand gate-induced drain current I GIDL1 It will rise.

[0029] Therefore, as Figure 2D As shown, when the control voltage V FL Adjusting the voltage to approximately 2.0V will result in a relatively small total leakage current in the antifuse OTP memory cell 200. This is achieved by selecting transistor M. S The impact current I Punch Approximately 50pA, select transistor M S Gate-induced drain current I GIDL1 Approximately 7nA, following transistor M FL Gate-induced drain current I GIDL2 It is approximately 7 nA.

[0030] However, as semiconductor manufacturing processes evolve and transistor sizes shrink, the leakage current of existing OTP memory 200 increases dramatically. For example, the leakage current situation will be even worse when the channel length of the transistor in the antifuse OTP memory cell 200 is less than 16nm. Summary of the Invention

[0031] This invention relates to a memory cell array structure. The memory cell array structure includes a first antifuse type programmable-once memory cell. The first antifuse type programmable-once memory cell includes: a first select element, a first terminal of which is connected to a first bit line, a second terminal of which is connected to a first node, and a select terminal of which is connected to a first word line; a first follower element, a first terminal of which is connected to the first node, a second terminal of which is connected to a second node, and a first control terminal of which is connected to a first follower control line; and a first antifuse transistor, a first drain / source terminal of which is connected to the second node. A gate terminal of the first antifuse transistor is connected to a first antifuse control line, and a second drain / source terminal of the first antifuse transistor is floating; wherein, the first selection element includes a first selection transistor and a second selection transistor, a first drain / source terminal of the first selection transistor is connected to the first bit line, a gate terminal of the first selection transistor is connected to the first word line, a second drain / source terminal of the first selection transistor is connected to a first drain / source terminal of the second selection transistor, a gate terminal of the second selection transistor is connected to the first word line, and a second drain / source terminal of the second selection transistor is connected to the first node.

[0032] This invention relates to a memory cell array structure. The memory cell array structure includes a first antifuse type programmable-once memory cell. The first antifuse type programmable-once memory cell includes: a first select element, a first terminal of which is connected to a first bit line, a second terminal of which is connected to a first node, and a select terminal of which is connected to a first word line; a first follower element, a first terminal of which is connected to the first node, a second terminal of which is connected to a second node, a first control terminal of which is connected to a first follower control line, and a second control terminal of which is connected to a second follower control line; and a first antifuse transistor, a first drain / source terminal of which... Connected to the second node, a gate terminal of the first antifuse transistor is connected to a first antifuse control line, and a second drain / source terminal of the first antifuse transistor is floating; wherein, the first follower element includes a first follower transistor and a second follower transistor, a first drain / source terminal of the first follower transistor is connected to the first node, a gate terminal of the first follower transistor is connected to the first follower control line, a second drain / source terminal of the first follower transistor is connected to a first drain / source terminal of the second follower transistor, a gate terminal of the second follower transistor is connected to the second follower control line, and a second drain / source terminal of the second follower transistor is connected to the second node.

[0033] To provide a better understanding of the above and other aspects of the present invention, preferred embodiments are described below in detail with reference to the accompanying drawings: Attached Figure Description

[0034] Figure 1A , Figure 1B and Figure 1C A schematic diagram of the bias voltage for an existing antifuse OTP memory cell and its programming and programming suppression operations;

[0035] Figure 2A , Figure 2B and Figure 2C This is a schematic diagram of the bias voltage for another existing antifuse OTP memory cell and its programming and programming suppression operations;

[0036] Figure 2D For existing anti-fuse OTP memory cells, the control voltage V is used during programming suppression. FL A schematic diagram showing the relationship between leakage current;

[0037] Figure 3A , Figure 3B and Figure 3C This is a schematic diagram of the bias voltage for the first embodiment of the antifuse OTP memory cell of the present invention, and the programming and programming suppression operations thereof;

[0038] Figure 4A , Figure 4B and Figure 4C This is a schematic diagram of the bias voltage for a second embodiment of the antifuse OTP memory cell of the present invention, showing its programming and programming suppression operations;

[0039] Figure 5 This is a schematic diagram of the memory cell array structure and its bias voltage composed of antifuse OTP memory cells according to the second embodiment of the present invention;

[0040] Figure 6A , Figure 6B and Figure 6C This is a third embodiment of the antifuse OTP memory cell of the present invention, and a bias diagram illustrating its programming and programming suppression operations; and

[0041] Figure 7 This is a schematic diagram of the memory cell array structure and its bias voltage composed of anti-fuse OTP memory cells according to the third embodiment of the present invention.

[0042] Symbol Explanation

[0043] 100, 200, 300, 400, 500: Anti-fuse OTP memory units

[0044] 310, 410, 451, 510, 551: Select component

[0045] 320, 420, 452, 520, 552: Follower components

[0046] 450, 550: Memory cell array structure Detailed Implementation

[0047] Please refer to Figure 3A The illustration depicts a first embodiment of the antifuse OTP memory cell of the present invention. The antifuse OTP memory cell 300 includes a select device 310, a follower device 320, and an antifuse transistor M. AF .

[0048] In the antifuse OTP memory cell 300, the first terminal of the select element 310 is connected to the bit line BL, the select terminal of the select element 310 is connected to the word line WL, the second terminal of the select element 310 is connected to node y, the first terminal of the follower element 320 is connected to node y, multiple control terminals of the follower element 320 are connected to multiple follower control lines FL1, FL2, and the second terminal of the follower element 320 is connected to node z. The antifuse transistor M... AF The first drain / source terminal is connected to node z, and the antifuse transistor M AFThe gate terminal of the antifuse transistor M is connected to the antifuse control line AF. AF The second drain / source terminal is floating.

[0049] According to a first embodiment of the present invention, the selection element 310 consists of two selection transistors M S1 M S2 The follower element 320 consists of two follower transistors M. FL1 M FL2 Composition. In the selection of component 310, select transistor M. S1 The first drain / source terminal is connected to the bit line BL, and the selection transistor M is selected. S1 The gate terminal is connected to the word line WL, and the selection transistor M is selected. S1 The second drain / source terminal is connected to the select transistor M. S2 The first drain / source terminal selects transistor M. S2 The gate terminal is connected to the word line WL, and the selection transistor M is selected. S2 The second drain / source terminal is connected to node y. In follower element 320, follower transistor M FL1 The first drain / source terminal is connected to node y, following transistor M. FL1 The gate terminal is connected to the follower control line FL1, and the follower transistor M FL1 The second drain / source terminal is connected to the follower transistor M. FL2 The first drain / source terminal, followed by transistor M FL2 The gate of the follower transistor M is connected to the follower control line FL2. FL2 The second drain / source is connected to node z.

[0050] Due to the antifuse transistor M AF The second drain / source terminal is floating, so the antifuse transistor M AF It can be considered as a capacitor. That is, the antifuse OTP memory cell 300 in the first embodiment is a four-transistor and one-capacitor memory cell (4T1C cell). Furthermore, the antifuse OTP memory cell 300 can selectively perform programming and programming suppression operations. During programming, the two selection transistors M... S1 M S2 Both selection transistors M will be activated simultaneously during the programmed suppression operation. S1 M S2 Both will be turned off simultaneously. The two follower transistors M... FL1 M FL2 The device is in the ON state during both programming and programming suppression operations. The following example, using a transistor channel length of 16nm, illustrates the bias voltage of the antifuse OTP memory cell 300 during programming and programming suppression operations.

[0051] Please refer to Figure 3B and Figure 3C The diagram shown is a bias diagram of the antifuse OTP memory cell in the first embodiment performing programming and programming suppression operations.

[0052] like Figure 3B As shown, during programming, the bit line BL receives the ground voltage (0V), and the antifuse control line AF receives the programming voltage (V). PP The word line WL receives the turn-on voltage (V). ON Follow control line FL1 receives the first control voltage V FL1 Following the control line FL2, it receives the second control voltage V. FL2 For example, the programming voltage V PP The voltage is 5V, and the turn-on voltage is V. ON The first control voltage is 1V. FL1 The second control voltage is 1.5V. FL2 It is 2V. Wherein, the turn-on voltage V ON Selectable transistor M can be turned on. S1 M S2 That is, to enable selection element 310. Additionally, two control voltages V... FL1 V FL2 Controllable follower transistor M FL1 M FL2 When the circuit is in the ON state, that is, when the follower element 320 is in the ON state, the connection between node y and node z is established. According to the first embodiment of the present invention, the programming voltage V... PP Greater than the second control voltage V FL2 The second control voltage V FL2 Greater than or equal to the first control voltage V FL1 First control voltage V FL1 Greater than the turn-on voltage V ON .

[0053] When selector 310 is turned on and follower 320 is in the on state, the ground voltage (0V) of bit line BL is transmitted to antifuse transistor M. AF The first drain / source terminal enables the antifuse transistor M to... AF The voltage stress between the gate terminal and the first drain / source terminal is the programming voltage V. PP This causes the antifuse transistor M to... AF The gate oxide layer of the antifuse transistor M ruptures. AFThe gate terminal and the first drain / source terminal exhibit a low resistance value. That is, the antifuse OTP memory cell 300 is in a low resistance storage state.

[0054] like Figure 3C As shown, during the programming suppression operation, the bit line BL receives the ground voltage (0V), and the antifuse control line AF receives the programming voltage V. PP The word line WL receives the turn-off voltage (V). OFF Follow control line FL1 receives the first control voltage V FL1 Following the control line FL2, it receives the second control voltage V. FL2 For example, the programming voltage V PP The voltage is 5V, and the shut-off voltage is V. OFF The voltage is 0V, and the first control voltage V is... FL1 The second control voltage is 1.5V. FL2 It is 2V. The shutdown voltage V is... OFF Turn-off selection transistor M S1 M S2 That is, to turn off the selection element 310.

[0055] When selector 310 is turned off and follower 320 is turned on (i.e., follower transistor M), FL1 M FL2 When in the ON state, the ground voltage (0V) of bit line BL cannot be transmitted to the antifuse transistor M. AF The first drain / source terminal enables the antifuse transistor M to... AF The voltage stress between the gate terminal and the first drain / source terminal is very small, and the antifuse transistor M... AF The gate oxide layer is not ruptured, and the antifuse transistor M... AF The gate terminal and the first drain / source terminal maintain a high resistance value. That is, the antifuse OTP memory cell 300 is in a high-resistance storage state.

[0056] In addition, such as Figure 3C As shown, when the programmed suppression action is performed, component 310 is turned off. At this time, the voltage Vy at node y is (V FL1 -V tFL1 Selecting component 310 will generate leakage current. For example, the inrush current I... Punch and gate-induced drain current I GIDL1 Additionally, the voltage at node z is Vz = (V PP -V tAF The follower transistor M in the follower electrical component 320 FL2This will generate leakage current. For example, the gate induces a drain leakage current I. GIDL2 Among them, V tFL1 To follow transistor M FL1 The critical voltage, V tAF For antifuse transistor M AF The critical voltage, V tFL1 Approximately 0.7V, V tAF It is approximately 1V.

[0057] As can be seen from the above explanation, adjusting the first control voltage V FL1 The voltage Vy at node y can be changed, and the inrush current I can be further adjusted. Punch and gate-induced drain current I GIDL1 Therefore, when the first control voltage V FL1 At 1.5V, the voltage Vy at node y is approximately 0.8V (1.5V-0.7V), ensuring that component 310 will hardly generate an inrush current I. Punch And the gate induces a drain current I GIDL1 Very low, approximately 1 nA.

[0058] Similarly, adjust the second control voltage V FL2 The follower transistor M can be changed FL2 The voltage difference between the second drain / source terminal (node ​​z) and the gate terminal is further adjusted to control the gate-induced drain current I. GIDL2 Therefore, when the second control voltage V FL2 When the voltage is 2V, the voltage Vz at node z is approximately 4V (5V-1V), following the transistor M. FL2 The voltage difference between the second drain / source terminal and the gate terminal is approximately 2V (4V-2V), and the gate induces a drain current I. GIDL2 Very low, approximately 3 nA.

[0059] In this embodiment, the selection element 310 includes two selection transistors M. S1 M S2 The series-connected selection transistor M S1 M S2 This allows for an increase in the effective channel length of the selector element 310, thereby reducing the leakage current Ipunch.

[0060] Furthermore, due to variations in semiconductor manufacturing processes, the selector element 310 may receive a turn-off voltage V. OFF However, a situation occurs where complete shutdown is not possible, resulting in increased leakage current. This is because the select element 310 includes two series-connected select transistors M. S1 M S2 As long as any one of the selection transistors M S1 M S2 Receive shutdown voltage VOFF A complete shutdown means that the selector 310 is completely turned off and the leakage current path is blocked. In other words, the antifuse OTP memory cell 300 will generate a small leakage current during the programmed suppression action.

[0061] In the first embodiment of the present invention, the selection element 310 and the follower element 320 are both illustrated using two transistors connected in series. However, the present invention is not limited to this. When the channel length of the transistor is shorter, more than two transistors can be connected in series in the selection element 310 or the follower element 320. For example, in an antifuse OTP memory cell, the selection element includes three selection transistors connected in series between bit line BL and node y, and the follower element includes two follower transistors connected in series between node y and node z, forming a 5T1C memory cell. The gates of the three selection transistors are connected to the word line, and the gates of the two follower transistors are connected to two different follower control lines.

[0062] Alternatively, the select element comprises two select transistors connected in series between bit line BL and node y, and the follower element comprises three follower transistors connected in series between node y and node z, forming a 5T1C memory cell. The gates of the two select transistors are connected to the word line, and the gates of the three follower transistors are connected to three different follower control lines.

[0063] Alternatively, the select element comprises three select transistors connected in series between bit line BL and node y, and the follower element comprises three follower transistors connected in series between node y and node z, forming a 6T1C memory cell. The gates of the three select transistors are connected to the word line, and the gates of the three follower transistors are connected to three different follower control lines.

[0064] Furthermore, considering that the leakage current of the antifuse OTP memory cell is within an acceptable range, the antifuse OTP memory cell of the present invention can also be a 3T1C memory cell. This will be explained below.

[0065] Please refer to Figure 4A The illustration depicts a second embodiment of the antifuse OTP memory cell of the present invention. The antifuse OTP memory cell 400 includes a select element 410, a follower element 420, and an antifuse transistor M. AF .

[0066] In the antifuse OTP memory cell 400, the first terminal of the select element 410 is connected to the bit line BL, the select terminal of the select element 410 is connected to the word line WL, the second terminal of the select element 410 is connected to node y, the first terminal of the follower element 420 is connected to node y, the control terminal of the follower element 420 is connected to the follower control line FL1, the second terminal of the follower element 420 is connected to node z, and the antifuse transistor M... AFThe first drain / source terminal is connected to node z, and the antifuse transistor M AF The gate terminal of the antifuse transistor M is connected to the antifuse control line AF. AF The second drain / source terminal is floating.

[0067] According to a second embodiment of the present invention, the selection element 410 consists of two selection transistors M S1 M S2 The follower element 420 consists of a follower transistor M. FL1 Composition. In the selection of component 410, select transistor M. S1 The first drain / source terminal is connected to the bit line BL, and the selection transistor M is selected. S1 The gate terminal is connected to the word line WL, and the selection transistor M is selected. S1 The second drain / source terminal is connected to the select transistor M. S2 The first drain / source terminal selects transistor M. S2 The gate terminal is connected to the word line WL, and the selection transistor M is selected. S2 The second drain / source terminal is connected to node y. In follower element 420, follower transistor M FL1 The first drain / source terminal is connected to node y, following transistor M. FL1 The gate terminal is connected to the follower control line FL1, and the follower transistor M FL1 The second drain / source is connected to node z.

[0068] Due to the antifuse transistor M AF The second drain / source terminal is floating, so the antifuse transistor M AF It can be considered as a capacitor. That is, the antifuse OTP memory cell 400 in the second embodiment is a three-transistor and one-capacitor memory cell (3T1C cell).

[0069] Please refer to Figure 4B and Figure 4C The diagram shown is a bias diagram of the antifuse OTP memory cell performing programming and programming suppression operations in the second embodiment.

[0070] like Figure 4B As shown, during programming, the bit line BL receives the ground voltage (0V), and the antifuse control line AF receives the programming voltage (V). PP The word line WL receives the turn-on voltage (V). ON Follow control line FL1 receives the first control voltage V FL1 For example, the programming voltage V PP The voltage is 5V, and the turn-on voltage is V. ON The first control voltage is 1.2V.FL1 It is 2V. Wherein, the turn-on voltage V ON Selectable transistor M can be turned on. S1 M S2 That is, to enable the selection element 410. Additionally, the first control voltage V... FL1 Controllable follower transistor M FL1 When the device is in the ON state, that is, when the follower element 420 is in the ON state, conduction is achieved between node y and node z. According to the second embodiment of the present invention, the programming voltage V... PP Greater than the first control voltage V FL1 First control voltage V FL1 Greater than the turn-on voltage V ON .

[0071] When selector 410 is turned on and follower 420 is in the on state, the ground voltage (0V) of bit line BL is transmitted to antifuse transistor M. AF The first drain / source terminal enables the antifuse transistor M to... AF The voltage stress between the gate terminal and the first drain / source terminal is the programming voltage V. PP This causes the antifuse transistor M to... AF The gate oxide layer of the antifuse transistor M ruptures. AF The gate terminal and the first drain / source terminal exhibit a low resistance value. That is, the antifuse OTP memory cell 400 is in a low resistance storage state.

[0072] like Figure 4C As shown, during the programming suppression operation, the bit line BL receives the ground voltage (0V), and the antifuse control line AF receives the programming voltage V. PP The word line WL receives the turn-off voltage (V). OFF Follow control line FL1 receives the first control voltage V FL1 For example, the programming voltage V PP The voltage is 5V, and the shut-off voltage is V. OFF The voltage is 0V, and the first control voltage V is... FL1 It is 2V. The shutdown voltage V is... OFF Selector transistor M can be turned off S1 M S2 That is, turn off the selection element 410.

[0073] When selector 410 is turned off and follower 420 is turned on, the ground voltage (0V) of bit line BL cannot be transmitted to antifuse transistor M. AFThe first drain / source terminal enables the antifuse transistor M to... AF The voltage stress between the gate terminal and the first drain / source terminal is very small, and the antifuse transistor M... AF The gate oxide layer is not ruptured, and the antifuse transistor M... AF The gate terminal and the first drain / source terminal maintain a high resistance value. That is, the antifuse OTP memory cell 400 is in a high resistance storage state.

[0074] In addition, such as Figure 4C As shown, when the programmed suppression action is performed, component 410 is turned off. At this time, the voltage Vy at node y is (V FL1 -V tFL1 Selecting component 410 will generate leakage current. For example, the inrush current I... Punch and gate-induced drain current I GIDL1 Additionally, the voltage at node z is Vz = (V PP -V tAF The follower transistor M in the follower electrical component 420 FL2 This will generate leakage current. For example, the gate induces a drain leakage current I. GIDL2 Among them, V tFL1 To follow transistor M FL1 The critical voltage, V tAF For antifuse transistor M AF The critical voltage, V tFL1 Approximately 0.7V, V tAF It is approximately 1V.

[0075] As can be seen from the above explanation, adjusting the first control voltage V FL1 The voltage Vy at node y can be changed, and the inrush current I can be further adjusted. Punch and gate-induced drain current I GIDL1 Therefore, when the first control voltage V FL1 When the voltage is 2V, the voltage Vy at node y is approximately 1.3V (2V - 0.7V), causing the surge current I generated by the selection element 410 to... Punch Approximately 50pA, and the gate-induced drain current I GIDL1 It is approximately 7 nA.

[0076] Similarly, adjust the first control voltage V FL1 The follower transistor M can be changed FL1 The voltage difference between the second drain / source terminal (node ​​z) and the gate terminal is further adjusted to control the gate-induced drain current I. GIDL2 Therefore, when the second control voltage V FL1 When the voltage is 2V, the voltage Vz at node z is approximately 4V (5V-1V), following the transistor M.FL1 The voltage difference between the second drain / source terminal and the gate terminal is approximately 2V (4V-2V), and the gate induces a drain current I. GIDL2 It is approximately 3nA.

[0077] Please refer to Figure 5 The diagram illustrates a memory cell array structure and its bias schematic representing an antifuse OTP memory cell array according to a second embodiment of the present invention. The memory cell array structure 450 consists of 2×2 antifuse OTP memory cells c11 to c22. However, the present invention is not limited to the memory cell array structure 450 with 2×2 antifuse OTP memory cells c11 to c22. Those skilled in the art can construct a memory cell array structure with m×n antifuse OTP memory cells according to the description of the present invention, where m and n are positive integers. For example, the antifuse OTP memory cell c11 includes a select element 451, a follower element 452, and an antifuse transistor M. AF Furthermore, the structures of antifuse OTP memory cells c11 to c22 are the same as... Figure 4A Its detailed structure will not be described in detail here.

[0078] In the memory cell array structure 450, two antifuse OTP memory cells c11-c12 in the first column are connected to word line WL1, follower line control line FL1, and antifuse control line AF1. The two antifuse OTP memory cells c11-c12 in the first column are also connected to the corresponding bit lines BL1 and BL2. Furthermore, two antifuse OTP memory cells c21-c22 in the second column are connected to word line WL2, follower line control line FL2, and antifuse control line AF2. The two antifuse OTP memory cells c21-c22 in the second column are also connected to the corresponding bit lines BL1 and BL2.

[0079] like Figure 5 As shown, the antifuse control lines AF1 and AF2 receive the programming voltage V. PP Follower control lines FL1 and FL2 receive the first control voltage V FL1 Bit line BL1 receives the ground voltage (0V), and bit line BL2 receives the inhibit voltage (V). INH The word line WL1 receives the turn-on voltage V. ON The word line WL2 receives the off voltage V. OFF For example, the programming voltage V PP The first control voltage is 5V. FL1 The voltage is 2V, and the turn-on voltage is V. ON The voltage is 1.2V, and the shutdown voltage is V. OFF The voltage is 0V, and the suppression voltage is V. INH It is 1.2V.

[0080] At this time, the first column connected to word line WL1 is the selected row, the second column connected to word line WL2 is the unselected row, and the two memory cells c21 to c22 in the second column are unselected cells. Additionally, bit line BL1 receives a ground voltage (0V) and bit line BL2 receives an inhibitor voltage (V). INH Therefore, antifuse OTP memory cell c11 is a selected cell, and antifuse OTP memory cell c12 is a non-selected cell. Furthermore, in the memory cell array structure 450, the selected cell c11 is programmed, while the non-selected cell is programmed and suppressed.

[0081] Please refer to Figure 6A The illustration depicts a third embodiment of the antifuse OTP memory cell of the present invention. The antifuse OTP memory cell 500 includes a select element 510, a follower element 520, and an antifuse transistor M. AF .

[0082] In the antifuse OTP memory cell 500, the first terminal of the select element 510 is connected to the bit line BL, the select terminal of the select element 510 is connected to the word line WL, the second terminal of the select element 510 is connected to node y, the first terminal of the follower element 520 is connected to node y, multiple control terminals of the follower element 520 are connected to multiple follower control lines FL1, FL2, and the second terminal of the follower element 520 is connected to node z. The antifuse transistor M... AF The first drain / source terminal is connected to node z, and the antifuse transistor M AF The gate terminal of the antifuse transistor M is connected to the antifuse control line AF. AF The second drain / source terminal is floating.

[0083] According to a third embodiment of the present invention, the selection element 510 comprises a selection transistor M S1 The follower element 520 consists of two follower transistors M. FL1 M FL2 Composition. In the selection of component 510, select transistor M. S1 The first drain / source terminal is connected to the bit line BL, and the selection transistor M is selected. S1 The gate terminal is connected to the word line WL, and the selection transistor M is selected. S1 The second drain / source terminal is connected to node y. In follower element 520, follower transistor M FL1 The first drain / source terminal is connected to node y, following transistor M. FL1 The gate terminal is connected to the follower control line FL1, and the follower transistor M FL1The second drain / source terminal is connected to the follower transistor M. FL2 The first drain / source terminal, followed by transistor M FL2 The gate of the follower transistor M is connected to the follower control line FL2. FL2 The second drain / source is connected to node z.

[0084] Due to the antifuse transistor M AF The second drain / source terminal is floating, so the antifuse transistor M AF It can be considered as a capacitor. That is, the antifuse OTP memory cell 500 in the third embodiment is a three-transistor and one-capacitor memory cell (3T1C cell).

[0085] Please refer to Figure 6B and Figure 6C The diagram shown is a bias diagram of the antifuse OTP memory cell performing programming and programming suppression operations according to the third embodiment.

[0086] like Figure 6B As shown, during programming, the bit line BL receives the ground voltage (0V), and the antifuse control line AF receives the programming voltage (V). PP The word line WL receives the turn-on voltage (V). ON Follow control line FL1 receives the first control voltage V FL1 Following the control line FL2, it receives the second control voltage V. FL2 For example, the programming voltage V PP The voltage is 5V, and the turn-on voltage is V. ON The first control voltage is 1V. FL1 The second control voltage is 1.5V. FL2 It is 2V. Wherein, the turn-on voltage V ON Selectable transistor M can be turned on. S1 That is, to enable selection element 510. Additionally, two control voltages V... FL1 V FL2 Controllable follower transistor M FL1 M FL2 When the device is in the ON state, that is, when the follower element 520 is in the ON state, conduction is achieved between node y and node z. According to the third embodiment of the present invention, the programming voltage V... PP Greater than the second control voltage V FL2 The second control voltage V FL2 Greater than or equal to the first control voltage V FL1 First control voltage V FL1 Greater than the turn-on voltage V ON .

[0087] When selector 510 is turned on and follower 520 is in the on state, the ground voltage (0V) of bit line BL is transmitted to antifuse transistor M. AF The first drain / source terminal enables the antifuse transistor M to... AF The voltage stress between the gate terminal and the first drain / source terminal is the programming voltage V. PP This causes the antifuse transistor M to... AF The gate oxide layer of the antifuse transistor M ruptures. AF The gate terminal and the first drain / source terminal exhibit a low resistance value. That is, the antifuse OTP memory cell 500 is in a low resistance storage state.

[0088] like Figure 6C As shown, during the programming suppression operation, the bit line BL receives the ground voltage (0V), and the antifuse control line AF receives the programming voltage V. PP The word line WL receives the turn-off voltage (V). OFF Follow control line FL1 receives the first control voltage V FL1 Following the control line FL2, it receives the second control voltage V. FL2 For example, the programming voltage V PP The voltage is 5V, and the shut-off voltage is V. OFF The voltage is 0V, and the first control voltage V is... FL1 The second control voltage is 1.5V. FL2 It is 2V. The shutdown voltage V is... OFF Turn-off selection transistor M S1 M S2 That is, turn off the selection element 510.

[0089] When selector 510 is turned off and follower 520 is turned on, the ground voltage (0V) of bit line BL cannot be transmitted to antifuse transistor M. AF The first drain / source terminal enables the antifuse transistor M to... AF The voltage stress between the gate terminal and the first drain / source terminal is very small, and the antifuse transistor M... AF The gate oxide layer is not ruptured, and the antifuse transistor M... AF The gate terminal and the first drain / source terminal maintain a high resistance value. That is, the antifuse OTP memory cell 500 is in a high-resistance storage state.

[0090] In addition, such as Figure 6CAs shown, when the programmed suppression action is performed, component 510 is turned off. At this time, the voltage Vy at node y is Vy = (V FL1 -V tFL1 Selecting component 510 will generate leakage current. For example, the inrush current I... Punch and gate-induced drain current I GIDL1 Additionally, the voltage at node z is Vz = (V PP -V tAF The follower transistor M in the follower electrical component 520 FL2 This will generate leakage current. For example, the gate induces a drain leakage current I. GIDL2 Among them, V tFL1 To follow transistor M FL1 The critical voltage, V tAF For antifuse transistor M AF The critical voltage, V tFL1 Approximately 0.7V, V tAF It is approximately 1V.

[0091] As can be seen from the above explanation, adjusting the first control voltage V FL1 The voltage Vy at node y can be changed, and the inrush current I can be further adjusted. Punch and gate-induced drain current I GIDL1 Therefore, when the first control voltage V FL1 At 1.5V, the voltage Vy at node y is approximately 0.8V (1.5V-0.7V), ensuring that component 510 will hardly generate an inrush current I. Punch And the gate induces a drain current I GIDL1 Very low, approximately 1 nA.

[0092] Similarly, adjust the second control voltage V FL2 The follower transistor M can be changed FL2 The voltage difference between the second drain / source terminal (node ​​z) and the gate terminal is further adjusted to control the gate-induced drain current I. GIDL2 Therefore, when the second control voltage V FL2 When the voltage is 2V, the voltage Vz at node z is approximately 4V (5V-1V), following the transistor M. FL2 The voltage difference between the second drain / source terminal and the gate terminal is approximately 2V (4V-2V), and the gate induces a drain current I. GIDL2 Very low, approximately 3 nA.

[0093] Please refer to Figure 7The diagram illustrates a memory cell array structure and its bias schematic representing an antifuse OTP memory cell array according to a third embodiment of the present invention. The memory cell array structure 550 consists of 2×2 antifuse OTP memory cells c11 to c22. However, the present invention is not limited to the memory cell array structure 550 with 2×2 antifuse OTP memory cells c11 to c22. Those skilled in the art can construct a memory cell array structure with m×n antifuse OTP memory cells according to the description of the present invention, where m and n are positive integers. For example, the antifuse OTP memory cell c11 includes a select element 551, a follower element 552, and an antifuse transistor M. AF Furthermore, the structures of antifuse OTP memory cells c11 to c22 are the same as... Figure 6A Its detailed structure will not be described in detail here.

[0094] In the memory cell array structure 550, two antifuse OTP memory cells c11-c12 in the first column are connected to word line WL1, follower line control lines FL1 and FL2, and antifuse control line AF1. The two antifuse OTP memory cells c11-c12 in the first column are also connected to the corresponding bit lines BL1 and BL2. Furthermore, two antifuse OTP memory cells c21-c22 in the second column are connected to word line WL2, follower line control lines FL3 and FL4, and antifuse control line AF2. The two antifuse OTP memory cells c21-c22 in the second column are also connected to the corresponding bit lines BL1 and BL2.

[0095] like Figure 7 As shown, the antifuse control lines AF1 and AF2 receive the programming voltage V. PP Follower control lines FL1 and FL3 receive the first control voltage V. FL1 Follower control lines FL2 and FL4 receive the second control voltage V. FL2 Bit line BL1 receives the ground voltage (0V), and bit line BL2 receives the inhibit voltage (V). INH The word line WL1 receives the turn-on voltage V. ON The word line WL2 receives the off voltage V. OFF For example, the programming voltage V PP The first control voltage is 5V. FL1 The second control voltage is 1.5V. FL2 The voltage is 2V, and the turn-on voltage is V. ON The voltage is 1V, and the off voltage is V. OFF The voltage is 0V, and the suppression voltage is V. INH It is 1.2V.

[0096] At this time, the first column connected to word line WL1 is the selected row, the second column connected to word line WL2 is the unselected row, and the two memory cells c21 to c22 in the second column are unselected cells. Additionally, bit line BL1 receives a ground voltage (0V) and bit line BL2 receives an inhibitor voltage (V). INH Therefore, antifuse OTP memory cell c11 is a selected cell, and antifuse OTP memory cell c12 is a non-selected cell. Furthermore, in the memory cell array structure 550, the selected cell c11 is programmed, while the non-selected cell is programmed and suppressed.

[0097] Similarly, the antifuse OTP memory cells of the first embodiment can also form a memory cell array, and an appropriate bias voltage is provided to the memory cell array so that the memory cells of the memory cell array perform programming operations or programming suppression operations. Furthermore, the various bias voltages disclosed in the programming and programming suppression operations of the antifuse OTP memory cell of the present invention are not intended to limit the present invention. Those skilled in the art can appropriately modify the bias voltages of the programming and programming suppression operations and apply them to the antifuse OTP memory cell of the present invention.

[0098] In summary, although the present invention has been disclosed in conjunction with the above preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A memory cell array structure, comprising a first antifuse type one-time programmable memory cell, a second antifuse type one-time programmable memory cell, and a third antifuse type one-time programmable memory cell, wherein the first antifuse type one-time programmable memory cell comprises: A first selection element, wherein a first end of the first selection element is connected to a first bit line, a second end of the first selection element is connected to a first node, and a selection end of the first selection element is connected to a first word line; A first follower element, wherein a first end of the first follower element is connected to the first node, a second end of the first follower element is connected to the second node, and a first control end of the first follower element is connected to a first follower control line; as well as A first antifuse transistor, wherein the first drain / source terminal of the first antifuse transistor is connected to the second node, the gate terminal of the first antifuse transistor is connected to the first antifuse control line, and the second drain / source terminal of the first antifuse transistor is floating; The first selection element includes a first selection transistor and a second selection transistor. The first drain / source terminal of the first selection transistor is connected to the first bit line, the gate terminal of the first selection transistor is connected to the first word line, the second drain / source terminal of the first selection transistor is connected to the first drain / source terminal of the second selection transistor, the gate terminal of the second selection transistor is connected to the first word line, and the second drain / source terminal of the second selection transistor is connected to the first node. The second antifuse type one-time programmable memory unit includes: A second selection element, wherein a first end of the second selection element is connected to a second bit line, a second end of the second selection element is connected to a third node, and a selection end of the second selection element is connected to the first word line; A second follower element, wherein a first end of the second follower element is connected to the third node, a second end of the second follower element is connected to the fourth node, and a first control end of the second follower element is connected to the first follower control line; and The second antifuse transistor has its first drain / source terminal connected to the fourth node, its gate terminal connected to the first antifuse control line, and its second drain / source terminal floating. The third antifuse type one-time programmable memory unit includes: The third selection element has a first end connected to the first bit line, a second end connected to the fifth node, and a selection end connected to the second word line. A third follower element, wherein a first end of the third follower element is connected to the fifth node, a second end of the third follower element is connected to the sixth node, and a first control end of the third follower element is connected to the second follower control line; and The third antifuse transistor has its first drain / source terminal connected to the sixth node, its gate terminal connected to the second antifuse control line, and its second drain / source terminal floating. When the first antifuse type primary programmable memory cell is programmed to suppress the operation, the first word line receives a shutdown voltage, the first selection transistor and the second selection transistor are turned off to completely shut down the first selection element and block the leakage current path of the surge current between the first node and the first bit line, so as to generate a smaller leakage current.

2. The memory cell array structure as claimed in claim 1, wherein the first follower element includes a first follower transistor, the first drain / source terminal of the first follower transistor is connected to the first node, the gate terminal of the first follower transistor is connected to the first follower control line, and the second drain / source terminal of the first follower transistor is connected to the second node.

3. The memory cell array structure as claimed in claim 1, wherein during programming, the first bit line receives a ground voltage, the first word line receives an enable voltage, the first follower control line receives a first control voltage, the first antifuse control line receives a programming voltage, the first select element is enabled, the first follower element is in a conducting state, the gate oxide layer of the first antifuse transistor is broken, and it presents a low resistance storage state.

4. The memory cell array structure as described in claim 3, wherein the programming voltage is greater than the first control voltage, and the first control voltage is greater than the turn-on voltage.

5. The memory cell array structure as claimed in claim 1, wherein during the programming suppression operation, the first bit line receives a ground voltage, the first word line receives the shutdown voltage, the first follower control line receives a first control voltage, the first antifuse control line receives a programming voltage, the first select element is off, the first follower element is on, the gate oxide layer of the first antifuse transistor is not broken, and it exhibits a high resistance storage state.

6. The memory cell array structure as claimed in claim 1, wherein the first follower element includes a first follower transistor and a second follower transistor, the first drain / source terminal of the first follower transistor is connected to the first node, the gate terminal of the first follower transistor is connected to the first follower control line, the second drain / source terminal of the first follower transistor is connected to the second drain / source terminal of the second follower transistor, the gate terminal of the second follower transistor is connected to the second follower control line, and the second drain / source terminal of the second follower transistor is connected to the second node.

7. The memory cell array structure as claimed in claim 6, wherein during programming, the first bit line receives a ground voltage, the first word line receives an enable voltage, the first follower control line receives a first control voltage, the second follower control line receives a second control voltage, the first antifuse control line receives a programming voltage, the first select element is enabled, the first follower element is in a conducting state, the gate oxide layer of the first antifuse transistor is broken, and it presents a low resistance storage state.

8. The memory cell array structure as claimed in claim 7, wherein the programming voltage is greater than the second control voltage, the second control voltage is greater than or equal to the first control voltage, and the first control voltage is greater than the turn-on voltage.

9. The memory cell array structure as claimed in claim 6, wherein during the programming suppression operation, the first bit line receives a ground voltage, the first word line receives a shutdown voltage, the first follower control line receives a first control voltage, the second follower control line receives a second control voltage, the first antifuse control line receives a programming voltage, the first select element is off, the first follower element is on, the gate oxide layer of the first antifuse transistor is not broken, and it exhibits a high resistance storage state.

10. A memory cell array structure, the memory cell array structure comprising a first antifuse type one-time programmable memory cell, a second antifuse type one-time programmable memory cell, and a third antifuse type one-time programmable memory cell, wherein the first antifuse type one-time programmable memory cell comprises: A first selection element, wherein a first end of the first selection element is connected to a first bit line, a second end of the first selection element is connected to a first node, and a selection end of the first selection element is connected to a first word line; A first following element, wherein a first end of the first following element is connected to the first node, a second end of the first following element is connected to the second node, a first control terminal of the first following element is connected to a first following control line, and a second control terminal of the first following element is connected to a second following control line; and A first antifuse transistor, wherein the first drain / source terminal of the first antifuse transistor is connected to the second node, the gate terminal of the first antifuse transistor is connected to the first antifuse control line, and the second drain / source terminal of the first antifuse transistor is floating; The first follower element includes a first follower transistor and a second follower transistor. The first drain / source terminal of the first follower transistor is connected to the first node, the gate terminal of the first follower transistor is connected to the first follower control line, the second drain / source terminal of the first follower transistor is connected to the first drain / source terminal of the second follower transistor, the gate terminal of the second follower transistor is connected to the second follower control line, and the second drain / source terminal of the second follower transistor is connected to the second node. The second antifuse type one-time programmable memory unit includes: A second selection element, wherein a first end of the second selection element is connected to a second bit line, a second end of the second selection element is connected to a third node, and a selection end of the second selection element is connected to the first word line; A second follower element, wherein a first end of the second follower element is connected to the third node, a second end of the second follower element is connected to the fourth node, a first control end of the second follower element is connected to the first follower control line, and a second control end of the second follower element is connected to the second follower control line; and The second antifuse transistor has its first drain / source terminal connected to the fourth node, its gate terminal connected to the first antifuse control line, and its second drain / source terminal floating. The third antifuse type one-time programmable memory unit includes: The third selection element has a first end connected to the first bit line, a second end connected to the fifth node, and a selection end connected to the second word line. A third follower element, wherein a first end of the third follower element is connected to the fifth node, a second end of the third follower element is connected to the sixth node, a first control end of the third follower element is connected to a third follower control line, and a second control end of the third follower element is connected to a fourth follower control line; and The third antifuse transistor has its first drain / source terminal connected to the sixth node, its gate terminal connected to the second antifuse control line, and its second drain / source terminal floating. When performing a programming suppression operation on the first antifuse type primary programmable memory cell, the first word line receives a shutdown voltage to shut down the first select element, and applies a first control voltage to the first follower control line to reduce the inrush current generated by the first select element and the first gate-induced drain current, and applies a second control voltage to the second follower control line to reduce the second gate-induced drain current generated by the second follower transistor.

11. The memory cell array structure of claim 10, wherein the first selection element includes a first selection transistor, the first drain / source terminal of the first selection transistor is connected to the first bit line, the gate terminal of the first selection transistor is connected to the first word line, and the second drain / source terminal of the first selection transistor is connected to the first node.

12. The memory cell array structure of claim 10, wherein during programming, the first bit line receives a ground voltage, the first word line receives an enable voltage, the first follower control line receives the first control voltage, the second follower control line receives the second control voltage, the first antifuse control line receives a programming voltage, the first select element is enabled, the first follower element is in a conducting state, the gate oxide layer of the first antifuse transistor is broken, and it presents a low resistance storage state.

13. The memory cell array structure of claim 12, wherein the programming voltage is greater than the second control voltage, the second control voltage is greater than or equal to the first control voltage, and the first control voltage is greater than the turn-on voltage.

14. The memory cell array structure of claim 10, wherein during the programming suppression operation, the first bit line receives a ground voltage, the first word line receives the shutdown voltage, the first follower control line receives a first control voltage, the second follower control line receives a second control voltage, the first antifuse control line receives a programming voltage, the first select element is off, the first follower element is on, the gate oxide layer of the first antifuse transistor is not broken, and it exhibits a high resistance storage state.

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