Read latency and stall mode

Abstract

This application relates to read latency and stall mode. A memory system can operate in a first operating mode associated with a first set of access operations including performing read operations, performing write operations, and stalling write operations. The memory system can receive an indication from a host system to switch to a second operating mode associated with a reduced latency for performing write operations based on limiting stalling write operations. For example, the host system can transmit a command including the indication to switch to the second operating mode. In another example, the host system can write a value to a register at the memory system including the indication to switch to the second operating mode. Based on receiving the indication from the host system, the memory system can then operate according to the second operating mode.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 395,295, filed August 5, 2021, entitled “Read Latency and Suspend Modes”, which is assigned to the assignee and is expressly incorporated herein by reference. Technical Field

[0003] The technical field involves read latency and pause modes. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to typically correspond to one of two supported states, logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, either of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time even without an external power supply. Summary of the Invention

[0006] A device is described. The device may include a memory device and a controller coupled to the memory device. The controller may be configured to cause the device to: operate the device according to a first operating mode associated with a first set of access operations, the first set of access operations including performing a read operation, performing a write operation, and pausing a write operation; receive from a host system an instruction to switch to a second operating mode based on operating the device according to the first operating mode, the second operating mode being associated with reduced latency for performing write operations based on limiting the paused write operation; and operate the device according to the second operating mode based on receiving the instruction.

[0007] Describe an apparatus. The apparatus may include a controller configured to couple to a memory system. The controller may be configured to cause the apparatus to: identify a first write execution latency associated with the memory system, the memory system operating according to a first operating mode associated with a first set of access operations including performing a read operation, performing a write operation, and pausing a write operation; based on the identification, transmit an indication to the memory system to switch to a second operating mode, the second operating mode being associated with reduced latency for performing write operations based on limiting the pausing write operations; and based on transmitting the indication, determine whether a second write execution latency associated with the memory system operating according to the second operating mode is less than the first write execution latency.

[0008] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code. The code may contain instructions that, when executed by a processor of an electronic device, cause the electronic device to: operate the electronic device according to a first operating mode associated with a first set of access operations including performing a read operation, performing a write operation, and pausing a write operation; receive from a host system an instruction to switch to a second operating mode based on operating the electronic device according to the first operating mode, the second operating mode being associated with reduced latency for performing a write operation based on limiting the paused write operation; and operate the electronic device according to the second operating mode based on receiving the instruction.

[0009] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code. The code may contain instructions that, when executed by a processor of an electronic device, cause the electronic device to: identify a first write execution latency associated with a memory system operating according to a first operating mode associated with a first set of access operations including performing a read operation, performing a write operation, and pausing a write operation; based on the identification, transmit an indication to the memory system to switch to a second operating mode, the second operating mode being associated with reduced latency for performing write operations based on limiting the pausing write operation; and based on transmitting the indication, determine whether a second write execution latency associated with the memory system operating according to the second operating mode is less than the first write execution latency. Attached Figure Description

[0010] Figure 1 This document describes instances of systems that support read latency and pause modes, based on the examples disclosed herein.

[0011] Figure 2 This document describes instances of systems that support read latency and pause modes, based on the examples disclosed herein.

[0012] Figure 3 This document describes instances of process flows that support read latency and pause modes, based on the examples disclosed herein.

[0013] Figure 4 A block diagram is shown illustrating a memory system that supports read latency and pause modes based on the examples disclosed herein.

[0014] Figure 5 A block diagram is shown illustrating a host system that supports read latency and pause modes based on the examples disclosed herein.

[0015] Figure 6 and 7 The flowchart illustrates one or more methods that support read latency and pause modes based on the examples disclosed in this article. Detailed Implementation

[0016] Memory systems can perform various types of access operations. For example, a memory system can perform read operations, write operations, erase operations, or any combination thereof. In some instances, write and erase operations may take longer to perform than read operations. For instance, in some NAND devices, performing a write operation (e.g., three-level cell (TLC) programming) or an erase operation (e.g., TLC erase) may take several milliseconds (ms), while a read operation can be performed in tens of microseconds (μs). In some cases, performing a write or erase operation can thus introduce latency into the execution of a read operation. To reduce the read operation latency introduced by write and erase operations, the memory system can pause the execution of write or erase operations to perform read operations (e.g., during a programming pause mode). To perform read operations as quickly as possible and reduce the latency associated with performing read operations, the memory system can reduce pause latency (e.g., interrupting an ongoing write or erase operation and making the memory array available for read operations in a relatively short amount of time). Additionally, the latency of paused operations can be increased by the pause duration (e.g., the time the operation is paused) and the time associated with preparing for the pause and resume operations. Pausing write and erase operations in a relatively quick manner can be associated with programming or erasing algorithms used for backup and recovery (e.g., repeating the last interrupted steps or, in some cases, repeating more steps), and increases the latency associated with the interrupted operation execution. In some cases (e.g., video recording), this increased latency associated with write operation execution can impact the user experience of the application (e.g., causing frame loss and degrading video quality).

[0017] As described herein, a memory system can operate according to a mode that reduces latency associated with write operations. For example, a memory system can operate according to an operating mode that restricts pauses in write and erase operations (e.g., thus reducing write execution latency). In some cases, the memory system can operate according to this operating mode in response to an instruction received from a host system. For example, the host system can transmit a command or set a flag to instruct the memory system to operate according to an operating mode associated with reduced write operation latency. Here, the memory system can switch from a first operating mode (e.g., where pauses in write operations are not restricted) based on or in response to an instruction received from the host system. Switching between operating modes can increase the performance of the memory system and improve the user experience.

[0018] First, refer to Figure 1 and 2 The features of this disclosure are described within the context of the system being described. (Referencing...) Figure 3 The features of this disclosure are described in the context of the process flow. These and other features of this disclosure are described by reference to... Figures 4 to 7Further explanation and description are provided in the context of device diagrams and flowcharts involving read latency and pause modes.

[0019] Figure 1 This describes an instance of system 100 that supports read latency and pause modes based on the examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0020] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-line Memory Module (DIMM), a Small Form Factor DIMM (SO-DIMM), or a Non-Volatile DIMM (NVDIMM), and other possibilities.

[0021] System 100 may be contained in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., an airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment or networked commercial device), or any other computing device containing memory and processing devices.

[0022] System 100 may include a host system 105, which may be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to the host system 105 or included in the host system), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110 to, for example, write data to and read data from the memory system 110. Although in Figure 1The image shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0023] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise transmit control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be included in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0024] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0025] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations generally referred to as access operations at the memory device 130, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to implement the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and with one or more memory devices 130 (e.g., in response to or otherwise associated with a command from the host system 105). For example, the memory system controller 115 may translate responses associated with the memory device 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0026] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, unused cell collection, error control operations such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0027] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0028] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, local memory 120 may act as a cache for the memory system controller 115. For example, if data is read from or written to memory device 130, data may be stored in local memory 120 and may be available in local memory 120 for subsequent retrieval or manipulation (e.g., updates) by the host system 105 according to a caching strategy (e.g., with reduced latency relative to memory device 130).

[0029] although Figure 1 The example of memory system 110 described herein has been illustrated as including memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on external controllers (e.g., implemented by host system 105) or one or more local controllers 135 within memory device 130 to perform the functions attributed herein to memory system controller 115. Generally, one or more functions attributed herein to memory system controller 115 may, in some cases, be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130, at least partially managed by memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0030] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0031] In some instances, memory device 130 may (e.g., on the same die or within the same package) include a local controller 135 that can perform operations on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. For example, such as Figure 1 As described, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a piece of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0033] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as a multi-level cell (MLC) when configured to store two bits of information, a TLC when configured to store three bits of information, a QLC when configured to store four bits of information, or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density than SLC memory cells, but in some cases, may involve narrower read or write tolerances or greater complexity to support the circuitry.

[0034] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations can occur within different planes 165. For example, parallel operations can be performed on memory cells within different blocks 170, as long as the different blocks 170 are located in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and virtual blocks 180 may refer to a group of blocks 170 within which parallel operations can occur. For example, parallel operations can be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d can be collectively referred to as virtual blocks 180. In some cases, virtual block 180 may contain blocks 170 from different memory devices 130 (e.g., blocks 170 in one or more planes 165 containing memory devices 130-a and 130-b). In some cases, blocks 170 within virtual block 180 may have the same block address within their respective planes 165 (e.g., block 170-a may be “block 0” of plane 165-a, block 170-b may be “block 0” of plane 165-b, and so on). In some cases, performing parallel operations in different planes 165 may be subject to one or more limitations, such as performing parallel operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., involving command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0035] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be called a bit line) (e.g., coupled thereto).

[0036] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first-level granularity (e.g., at the page level), but may be erased at a second-level granularity (e.g., at the block level). That is, page 175 may be the smallest unit of memory (e.g., a group of memory cells) that can be independently programmed or read (e.g., programmed or read in parallel as part of a single programming or reading operation), and block 170 may be the smallest unit of memory (e.g., a group of memory cells) that can be independently erased (e.g., erased in parallel as part of a single erase operation). Furthermore, in some cases, NAND memory cells may be erased before they can be rewritten with new data. Therefore, for example, in some cases, used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0037] In some cases, to update some data within block 170 while retaining other data within block 170, memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages 175 of the new block 170. Memory device 130 (e.g., local controller 135) or memory system controller 115 may mark or otherwise designate data held in the old block 170 as invalid or obsolete, and may update the logical-to-physical (L2P) mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170 rather than the old invalid block 170. In some cases, such copying and remapping may be performed instead of erasing and rewriting the entire old block 170, for example, due to latency or attrition considerations. In some cases, one or more copies of the L2P mapping table may be stored within memory cells of memory device 130 (e.g., within one or more blocks 170 or planes 165) for use by local controller 135 or memory system controller 115 (e.g., for reference and updating).

[0038] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, useless cell collection, cleanup, block scan, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in block 170 to have invalid data before erasing and reusing block 170, an algorithm called “useless cell collection” may be invoked to allow block 170 to be erased and freed up for subsequent write operations. Useless cell collection may refer to a set of media management operations that include, for example, selecting block 170 containing valid and invalid data, selecting pages 175 in the block containing valid data, copying the valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected pages 175 as invalid, and erasing the selected block 170. Therefore, the number of erased blocks 170 can be increased so that more blocks 170 can be used to store subsequent data (e.g., data subsequently received from the host system 105).

[0039] System 100 may include any number of non-transitory computer-readable media that support read latency and pause modes. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform functions belonging to host system 105, memory system controller 115, or memory device 130 herein. For example, if executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), such instructions may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0040] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system 110, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of managed memory system 110 is a managed NAND (MNAND) system.

[0041] In some cases, the memory system controller 115 or local controller 135 may adjust the operation of the memory system 110 based on or in response to the workload associated with the memory system 110 (e.g., based on or in response to a queue of operations to be performed by the memory system 110). That is, the memory system controller 115 or local controller 135 may operate the memory system 110 differently when performing multiple read operations (e.g., random read operations) and when performing multiple write operations. In some cases, the memory system controller 115 or local controller 135 (e.g., executing the firmware of the memory system 110) may reorganize resources based on or in response to the workload associated with the memory system 110. That is, the memory system controller 115 or local controller 135 may reallocate SRAM from a buffer (e.g., at the memory system 110) to a table cache, prefetch data, enable deeper pipelines, or perform other operations to reorganize resources based on or in response to the workload associated with the memory system 110.

[0042] In some instances, the memory system controller 115 or the local controller 135 may selectively suspend the execution of write and erase operations on the memory device 130 (e.g., by entering a programming pause mode). That is, performing write and erase operations on the memory device 130 may take longer than performing read operations on the memory device 130. For example, performing a write operation on the memory device 130 may take one to twenty ms, while performing a read operation may take about ten μs. By entering a programming pause mode, the memory system controller 115 or the local controller 135 can pause write and erase operations while continuing to perform read operations on the memory device 130. Therefore, the read execution latency associated with the memory device 130 can be reduced during the programming pause mode.

[0043] In some cases, the memory system controller 115 or the local controller 135 may enter a programming pause mode based on or in response to pre-configured settings. For example, the memory system 110 may enter a programming pause mode based on or in response to hardware decoding settings in the firmware of the memory system 110. In cases of mixed workloads (e.g., the memory system 110 is performing read, write, and erase operations), entering a programming pause mode based on pre-configured settings may not improve the overall performance of the memory system 110. That is, when the memory system 110 is performing operations associated with a large number of write operations (e.g., video recording), entering a programming pause mode based on pre-configured settings can significantly impact the performance of the memory system 110 and the user experience.

[0044] In an example of system 100, host system 105 may be configured to instruct memory system 110 to operate according to an operating mode associated with reduced write operation latency. For example, when host system 105 relies on memory system 110 to perform a workload associated with more write operations than read operations (e.g., for video recording), host system 105 may instruct memory system 110 to operate according to an operating mode associated with reduced write operation latency. In response to memory system 110 receiving an instruction from host system 105 to operate according to an operating mode associated with reduced write operation latency, memory system 110 may switch from a first operating mode (e.g., associated with entering a programming pause mode according to preconfigured settings) to a second operating mode (e.g., associated with limiting the pause of write operations). Thus, the performance of memory system 110 may be improved (e.g., by limiting the pause of write operations). In some cases, host system 105 may subsequently instruct memory system 110 to switch back to the first operating mode, where memory system 110 enters the programming pause mode according to preconfigured settings.

[0045] Figure 2 This document describes an instance of System 200 that supports read latency and pause modes, based on the examples disclosed herein. System 200 may be used as a reference. Figure 1 Examples of the described system 100 or its aspects thereof. System 200 may include a memory system 210 configured to store data received from host system 205 and to send data to host system 205 upon request by host system 205 using access commands (e.g., read commands or write commands). System 200 may be implemented as referenced. Figure 1 The various aspects of the system 100 described. For example, memory system 210 and host system 205 may be instances of memory system 110 and host system 105, respectively.

[0046] As described herein, memory system 210 may include memory device 240 for storing, for example, data transferred between memory system 210 and host system 205 in response to receiving an access command from host system 205. Memory device 240 may include, as referenced... Figure 1 The memory device 240 may include one or more memory devices as described. For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-point, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0047] Memory system 210 may include a memory controller 230 for controlling the transfer of data directly to and from memory device 240, for example, for storing data, retrieving data, and determining memory locations where data is to be stored and retrieved. The memory controller 230 may communicate with memory device 240 directly or via a bus (not shown) using protocols specific to each type of memory device 240. In some cases, a single memory controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, memory system 210 may include multiple memory controllers 230, for example, different memory controllers 230 for each type of memory device 240. In some cases, the memory controller 230 may implement a reference... Figure 1 The local controller 135 is described in various aspects.

[0048] The memory system 210 may additionally include an interface 220 for communicating with the host system 205, and a buffer 225 for temporarily storing data being transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 can be used to transfer data between the host system 205 and the memory device 240, as illustrated by the data path 250, and can be collectively referred to as the data path components.

[0049] Using buffer 225 to temporarily store data during transmission allows data to be buffered while commands are being processed, thereby reducing latency between commands and allowing for arbitrary data sizes associated with commands. This also allows for handling command bursts, and once the burst stops, the buffered data can be stored or transmitted (or both). Buffer 225 may contain relatively fast memory (e.g., some type of volatile memory such as SRAM or DRAM) or hardware accelerators or both to allow for fast storage and retrieval of data in and out of buffer 225. Buffer 225 may include data path switching components for bidirectional data transfer between buffer 225 and other components.

[0050] Temporary storage of data within buffer 225 refers to the storage of data in buffer 225 during the execution of an access command. That is, after the access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., data may be overwritten using additional access commands). Additionally, buffer 225 can be a non-cached buffer. That is, the host system 205 may not read data directly from buffer 225. For example, a read command can be added to a queue without performing an operation to match the address with an address already existing in buffer 225 (e.g., no cached address matching or lookup operation).

[0051] The memory system 210 may additionally include a memory system controller 215 for executing commands received from the host system 205 and controlling data path components when moving data. The memory system controller 215 may be as described in reference... Figure 1 An example of the described memory system controller 115. Bus 235 can be used for communication between system components.

[0052] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and storage queue 270) can be used to control the processing of access commands and the movement of corresponding data. This can be advantageous, for example, when the memory system 210 processes more than one access command from the host system 205 in parallel. As examples of possible implementations, command queue 260, buffer queue 265, and storage queue 270 are depicted at interface 220, memory system controller 215, and storage controller 230, respectively. However, they can be located anywhere within the memory system 210 if used.

[0053] Data transferred between host system 205 and memory device 240 may take a different path within memory system 210 than non-data information (e.g., commands, status information). For example, system components in memory system 210 may communicate with each other using bus 235, while data may use data path 250 via data path components instead of bus 235. Memory system controller 215 may control how and whether data is transferred between host system 205 and memory device 240 by communicating with data path components via bus 235 (e.g., using a protocol specific to memory system 210).

[0054] If host system 205 transmits an access command to memory system 210, the command can be received by interface 220, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). Therefore, interface 220 can be considered as the front end of memory system 210. Upon receiving each access command, interface 220 can transmit the command to memory system controller 215, for example, via bus 235. In some cases, each command can be added to command queue 260 via interface 220 to transmit the command to memory system controller 215.

[0055] The memory system controller 215 may determine whether an access command has been received based on or in response to communication from the interface 220. In some cases, the memory system controller 215 may determine that the command has been received by retrieving the access command from the command queue 260. The command may be removed from the command queue 260 after it has been retrieved, for example, by the memory system controller 215. In some cases, the memory system controller 215 may cause the interface 220 to remove the command from the command queue 260, for example, via the bus 235.

[0056] When it is determined that an access command has been received, the memory system controller 215 may execute the access command. For a read command, this may mean obtaining data from the memory device 240 and transferring the data to the host system 205. For a write command, this may mean receiving data from the host system 205 and moving the data to the memory device 240. In some cases, the memory system controller 215 may determine that an access command has not yet been received and may not execute the access command.

[0057] In either case, the memory system controller 215 may use the buffer 225, particularly for temporary storage of data received from or sent to the host system 205. The buffer 225 can be considered as an intermediate part of the memory system 210. In some cases, buffer address management (e.g., pointers to address locations within the buffer 225) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0058] In order to process a write command received from host system 205, memory system controller 215 may first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine, for example, via firmware (e.g., controller firmware) whether the amount of space within buffer 225 is available to store the data associated with the write command.

[0059] In some cases, buffer queue 265 can be used to control a stream of commands associated with data stored in buffer 225, the stream of commands including write commands. Buffer queue 265 may contain access commands associated with data currently stored in buffer 225. In some cases, commands in command queue 260 can be moved to buffer queue 265 via memory system controller 215 and can remain in buffer queue 265 while the associated data is stored in buffer 225. In some cases, each command in buffer queue 265 may be associated with an address at buffer 225. That is, a pointer indicating where the data associated with each command is stored in buffer 225 can be maintained. Using buffer queue 265, multiple access commands can be received sequentially from host system 205 and at least a portion of the access commands can be processed in parallel.

[0060] If buffer 225 has sufficient space to store the write data, memory system controller 215 may cause interface 220 to transmit an availability indication (e.g., a "ready to transfer" indication) to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). When interface 220 subsequently receives data associated with the write command from host system 205, interface 220 may use data path 250 to transfer the data to buffer 225 for temporary storage. In some cases, interface 220 may obtain the location of the stored data within buffer 225 from buffer 225 or buffer queue 265. Interface 220 may indicate to memory system controller 215, for example, via bus 235 whether the data transfer to buffer 225 has been completed.

[0061] Once the written data has been stored in buffer 225 via interface 220, the data can be transferred from buffer 225 and stored in memory device 240. This can be accomplished using memory controller 230. For example, memory system controller 215 can cause memory controller 230 to retrieve data from buffer 225 using data path 250 and transfer the data to memory device 240. Memory controller 230 can be considered as the back-end of memory system 210. Memory controller 230 can, for example, indicate to memory system controller 215 via bus 235 that the data transfer to memory device 240 has been completed.

[0062] In some cases, storage queue 270 can be used to assist in the transfer of write data. For example, memory system controller 215 can push write commands from buffer queue 265 (e.g., via bus 235) to storage queue 270 for processing. Storage queue 270 may contain entries for each access command. In some instances, storage queue 270 may additionally include: a buffer pointer (e.g., an address) indicating where in buffer 225 the data associated with the command is stored; and a storage pointer (e.g., an address) indicating the location in memory device 240 associated with said data. In some cases, storage controller 230 can obtain the location within buffer 225 from which data is to be obtained, from buffer 225, buffer queue 265, or storage queue 270. Storage controller 230 can manage the location within memory device 240 where data is to be stored (e.g., performing wear leveling, waste cell collection, etc.). Entries can be added to storage queue 270, for example, via memory system controller 215. After the data transfer is complete, the entry can be removed from the storage queue 270, for example, by the storage controller 230 or the memory system controller 215.

[0063] In order to process a read command received from host system 205, memory system controller 215 may again first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine, for example via firmware (e.g., controller firmware), whether the amount of space within buffer 225 is available to store the data associated with the read command.

[0064] In some cases, buffer queue 265 can be used to supplement buffer storage of data associated with a read command in a manner similar to that discussed above with respect to write commands. For example, if buffer 225 has sufficient space to store the read data, memory system controller 215 can cause memory controller 230 to retrieve the data associated with the read command from memory device 240 and store the data in buffer 225 for temporary storage using data path 250. Memory controller 230 can indicate to memory system controller 215, for example, via bus 235, whether the data transfer to buffer 225 has been completed.

[0065] In some cases, the storage queue 270 can be used to assist in the transfer of read data. For example, the memory system controller 215 can push a read command to the storage queue 270 for processing. In some cases, the storage controller 230 can obtain the location within the memory device 240 from the buffer 225 or the storage queue 270 for retrieving data. In some cases, the storage controller 230 can obtain the location within the buffer 225 for storing data from the buffer queue 265. In some cases, the storage controller 230 can obtain the location within the buffer 225 for storing data from the storage queue 270. In some cases, the memory system controller 215 can move commands processed by the storage queue 270 back to the command queue 260.

[0066] Once data has been stored in buffer 225 by storage controller 230, it can be transferred out of buffer 225 and sent to host system 205. For example, storage system controller 215 can enable interface 220 to retrieve data from buffer 225 using data path 250 and transfer the data to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). For example, interface 220 can process commands from command queue 260 and can indicate to storage system controller 215, for example, via bus 235, that the data transfer to host system 205 is complete.

[0067] The memory system controller 215 can execute received commands in a sequence (e.g., according to the order of command queue 260, in a first-in, first-out order). For each command, the memory system controller 215 can cause the data corresponding to the command to move in and out of buffer 225, as discussed above. While the data is moved into and stored in buffer 225, the command can remain in buffer queue 265. If processing of the command has been completed (e.g., if the data corresponding to the access command has been transferred out of buffer 225), the command can be removed from buffer queue 265, for example, via the memory system controller 215. If the command is removed from buffer queue 265, the address where the data previously associated with the command was stored can be used to store the data associated with the new command.

[0068] In some cases, the memory system controller 215 may adjust the operation of the memory system 210 based on or in response to commands in the command queue 260 (e.g., based on or in response to the workload associated with the memory system 210). That is, the memory system controller 215 may operate the memory system 210 differently when performing multiple random read operations versus performing multiple write operations. In some cases, the memory system controller 215 (e.g., executing the firmware of the memory system 210) may reorganize resources based on or in response to the workload associated with the memory system 210. That is, the memory system controller 215 may reallocate SRAM from buffer 225 to table cache, prefetch data (e.g., from memory device 240), enable deeper pipelines, or perform other operations to reorganize resources based on or in response to commands in the command queue 260.

[0069] In some instances, the memory system controller 215 can selectively suspend the execution of write and erase operations on the memory device 240 (e.g., by entering a programming pause mode). That is, performing write and erase operations on the memory device 240 may take longer than performing read operations on the memory device 240. For example, performing a write operation on the memory device 240 may take one to twenty ms, while performing a read operation may take about ten μs. By entering a programming pause mode, the memory system controller 215 can pause write and erase operations while continuing to perform read operations on the memory device 240. Therefore, the read execution latency associated with the memory device 240 can be reduced during the programming pause mode.

[0070] In some cases, the memory system controller 215 may enter a programming pause mode based on or in response to pre-configured settings. For example, the memory system 210 may enter a programming pause mode based on or in response to hardware decoding settings in the firmware of the memory system 210. In cases of mixed workloads (e.g., the memory system 210 is performing read, write, and erase operations), entering a programming pause mode based on pre-configured settings may not improve the overall performance of the memory system 210. That is, when the memory system 210 is performing operations associated with a large number of write operations (e.g., video recording), entering a programming pause mode based on pre-configured settings can significantly impact the performance of the memory system 210 and the user experience.

[0071] In an example of system 200, host system 205 may instruct memory system 210 to operate according to an operating mode associated with reduced write operation latency. For example, when host system 205 relies on memory system 210 to perform a workload associated with more write operations than read operations (e.g., for video recording), host system 205 may instruct memory system 210 to operate according to an operating mode associated with reduced write operation latency. Host system 205 may instruct memory system 210 to operate according to an operating mode associated with reduced write operation latency by transmitting a command (e.g., via interface 220 to memory system controller 215) or by setting a register at memory system 210 (e.g., within interface 220) to a value indicating an operating mode associated with reduced write operation latency. In response to memory system 210 receiving an instruction from host system 205 to operate according to an operating mode associated with reduced write operation latency, memory system 210 may switch from a first operating mode (e.g., associated with entering a programming pause mode according to preconfigured settings) to a second operating mode (e.g., associated with a pause that restricts write operations). Therefore, the performance of memory system 210 can be improved (e.g., by limiting the pause of write operations). In some cases, host system 205 may subsequently instruct memory system 210 to switch back to a first operating mode, wherein memory system 210 enters a programming pause mode according to pre-configured settings.

[0072] The memory system controller 215 may be additionally configured for operations associated with the memory device 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling, unused cell collection, error control operations such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue commands indicating one or more LBAs, and the memory system controller 215 may identify one or more physical block addresses indicated by the LBAs. In some cases, one or more consecutive LBAs may correspond to non-consecutive physical block addresses. In some cases, the memory controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the memory controller 230, and the memory controller 230 may be omitted.

[0073] Figure 3 This document describes an instance of process flow 300 that supports read latency and pause modes, based on the examples disclosed herein. Process flow 300 can be implemented as a reference. Figure 1 and 2 The various aspects of systems 100 and 200 are described. For example, the memory system 310 and the host system 305 may be as described in the reference. Figure 1 and 2 Examples of the described memory system and host system. Aspects of process flow 300 may be implemented by a controller and other components. Alternatively, aspects of process flow 300 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to host system 305 or memory system 310). For example, when executed by a controller (e.g., memory system controller, local controller, host system controller), the instructions cause the controller to perform the operations of process flow 300.

[0074] At 315, the memory system 310 can be operated according to a first operating mode. Here, the memory system 310 can operate according to the first operating mode by performing a read operation, performing a write operation, and pausing a write operation. That is, when operating according to the first operating mode, the memory system 310 can select to pause write and erase operations based on or in response to the firmware of the memory system 310 (e.g., by entering a programming pause mode). In response to the memory system 310 determining to enter the programming pause mode, the memory system can pause the execution of a write operation, an erase operation, or both. In some cases, the memory system 310 can operate according to the programming pause mode for a set or determined time period (e.g., indicated by the firmware of the memory system 310). Alternatively or concurrently, the memory system 310 can operate according to the programming pause mode until a set or determined amount of read operations has been performed (e.g., a set or determined amount of read operations indicated by the firmware of the memory system 310). After performing the time period or the amount of read operations, the memory system 310 can exit the programming pause mode and, based on or in response to, as referenced... Figure 2 The described order of operations continues (e.g., read, write, erase).

[0075] At 320, an indication of write execution latency may be transmitted from memory system 310 to host system 305. That is, memory system 310 may optionally transmit the indication of write execution latency based on or in response to operating memory system 310 according to a first operating mode. In some cases, the write execution latency may be based on or in response to the amount of time spent by memory system 310 in a programming pause mode while operating according to the first operating mode. That is, the write execution latency may increase as the amount of time spent by memory system 310 in programming pause mode increases. Conversely, the write execution latency may decrease as the amount of time spent by memory system 310 in programming pause mode decreases.

[0076] At 325, the host system 305 may identify the write execution latency associated with the memory system 310. In some cases, the host system 305 may identify the write execution latency associated with the memory system 310 based on or in response to receiving an indication of the write execution latency from the memory system 310 at 320. In other cases (e.g., where the memory system 310 does not transmit a write execution latency indication to the host system 305 at 320), the host system 305 may identify the write execution latency based on or in response to the performance of the memory system 310. For example, the memory system 310 may indicate to the host system 305 in response to the completion of a write command. Here, the host system 305 may identify the write execution latency based on or in response to the amount of time between transmitting the write command to the memory system 310 and receiving a completion indication of the write command from the memory system 310. In another instance, the memory system 310 may indicate to the host system 305 the capacity for receiving and executing write commands. Here, host system 305 may identify write execution latency based on or in response to the indicated capacity of the write command received and executed by memory system 310.

[0077] Based on or in response to the write execution latency associated with memory system 310 identified at 325, the host system may determine to instruct memory system 310 to switch to a second operating mode, the second operating mode being associated with reduced latency for performing write operations based on or in response to limiting paused write operations. For example, host system 305 may determine whether the write execution latency exceeds a threshold. Alternatively, host system 305 may determine whether the workload of memory system 310 is associated with a large number of write operations (e.g., compared to the amount of read operations). For example, host system 305 may determine that memory system 310 is capable of performing operations associated with video recording (e.g., the video recording is associated with a large number of read operations compared to the amount of write operations). Here, host system 305 may determine to prioritize write execution latency over read execution latency (e.g., to improve the performance of memory system 310, thereby improving the user experience) by instructing memory system 310 to switch to the second operating mode associated with reduced latency for performing write operations.

[0078] At 330, the host system 305 may transmit an indication to the memory system 310 to switch to a second operating mode associated with reduced latency for performing write operations, based on or in response to limiting write operations to pause. That is, the second operating mode may restrict the memory system 310 to operate in a programming pause mode (e.g., where the memory system 310 pauses write operations, erase operations, or both). In one example, the host system 305 may instruct the memory system 310 to switch to the second operating mode by writing a value containing the indication to a register at the memory system (e.g., setting a flag to instruct the memory system 310 to switch to the second operating mode). Here, the memory system 310 may poll the register and determine the switch to the second operating mode based on or in response to a value stored in the register instructing the memory system 310 to switch to the second operating mode. In another example, the host system 305 may instruct the memory system 310 to switch to the second operating mode by transmitting a command containing the indication to switch to the second operating mode to the memory system 310.

[0079] At 335, the memory system 310 may optionally select a second operating mode from a plurality of operating modes, each of which is associated with reduced latency for performing write operations based on or in response to a restricted pause write operation. That is, the memory system 310 may be configured to operate according to a plurality of different operating modes that restrict write operation pauses (e.g., a restricted programming pause mode). For example, the memory system 310 may be configured to operate according to an operating mode that disables write operation pauses, a mode that significantly reduces write operation pauses, and a mode that slightly reduces write operation pauses (e.g., compared to a first operating mode). Here, the memory system 310 may select the second operating mode from one of the possible operating modes that restrict write operation pauses (e.g., based on or in response to a possible operating mode indicated by the host system 305, based on or in response to a predicted workload of the memory system 310, based on or in response to past operations of the memory system 310).

[0080] At 340, the memory system 310 may be operated according to a second operating mode based on or in response to an instruction received from the host system 305 at 330. If the memory system 310 selects a second operating mode from a plurality of operating modes each associated with reduced latency for performing write operations (e.g., at 335), the memory system 310 may operate at 340 according to the selected second operating mode. In some cases, the memory system 310 may operate according to the second operating mode without needing to receive an instruction from the host system at 330. That is, the memory system 310 may determine to operate according to the second operating mode based on or in response to a workload or planned workload to be performed by the memory system 310 (e.g., a set of commands or a set of predicted commands).

[0081] In one instance, the second operating mode can limit the pause of write operations by disabling the pause of write operations, disabling the pause of erase operations, or disabling the pause of both write and erase operations (e.g., disabling the programming pause mode). Here, the memory system 310 can operate according to the second operating mode by disabling the pause of write operations. Here, the memory system 310 can operate according to the second operating mode by performing read operations and performing write operations.

[0082] In another instance, the second operating mode can limit the pause of write operations by limiting the amount of write operation pauses when operating the memory system 310 according to the second operating mode. For example, the second operating mode may be associated with a threshold amount of write operation pauses (or a threshold amount of a programmed pause mode entry). In some cases, the host system 305 may indicate the threshold amount of write operation pauses associated with the second operating mode within an instruction to switch to the second operating mode. In some other cases, the memory system 310 may identify the threshold amount of write operation pauses associated with the second operating mode at 335 (e.g., based on or in response to a predicted workload of the memory system 310, based on or in response to past operations of the memory system 310). Alternatively or additionally, the second operating mode may be associated with a maximum amount of write operation pauses for each write operation execution. In either case, the memory system 310 may operate according to the second operating mode by identifying a threshold amount of write operation pauses and (e.g., when the memory system 310 operates according to the second operating mode) pausing a certain amount of write operations less than the threshold amount of write operation pauses. Here, the memory system 310 can operate according to the second operating mode by performing a read operation, performing a write operation, and pausing a write operation of a certain amount that is less than a threshold amount.

[0083] In another instance, the second operating mode can limit the pause of write operations by limiting a certain number of read operations performed during each programming pause mode (e.g., during each write pause duration). For example, the second operating mode can be associated with a threshold amount of read operations performed during each programming pause mode (e.g., during each write pause duration). In some cases, host system 305 can indicate the threshold amount of read operations associated with the second operating mode within an indication to switch to the second operating mode. In some other cases, memory system 310 can identify the threshold amount of read operations associated with the second operating mode at 335 (e.g., based on or in response to a predicted workload of memory system 310, based on or in response to past operations of memory system 310). Memory system 310 can operate according to the second operating mode by identifying the threshold amount of read operations performed during the write pause duration and performing fewer read operations than the threshold amount while pausing write operations when operating according to the second operating mode. That is, memory system 310 can operate according to the second operating mode by performing read operations, performing write operations, and performing fewer read operations than the threshold amount when pausing write operations.

[0084] In another instance, the second operating mode can limit the overhead associated with pausing and resuming write operations by changing settings associated with memory system 310 (e.g., pre-configured settings associated with entering a programming pause mode). That is, memory system 310 may include firmware that, when operating memory system 310 according to the first operating mode, triggers memory system 310 to enter a programming pause mode for a certain period of time (e.g., to pause write operations, pause erase operations, pause write operations, and pause erase operations). In some cases, the second operating mode can limit the pause of write operations by reducing the amount of triggering events used to enter programming pause mode (e.g., enabling more or less checkpointing and reducing write operation latency). Memory system 310 can operate according to the second operating mode by reducing the amount of triggering events associated with pausing write operations to limit the pause of write operations. Here, memory system 310 can operate according to the second operating mode by performing read operations, performing write operations, and pausing write operations in response to the reduced amount of triggering events.

[0085] In another instance, the second operating mode can limit the pause of write operations by enabling a cache associated with performing a write operation. That is, the memory system 310 can enable or disable a write cache (e.g., a programming cache) to increase write execution performance, at the cost of longer pause latency. Here, the memory system 310 may operate according to the second operating mode based on or in response to enabling the cache.

[0086] At 345, the host system 305 may determine, based on or in response to an indication transmitted at 330, whether the write execution latency associated with (e.g., operating according to a second operating mode) the memory system 310 is less than the write execution latency associated with the memory system 310 identified at 325 (e.g., when the memory system 310 operates according to a first operating mode). In some cases, the host system 305 may determine, based on or in response to the memory system 310 operating according to a second operating mode associated with reduced latency for performing write operations, that the write execution latency associated with the memory system 310 has been reduced. In some cases, the host system 305 may identify the write execution latency associated with the memory system 310 based on or in response to receiving an indication of the write execution latency from the memory system 310 (e.g., after 340). In some other cases (e.g., where the memory system 310 does not transmit a write execution latency indication to the host system 305 at 320), the host system 305 may identify the write execution latency based on or in response to the performance of the memory system 310. For example, memory system 310 may indicate to host system 305 in response to the completion of a write command. Here, host system 305 may identify the write execution latency based on or in response to the amount of time between transmitting the write command to memory system 310 and receiving a completion indication of the write command from memory system 310. In another example, memory system 310 may indicate to host system 305 the capacity for receiving and executing write commands. Here, host system 305 may identify the write execution latency based on or in response to the indicated capacity for receiving and executing write commands by memory system 310.

[0087] At 350, an instruction to switch to the first operating mode may optionally be transmitted from the host system 305 to the memory system 310. For example, the host system 305 may (e.g., at 345) determine whether the write execution latency state of the memory system 310 has been reduced. Alternatively, the host system 305 may determine whether the workload of the memory system 310 is likely not associated with a large number of write operations (e.g., compared to read operations). For example, the host system 305 may determine that the memory system 310 can perform operations associated with video streaming (e.g., the video streaming is associated with a large number of read operations compared to the amount of write operations).

[0088] In either case, host system 305 may determine to prioritize read execution latency over write execution latency and may therefore transmit the instruction to memory system to operate according to a first operating mode (e.g., which does not restrict the pause of write operations). For example, host system 305 may transmit a command containing an instruction to switch to the first operating mode to memory system 310. In another instance, host system 305 may write a value containing an instruction to switch to the first operating mode to a register at memory system 310.

[0089] At 355, the memory system 310 may optionally be operated according to a first operating mode (e.g., if the memory system 310 receives an instruction from the host system 305 at 350 to switch to the first operating mode). When operating according to the first operating mode, the memory system 310 may select to suspend write and erase operations based on or in response to settings contained in the firmware of the memory system 310 (e.g., by entering a programming pause mode).

[0090] Figure 4 A block diagram 400 illustrates a memory system 420 that supports read latency and pause modes according to the examples disclosed herein. The memory system 420 may be a reference... Figures 1 to 3 Examples of various aspects of the described memory system. Memory system 420 or its various components may be examples of constructs for performing various aspects of the read latency and pause modes as described herein. For example, memory system 420 may include a first operating mode component 425, an indication receiver 430, a second operating mode component 435, a mode selection component 440, a switching identifier component 445, a latency indication transmitter 450, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0091] The first operating mode component 425 may be configured or otherwise supported for operating the memory system according to a first operating mode associated with a first set of access operations including performing a read operation, performing a write operation, and pausing a write operation. The instruction receiver 430 may be configured or otherwise supported for receiving an instruction from the host system to switch to a second operating mode, at least in part, based on operating the memory system according to the first operating mode, the second operating mode being associated with reduced latency for performing write operations, at least in part, based on limiting pausing write operations. The second operating mode component 435 may be configured or otherwise supported for operating the memory system according to the second operating mode, at least in part, based on receiving the instruction.

[0092] In some instances, mode selection component 440 may be configured or otherwise support components for selecting a second operating mode from a plurality of operating modes, each associated with reduced latency for performing write operations based at least in part on receiving an instruction to switch to a second operating mode, wherein the memory system operates according to the second operating mode based at least in part on the selection.

[0093] In some instances, the second operation mode component 435 may be configured or otherwise support a component for disabling a pause in a write operation at least in part based on a restriction pause write operation, wherein operating the memory system according to the second operation mode is at least in part based on the deactivation and includes performing read operations and performing write operations.

[0094] In some instances, the second operating mode component 435 may be configured or otherwise supported to identify a threshold amount for limiting write operation pauses based at least in part on receiving an indication to switch to the second operating mode, wherein the second operating mode is associated with a second set of access operations including performing read operations, performing write operations, and pausing some amount of write operations less than the threshold amount for write operation pauses.

[0095] In some instances, the second operating mode component 435 may be configured or otherwise supported to support a threshold amount for identifying the number of read operations performed during the write pause duration, the threshold amount of read operations being used to limit paused write operations at least in part based on receiving an indication to switch to the second operating mode, wherein the second operating mode is associated with a second set of access operations including performing read operations, performing write operations, and performing fewer read operations than the threshold amount of read operations during the paused write operations.

[0096] In some instances, the second operating mode component 435 may be configured or otherwise supported to limit the paused write operation by reducing the amount of triggering events associated with the paused write operation, at least in part, based on receiving an indication to switch to the second operating mode, wherein the second operating mode is associated with a second set of access operations including performing a read operation, performing a write operation, and pausing the write operation in response to the reduced amount of triggering events.

[0097] In some instances, to support receiving an indication to switch to a second operating mode, the switching identification component 445 may be configured or otherwise supported to identify that a register at the memory system is storing a value containing an indication to switch to the second operating mode.

[0098] In some instances, in order to support receiving an indication to switch to a second operating mode, the indication receiver 430 may be configured or otherwise supported to support components for receiving a command containing an indication to switch to a second operating mode.

[0099] In some instances, the second operating mode component 435 may be configured or otherwise supported to enable a cache associated with performing a write operation, at least in part based on receiving an instruction to switch to the second operating mode, wherein operating the memory system according to the second operating mode is at least in part based on enabling the cache.

[0100] In some instances, the latency indication transmitter 450 may be configured or otherwise supported for transmitting a second indication of write execution latency to a host system based at least in part on operating the memory system according to a first operating mode, wherein receiving an indication to switch to a second operating mode is based at least in part on transmitting the second indication of write execution latency.

[0101] In some instances, the first set of access operations includes a pause-erase operation. In some instances, the second operating mode is associated with reduced latency for performing erase operations based at least in part on limiting the pause-erase operation.

[0102] Figure 5 A block diagram 500 illustrates a host system 520 that supports read latency and pause modes according to the examples disclosed herein. The host system 520 can be as shown in the reference... Figures 1 to 3 Examples of various aspects of the described host system. Host system 520 or its various components may be examples of constructs for performing various aspects of read latency and pause modes as described herein. For example, host system 520 may include latency identification component 525, mode indication transmitter 530, operation mode selector 535, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0103] The latency identification component 525 may be configured or otherwise supported to identify a first write execution latency associated with a memory system operating according to a first operating mode, which is associated with a first set of access operations including performing a read operation, performing a write operation, and pausing a write operation. The mode indication transmitter 530 may be configured or otherwise supported to transmit an indication to the memory system, at least in part based on the identification, to switch to a second operating mode associated with reduced latency for performing a write operation, at least in part based on limiting the pausing write operation. In some instances, the latency identification component 525 may be configured or otherwise supported to determine, at least in part based on transmitting the indication, whether a second write execution latency associated with a memory system operating according to the second operating mode is less than a first write execution latency.

[0104] In some instances, to support the transmission of the indication to switch to the second operating mode, the mode indication transmitter 530 may be configured or otherwise supported to support means for writing a value containing the indication to switch to the second operating mode to a register at the memory system.

[0105] In some instances, in order to support the transmission of the indication to switch to the second operating mode, the mode indication transmitter 530 may be configured or otherwise support components for transmitting commands containing the indication to switch to the second operating mode.

[0106] In some instances, the latency identification component 525 may be configured or otherwise supported for a means of receiving a second indication of a first write execution latency from the memory system, wherein the identification of the first write execution latency is based at least in part on receiving the second indication.

[0107] In some instances, the operation mode selector 535 may be configured or otherwise supported to include means for determining whether a first write execution latency exceeds a threshold, wherein the indication for switching the transmission to a second operation mode is based at least in part on determining that the first write execution latency exceeds the threshold.

[0108] Figure 6 The flowchart illustrates a method 600 that supports read latency and pause modes according to the examples disclosed herein. The operation of method 600 can be implemented by the memory system or its components described herein. For example, the operation of method 600 can be implemented by a reference... Figures 1 to 4 The described memory system performs the function. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the memory system may use dedicated hardware to perform aspects of the described function.

[0109] At 605, the method may include operating the memory system according to a first operating mode associated with a first set of access operations including performing a read operation, performing a write operation, and pausing a write operation. The operation at 605 may be performed according to the examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 4 The first operating mode component 425 described performs various aspects of the operation of 605.

[0110] At 610, the method may include receiving, at least in part, an instruction from the host system to switch to a second operating mode based on operating the memory system according to a first operating mode, the second operating mode being associated with reduced latency for performing write operations at least in part based on limiting paused write operations. The operation of 610 may be performed according to the examples disclosed herein. In some instances, aspects of the operation of 610 may be as described in references... Figure 4 The described instructions are executed by receiver 430.

[0111] At 615, the method may include operating the memory system according to a second operating mode, at least in part based on receiving the instruction. The operation at 615 may be performed according to the examples disclosed herein. In some instances, it may be performed by reference... Figure 4 The second operating mode component 435 described performs various aspects of the operation of 615.

[0112] In some instances, the device described herein may perform one or more methods, such as method 600. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: operating a memory system according to a first operating mode associated with a first set of access operations including performing a read operation, performing a write operation, and pausing a write operation; receiving, at least in part, an instruction from a host system to switch to a second operating mode based on operating the memory system according to the first operating mode, the second operating mode being associated with reduced latency for performing write operations at least in part based on limiting pausing write operations; and operating the memory system according to the second operating mode at least in part based on receiving the instruction.

[0113] Some instances of the method 600 and device described herein may further include operations, features, circuit systems, logic, components, or instructions for: selecting a second operating mode from a plurality of operating modes, each associated with reduced latency for performing write operations at least in part based on receiving an indication to switch to a second operating mode, wherein the memory system is operated according to the second operating mode at least in part based on the selection.

[0114] Some instances of the method 600 and device described herein may further include operations, features, circuit systems, logic, components, or instructions for: disabling a pause in a write operation at least in part based on a restriction pause write operation, wherein operating the memory system according to a second operating mode may be at least in part based on the disabling and includes performing read operations and performing write operations.

[0115] Some instances of the method 600 and device described herein may further include operations, features, circuit systems, logic, components, or instructions for: identifying a threshold amount for limiting write operation pauses, at least in part based on receiving an indication to switch to a second operating mode, wherein the second operating mode may be associated with a second set of access operations that includes performing read operations, performing write operations, and pausing write operations by an amount less than the threshold amount of write operation pauses.

[0116] Some examples of the method 600 and device described herein may further include operations, features, circuitry, logic, components, or instructions for: identifying a threshold amount of read operations performed during a write pause duration, the threshold amount of read operations being used to limit paused write operations at least in part based on receiving an indication to switch to a second operating mode, wherein the second operating mode may be associated with a second set of access operations comprising performing read operations, performing write operations, and performing fewer read operations than the threshold amount of read operations during a paused write operation.

[0117] Some instances of the method 600 and device described herein may further include operations, features, circuitry, logic, components, or instructions for: at least in part based on receiving an indication to switch to a second operating mode to reduce the amount of triggering events associated with a paused write operation to limit the paused write operation, wherein the second operating mode may be associated with a second set of access operations including performing a read operation, performing a write operation, and pausing the write operation in response to the reduced amount of triggering events.

[0118] In some instances of the method 600 and apparatus described herein, receiving an indication to switch to a second operating mode may include identifying an operation, feature, circuit system, logic, component, or instruction in a register at a memory system that stores a value containing the indication to switch to the second operating mode.

[0119] In some instances of the method 600 and apparatus described herein, receiving an indication to switch to a second operating mode may include operations, features, circuitry, logic, components, or instructions for receiving a command containing the indication to switch to the second operating mode.

[0120] Some instances of the method 600 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: enabling a cache associated with performing a write operation, at least in part based on receiving an instruction to switch to a second operating mode, wherein operating the memory system according to the second operating mode may be at least in part based on enabling the cache.

[0121] Some examples of the method 600 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: transmitting a second indication of write execution latency to a host system, at least in part based on operating the memory system according to a first operating mode, wherein receiving an indication to switch to a second operating mode may be at least in part based on transmitting the second indication of write execution latency.

[0122] In some instances of the method 600 and device described herein, the first set of access operations includes a pause erase operation, and the second operating mode may be associated with reduced latency for performing erase operations based at least in part on limiting the pause erase operation.

[0123] Figure 7 The flowchart illustrates a method 700 that supports read latency and pause modes based on the examples disclosed herein. The operation of method 700 can be implemented by a host system or its components as described herein. For example, the operation of method 700 can be implemented by, as referenced... Figures 1 to 3 The host system described in section 5 performs the functions described herein. In some instances, the host system may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the host system may use dedicated hardware to perform aspects of the described functions.

[0124] At 705, the method may include identifying a first write execution delay associated with a memory system operating according to a first operating mode, the first operating mode being associated with a first set of access operations including performing a read operation, performing a write operation, and pausing a write operation. The operation at 705 may be performed according to the examples disclosed herein. In some instances, aspects of the operation at 705 may be referenced from... Figure 5 The described delay identification component 525 is executed.

[0125] At 710, the method may include transmitting an indication to the memory system, at least in part based on the identifier, to switch to a second operating mode, the second operating mode being associated with reduced latency for performing write operations at least in part based on limiting paused write operations. The operation at 710 may be performed according to the examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 5 The described pattern instructs the transmitter 530 to perform various aspects of the operation of 710.

[0126] At 715, the method may include determining, at least in part, whether a second write execution latency associated with a memory system operating according to a second operating mode is less than a first write execution latency, based on transmitting the instruction. The operation at 715 may be performed according to the examples disclosed herein. In some instances, aspects of the operation at 715 may be referenced... Figure 5 The described delay identification component 525 is executed.

[0127] In some instances, the device described herein may perform one or more methods, such as method 700. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: identifying a first write execution latency associated with a memory system operating according to a first operating mode, the first operating mode being associated with a first set of access operations including performing a read operation, performing a write operation, and pausing a write operation; transmitting an indication to the memory system, at least in part based on the identification, the second operating mode being associated with reduced latency for performing a write operation at least in part based on limiting the pausing write operation; and determining, at least in part based on transmitting the indication, whether a second write execution latency associated with the memory system operating according to the second operating mode is less than the first write execution latency.

[0128] In some instances of the method 700 and apparatus described herein, the instruction to switch to a second operating mode may include an operation, feature, circuitry, logic, component, or instruction for writing a value containing the instruction to switch to the second operating mode into a register in the memory system.

[0129] In some instances of the method 700 and apparatus described herein, the transmission of an indication to switch to a second operating mode may include operations, features, circuitry, logic, components, or instructions for transmitting a command containing the indication to switch to the second operating mode.

[0130] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for receiving a second indication of a first write execution delay from a memory system, wherein identifying the first write execution delay may be based at least in part on receiving the second indication.

[0131] Some examples of the method 700 and device described herein may further include operations, features, circuitry, logic, components, or instructions for determining whether a first write execution delay exceeds a threshold, wherein the indication for switching transmission to a second operating mode may be based at least in part on determining that the first write execution delay exceeds the threshold.

[0132] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions of two or more methods described may be combined.

[0133] Describe a device. The device may include a memory device and a controller, the controller being coupled to the memory device and configured to cause the device to: operate the device according to a first operating mode associated with a first set of access operations, the first set of access operations including performing a read operation, performing a write operation, and pausing a write operation; receive, at least in part, an instruction from a host system to switch to a second operating mode based on operating the device according to the first operating mode, the second operating mode being associated with reduced latency for performing a write operation at least in part based on limiting the paused write operation; and operate the device according to the second operating mode at least in part based on receiving the instruction.

[0134] In some cases, the controller may be further configured to cause the device to select a second operating mode from a plurality of operating modes, each associated with reduced latency for performing write operations based at least in part on a restriction of pausing write operations, based at least in part on receiving an instruction to switch to a second operating mode, wherein the device operates according to the second operating mode based at least in part on the selection.

[0135] In some cases, the controller may be further configured to disable the pause of write operations at least in part based on the restriction of paused write operations, wherein operating the device according to a second operating mode is at least in part based on the disable and includes performing read operations and performing write operations.

[0136] In some cases, the controller may be further configured to enable the device to: identify a threshold amount for limiting write operation pauses based at least in part on receiving an indication to switch to a second operating mode, wherein the second operating mode is associated with a second set of access operations including performing read operations, performing write operations, and pausing some amount of write operations less than the threshold amount for write operation pauses.

[0137] In some cases, the controller may be further configured to enable the device to: identify a threshold amount of read operations performed during the write pause duration, the threshold amount of read operations being used to limit paused write operations at least in part based on receiving an indication to switch to a second operating mode, wherein the second operating mode is associated with a second set of access operations including performing read operations, performing write operations, and performing fewer read operations than the threshold amount of read operations during the paused write operations.

[0138] In some cases, the controller may be further configured to cause the device to: at least in part, reduce the amount of triggering events associated with a paused write operation based on receiving an indication to switch to a second operating mode, thereby limiting the paused write operation, wherein the second operating mode is associated with a second set of access operations including performing a read operation, performing a write operation, and pausing the write operation in response to the reduced amount of triggering events.

[0139] In some cases, receiving an instruction to switch to a second operating mode may include identifying that a register at the device is storing a value that includes the instruction to switch to the second operating mode.

[0140] In some cases, receiving an instruction to switch to a second operating mode may include receiving a command that includes an instruction to switch to a second operating mode.

[0141] In some cases, the controller may be further configured to enable a cache associated with performing a write operation, at least in part, based on receiving the instruction to switch to a second operating mode, wherein operating the device according to the second operating mode is at least in part based on enabling the cache.

[0142] In some cases, the controller may be further configured to transmit a second indication of write execution latency to the host system, at least in part, based on operating the device according to a first operating mode, wherein receiving an indication to switch to a second operating mode is at least in part based on transmitting the second indication of write execution latency.

[0143] In some instances of the device, the first set of access operations includes a pause erase operation, and the second operating mode is associated with reduced latency for performing erase operations based at least in part on limiting the pause erase operation.

[0144] Describe an apparatus. The apparatus may include a controller configured to couple to a memory system, wherein the controller is configured to: identify a first write execution latency associated with the memory system operating according to a first operating mode, the first operating mode being associated with a first set of access operations including performing a read operation, performing a write operation, and pausing a write operation; transmit an indication to the memory system, at least in part based on the identification, the second operating mode being associated with reduced latency for performing a write operation at least in part based on limiting the pausing write operation; and determine, at least in part based on transmitting the indication, whether a second write execution latency associated with the memory system operating according to the second operating mode is less than the first write execution latency.

[0145] In some instances of the device, the instruction to switch to the second operating mode involves writing a value, including the instruction to switch to the second operating mode, into a register in the memory system.

[0146] In some instances of the device, the transmission of the instruction to switch to the second operating mode includes the transmission of a command that includes the instruction to switch to the second operating mode.

[0147] In some cases, the controller may be further configured to enable the device to receive a second indication of a first write execution delay from the memory system, wherein the first write execution delay is identified as being at least partially based on the receipt of the second indication.

[0148] In some cases, the controller may be further configured to enable the device to determine whether the first write execution latency exceeds a threshold, wherein the indication to switch the transmission to a second operating mode is based at least in part on determining that the first write execution latency exceeds the threshold.

[0149] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a bus of signals, which may have various bit widths.

[0150] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" refer to the relationship between components that enables the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that enables the flow of signals between them at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between components, or it can be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, may be used to interrupt the signal flow between connected components for a period of time.

[0151] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently be transmitted between components via a conductive path, while in a closed-circuit relationship, signals can be transmitted between components via a conductive path. If a component, such as a controller, couples other components together, that component initiates a change to allow signals to flow between the other components via conductive paths that were previously not permitted.

[0152] The term "isolation" refers to a relationship between components in which signals cannot currently flow between them. If an open circuit exists between components, the components are separated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. If a controller isolates two components, the controller implements a change to prevent signals from flowing between the components using previously permitted conductive paths.

[0153] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0154] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a preceding condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of a preceding condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0155] Additionally, the terms "directly in response to" or "directly in response to" can refer to a condition or action that occurs as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part based on," or "in response to" some other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) be performed "directly in response to" or "directly in response to" such other conditions or actions.

[0156] The devices, including memory arrays, discussed herein can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial material of a semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by using doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0157] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. Each terminal may be connected to other electronic components via a conductive material such as a metal. The source and drain may be conductive and may include heavily doped semiconductor regions, such as degenerate semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor is "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor is "off" or "deactivated."

[0158] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all implementable or claim-scoped instances. The term "exemplary" as used herein means "serving as an example, illustration, or diagram" and is not necessarily "preferred" or "superior to other instances." The detailed description includes specific details that provide an understanding of the described techniques. However, embodiments may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0159] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral for differentiation among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0160] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted over a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that portions of the functions are implemented in different physical locations.

[0161] For example, the various illustrative blocks and components described herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0162] As used herein, the "or" used in the claims (e.g., the list of items preceding, for example, "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be understood in the same manner as the phrase "at least partially based on".

[0163] Computer-readable media includes both non-transitory computer storage media and communication media, wherein the communication media includes any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Additionally, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0164] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: Memory devices; as well as A controller, coupled to the memory device and configured to cause the device to perform the following operations: The device operates according to a first operating mode associated with a first set of access operations, including performing a read operation, performing a write operation, and pausing a write operation; The instruction to switch to a second operating mode is received from the host system at least in part based on operating the device according to the first operating mode, the second operating mode being associated with reduced latency for performing write operations at least in part based on limiting the paused write operations; The registers at the device are identified as storing a threshold associated with limiting the paused write operation, at least in part based on the received instruction to switch to the second operating mode, the threshold being compared with the number of read operations performed during the write pause duration; as well as The device operates according to the second operating mode, at least in part based on the received instruction and the threshold.

2. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: The second operating mode is selected from a plurality of operating modes, each associated with the latency reduction for performing write operations based at least in part on limiting the paused write operation, based at least in part on receiving an instruction to switch to the second operating mode, wherein the device operates according to the second operating mode based at least in part on the selection.

3. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: The pause of the write operation is disabled at least in part based on the restriction of the paused write operation, wherein operating the device according to the second operating mode is at least in part based on the disablement and includes performing read operations and performing write operations.

4. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: The threshold amount for limiting the pause of the write operation is identified at least in part based on the received instruction to switch to the second operating mode, wherein the second operating mode is associated with a second set of access operations including performing a read operation, performing a write operation, and pausing a certain amount of write operations less than the threshold amount of the write operation pause.

5. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: The device is operated according to a first operating mode associated with a first set of access operations, the first set of access operations including performing a read operation, performing a write operation, and pausing a write operation; At least in part based on receiving an instruction from the host system to switch to a second operating mode associated with reduced latency for performing write operations at least in part based on limiting the paused write operation, while operating the device according to the first operating mode; A threshold amount of read operations performed during the write pause duration is used to limit the paused write operations at least in part based on receiving the indication to switch to the second operating mode, wherein the second operating mode is associated with a second set of access operations including performing read operations, performing write operations, and performing fewer read operations than the threshold amount of read operations during the paused write operation; as well as The device is operated according to the second operating mode, at least in part based on the received instruction and the threshold.

6. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: The paused write operation is limited by reducing the number of triggering events associated with it, at least in part, based on the instruction to switch to the second operating mode, wherein the second operating mode is associated with a second set of access operations including performing a read operation, performing a write operation, and pausing the write operation in response to the reduced number of triggering events.

7. The device of claim 1, wherein receiving the instruction to switch to the second operating mode further comprises the controller being configured to cause the device to perform the following operations: Receive a command including the instruction to switch to the second operating mode.

8. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: The cache associated with performing the write operation is enabled at least in part based on receiving the instruction to switch to the second operating mode, wherein operating the device according to the second operating mode is at least in part based on enabling the cache.

9. The device of claim 1, wherein the controller is further configured to cause the device to perform the following operations: The second indication of write execution latency is transmitted to the host system at least in part based on operating the device according to the first operating mode, wherein receiving the indication to switch to the second operating mode is at least in part based on transmitting the second indication of write execution latency.

10. The device according to claim 1, wherein: The first set of access operations includes pausing the erase operation; and The second operating mode is associated with reduced latency for performing the erase operation based at least in part on limiting the pause erase operation.

11. An apparatus comprising: A controller configured to couple with a memory system, wherein the controller is configured to cause the device to perform the following operations: A first write execution latency is identified as associated with the memory system operating according to a first operating mode, the first operating mode being associated with a first set of access operations including performing a read operation, performing a write operation, and pausing a write operation; An indication to switch to a second operating mode is transmitted to the memory system, at least in part based on the identifier, the second operating mode being associated with reduced latency for performing write operations at least in part based on limiting the paused write operations, wherein the transmission includes writing a threshold associated with limiting the paused write operations to a register at the memory system, the threshold being compared with the number of read operations performed during the write pause duration; as well as Whether the second write execution latency associated with the memory system operating according to the second operating mode is less than the first write execution latency is determined at least in part based on the transmission of the instruction.

12. The device of claim 11, wherein the instruction to switch the transmission to the second operating mode further comprises the controller being configured to cause the device to perform the following operations: The transmission includes a command indicating the switching to the second operating mode.

13. The device of claim 11, wherein the controller is further configured to cause the device to perform the following operations: A second indication of the first write execution delay is received from the memory system, wherein the first write execution delay is at least partially based on the receipt of the second indication.

14. The device of claim 11, wherein the controller is further configured to cause the device to perform the following operations: Determine whether the first write execution latency exceeds a second threshold, wherein the indication to switch the transmission to the second operating mode is based at least in part on determining that the first write execution latency exceeds the second threshold.

15. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to perform the following operations: The electronic device operates according to a first operating mode associated with a first set of access operations, including performing a read operation, performing a write operation, and pausing a write operation; The instruction to switch to a second operating mode is received from the host system at least in part based on operating the electronic device according to the first operating mode, the second operating mode being associated with reduced latency for performing write operations at least in part based on limiting the pause write operation; The register at the electronic device is identified as storing a threshold associated with limiting the paused write operation, at least in part based on the received instruction to switch to the second operating mode, the threshold being compared with the number of read operations performed during the write pause duration; as well as The electronic device is operated according to the second operating mode, at least in part based on the received instruction and the threshold.

16. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: The second operating mode is selected from a plurality of operating modes, each associated with the reduction of latency for performing a write operation based at least in part on limiting the pause write operation, based at least in part on the receipt of the instruction to switch to the second operating mode, wherein the operation of the electronic device according to the second operating mode is based at least in part on the selection.

17. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: The pause of the write operation is disabled at least in part based on the restriction of the paused write operation, wherein operating the electronic device according to the second operating mode is at least in part based on the disable and includes performing read operations and performing write operations.

18. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: The threshold amount for limiting the pause of the write operation is identified at least in part based on the received instruction to switch to the second operating mode, wherein the second operating mode is associated with a second set of access operations including performing a read operation, performing a write operation, and pausing a certain amount of write operations less than the threshold amount of the write operation pause.

19. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: The electronic device is operated according to a first operating mode associated with a first set of access operations, the first set of access operations including performing a read operation, performing a write operation, and pausing a write operation; At least in part, based on operating the electronic device according to the first operating mode, receiving from the host system an instruction to switch to a second operating mode associated with reduced latency for performing write operations at least in part based on limiting the paused write operation; A threshold amount of read operations performed during the write pause duration is used to limit the paused write operations at least in part based on receiving the indication to switch to the second operating mode, wherein the second operating mode is associated with a second set of access operations including performing read operations, performing write operations, and performing fewer read operations than the threshold amount of read operations during the paused write operation; as well as The electronic device is operated according to the second operating mode, at least in part based on the received instruction and the threshold.

20. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: The paused write operation is limited by reducing the number of triggering events associated with it, at least in part, based on the instruction to switch to the second operating mode, wherein the second operating mode is associated with a second set of access operations including performing a read operation, performing a write operation, and pausing the write operation in response to the reduced number of triggering events.

21. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to perform the following operations: A first write execution latency is identified as associated with a memory system operating according to a first operating mode, the first operating mode being associated with a first set of access operations including performing a read operation, performing a write operation, and pausing a write operation; An indication to switch to a second operating mode is transmitted to the memory system, at least in part based on the identifier, the second operating mode being associated with reduced latency for performing write operations at least in part based on limiting the paused write operations, wherein the transmission includes writing a threshold associated with limiting the paused write operations to a register at the memory system, the threshold being compared with the number of read operations performed during the write pause duration; as well as Whether the second write execution latency associated with the memory system operating according to the second operating mode is less than the first write execution latency is determined at least in part based on the transmission of the instruction.

22. The non-transitory computer-readable medium of claim 21, wherein the instruction transmitting the indication to switch to the second operating mode, when executed by the processor of the electronic device, further causes the electronic device to perform the following operations: The transmission includes a command indicating the switching to the second operating mode.

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