True erase of memory with pulse step size to facilitate erase pause

Abstract

The memory device includes a memory array of memory cells and control logic operatively coupled to the memory array. The control logic performs a memory erase operation comprising: performing a true erase sub-operation by causing a plurality of pulse steps to be sequentially applied to a group of memory cells in the memory array, wherein each of the plurality of pulse steps occurs during a pulse step period and at a higher voltage than the previous pulse step; pausing the true erase sub-operation at the beginning of a subsequent pulse step period after the pulse step in response to detecting an erase pause command during the pulse step; and restarting the true erase sub-operation at the end of the subsequent pulse step period.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to true memory erasure with pulse step sizes to facilitate erase pauses. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Attached Figure Description

[0003] This disclosure will be more fully understood from the detailed descriptions given below and from the accompanying drawings of some embodiments thereof.

[0004] Figure 1A This describes an instance computing system including a memory subsystem according to some embodiments.

[0005] Figure 1B This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to an embodiment.

[0006] Figure 2A-2C This is a reference based on the embodiments. Figure 1B A schematic diagram of a portion of the memory cell array in the described type of memory.

[0007] Figure 3 According to the embodiments, see reference Figure 1B A schematic block diagram of a portion of the memory cell array used in the type of memory described.

[0008] Figure 4A It is a voltage waveform description of an erase operation of a specified group of memory cells in a memory array (e.g., a block of memory cells) according to some embodiments.

[0009] Figure 4B This is a description of the voltage waveforms of the erased memory cell group during a true erase verification sub-operation, according to some embodiments.

[0010] Figure 4C This is a description of the voltage waveforms of the erased memory cell group during subsequent soft programming verification sub-operations, according to some embodiments.

[0011] Figure 4D This is a description of the voltage waveforms of the erased memory cell group during the final erase verification sub-operation, according to some embodiments.

[0012] Figure 5AThis is a voltage waveform description of a true eraser operation using a single pulse, according to an embodiment.

[0013] Figure 5B It is a voltage waveform description of a true eraser operation employing a series of increasingly larger pulse steps, according to at least one embodiment.

[0014] Figure 6A It is based on at least one embodiment and is currently Figure 5B The voltage waveform description of the pause command processed during one period of the pulse step is illustrated in the description.

[0015] Figure 6B This is a description of the voltage waveforms used to handle a failed true erase verification sub-operation when performing a true erase using a pulse step size, according to at least one embodiment.

[0016] Figure 7 It is a graph comparing the threshold voltage progress during an erase operation using a single pulse versus using an increasingly larger series of pulse steps, according to some embodiments.

[0017] Figure 8 This is a flowchart of an example method for performing a true erase using multiple pulse steps, according to some embodiments.

[0018] Figure 9 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0019] Embodiments of this disclosure pertain to true erase of memory with a pulse step size to facilitate erase pause. The memory device can be a non-volatile memory device. An example of a non-volatile memory device is a NAND memory device. The following description is in conjunction with… Figure 1A Other examples of non-volatile memory devices are described. In a particular memory device, such as a NAND (or flash) memory device, the memory cell is erased before it is programmed; this is often referred to as a program / erase cycle.

[0020] In these memory devices, each erase operation may comprise several sub-operations, such as pre-programming, true erase, true erase verification, soft programming, soft programming verification, and final erase verification, each of which will be discussed in more detail. For example, each of these sub-operations takes a relatively short time, such as 40-60 microseconds (µs), but the true erase sub-operation, except for the true erase sub-operation itself, can take up to 1 millisecond (ms) or longer. The true erase sub-operation involves applying an actual erase pulse to the memory cell being erased. Compared to other memory operations and other sub-operations of the erase operation, the true erase sub-operation takes a significantly longer time period (or duration). The duration of the true erase sub-operation is attributed to the considerably large bias voltage (Vera) of, for example, about 18-22 volts (V) applied to the erase pulse of the string of memory cells being erased. After the true erase sub-operation completes, the string of memory cells takes a considerable amount of time to ramp up to this bias voltage and a significant amount of time to recover, such as to discharge.

[0021] For example, in NAND memory devices, read operations are faster than erase operations and are typically given higher priority than erase operations. For this reason, erase operations are frequently interrupted when the host system (or coupled memory subsystem controller) sends a pause command to temporarily suspend the erase operation to support alternative read or other memory operations. The erase pause command can be of the "forward process" type, where the erase operation is not immediately paused to allow the current sub-operation to complete before the erase operation is actually paused. Enabling forward process is understood to be efficient and safe when enabling the memory structure of the memory device to naturally complete voltage ramping and / or recovery.

[0022] Correspondingly, if a pause command interrupts the erase operation during a true erase sub-operation, then higher-priority memory operations (such as read operations) must still wait for the true erase sub-operation to complete for a long period before a pause command can be executed and the memory operation can be completed. This significant delay, occurring whenever a pause command is received during a true erase sub-operation, significantly and adversely affects the Quality of Service (QoS) performance of the memory device. For example, the latency caused by repeatedly waiting for the true erase sub-operation to complete when interrupted by a pause command can significantly degrade memory performance.

[0023] This disclosure addresses the above and other drawbacks by dividing the erase pulse into multiple pulse steps, thus incorporating a natural disconnection in the memory cell string ramp-up to the erase voltage bias (Vera). If the erase pause command arrives during a true erase sub-operation, the erase operation can be paused immediately, for example, within a short time period of the pulse step length, not longer than the period of each pulse step. In some embodiments, the multiple pulse steps are at least three pulse steps, but additional pulse steps are envisioned. In one embodiment, the pulse step period is approximately the duration of the erase sub-operation excluding the true erase sub-operation. The erase operation can then be immediately restarted within another pulse step period, significantly reducing the overall latency, for example, approximately 20 times faster than the typical duration of a true erase sub-operation.

[0024] In one embodiment, the memory device includes a memory array of memory cells and control logic operatively coupled to the memory array. The control logic may be adapted to perform operations to execute an erase operation, as well as other memory operations. In at least some embodiments, the memory erase operation includes causing a plurality of pulse steps to be sequentially applied to a group of memory cells in the memory array during a true erase sub-operation. Each of the plurality of pulse steps may occur at a higher voltage during a pulse step period and compared to the previous pulse step. Each pulse step period may be a time length significantly shorter than the length of the entire true erase sub-operation. The operation may further include pausing the true erase sub-operation at the beginning of a subsequent pulse step period in response to detecting an erase pause command during the pulse step period and resuming the true erase sub-operation at the end of the subsequent pulse step period.

[0025] Therefore, the advantages of the systems and methods implemented according to some embodiments of this disclosure include, but are not limited to, significantly improved QoS related to memory performance by reducing latency attributable to erase pause commands received during the true erase sub-operations of an erase operation. Additionally, due to the more linear progression of the Vt distribution of the group of memory cells being erased when using pulse steps, the restarting of the erase operation can be performed more accurately compared to restarting the erase operation when using a single pulse step. Other advantages will be apparent to those skilled in the art of memory operations, including those associated with the erase operations discussed below.

[0026] Figure 1AThis description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or combinations of such media or memory devices. The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules.

[0027] Memory device 130 may be a non-volatile memory device. An example of a non-volatile memory device is a NAND memory device. A non-volatile memory device is a package of one or more dies. Each die may contain one or more planes. Planes may be grouped into logic units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane contains a set of physical blocks. Each block contains a set of pages. Each page contains a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits stored. Logic states may be represented by binary values ​​(e.g., “0” and “1” or combinations of such values).

[0028] Memory device 130 may consist of bits arranged in a two-dimensional or three-dimensional grid, also referred to as a memory array. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line may refer to one or more rows of memory cells in the memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of bit lines and word lines constitutes the address of the memory cell.

[0029] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital storage (SD) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0030] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., computer contained in a vehicle, industrial equipment or networked commercially available device), or such computing device that includes memory and processing power.

[0031] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1A This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intervening component), whether wired or wireless, and includes connections such as electrical, optical, and magnetic connections.

[0032] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache buffers, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses, for example, memory subsystem 110 to write data to and read data from memory subsystem 110.

[0033] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., PCIe bus), host system 120 can additionally utilize an NVM High Speed ​​(NVMe) interface, an Open NAND Flash Interface (ONFI) interface, or some other interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1AThe memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0034] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0035] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional cross-point ("3D cross-point") memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0036] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells (e.g., multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC)) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0037] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0038] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0039] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0040] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although in Figure 1A The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but instead may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0041] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0042] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0043] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory system controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0044] In some embodiments, the control logic of the local media controller 135 may implement an erase operation manager 138. The erase operation manager 138 may perform true erase sub-operations with pulse steps to facilitate erase pauses, as described in more detail below. In some embodiments, the erase operation manager 138 is wholly or partially integrated within the memory subsystem controller 115 and / or the host system 120.

[0045] Figure 1BThe first device in the form of a presentable memory device 130 and the presentable memory subsystem (e.g., according to the embodiment) are presentable memory devices 130. Figure 1A A simplified block diagram of communication between a second device and a memory subsystem controller 115 (of the memory subsystem 110). Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and the like. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0046] Memory device 130 includes an array 104 of memory cells logically arranged in rows and columns. Memory cells arranged in logical rows are typically connected to the same access line (e.g., a word line), while memory cells arranged in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1B (Not shown in the image) can be programmed to one of at least two target data states.

[0047] Row decoding circuitry 108 and column decoding circuitry 111 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 130 also includes input / output (I / O) control circuitry 112 for managing inputs of commands, addresses, and data to memory device 130, as well as outputs of data and status information from memory device 130. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 111 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and local media controller 135 to latch incoming commands.

[0048] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 104 in response to commands and generates status information for external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on memory cell array 104. In at least some embodiments, the local media controller 135 includes an erase operation manager 138. The local media controller 135 communicates with row decoding circuitry 108 and column decoding circuitry 111 to control row decoding circuitry 108 and column decoding circuitry 111 in response to addresses.

[0049] The local media controller 135 also communicates with cache register 118 and data register 121. Cache register 118 latches incoming or outgoing data, such as data initiated by the local media controller 135, to temporarily store data while the memory cell array 104 is busy writing or reading other data. During a programming operation (e.g., a write operation), data can be transferred from cache register 118 to data register 121 for transmission to the memory cell array 104; then, new data can be latched from I / O control circuitry 112 into cache register 118. During a read operation, data can be transferred from cache register 118 to I / O control circuitry 112 for output to memory subsystem controller 115; then, new data can be transferred from data register 121 to cache register 118. Cache register 118 and / or data register 121 may form a page buffer for the memory device 130 (e.g., at least a portion thereof). The page buffer may further include sensing devices (e.g., a sensing amplifier) ​​to sense the data status of the memory cells in the memory cell array 104, for example, by sensing the status of the data lines connected to the memory cells. The status register 122 may communicate with the I / O control circuitry system 112 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0050] Memory device 130 receives control signals from local media controller 135 at memory subsystem controller 115 via control link 132. For example, control signals may include chip enable signal CE#, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE#, read enable signal RE#, and write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may also be received via control link 132. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 134, and outputs data to memory subsystem controller 115 via I / O bus 134.

[0051] For example, a command can be received at I / O control circuit 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then written to command register 124. An address can be received at I / O control circuit 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then written to address register 114. Data can be received at I / O control circuit 112 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 118. The data can then be written to data register 121 for programming memory cell array 104.

[0052] In this embodiment, the cache register 118 may be omitted, and data may be written directly to the data register 121. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. Although references may be made to the I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connection to the memory device 130 via an external device (e.g., the memory subsystem controller 115).

[0053] Those skilled in the art should understand that additional circuitry and signals can be provided and have been simplified. Figure 1B The memory device 130. It should be understood that, reference Figure 1B The functionality of the various block components described need not be separated from different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1B The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1B The functionality of a single block component. Additionally, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0054] Figure 2A-2C It can be, for example, part of memory cell array 104 according to an embodiment in reference. Figure 1B A schematic diagram of a portion of a memory cell array 200A, such as a NAND memory array, used in the type of memory described. The memory array 200A includes, for example, word lines 2020 to 202. N Access lines and, for example, bit lines 2040 to 204 MThe data cable. Word line 202 can be connected in a many-to-one relationship to... Figure 2A Global access lines (e.g., global word lines) not shown. In some embodiments, the memory array 200A may be formed over a semiconductor, which may be conductively doped to have a conductivity type such as p-type conductivity to form a p-well, or have n-type conductivity to form an n-well, for example.

[0055] The memory array 200A can be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can contain a string of memory cells (e.g., non-volatile memory cells) connected in series, such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 216 and may contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for storing data. Memory cell 208 in each NAND string 206 may be connected in series with select gate 210 (e.g., a field-effect transistor) (e.g., select gates 2100 to 210). M One of them (e.g., it may be a source-select transistor, often referred to as a select-gate source) and select-gate 212 (e.g., a field-effect transistor) (e.g., select-gate 2120 to 212). M One of them (for example, it could be a drain-select transistor, often referred to as the select gate drain)). Select gate 2100 to 210 M They can be commonly connected to select line 214, such as source select line (SGS), and select gates 2120 to 212. M They can be commonly connected to select line 215, such as drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent several select gates connected in series, each selected gate configured in series to receive the same or independent control signals.

[0056] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to a memory cell 2080 in the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to a memory cell 2080 in the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to a select line 214.

[0057] The drain of each select gate 212 can be connected to bit line 204 for the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to bit line 2040 for the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0058] Figure 2A The memory array 200A can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and bit line 204 extend in a substantially parallel plane. Alternatively, Figure 2A The memory array 200A in the memory array may be a three-dimensional memory array, for example, in which the NAND string 206 may extend substantially perpendicular to the plane containing the common source 216 and substantially perpendicular to the plane containing the bit line 204, which may be substantially parallel to the plane containing the common source 216.

[0059] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, etc.) that determines the data state of the memory cell (e.g., by changing a threshold voltage), and a control gate 236, such as... Figure 2A As shown. The data storage structure 234 may include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may additionally have defined source / drain (e.g., source) 230 and defined source / drain (e.g., drain) 232. The memory cell 208 connects its control gate 236 to (and in some cases, forms) a word line 202.

[0060] A column of memory cells 208 may be a NAND string 206 or several NAND strings 206 selectively connected to a given word line 204. A row of memory cells 208 may be memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may (but not necessarily) contain all memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 typically contains every other memory cell 208 commonly connected to a given word line 202. For example, commonly connected to word line 202...N Furthermore, memory cells 208 selectively connected to even-numbered bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), while those commonly connected to word line 202 N Furthermore, the memory cell 208 selectively connected to the odd bit line 204 (e.g., bit line 2041, 2043, 2045, etc.) can be another physical page of the memory cell 208 (e.g., the odd memory cell).

[0061] Although Figure 2A Although bit lines 2043 and 2045 are not explicitly depicted in the figure, it is evident from the figure that bit line 204 of the memory cell array 200A can be connected from bit line 2040 to bit line 204. M Sequential numbering. Other groups of memory cells 208 commonly connected to a given word line 202 may also define physical pages of memory cells 208. For some memory devices, all memory cells commonly connected to a given word line may be considered physical pages of the memory cells. A portion of a physical page of a memory cell (in some embodiments, it may still be an entire row) that is read during a single read operation or programmed during a single programmable operation (e.g., the upper or lower page of the memory cell) may be considered a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to word lines 2020-202. N All memory cells (e.g., all NAND strings 206 sharing a common word line 202). Unless explicitly distinguished, a reference to a page of a memory cell herein refers to the memory cell of the logical page of the memory cell. This is in conjunction with the discussion of NAND flash memory. Figure 2A Examples are provided, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS, phase-change, ferroelectric, etc.) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0062] Figure 2B It can be, for example, part of memory cell array 104 in reference Figure 1B Another schematic diagram of a portion of the memory cell array 200B used in the type of memory described. Figure 2B Elements with the same number in the text correspond to, for example, elements related to, the same number in the text. Figure 2A The description provided. Figure 2BFurther details are provided for an example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B may incorporate a vertical structure that may contain semiconductor pillars, a portion of which may serve as channel regions for the memory cells of the NAND strings 206. Each of the NAND strings 206 may be selectively connected to bit lines 2040-204 via a select gate 212 (e.g., a drain select transistor, commonly referred to as a select gate drain). M And the gate 210 (e.g., a source-select transistor, often referred to as a select-gate-source) is selectively connected to a common source 216. Multiple NAND strings 206 can be selectively connected to the same bit line 204. A subset of NAND strings 206 can be connected via select lines 2150-215. K A bias voltage is applied to connect to its corresponding bit line 204 to selectively activate a specific select gate 212 between the NAND string 206 and the bit line 204. A select gate 210 can be activated by applying a bias voltage to select line 214. Each word line 202 can be connected to multiple rows of memory cells in the memory array 200B. Rows of memory cells that are collectively connected to each other via specific word lines 202 can be collectively referred to as a layer.

[0063] Figure 2C It can be, for example, part of memory cell array 104 in reference Figure 1B Another schematic diagram of a portion of the memory cell array 200C used in the type of memory described. Figure 2C Elements with the same number in the text correspond to, for example, elements related to, the same number in the text. Figure 2A The provided description. The memory cell array 200C may contain, for example: Figure 2A The memory cell array 200A depicts a series-connected string of memory cells (e.g., a NAND string) 206, an access (e.g., a word) line 202, a data (e.g., a bit) line 204, a select line 214 (e.g., a source select line), a select line 215 (e.g., a drain select line), and a source 216. For example, a portion of the memory cell array 200A may be a portion of the memory cell array 200C.

[0064] Figure 2C The diagram depicts the NAND string 206 being grouped into memory cell blocks 250, such as memory cell blocks 2500 to 250. L Memory cell block 250 may be a grouping of memory cells 208 that can be erased together in a single erase operation, sometimes referred to as an erase block. Each memory cell block 250 may represent those NAND strings 206 that are associated with, for example, a single select line 215 of select line 2150. The source 216 of memory cell block 250 may be associated with memory cell block 250. LThe source 216 is the same as the source. For example, each memory cell block 2500-250 L They can be selectively connected together to source 216. Access lines 202 and select lines 214 and 215 of a memory cell block 250 are respectively connected to memory cell blocks 2500-250. L Access lines 202 and select lines 214 and 215 of any other memory cell block may not have a direct connection.

[0065] Bit line 2040-204 M It can be connected (e.g., selectively connected) to a buffer portion 240 that may be part of a page buffer of memory device 130. Buffer portion 240 may correspond to a memory plane (e.g., memory cell block 2500-250). L (The set). Buffer section 240 may include sensing circuitry (which may include a sensing amplifier) ​​for sensing the data value indicated on the corresponding bit line 204.

[0066] Figure 3 For reference only Figure 1B A block diagram of a portion of a memory cell array 300 in a memory of the described type. The memory cell array 300 is depicted having four memory planes 350 (e.g., memory planes 3500-3503), each communicating with a corresponding buffer portion 240, which together form a page buffer 352. Although four memory planes 350 are depicted, other numbers of memory planes 350 may communicate together with the page buffer 352. Each memory plane 350 is depicted containing L+1 memory cell blocks 250 (e.g., memory cell blocks 2500-250...). L ).

[0067] Figure 4A This is a voltage waveform description of an erase operation on a specified group of memory cells (e.g., a block of memory cells) of a memory array according to some embodiments. During an optional pre-programming sub-operation 403, the memory device 130 may apply a soft-programming voltage to the word lines of the specified group of memory cells to pre-adjust the memory array and thus avoid over-erasing. In some embodiments, the group of memory cells targeted by the erase operation is organized as a physical block of memory cells. In other embodiments, the group of memory cells targeted by the erase operation comprises one or more strings of memory cells.

[0068] During the true erase sub-operation 405, the local media controller 135 (e.g., erase operation manager 138) can select gates 2100 to 210. M When the (SGS transistor) is turned on, it causes the common source voltage line, such as SRC 216 ( Figure 2AThe pulse step size is used to ramp up to the erase voltage (Vera). As discussed, ramping up to this high-bias erase voltage and then recovering from this voltage ramp takes a considerable amount of time. Meanwhile, the erase operation manager 138 can cause the selection gates 2120 to 212 to be selected. M ( Figure 2A Turn off to select gates 2120 to 212 M The drain can float, which causes the bit line to move from 2040 to 204. M It also floats. Additionally, the erase operation manager 138 can erase word lines 202 ( Figure 2A Coupled to ground, for example, zero volts. This voltage level set at memory array 200A can cause the erasure of memory cells 2080 to 208... N The erase potential, for example, forces electrons through the body of each memory cell to leave the floating bit line 2040 to 204. M .

[0069] In memory cells 2080 to 208 N After erasure, the erase operation manager 138 can perform a series of erase / program verification sub-operations to ensure that memory cells 2080 to 208 of the memory cell group are cleared. N Having a range around a specific threshold voltage (e.g., below and / or approximately a small negative voltage (-V)) L The voltage distributions (e.g., -1.5 V, -1.25 V, -1.0 V, etc.) can be used to define different verification sub-operations, which may include a true erase verification sub-operation 407, a soft programming verification sub-operation 409, and a final erase verification sub-operation 411, respectively. (Refer to the relevant documentation for details.) Figure 4B-4D To elaborate.

[0070] Figure 4B This is a description of the voltage waveforms of the erased memory cell group during a true erase verification sub-operation 407, according to some embodiments. During the true erase verification sub-operation 407, the erase operation manager 138 may determine whether the threshold voltage (Vt) distribution of the erased memory cells is below -V. L If the Vt distribution contains elements that satisfy or exceed -V L If a certain part is not cleared, then the true erase verification sub-operation 407 can be considered as failing.

[0071] Figure 4C This is a description of the voltage waveforms of the erased memory cell group during a subsequent soft programming verification sub-operation 409, according to some embodiments. The soft programming verification sub-operation 409 is applied between soft programming operations, including causing a series of low-voltage programming pulses to be applied to bring the erase state of the Vt distribution closer to -V. LHowever, it is still below 0 V. A software verification sub-operation 409 can be performed after each software programming operation to verify that the erase state of the Vt distribution is closer to -V. L However, it remains below 0 V. It can be locked during the next soft programming verification sub-operation, for example, to suppress erased memory cell groups that would be programmed to be above -V during soft programming. L Any unit.

[0072] Figure 4D This is a description of the voltage waveform of the erased memory cell group during the final erase verification sub-operation 411, according to some embodiments. During the final erase verification sub-operation 411, the memory operation manager 138 can ensure that the Vt distribution of the erased memory cell group remains below or even smaller than a negative voltage (-V). L / 2 For example, it can be understood as approximately -V L Half of Vt distribution. If any part of the Vt distribution satisfies or exceeds -V L / 2 Therefore, the final erase verification sub-operation 411 can be considered as failing.

[0073] Figure 5A This is a voltage waveform description of a true eraser operation using a single pulse according to an embodiment. As discussed, in a particular memory device, a true eraser operation is performed by a single pulse to ramp up the common source voltage (Vsrc) to the erase voltage (Vera). Doing so can cause significant delays in both the ramp-up to reach Vera and in the recovery during the discharge of this higher erase voltage. This is in contrast to multiple pulse steps ( Figure 5B The purpose is to explain the time period (or duration) of the signal pulse.

[0074] Figure 5B This is a voltage waveform description of a true erase sub-operation employing a series of increasingly larger pulse steps, according to at least one embodiment. In this way, the erase voltage of Vsrc can increase incrementally toward Vera but can be stopped between pulse steps, for example to allow the handling of a pause command. The three pulse steps illustrated are exemplary and may contain more or fewer pulse steps depending on the length of each pulse step period 501 and the total length of the true erase sub-operation. Each pulse step period 501 may be of the same time length (or duration), for example, for predictability when handling an erase restart command, as will be discussed. Additionally, in some embodiments, in each sequential pulse step (e.g., the 1st, 2nd, 3rd, and so on), each pulse step progressively increases (increases) the same amount of voltage.

[0075] Figure 6A It is based on at least one embodiment and is currently Figure 5BThe voltage waveform description of the pause command processed during one of the pulse steps is illustrated. As illustrated, an erase pause command 620 is received during one of the pulse steps (in this case, the second pulse step). In response to the detection of the erase pause command during the pulse step, the erase operation manager 138 may cause the true erase sub-operation to be paused at the start of the next pulse step cycle 625 after said pulse step. The pause of the true erase sub-operation can be understood as a temporary suspension of the operation process, and therefore, as illustrated, the pulse step during the next pulse step cycle 625 is skipped. Waiting until the start of the next pulse step cycle 625 to formally "suspend" the operation can be attributed to the forward progress of the erase operation. In various embodiments, the memory device 130 may guide the execution of memory operations (e.g., read or write operations) that will be performed during the next pulse step cycle 625.

[0076] In at least one embodiment, the erase operation manager 138 restarts the true erase sub-operation at the end of the next pulse step period 625. In at least another embodiment, the erase operation manager 138 detects an erase restart command 630 before the end of the next pulse step period 625. In response to this detection, the erase operation manager 138 may restart the true erase sub-operation at the end of the next pulse step period 625.

[0077] Figure 6B This is a description of voltage waveforms handling a failed true erase verification sub-operation during a true erase operation performed using a pulse step size, according to at least one embodiment. In some embodiments, in response to not receiving an erase pause command during a true erase sub-operation, the erase operation manager 138 may cause a true erase verification sub-operation 407A to be performed on a group of memory cells. Additionally, upon receiving an erase restart command and completing the true erase sub-operation 407A (e.g., ...), ... Figure 6A Following the description in the document, the erase operation manager 138 can cause a true erase verification sub-operation to be performed on the memory cell group.

[0078] If the true erase verification sub-operation 407A fails, the erase operation manager 138 may restart the true erase sub-operation of the erase operation. As explained, restarting the true erase sub-operation means causing a higher voltage pulse step (and the same pulse step period) to be applied to the memory cell group. For example, in one embodiment, the subsequent pulse step after the restart of the true erase sub-operation (such as the fourth pulse step described) is a higher voltage than the pulse step applied immediately before the true erase verification sub-operation 407A (such as the third pulse step described). The series of pulse steps sent to the memory cell group (e.g., the fifth, sixth, ...) also have progressively higher voltages. Therefore, at the end of another true erase time period, the erase operation manager 138 may cause the execution of a second true erase verification sub-operation 407B. As explained, this second true erase verification sub-operation 407B passes, and thus the process moves to the execution of the soft programming verification sub-operation.

[0079] Figure 7 This is a graph comparing the threshold voltage progress during an erase operation using a single pulse (bottom curve) compared to using an increasingly larger series of pulse steps (top curve), according to some embodiments. As illustrated with reference to the single-pulse curve, due to the rapid change in the Vt distribution, especially in the early portion 702 of the single-pulse curve, it is difficult to accurately pause the erase operation. Furthermore, it is difficult to accurately restart the erase operation because, as explained in the later portion 704 of the single-pulse curve, even a slight decrease in the erase voltage after restarting may still hinder the erase process.

[0080] In contrast, using multiple increasingly larger voltage pulse steps (top curve) results in a more linear progression of the Vt distribution. This linear progression of the Vt distribution enables accurate prediction of the Vt-distributed erasure process over time. Therefore, by employing the disclosed technique of using increasingly larger voltage pulse steps instead of a single long pulse step, it is also easier to pause the erasure operation and return to accurately restarting it.

[0081] Figure 8 This is a flowchart of an example method 800 for performing a true erase using multiple pulse steps according to some embodiments. Method 800 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 800 is performed by… Figure 1A-1BThe local media controller 135, which includes the erase operation manager 138, executes the process. Although shown in a specific order or sequence, the order of the processes can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0082] At operation 810, a true erase sub-operation is performed. More specifically, the processing logic performs the true erase sub-operation by causing a plurality of pulse steps to be sequentially applied to a group of memory cells in the memory array. In some embodiments, each of the plurality of pulse steps occurs during the pulse step period and at a higher voltage than the previous pulse step, such as... Figure 5B As explained in the text.

[0083] At operation 815, an erase pause command was detected. More specifically, the processing logic determines whether an erase pause command has been received.

[0084] If an erase command is received at operation 815, then at operation 820, the processing logic pauses the true erase sub-operation at the beginning of the next pulse step period after the pulse step length. Figure 6A As explained in the text.

[0085] At operation 830, memory operations are optionally processed. More specifically, the processing logic causes memory operations (e.g., read or write operations) to be performed during a pause cycle (e.g., the next pulse step cycle).

[0086] At operation 840, restart the true erase sub-operation. Figure 6A More specifically, the processing logic restarts the true erase sub-operation at the end of the next pulse step period. In some embodiments, restarting the true erase sub-operation at the end of the next pulse step period is in response to receiving an erase restart command before the end of the next pulse step period, such as... Figure 6A As explained in the text.

[0087] If no erase pause command is received at operation 815 (or no additional erase pause command is received after restarting the true erase sub-operation at operation 840), then method 800 continues to operation 850.

[0088] At operation 850, the True Erase Verification (TEV) sub-operation is executed. More specifically, the processing logic causes the execution of the True Erase Verification (TEV) sub-operation, see reference [link to relevant documentation]. Figure 4B To elaborate.

[0089] At operation 860, the verification is determined as passed / failed. More specifically, the processing logic determines whether the true erase verification sub-operation passed or failed; see reference [link to relevant documentation]. Figure 4B To elaborate.

[0090] If the true erase validation sub-operation passes at operation 860, then the erase operation ends. In response to a failure caused by the true erase validation sub-operation at operation 860, the processing logic restarts the true erase sub-operation of the erase operation at operation 870, as follows: Figure 6B As described in the document. In at least some embodiments, the subsequent pulse step size after restarting the true erase sub-operation is a higher voltage compared to the pulse step size immediately preceding the execution of the true erase verification sub-operation.

[0091] Figure 9 An example machine is described as a computer system 900, within which a set of instructions is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, the computer system 900 may correspond to a host system (e.g., Figure 1A The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1A The memory subsystem 110), or may be used to perform controller operations (e.g., to execute an operating system to perform operations corresponding to...). Figure 1A (Operation of the memory subsystem controller 115). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer (or distributed) network machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0092] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should also be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0093] The example computer system 900 includes a processing device 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 910 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 918, which communicate with each other via a bus 930.

[0094] Processing device 902 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 902 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 902 is configured to execute instructions 928 for performing the operations and steps discussed herein. Computer system 900 may additionally include a network interface device 912 for communication on network 920.

[0095] The data storage system 918 may include a machine-readable storage medium 924 (also referred to as a non-transitory computer-readable medium) storing one or more sets of instructions 928 or software embodying any or more of the methods or functions described herein. The data storage system 918 may additionally include a local media controller 135, which includes the erase operation manager 138 discussed earlier. The instructions 928 may also reside wholly or at least partially in main memory 904 and / or processing device 902 during execution by computer system 900, which also constitute machine-readable storage media. The machine-readable storage medium 924, the data storage system 918, and / or main memory 904 may correspond to... Figure 1A The memory subsystem 110.

[0096] In one embodiment, instruction 926 includes instructions for implementing a controller (e.g., Figure 1AThe memory subsystem controller 115) provides functional instructions. Although the machine-readable storage medium 924 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods disclosed herein. The term "machine-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0097] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0098] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0099] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0100] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0101] This disclosure may be provided as a computer program product or software, which may include machine-readable media having instructions stored thereon for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., non-transitory computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0102] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory device comprising: A memory array, comprising memory cells; and Control logic operatively coupled to the memory array performs a memory erase operation including the following operations: A true erase sub-operation is performed by causing a plurality of pulse steps to be sequentially applied to a group of memory cells in the memory array, wherein each of the plurality of pulse steps occurs during a pulse step period and at a higher voltage than the previous pulse step. In response to detecting an erase pause command during the pulse step period of one of the plurality of pulse steps, the true erase sub-operation is paused at the beginning of the next pulse step period after the pulse step period of the one pulse step. and The true erase sub-operation restarts at the end of the next pulse step period.

2. The memory device of claim 1, wherein the group of memory cells is a block of memory cells.

3. The memory device of claim 1, wherein the plurality of pulse steps includes at least three pulse steps.

4. The memory device of claim 1, wherein the memory erase operation further includes causing a read operation to be performed during the subsequent pulse step period.

5. The memory device of claim 1, wherein the memory erase operation further includes the true erase sub-operation that restarts the erase operation in response to a true erase verification sub-operation causing a failure.

6. The memory device of claim 5, wherein the subsequent pulse step after restarting the true erase sub-operation includes a higher voltage than the pulse step immediately preceding the execution of the true erase verification sub-operation.

7. The memory device of claim 1, wherein restarting the true erase sub-operation at the end of the subsequent pulse step period is in response to receiving an erase restart command before the end of the subsequent pulse step period.

8. A method comprising: A true erase sub-operation is performed by the control logic of the memory device by causing a plurality of pulse steps to be sequentially applied to a group of memory cells in the memory array, wherein each of the plurality of pulse steps occurs at a higher voltage during a pulse step period and compared to the previous pulse step. In response to detecting an erase pause command during the pulse step period of one of the plurality of pulse steps, the control logic pauses the true erase sub-operation at the start of the next pulse step period after the pulse step period of the one pulse step. and The control logic restarts the true erase sub-operation at the end of the next pulse step period.

9. The method of claim 8, wherein the group of memory cells is a block of memory cells.

10. The method of claim 8, wherein the plurality of pulse steps comprises at least three pulse steps.

11. The method of claim 8, further comprising causing a read operation to be performed during the subsequent pulse step period.

12. The method of claim 8, further comprising the true erase sub-operation that restarts the erase operation in response to a failure caused by the true erase verification sub-operation.

13. The method of claim 12, wherein the subsequent pulse step after restarting the true erase sub-operation includes a higher voltage compared to the pulse step immediately preceding the execution of the true erase verification sub-operation.

14. The method of claim 8, wherein restarting the true erase sub-operation at the end of the subsequent pulse step period is in response to receiving an erase restart command before the end of the subsequent pulse step period.

15. A non-transitory computer-readable medium storing instructions, said instructions, when executed by control logic coupled to a memory array operably with a memory device, the control logic performing a plurality of memory erase operations including: A true erase sub-operation is performed by causing a plurality of pulse steps to be sequentially applied to a group of memory cells in the memory array, wherein each of the plurality of pulse steps occurs during a pulse step period and at a higher voltage than the previous pulse step. If no erase pause command is received during the true erase sub-operation, a true erase verification sub-operation is executed. and In response to the detection of an erase pause command during the pulse step period of one of the plurality of pulse steps, the true erase sub-operation is paused at the beginning of the next pulse step period after the pulse step period of the one pulse step.

16. The non-transitory computer-readable medium of claim 15, wherein the plurality of memory erase operations further includes restarting the true erase sub-operation at the end of the subsequent pulse step period.

17. The non-transitory computer-readable medium of claim 15, wherein the plurality of memory erase operations further includes restarting the true erase sub-operation at the end of the subsequent pulse step period in response to receiving an erase restart command before the end of the subsequent pulse step period.

18. The non-transitory computer-readable medium of claim 15, wherein the plurality of memory erase operations further include causing a read operation to be performed during the subsequent pulse step period.

19. The non-transitory computer-readable medium of claim 15, wherein the plurality of memory erasure operations further comprise: Perform the true erase sub-operation; and In response to the failure of the true erase verification sub-operation, the true erase sub-operation is restarted.

20. The non-transitory computer-readable medium of claim 19, wherein the subsequent pulse step after restarting the true erase sub-operation includes a higher voltage than the pulse step immediately preceding the execution of the true erase verification sub-operation.

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