Dynamic read level thresholding in memory systems

Abstract

This disclosure relates to dynamic read level thresholds in a memory subsystem. It identifies the current operational characteristic value of a cell in the memory device. Operational characteristic thresholds are identified from a set of operational characteristic thresholds, wherein the current operational characteristic value satisfies an operational characteristic threshold criterion based on the operational characteristic thresholds. A set of W2R delay time thresholds corresponding to the operational characteristic thresholds is identified from a plurality of write-to-read W2R delay time threshold sets. Each of the W2R delay time thresholds in the set is associated with a corresponding read voltage level. A W2R delay time threshold associated with a W2R delay time threshold criterion is identified from the set of W2R delay time thresholds, wherein the current W2R delay time of the memory subsystem satisfies the W2R threshold criterion. The read voltage level associated with the identified W2R delay time threshold is identified.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically, to dynamic read level thresholds in memory subsystems. Background Technology

[0002] A memory subsystem can be a memory system, a memory module, or a combination of memory devices and memory modules. A memory subsystem can contain one or more memory devices for storing data. Memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] Embodiments of this disclosure provide a system comprising: a memory device; and a processing means operatively coupled to the memory device to perform operations including: determining a first current operating characteristic value of a cell of the memory device; identifying a first operating characteristic threshold from a first set of operating characteristic thresholds, wherein the first current operating characteristic value satisfies a first operating characteristic threshold criterion based on the first operating characteristic threshold; identifying a set of W2R latency thresholds corresponding to the first operating characteristic threshold from a plurality of write-to-read (W2R) latency thresholds, wherein each of the W2R latency thresholds in the set is associated with a corresponding read voltage level; identifying a W2R latency threshold from the set of W2R latency thresholds, for which the current W2R latency of the cell of the memory device satisfies an associated W2R latency threshold criterion; and identifying a read voltage level associated with the identified W2R latency threshold.

[0004] Another embodiment of this disclosure provides a non-transitory computer-readable medium including instructions that, when executed by a processing device, cause the processing device to perform operations including: identifying a current cycle count associated with a cell of a memory device; identifying a cycle count range containing the current cycle count from a set of cycle count ranges; identifying a set of W2R delay time ranges corresponding to the cycle count range from a set of multiple write-to-read (W2R) delay time ranges, wherein each of the W2R delay time ranges represents a plurality of W2R delay times and is associated with a corresponding read voltage level for performing a read operation on a cell of the memory device having a W2R delay time within the W2R delay time range; identifying the W2R delay time of the cell of the memory device, wherein the identified W2R delay time is based on the time difference between a write operation and a read operation performed by the cell of the memory device; identifying a W2R delay time range containing the W2R delay time of the cell of the memory device from the set of delay time ranges; identifying the read voltage level corresponding to the identified W2R delay time range; and performing a read operation at the cell of the memory device based on the identified read voltage level.

[0005] Another embodiment of this disclosure provides a method comprising: determining a first current operating characteristic value of a cell of a memory device; identifying a first operating characteristic threshold from a first set of operating characteristic thresholds, wherein the first current operating characteristic value satisfies a first operating characteristic threshold criterion based on the first operating characteristic threshold; identifying a set of W2R delay time thresholds corresponding to the first operating characteristic threshold from a plurality of write-to-read (W2R) delay time threshold sets, wherein each of the W2R delay time thresholds in the set is associated with a corresponding read voltage level; identifying a W2R delay time threshold from the set of W2R delay time thresholds, for which the current W2R delay time of the cell of the memory device satisfies an associated W2R delay time threshold criterion; and identifying a read voltage level associated with the identified W2R delay time threshold. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0007] Figure 1 An example computing system including a memory subsystem is shown according to some embodiments of the present disclosure.

[0008] Figure 2A-2C Examples of voltage shifting according to some embodiments are shown.

[0009] Figure 3A An example latency threshold determiner is shown, which adjusts the write-to-read latency threshold according to some embodiments.

[0010] Figure 3B An example read level determiner is shown, according to some embodiments, using an adjustable write-to-read latency time threshold.

[0011] Figure 4A This is a flowchart of an example method for adjusting the delay time threshold and determining the corresponding read level according to some embodiments.

[0012] Figure 4B This is a flowchart of an example method for adjusting the delay time range and performing a read operation using the corresponding read level, according to some embodiments.

[0013] Figures 5A-5C A table is shown that, according to some embodiments, contains example writes to a set of read latency times corresponding to example operating characteristic values ​​of the memory subsystem.

[0014] Figures 6A-6C The table shown represents, according to some embodiments, a set of example writes to a read latency time offset corresponding to example operating characteristic values ​​of the memory subsystem.

[0015] Figure 7 This is a block diagram of an example computer system in which embodiments of this disclosure may operate. Detailed Implementation

[0016] This disclosure relates to adjusting the read voltage of a memory in a memory subsystem based on changes in operational characteristics using an adjustable write-to-read latency threshold. The memory subsystem may be a storage device, a memory module, or a combination of both. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem, which includes one or more components, such as memory devices for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0017] The memory subsystem can contain high-density non-volatile memory devices where data retention is required when no power is supplied to the memory device. One example of a non-volatile memory device is a three-dimensional cross-point (“3D cross-point”) memory device containing an array of non-volatile memory cells. 3D cross-point memory devices can combine stackable cross-grid data access arrays for bit storage based on changes in volume resistance. Another example is a NAND flash memory device. The following section will discuss this further. Figure 1Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits stored. The logic states may be represented by binary values ​​(e.g., “0” and “1”) or combinations of these values.

[0018] Memory devices can consist of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line can refer to one or more rows of memory cells in a memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of bit lines and word lines constitutes the address of a memory cell. Hereinafter, a block refers to a cell of a memory device used to store data and can contain groups of memory cells, groups of word lines, word lines, or individual memory cells. One or more blocks can be grouped together to form a plane of a memory device to allow concurrent operation on each plane. A memory device can be referred to as a "drive" having multiple dies layered in multiple "stacks".

[0019] A read operation can be performed using a signal with a read voltage level (e.g., a word line applied to a memory array). The read threshold voltage level or value (referred to herein as "read voltage level") can be a specific voltage applied to a memory cell of the memory device to read data stored at that memory cell. For example, if the threshold voltage of a particular memory cell is identified as being lower than the read voltage level applied to that memory cell, the data stored at that memory cell can be a specific value (e.g., '1'), and if the threshold voltage of a particular memory cell is identified as being higher than the read voltage level, the data stored at that memory cell can be another value (e.g., '0'). Therefore, a read voltage level can be applied to the memory cell to determine the value stored at the memory cell.

[0020] In a conventional memory subsystem, when the threshold voltage programming distribution of a memory cell changes, the applied read voltage level may be inaccurate relative to the changed threshold voltage. For example, a memory cell may be programmed to have a threshold voltage lower than the read voltage level. The programmed threshold voltage can change over time and may transition to a level higher than the read voltage level. For instance, the threshold voltage of a memory cell may change from initially being lower than the read voltage level to being higher than the read voltage level. Therefore, when a read voltage level is applied to the memory cell, the data stored at the memory cell may be misread or misinterpreted as an incorrect value compared to the initially stored value before the threshold voltage transition.

[0021] For certain memory types (i.e., memory subsystems employing certain types of storage media), the error rate can change over time. Specifically, some non-volatile memories have a threshold voltage programming distribution that shifts or "drifts" higher over time. At a given read voltage level (i.e., the value of the voltage applied to a memory cell as part of a read operation), if the threshold voltage programming distribution shifts, certain reliability statistics may also be affected. One example of a reliability statistic is the bit error rate (BER). BER can be defined as the ratio of the number of faulty bits to the total number of data bits stored in a cell within a memory subsystem, where a cell can be the entire memory subsystem, the die of a memory device, a collection of codewords, or any other meaningful part of the memory subsystem.

[0022] The drift rate or velocity of the threshold voltage programming distribution, and the corresponding BER of a conventional memory subsystem, are influenced by one or more operating characteristics of the memory subsystem. Example operating characteristics include wear conditions (e.g., write count), die temperature, and write-to-read (W2R) latency (i.e., the time elapsed between writing to a memory cell (e.g., a memory page) and reading that memory cell). For example, when experiencing the same W2R latency, the drift rate is faster at a higher die temperature than at a lower temperature. In another example, a longer W2R latency results in a larger threshold voltage drift compared to a shorter W2R latency. In this example, the read retry trigger rate (i.e., the error rate that triggers error correction processing) is higher with a longer W2R latency than with a shorter W2R latency.

[0023] Existing memory subsystems adjust the read voltage level based on the W2R delay time by establishing one or more static W2R delay time ranges and associating the read voltage level with each static W2R delay time range. The read voltage level is adjusted at the appropriate time by measuring the current W2R delay time and identifying the static W2R delay time range corresponding to the current W2R delay time. A read operation is then performed using the read voltage level associated with the identified static W2R delay time range. For example, two static W2R delay time ranges (with associated W2R delay time thresholds) can be defined using the drift tracking characteristics of the memory subsystem: a first threshold with a value of 50,000 write cycles and a second threshold with 100,000 write cycles. Each threshold can correspond to a boundary or endpoint of a static write cycle range. Thus, in this example, the first threshold corresponds to a first static range of 0-50,000 cycles, and the second threshold corresponds to a second static range of 50,000-100,000 cycles.

[0024] The drift tracking feature associates a first static W2R delay time threshold with a first read voltage level optimized for a first static write cycle range, and associates a second static W2R delay time threshold with a second read voltage level optimized for a second static write cycle range. The drift tracking feature can measure the current W2R delay time at an appropriate time during memory subsystem operation and adjust the read voltage level based on the static range to which the current W2R delay time belongs. For example, if the current W2R delay time belongs to a first static range ending at a first threshold, the read voltage level is set to the first read voltage level because the first read level is associated with the first static threshold. If the current W2R delay time belongs to a second static range ending at a second threshold, the read voltage level is set to the second read voltage level because the second read voltage level is associated with the second static threshold.

[0025] The static W2R latency threshold used by the drift tracking feature is set to meet the acceptable BER of the memory device. The preset static W2R latency threshold remains constant throughout multiple different lifecycle phases of the memory device, including the Start of Life (BOL), Mid-Life (MOL), and End of Life (EOL) phases. Therefore, in operation, the drift tracking feature uses a static W2R latency threshold optimized for specific operating characteristics, such as specific wear conditions (e.g., the write count range corresponding to the EOL phase) and specific temperatures. However, the appropriate W2R latency threshold used to accurately determine whether the read voltage level has a first or second value can vary with the wear conditions, temperature, and / or other operating characteristics of the memory device, as these operating characteristics affect the threshold voltage shift. The static W2R latency threshold used to adjust the read voltage level may not be suitable for accurately determining the read voltage level under certain operating conditions, such as wear conditions or temperatures significantly different from those optimized by the static W2R latency threshold. Therefore, using a static W2R latency threshold leads to system performance degradation due to more frequent read errors and read retries, and the performance degradation is exacerbated by the increased number of retried read operations.

[0026] This disclosure addresses the aforementioned and other drawbacks by using a read voltage adjustment technique based on comparing the write-to-read latency time with one or more time thresholds adjusted according to changes in the operating characteristics of the memory subsystem. In one embodiment, each latency threshold is associated with a read voltage level, and the memory subsystem identifies the read voltage level for a read operation by determining the current write-to-read latency time and determining which latency threshold (e.g., exceeding but not exceeding any higher latency threshold) the current write-to-read latency time corresponds to. The latency threshold corresponding to the current write-to-read latency time has an associated read voltage level, which the memory subsystem can use to perform a read operation. For example, the memory subsystem can determine the current write-to-read latency time based on the time difference between a read operation and a write operation.

[0027] The memory subsystem adjusts latency thresholds based on its operating characteristics (e.g., cycle count, operating temperature, which layer of the memory device contains the cell to be read, or which region of the layer contains the cell to be read). The memory subsystem can use a mapping from operating characteristic values ​​to latency thresholds to determine latency thresholds based on specific values ​​of the operating characteristics. The mapping can specify multiple latency thresholds, and each latency threshold will be applied to the operating characteristic value (e.g., as a threshold or range). Latency thresholds can be specified as specific values ​​or offsets applied to specific values. The memory subsystem can adjust write-to-read latency thresholds at appropriate times during operation, such as at a specific cycle count threshold, in response to changes in operating characteristics, at periodic intervals, or based on other criteria.

[0028] In other implementations, the memory subsystem may maintain multiple write-to-read latency ranges and adjust the endpoints of these ranges according to changes in operating characteristics. The endpoints of the ranges may correspond to the latency thresholds described above. Similar to the adjustment of the latency thresholds described above, the ranges are adjusted based on operating characteristics at appropriate times. Each range is associated with a read voltage level. The memory subsystem can perform a read operation using the read voltage level associated with the range to which the current read-to-write latency has decreased.

[0029] The advantages of this disclosure include, but are not limited to, improved performance under a range of operating conditions, including attenuation conditions related to write count, temperature conditions, memory device layers, and regions of memory device layers. Different layers (or regions of layers) can have different physical properties that affect latency thresholds, and advantageously, adjusted write-to-read latency thresholds can be identified and applied based on one or more operating characteristics of the memory subsystem (e.g., write count, temperature level, layer, or region of layer). Adjusting W2R latency based on operating characteristics improves efficiency and performance over a broader range of operating characteristics that differ from those that can be optimized for static write-to-read latency thresholds. Improved efficiency and performance over this broader range of operating characteristics can include, for example, fewer errors and read retries, which can also result in slower media degradation.

[0030] Figure 1 An example computing system 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0031] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0032] The computing environment 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. The host system 120 uses the memory subsystem 110, for example, to write data to and read data from the memory subsystem 110. As used herein, “coupled to” generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical connections, optical connections, magnetic connections, etc.

[0033] Host system 120 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., aircraft, drone, train, automobile, or other means of transportation), Internet of Things (IoT) device, embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment, or networked commercial device), or such computing device containing memory and processing power. Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 may further utilize an NVM High Speed ​​(NVMe) interface to access memory components (e.g., memory device 130). The physical host interface can provide an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120.

[0034] The memory device may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory device (e.g., memory device 140) may be, but is not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0035] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and write-in-place memory, such as three-dimensional crosspoint (“3D crosspoint”) memory. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them.

[0036] Although non-volatile memory components such as 3D cross-point memory are described, memory device 130 can be based on any other type of non-volatile memory, such as NAND, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0037] One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory component may include an SLC portion of memory cells as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages or codewords, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks. Some types of memory (e.g., 3D cross-connects) may group pages across the die and channels to form management units (MUs).

[0038] The memory subsystem controller 115 can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include digital circuitry with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0039] The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0040] In some embodiments, local memory 119 may include memory registers storing memory pointers, acquired data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The example memory subsystem 110 in the present disclosure is shown to include a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0041] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to enable the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical block addresses and physical block addresses associated with the memory device 130. The memory subsystem controller 115 may further include host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0042] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0043] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 may be a managed memory device, which is a native memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0044] The memory subsystem 110 includes a read voltage adjustment component 113, which can be used to determine an adjusted read threshold based on an adjustable W2R delay threshold. The read voltage adjustment component 113 includes a delay time threshold determiner 114 and a read voltage level determiner 116. The read voltage adjustment component 113 monitors the operating characteristics of the memory subsystem 110 and adjusts the W2R delay threshold based on said operating characteristics. In embodiments, the operating characteristics may be measured, determined, or calculated values ​​or levels corresponding to characteristics or conditions of the memory subsystem 110 during operation. In embodiments, the operating characteristics may be operating levels or conditions that affect the threshold voltage drift of the memory subsystem 110. For example, the operating characteristics may be the memory subsystem's cycle count, temperature, stack (which may correspond to a layer), or electrical distance (which may correspond to a region of the stack).

[0045] In some embodiments, controller 115 includes at least a portion of read voltage adjustment component 113. Memory subsystem 110 may adjust the W2R delay threshold at appropriate times during operation, such as at a specific write count threshold, in response to changes in operating characteristics, at periodic intervals, or based on other criteria. Delay time threshold determiner 114 may determine a set of delay time thresholds based on one or more operating characteristics of memory subsystem 110. Each of the set of delay time thresholds may correspond to a delay time range. When the W2R delay time of memory subsystem 110 corresponds to an associated threshold (e.g., satisfies a criterion associated with the corresponding threshold) (or falls within a corresponding range), each of the delay time thresholds (or ranges) may be associated with a corresponding read voltage level to be used in a read operation. Read voltage level determiner 116 may determine the read voltage level to be used in a read operation by determining the current W2R delay time and determining which threshold (or range) the current W2R delay time corresponds to (or which range the current W2R delay time belongs to). Memory subsystem 110 then performs a read operation using the corresponding read voltage level associated with the determined threshold (or range).

[0046] For example, controller 115 may include processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, read voltage adjustment component 113 is part of host system 120, an application, or an operating system. In the same or alternative embodiments, a portion of read voltage adjustment component 113 is part of host system 120, while other portions of read voltage adjustment component 113 are executed at controller 115.

[0047] In an embodiment, based on the operating characteristics of the memory subsystem 110, the read voltage adjustment component 113 determines a set of W2R latency thresholds, which can then be used to determine read levels corresponding to the operating characteristics. During operation of the memory subsystem 110, the read voltage adjustment component 113 determines a set of current operating characteristic values of the memory subsystem (e.g., write count and temperature), and uses a data structure that maps operating characteristic values to the set of W2R latency thresholds (e.g., via a lookup operation) to identify the corresponding set of W2R latency thresholds. For example, the data structure can include multiple sets of W2R latency thresholds, and each set can be associated with an operating characteristic threshold. The read voltage adjustment component 113 can compare the current operating characteristic value (e.g., the current write count) with the operating characteristic thresholds associated with each W2R latency threshold. The comparison can be performed using criteria based on the operating characteristic thresholds. The read voltage adjustment component 113 can select the set of W2R latency thresholds for which the current operating characteristic value meets the criteria. For example, if the current operating characteristic value is between an operating characteristic threshold and the next lower (or next higher) operating characteristic threshold, the current operating characteristic value can meet the criteria based on the operating characteristic threshold. "Between" when used in reference to a threshold or range can indicate an inclusive threshold or range that includes the threshold or range endpoint values (e.g., if 0 <= a <= threshold, then a is between 0 and the threshold), or can indicate an exclusive threshold or range that includes values up to but not including the threshold or range endpoint values (e.g., 0 < a < threshold). Whether a particular threshold or range includes the threshold or range endpoint values can be specified by information associated with the threshold or range, such as the criteria that includes the threshold or range. For example, the criteria based on the threshold can be 0 <= a <= threshold, and values of a between 0 and the threshold (including 0 and the threshold) meet the criteria.

[0048] Each W2R latency threshold in the W2R latency threshold set is associated with a read voltage level. For example, the data structure described above can further associate each W2R latency threshold in each W2R latency threshold set with a corresponding read level. Thus, if the current W2R latency of the memory subsystem 110 meets the criteria based on one of the W2R latency thresholds, the read voltage adjustment component 113 can cause the memory subsystem controller 115 to perform subsequent read operations using the read voltage level associated with the W2R latency threshold that the current W2R latency meets. For example, if the current W2R latency is between the W2R latency threshold in the W2R latency threshold set and the next lower (or next higher) W2R latency threshold, then the current W2R latency can meet the criteria based on the W2R latency threshold in the set. "Between... and" when used in reference to a threshold or range can indicate an inclusive threshold or range that includes the threshold or range endpoint values (e.g., if 0 <= a <= threshold, then a is between 0 and the threshold), or can indicate an exclusive threshold or range that includes values up to the threshold or range endpoint value but does not include the threshold or range endpoint value (e.g., 0 < a < threshold). Whether a particular threshold or range includes the threshold or range endpoint value can be specified by information associated with the threshold or range, such as the criteria that include the threshold or range. For example, the criteria based on the threshold can be 0 <= a <= threshold, and values of a between 0 and the threshold (including 0 and the threshold) meet the criteria.

[0049] In an embodiment, the W2R latency time threshold can be determined as a function of multiple different types of operating characteristics. The read voltage adjustment component 113 can determine each W2R latency time threshold as the sum of a base threshold and one or more W2R latency offset values. The base threshold can be the amount of time determined for a first type of operating characteristic associated with the memory device (e.g., write count as described above), and each offset value can be the amount of time determined for a corresponding different type of operating characteristic associated with the memory device (e.g., temperature, bank, electrical distance, or other operating characteristics). Thus, a temperature-based W2R latency offset can be determined and added to the base threshold. Similarly, a bank-based offset can be determined based on the bank identifier of the memory device, and an electrical-distance-based offset can be determined based on the electrical distance of the memory device and added to the base threshold. Additionally, if the base threshold is determined based on an operating characteristic other than write count, a write-count-based offset can be determined based on the write count and added to the base threshold.

[0050] The offset for each type of operational characteristic (e.g., temperature, stacking, electrical distance, write count, or other operational characteristics) can be determined using a data structure that maps operational characteristic values ​​of offset types to W2R delay offset sets. For example, a data structure that maps temperature to delay time offset sets can be used to determine a temperature-based offset. The read voltage adjustment component 113 can compare the current temperature of the memory device with the temperature range associated with each W2R delay offset set in the table. The read voltage adjustment component 113 can select the W2R delay offset set associated with the temperature range to which the current temperature has dropped. The offsets for other types of operational characteristics can be determined similarly.

[0051] In the same or alternative embodiments, as an alternative to or supplement to the threshold, the data structure can map operational characteristic values ​​to a set of W2R delay ranges. The threshold can represent one endpoint of the range, and the other endpoint of the range can be represented by another threshold. The read voltage adjustment component 113 can determine the current set of operational characteristic values ​​of the memory subsystem (e.g., write count and temperature) and identify the corresponding W2R delay range set using the data structure that maps operational characteristic values ​​to a set of W2R delay ranges (e.g., via a lookup operation). For example, the data structure can contain multiple sets of W2R delay ranges, and each set can be associated with an operational characteristic range. The range can contain a first endpoint and a second endpoint. If a value lies between the first endpoint and the second endpoint, the value may belong to a range. The read voltage adjustment component 113 can determine which operational characteristic range the current operational characteristic value (e.g., the current write count) belongs to and select a set of W2R delay thresholds associated with the range to which the current operational characteristic belongs.

[0052] Each W2R delay range in the set of W2R delay ranges is associated with a read voltage level. For example, the data structure described above can further associate each W2R delay range in each set of W2R delay ranges with a corresponding read level. Therefore, if the current W2R delay of memory subsystem 110 belongs to one of the W2R delay ranges in the set, read voltage adjustment component 113 can cause memory subsystem controller 115 to perform subsequent read operations using the read voltage level associated with the W2R delay range to which the current W2R delay belongs. The delay offset described above can be added to one or both endpoints of the corresponding W2R delay range. Further details relating to the operation of read voltage adjustment component 113 are described below.

[0053] Figure 2A-2C Examples of voltage shifting according to some embodiments are shown. Figure 2AA graph 200 is shown for the initial time T1. The graph 200 shows a setup voltage distribution 202A corresponding to a programmed value, for example, 0, and a reset voltage distribution 204A corresponding to a programmed value, for example, 1. The horizontal (volt) axis represents the voltage values, increasing to the right. The initial read voltage level VDM1 divides the setup distribution 202A and reset distribution 204A of a specific area (e.g., stack or electrical distance) of the memory device in the memory subsystem into a specific number of cycles. However, for the same number of cycles, the read voltage level VDM1 does not clearly divide the setup distribution 203 and reset distribution 205 into different areas of the memory subsystem (e.g., different stacks or different electrical distances). Due to the suboptimal VDM1 for different stacks (or electrical distances), bits in different areas within the ellipse 207 surrounding the intersection of VDM1 and setup distribution 203 may be read as incorrect values. Therefore, the read voltage level VDM1 is not suitable for use in read operations on different areas of the memory subsystem, and it is better to clearly distinguish the different read voltage levels of the set distribution 203 and the reset distribution 205 than VDM1.

[0054] Figure 2B Graph 210 shows the time T2 occurring after time T1. During the time interval between T1 and T2, the initial setting distribution 202A has drifted to the first shifted setting distribution 202B. Similarly, the initial reset distribution 204A has drifted to the first shifted reset distribution 204B during the same time interval. VDM1 is the suboptimal read voltage level at time T2 because VDM1 overlaps with the first shifted setting distribution 202B. At time T2, the distinct read voltage VDM2, which clearly distinguishes the first shifted setting distribution 202B and the first shifted reset distribution 204B, is superior to VDM1.

[0055] Figure 2C Graph 220 shows the time T3 occurring after time T2. It can be seen that since time T2, because the reset distribution drifts at a faster rate than the setting distribution, the reset distribution has drifted further to the left than the setting distribution. Therefore, the different distributions drift at different rates. During the time period between T2 and T3, the first shifted setting distribution 202B has drifted to the second shifted setting distribution 202C. Similarly, the first shifted reset distribution 204B has drifted to the second shifted reset distribution 204B during the same time period. VDM2 is the suboptimal read voltage level at time T3 because VDM2 overlaps with the second shifted setting distribution 202C. At time T3, the distinct read voltage VDM3, which clearly distinguishes the second shifted setting distribution 202C from the second shifted reset distribution 204C, is superior to VDM2.

[0056] Figure 3AAn example latency threshold determiner 114, according to some embodiments, adjusts the write-to-read latency threshold. The latency threshold determiner 114 receives one or more current operational characteristic values ​​302 as input. Each operational characteristic value 302 may be a characteristic of one or more cells of the memory device 130 of the memory subsystem 110. The operational characteristic value 302 may include cycle counts, such as write counts, temperature, stacking, electrical distance, or other characteristics of the cells of the memory device 130. The temperature of the memory device 130 may be based on, for example, a temperature measurement of the memory subsystem 110 or a temperature measurement of the memory device 130. A stack may be, for example, a layer of the memory device 130. An electrical distance may be, for example, the distance from a voltage source to a memory cell in the memory array of the memory device 130. The electrical distance may correspond to a region of a stack. For example, a first electrical distance may correspond to a first region containing cells at a first distance from the voltage source, and a second electrical distance may correspond to a second region containing cells at a second distance from the voltage source.

[0057] The delay time threshold determiner 114 determines a W2R delay time threshold set 314 based on the operating characteristic value 302. The delay time threshold determiner 114 includes or accesses an operating characteristic (“OC”) threshold set 304, each of which is associated with the delay time threshold set 314. The OC threshold 304 and the delay time threshold 312 can be determined, for example, based on media characterization information and / or empirical data associated with the memory device 130. The OC threshold 304 and the associated delay time threshold set 312 can be stored in a data structure, such as... Figure 5A The mapping table 500 or other representation of the mapping table. The OC threshold set 304 contains a first OC threshold 306A, a second OC threshold 306B, and a third OC threshold 306C, respectively. The data structure associates each of the OC thresholds 306 with a corresponding W2R delay time threshold set 312, and further associates each W2R delay time threshold 316 in each W2R delay time threshold set 312 with a voltage readout level, as discussed below regarding... Figure 3B describe.

[0058] The delay time threshold determiner 112 can select a W2R delay threshold set 312 for which the current operating characteristic value 302 satisfies the corresponding criterion 308. To select a W2R delay threshold set 312, the delay time threshold determiner 114 compares the current operating characteristic value 302 with an OC threshold 306 associated with each W2R delay threshold set 312. This comparison can be performed using criterion 308 based on the OC threshold 306 corresponding to criterion 308. For example, criterion 308A (“between 0 and a first OC threshold”) is associated with a first OC threshold 306A (“50,000”).

[0059] If the current operating characteristic value 302 satisfies criterion 308, the delay time threshold determiner 112 can select the OC threshold 306A corresponding to the satisfied criterion 308. Then, the delay time threshold determiner 112 can select a W2R delay time threshold set 312 associated with the selected OC threshold 306. For example, a first W2R delay time threshold set 312A is associated with a first OC threshold 306A; therefore, when the operating characteristic value 302 satisfies criterion 308A based on the first OC threshold 306A, the selected W2R delay time threshold set 314 is the first W2R delay time threshold set 312A. Similarly, as another example, a second W2R delay time threshold set 312B is associated with a second OC threshold 306B; therefore, when the operating characteristic value 302 satisfies criterion 308B based on the second OC threshold 306B, the selected W2R delay time threshold set 314 is the second W2R delay time threshold set 312B. As another example, the third W2R delay time threshold set 312C is associated with the third OC threshold 306C. Therefore, when the operating characteristic value 302 satisfies the criterion 308C based on the third OC threshold 306C, the selected W2R delay time threshold set 314 is the third W2R delay time threshold set 312C.

[0060] For example, the first OC threshold 306A can be 50,000 writes, and the first criterion "between 0 and 50,000" can be based on the first OC threshold 306A. The second OC threshold 306B can be 100,000 writes, and the second criterion "between 50,000 and 100,000" can be based on the second OC threshold 306B. The third OC threshold 306C can be 150,000 writes, and the third criterion "between 100,000 and 150,000" can be based on the third OC threshold 306C. For example, if the operational characteristic value is 65,000 writes, the latency threshold determiner 114 selects the second W2R latency threshold set 312B because 65,000 satisfies the second criterion ("between 50,000 and 100,000 writes").

[0061] The selected W2R delay threshold set 314 includes one or more delay thresholds 316, such as a first delay threshold 316A corresponding to a first read level, a second delay threshold 316B corresponding to a second read level, and a third delay threshold 316C corresponding to a third read level. The delay thresholds 316 can be selected from the W2R delay threshold set 314 and are used to identify the read level, as described below. Figure 3B As described.

[0062] In an embodiment, for example, if the current operating characteristic value is between the OC threshold 306 and a higher (or next lower) operating characteristic threshold 306, then the current operating characteristic value 302 can satisfy the criteria based on the OC threshold 306. For example, the delay time threshold determiner 114 can select a W2R delay threshold set 314 as follows. Since the operating characteristic value of 65,000 is between the first OC threshold 306A and the second OC threshold 306B, and the delay time threshold determiner 114 selects (e.g., conventionally) an upper limit threshold that includes the range of operating characteristic value 302, the selected threshold is the second OC threshold 306B. The W2R delay time threshold set 312B associated with the selected threshold (306B) is the second W2R delay time threshold set 312B.

[0063] In an embodiment, the delay time threshold determiner 114 can determine the W2R delay time threshold 316 as a function of multiple different types of operating characteristics 302. The delay time threshold determiner 114 can determine each W2R delay threshold as a sum of a base threshold and one or more W2R delay offset values. The base threshold can be a time amount determined for a first type of operating characteristic associated with the memory device (e.g., write count as described above), and each offset value can be a time amount determined for a corresponding different type of operating characteristic associated with the memory device (e.g., temperature, stack, electrical distance, or other operating characteristics). Therefore, the delay time threshold determiner 114 can determine a temperature-based W2R delay offset and add it to the base threshold. Similarly, the delay time threshold determiner 114 can determine a stack-based offset based on the stack identifier of the memory device and can determine an electrical distance-based offset based on the electrical distance of the memory device, and add these offsets to the base threshold. Furthermore, if the base threshold is determined based on an operating characteristic other than the write count, the delay time threshold determiner 114 can determine a write count base offset based on the write count.

[0064] The delay time threshold determiner 114 can use a data structure that maps offset type operational characteristic values ​​to a W2R delay offset set to determine the offset for each type of operational characteristic (e.g., temperature, stacking, electrical distance, write count, or other operational characteristics). For example, a data structure that maps temperature to a delay time offset set (e.g., ...) can be used. Figure 6AThe temperature offset table 600 shown indicates that a temperature-based offset is determined. The read voltage adjustment component 113 can compare the current temperature of the memory device with the temperature range associated with each W2R delay offset set in the table. The read voltage adjustment component 113 can select the W2R delay offset set associated with the temperature range to which the current temperature belongs and add each of the W2R delay offsets to a delay time threshold corresponding to the read level of the W2R delay offset. Offsets for other types of operating characteristics can be determined similarly. For example, offsets can be determined using… Figure 6B The stack offset table 610 shown determines the stack-based offset, and can be used... Figure 6C The electrical distance offset table 620 shown determines the offset based on electrical distance. In other embodiments, for example, the read voltage adjustment component 113 can add each of the W2R delay offsets to the delay range corresponding to the read level of the W2R delay offset by adding each W2R delay offset to both ends of the delay range corresponding to the read level of the W2R delay offset.

[0065] Although the delay time threshold determiner 114 is described as processing the OC threshold 306 and determining the W2R delay time threshold 314, in other embodiments, the delay time threshold determiner 114 may process an OC threshold range and / or determine a W2R delay time range. Each endpoint of the time range may correspond to a threshold. Therefore, in other embodiments, an OC threshold range may be converted to an OC threshold 306 or an OC threshold may be converted to an OC threshold range, and a W2R delay time range may be converted to a W2R delay time threshold 314 or a W2R delay time threshold may be converted to a W2R delay time range.

[0066] Figure 3B An example read level determiner 116, according to some embodiments, is shown using an adjustable write-to-read latency time threshold. The read level determiner 116 determines a read voltage level 326 based on a W2R latency time threshold set 314 and a current W2R latency time 322. The read level determiner 116 may receive the W2R latency time threshold set 314 and the current W2R latency time 322 as input. If no W2R latency time 322 is received as input, the read level determiner may generate the W2R latency time. The W2R latency time 322 may be generated based on the latency between a write operation and a read operation performed by the memory subsystem on a memory cell of the memory device 130. The W2R latency time 322 may, for example, be the difference between the time of performing a read operation and the time of performing a write operation before the read operation.

[0067] The W2R delay time threshold set can be based on one or more operational characteristic values ​​302 and is provided by the delay time threshold determiner 114, as described above. Figure 3AAs described. The read level determiner 116 includes or accesses a mapping between a delay time threshold 316 and a read voltage level 324. This mapping can be stored in a data structure, such as... Figure 5A The mapping table 500 or other representation of the mapping table. When a criterion based on a delay time threshold 316 is met, the data structure associates each of the delay time thresholds 316 with a corresponding read level voltage 324 used for the read operation. The criterion may include a comparison between the current W2R delay time 322 and one or more of the W2R delay time thresholds 316 in the W2R delay time threshold set 314.

[0068] Each W2R delay threshold 316 in the selected W2R delay threshold set 314 can be associated with a read voltage level. For example, the data structure described above can further associate each W2R delay threshold 316 in each W2R delay threshold set 314 with a corresponding read level.

[0069] The read level determiner 116 can select a read voltage level 326 for which the current W2R delay time 322 satisfies the corresponding criterion 320. To select the read voltage level 326, the read level determiner 116 compares the current W2R delay time 322 with each W2R delay time threshold 316 in the W2R delay time threshold set 314 and determines which W2R delay time threshold 316 satisfies the criterion 320. This comparison can be performed using criterion 320A based on the W2R delay time threshold 316 corresponding to criterion 320. For example, if the current W2R delay time 322 is between the W2R delay threshold 316 and the next higher (or next lower) W2R delay threshold 316 in the set 314, then the current W2R delay time 322 satisfies the criterion based on the W2R delay time threshold 316 in the W2R delay threshold set 314. If the W2R delay time threshold 316 is associated with a range (e.g., it is an endpoint of the range), then if the current W2R delay time 322 falls within the range associated with the W2R delay time threshold, then the current W2R delay time 322 satisfies the criterion based on the W2R delay time threshold 316. For example, the first W2R delay time threshold 316A can be 1 second, and the first W2R delay time threshold 316A can be associated with a first range "0 seconds <= current W2R delay time < 1 second". The first range can correspond to the first criterion 320A. Furthermore, the second W2R delay time threshold 316B can be 10 seconds, and the second W2R delay time threshold 316B can be associated with a second range "1 second <= current W2R delay time < 10 seconds". The second range can correspond to the second criterion 320B. In this example, a current W2R delay time of 5 seconds satisfies the criterion 320B associated with the second W2R delay time 316B.

[0070] If the current W2R delay time 322 satisfies criterion 320, the read level determiner 116 can select the W2R delay time threshold 316 corresponding to the satisfied criterion 320. Then, the read level determiner 116 can select a read voltage level 324 associated with the selected W2R delay time threshold. For example, a first read voltage level 324A is associated with a first W2R delay time threshold 316A; therefore, when the current W2R delay time 322 satisfies criterion 320A based on the first W2R delay time threshold 316A, the selected read voltage level 326 is the first read voltage level 324A.

[0071] Similarly, in another example, the second read voltage level 324B is associated with a second W2R delay time threshold 316B. Therefore, when the current W2R delay time 322 satisfies criterion 320B based on the second W2R delay time threshold 316B, the selected read voltage level 326 is the second read voltage level 324B. As yet another example, the third read voltage level 324C is associated with a third W2R delay time threshold 316C. Therefore, when the current W2R delay time 322 satisfies criterion 320C based on the third W2R delay time threshold 316C, the selected read voltage level 326 is the third read voltage level 324C.

[0072] Therefore, if the current W2R delay time 322 of the memory subsystem 110 satisfies the criterion 320 based on either the W2R delay threshold 316 or the current W2R delay time, the read level determiner 116 can determine the read voltage level 326 and cause the memory subsystem controller 115 to perform one or more subsequent read operations using the selected read voltage level 326.

[0073] Although the read level determiner 116 is described as handling the W2R delay time threshold 314, in other embodiments, the read level determiner 116 may handle a W2R delay time range.

[0074] Figure 4A This is a flowchart of an example method 400 for adjusting a delay time threshold and determining a corresponding read level according to some embodiments. Method 400 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1The reading voltage adjustment component 113 performs the operation. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0075] In operation 402, the processing device determines a first current operating characteristic value for a cell of the memory device. In operation 404, the processing device identifies a first operating characteristic threshold from a set of first operating characteristic thresholds, wherein the first current operating characteristic value satisfies a first operating characteristic threshold criterion based on the first operating characteristic threshold. Each of the operating characteristic thresholds may correspond to an operating characteristic range having a first endpoint specified by the corresponding operating characteristic threshold.

[0076] In operation 406, the processing device identifies a set of delay time thresholds corresponding to a first operational characteristic threshold from a plurality of delay time threshold sets, wherein each of the delay time thresholds in the set is associated with a corresponding read voltage level. Each of the delay time thresholds in the set may represent an endpoint of a corresponding write-to-read delay time range, and the corresponding read voltage level associated with each of the delay time thresholds in the set may be used to perform a read operation on a memory component having a write-to-read delay time within the corresponding write-to-read delay time range.

[0077] A first mapping table that maps operational characteristic thresholds to a set of delay time thresholds can be used to identify a delay time threshold set, wherein the first mapping table maps each operational characteristic threshold to a corresponding delay time threshold set. The first mapping table may contain a set of records, each record including a specific operational characteristic threshold and a corresponding delay time threshold set. The processing device can identify records in the first mapping table that contain a first operational characteristic threshold, wherein the record further contains the identified delay time threshold set. The first mapping table can map each delay time threshold of each delay time threshold set to a corresponding read voltage level, and the first mapping table can be used to identify the read voltage level associated with the identified delay time threshold.

[0078] In operation 408, the processing device identifies a latency threshold from a set of latency thresholds, for which the current write-to-read latency of a cell in the memory device satisfies an associated latency threshold criterion. In operation 410, the processing device identifies a read voltage level associated with the identified latency threshold. The processing device can then perform a read operation at a cell in the memory device based on the read voltage level.

[0079] Figure 4BThis is a flowchart of an example method 420 for adjusting the delay time range and performing a read operation using a corresponding read level, according to some embodiments. Method 420 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 420 is performed by… Figure 1 The reading voltage adjustment component 113 performs the operation. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0080] In operation 422, the processing device identifies the current loop count associated with the memory subsystem. In operation 424, the processing device identifies a loop count range containing the current loop count from the set of loop count ranges.

[0081] In operation 426, the processing device identifies a set of W2R delay time ranges corresponding to a cycle count range from a set of multiple write-to-read (W2R) delay time ranges, where each of the W2R delay time ranges represents a plurality of W2R delay times and is associated with a corresponding read voltage level for performing a read operation on a cell of a memory device having a W2R delay time within the W2R delay time range. The W2R delay time range set can be identified using a first mapping table that maps cycle count ranges to sets of W2R delay time ranges. The first mapping table may contain a set of records, and each record may contain a specific cycle count range and a corresponding set of W2R delay time ranges. The processing device can identify and search for records in the first mapping table that contain a cycle count range of the current cycle count. If the record is found, it specifies the identified set of W2R delay time ranges. Furthermore, the first mapping table maps each W2R delay time range of each set of W2R delay time ranges to a corresponding read voltage level, and the processing device can use the first mapping table to identify the read voltage level associated with the identified W2R delay time range.

[0082] The processing device can measure the current temperature associated with the memory subsystem and identify temperature ranges from a set of temperature ranges that include the current temperature associated with the memory subsystem. The processing device can also identify a set of W2R delay time offsets corresponding to the current temperature associated with the memory subsystem from multiple sets of W2R delay time offsets, such that each W2R delay time offset in the set of W2R delay time offsets is associated with a corresponding read voltage level. The processing device can adjust the set of W2R delay time ranges based on the identified set of write-to-read (W2R) delay time offsets. The processing device can adjust the set of W2R delay time ranges by adding each W2R delay time offset from the identified set of W2R delay time offsets to each endpoint of each W2R delay time range in the identified set of W2R delay time ranges.

[0083] In operation 428, the processing device identifies the W2R delay time of a cell in the memory device, wherein the identified W2R delay time is based on the time difference between a write operation and a read operation performed by a cell in the memory device. In operation 430, the processing device identifies a W2R delay time range from a set of delay time ranges that includes the W2R delay times of cells in the memory device. In operation 432, the processing device identifies a read voltage level corresponding to the identified W2R delay time range. In operation 434, the processing device performs a read operation at a cell in the memory device based on the determined read voltage level.

[0084] Figure 5A Table 500 illustrates, according to some embodiments, a set of example write-to-read latency thresholds corresponding to example threshold operation characteristic values ​​of a memory subsystem. Table 500 maps write count thresholds 502 to W2R latency threshold sets 506. Table 500 further maps each latency threshold in each set 506 to a read level 504. Table 500 specifies that for a first write count threshold (e.g., 50,000 writes) 502A, the corresponding first latency threshold set 506A includes a first latency threshold for a first read level 504A, a second latency threshold for a second read level 504B, and a third latency threshold for a third read level 504C. The first latency threshold, second latency threshold, and third latency threshold of the first set 506A can be, for example, 1 microsecond, 1 second, and 1 hour, respectively. Figures 5A-5C The tables shown in 6A-6C can be generated, for example, based on media characterization information associated with memory device 130 and / or based on empirical data.

[0085] Table 500 specifies, for example, that a first latency threshold set 506A will be used when the current write count of the memory subsystem is between a lower limit (e.g., 0 writes) and a first write count threshold 502A (e.g., 50,000 writes). Furthermore, the first set 506A specifies that a first read level 504A will be used when the current latency value is between a lower limit (e.g., 0 seconds) and a first latency threshold (e.g., 1 microsecond). The first set 506A also specifies that a second read level 504B will be used when the current latency value is between a first latency threshold (e.g., 1 microsecond) and a second latency threshold (e.g., 1 second). The first set 506A further specifies that a third read level 504C will be used when the current latency value is between a second latency threshold (e.g., 1 second) and a third latency threshold (e.g., 1 hour).

[0086] Table 500 also specifies that a second latency threshold set 506B will be used when the current write count of the memory subsystem is between a first write count threshold 502A (e.g., 50,000 writes) and a second write count threshold 502B (e.g., 100,000 writes). Furthermore, the second set 506B specifies that a first read level 504A will be used when the current latency value is between a lower limit (e.g., 0 seconds) and a first latency threshold (e.g., 1 microsecond). The second set 506B also specifies that a second read level 504B will be used when the current latency value is between a first latency threshold (e.g., 1 microsecond) and a second latency threshold (e.g., 0.5 seconds). The second set 506B further specifies that a third read level 504C will be used when the current latency value is between a second latency threshold (e.g., 0.5 seconds) and a third latency threshold (e.g., 0.5 hours).

[0087] Table 500 also specifies, for example, that a third latency threshold set 506C will be used when the current write count of the memory subsystem is between a second write count threshold 502B (e.g., 100,000 writes) and a third write count threshold 502C (e.g., 150,000 writes). Furthermore, the third set 506C specifies that a first read level 504A will be used when the current latency value is between a lower limit (e.g., 0 seconds) and a first latency threshold (e.g., 1 microsecond). The third set 506C also specifies that a second read level 504B will be used when the current latency value is between the first latency threshold (e.g., 1 microsecond) and a second latency threshold (e.g., 0.2 seconds). The third set 506C further specifies that a third read level 504C will be used when the current latency value is between the second latency threshold (e.g., 0.2 seconds) and a third latency threshold (e.g., 0.2 hours).

[0088] Figure 5BTable 510 illustrates a set of example write latency thresholds corresponding to example operational characteristic value ranges of a memory subsystem, according to some embodiments. Table 510 maps write count range 512 to W2R latency threshold set 516. Table 510 further maps each latency threshold in each set 516 to a read level 514. Table 510 specifies that for a first write count range (e.g., 0-50,000 writes) 512A, the corresponding first latency threshold set 516A includes a first latency threshold for a first read level 514A, a second latency threshold for a second read level 514B, and a third latency threshold for a third read level 514C. The first latency threshold, second latency threshold, and third latency threshold of the first set 516A can be, for example, 1 microsecond, 1 second, and 1 hour, respectively.

[0089] Table 510 specifies, for example, that a first latency threshold set 516A will be used when the current write count of the memory subsystem is within the first range 512A (e.g., 0-50,000 writes). The first set 516A is specified as described above for... Figure 5A Table 500 describes the latency thresholds. Table 500 also specifies that a second latency threshold set 506B will be used when the current write count of the memory subsystem is within the second range 512B (e.g., 50,000-100,000 writes). The second set 516B specifies as above for... Figure 5A Table 500 describes the latency thresholds. Table 510 also specifies, for example, that a third latency threshold set 506C will be used when the current write count of the memory subsystem is within a third range 512C (e.g., 100,000-150,000 writes). The third set 516C is specified as above for... Figure 5A The delay time thresholds described in Table 500.

[0090] Figure 5C Table 520 illustrates a set of example write latency ranges corresponding to example operational characteristic value ranges of a memory subsystem, according to some embodiments. Table 520 maps write count ranges 522 to W2R latency ranges 526. Table 520 further maps each latency range in each set 526 to a read level 524. Table 520 specifies that for a first write count range (e.g., 0-50,000 writes) 522A, the corresponding first latency range set 526A includes a first latency range of a first read level 524A, a second latency range of a second read level 524B, and a third latency range of a third read level 524C. The first latency range, second latency range, and third latency range of the first set 526A can be (0 seconds, 1 second), (1 second, 1 hour), and (1 hour, infinity), respectively.

[0091] Table 520 specifies, for example, that a first delay time range set 526A will be used when the current write count of the memory subsystem is within a first range 522A (e.g., 0-50,000 writes). The first set 526A specifies that a first read level 524A will be used when the current W2R delay time is within a first delay time range of the first set 526A, a second read level 524B will be used when the current W2R delay time is within a second delay time range of the first set 526A, and a third read level 524C will be used when the current W2R delay time is within a third delay time range of the first set 526A.

[0092] Table 520 also specifies, for example, that a second delay time range set 526B will be used when the current write count of the memory subsystem is within the second range 522B (e.g., 50,000-1,000,000 writes). The second set 526B specifies that a first read level 524A will be used when the current W2R delay time is within a first delay time range of the second set 526B, a second read level 524B will be used when the current W2R delay time is within a second delay time range of the second set 526B, and a third read level 524C will be used when the current W2R delay time is within a third delay time range of the second set 526B.

[0093] Table 520 further specifies, for example, that a third delay time range set 526C will be used when the current write count of the memory subsystem is in the third range 522C (e.g., 100,000-1,500,000 writes). The third set 526C specifies that a first read level 524A will be used when the current W2R delay time is in the first delay time range of the third set 526C, a second read level 524B will be used when the current W2R delay time is in the second delay time range of the third set 526C, and a third read level 524C will be used when the current W2R delay time is in the third delay time range of the third set 526C.

[0094] Figure 6ATable 600 illustrates an example W2R delay time offset set 606 corresponding to a temperature 602 of a memory subsystem, according to some embodiments. Table 600 maps the temperature range 602 to the W2R delay offset set 606. Table 600 further maps each offset in each set 606 to a read level 604. Table 600 specifies that for a first temperature range (e.g., 0-45°C) 602A, the corresponding first delay offset set 606A includes a first delay offset for a first read level 604A, a second delay offset for a second read level 604B, and a third delay offset for a third read level 604C. The first, second, and third delay offsets in the first set 606A are 0 microseconds, -100 milliseconds, and -2 minutes, respectively.

[0095] Table 600 also specifies that for the second temperature range (e.g., 45°C–70°C) 602B, the corresponding second delay offset set 606B includes a first delay offset for the first read level 604A, a second delay offset for the second read level 604B, and a third delay offset for the third read level 604C. The first, second, and third delay offsets in the second set 606B are 0 microseconds, -300 milliseconds, and -4 minutes, respectively.

[0096] Figure 6B Table 610 illustrates an example W2R delay time offset set 616 corresponding to a stack value 612 of a memory subsystem, according to some embodiments. Table 610 maps the stack value 612 to the W2R delay offset set 616. Table 610 further maps each offset in each set 616 to a read level 614. Table 610 specifies that for a first stack (e.g., stack 0) 612A, the corresponding first delay offset set 616 includes a first delay offset for a first read level 614A, a second delay offset for a second read level 614B, and a third delay offset for a third read level 614C. The first, second, and third delay offsets of the first stack 612A are 0 microseconds, -260 milliseconds, and -2 minutes, respectively.

[0097] Table 610 also specifies that for the second stack (e.g., stack 1) 612B, the corresponding second delay offset set 616 includes a first delay offset for the first read level 614A, a second delay offset for the second read level 614B, and a third delay offset for the third read level 614C. The first, second, and third delay offsets of the second stack 612B are 0 microseconds, -460 milliseconds, and -3 minutes, respectively.

[0098] Figure 6CTable 620 illustrates example writes to a read latency offset set 626 corresponding to an electrical distance 622 of the memory subsystem, according to some embodiments. Table 620 maps the electrical distance 622 to the W2R latency offset set 626. Table 620 further maps each offset in each set 626 to a read level 624. Table 620 specifies that for an electrical distance (e.g., electrical distance 0) 622A, the corresponding first latency offset set 626 includes a first latency offset for a first read level 624A, a second latency offset for a second read level 624B, and a third latency offset for a third read level 624C. The first latency offset, second latency offset, and third latency offset for the electrical distance 622A are 0 microseconds, -325 milliseconds, and -1 minute, respectively.

[0099] Table 620 also specifies that for the second electrical distance (e.g., electrical distance 1) 622B, the corresponding second delay offset set 626 includes a first delay offset of the first read level 624A, a second delay offset of the second read level 624B, and a third delay offset of the third read level 624C. The first delay offset, second delay offset, and third delay offset of the second electrical distance 622B are 0 microseconds, -400 milliseconds, and -2 minutes, respectively.

[0100] Figure 7 An example machine of computer system 700 is shown, wherein an instruction set can be executed to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 700 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations related to...). Figure 1 (The operation corresponding to the read voltage adjustment component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer (or distributed) network machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0101] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch or bridge, or non-digital circuitry, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should also be considered to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0102] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0103] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 communicating via network 720.

[0104] The data storage system 718 may include a machine-readable storage medium 724 (also called a computer-readable medium) on which one or more instruction sets 726 or software embodying any one or more of the methods or functions described herein are stored. The instructions 726 may also reside wholly or at least partially within main memory 704 and / or processing device 702 during execution by computer system 700, the main memory 704 and processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0105] In one embodiment, instruction 726 includes implementing and reading voltage adjustment components (e.g., Figure 1The instructions correspond to the functions of the read voltage adjustment component 113. Although the machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "computer-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0106] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0107] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0108] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions and each coupled to a computer system bus.

[0109] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0110] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0111] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A system comprising: Memory devices; as well as A processing device operatively coupled to the memory device to perform operations including: Determine the first current operating characteristic value of the cell of the memory device; A first operational characteristic threshold is identified from a first operational characteristic threshold set, wherein the first current operational characteristic value satisfies a first operational characteristic threshold criterion based on the first operational characteristic threshold. Identify a set of W2R delay time thresholds corresponding to the first operating characteristic threshold from a set of multiple write-to-read W2R delay time thresholds, wherein each of the W2R delay time thresholds in the set is associated with a corresponding read voltage level; W2R latency thresholds are identified from the set of W2R latency thresholds, and for each W2R latency threshold, the current W2R latency of the cell in the memory device satisfies an associated W2R latency threshold criterion; and Identify the read voltage level associated with the identified W2R delay time threshold.

2. The system according to claim 1, wherein the operation further comprises: A read operation is performed at the cell of the memory device based on the read voltage level associated with the identified W2R delay time threshold.

3. The system according to claim 1, wherein the operation further comprises: The current W2R delay time of the cell of the memory device is determined based on the time difference between a read operation performed on the cell of the memory device and a write operation prior to the read operation.

4. The system of claim 1, wherein each of the operating characteristic thresholds corresponds to a corresponding operating characteristic range having a first endpoint specified by the corresponding operating characteristic threshold.

5. The system of claim 1, wherein each of the W2R delay time thresholds in the set represents an endpoint of a corresponding W2R delay time range, and a corresponding read voltage level associated with each of the W2R delay time thresholds in the set is used to perform a read operation on a cell of the memory device having a W2R delay time within the corresponding W2R delay time range.

6. The system of claim 1, wherein the W2R delay time threshold set is identified using a first mapping table that maps operational characteristic thresholds to the W2R delay time threshold set, wherein the first mapping table maps each operational characteristic threshold to a corresponding W2R delay time threshold set.

7. The system of claim 6, wherein the first mapping table comprises a plurality of records, each record comprising an operational characteristic threshold and a corresponding set of W2R latency thresholds, and wherein identifying the set of W2R latency thresholds corresponding to the first operational characteristic threshold from the plurality of W2R latency threshold sets comprises: Identify records in the first mapping table that include the first operational characteristic threshold, wherein the records further include the identified set of W2R delay time thresholds.

8. The system of claim 6, wherein the first mapping table further maps each W2R delay time threshold in each set of W2R delay time thresholds to a corresponding read voltage level, and the read voltage level associated with the identified W2R delay time threshold is identified using the first mapping table.

9. The system of claim 1, wherein the first current operating characteristic value includes one or more of the following: the write count of the cell of the memory device, the operating temperature, the layer identifier of the cell of the memory device, or the electrical distance of the cell of the memory device.

10. The system according to claim 1, wherein the operation further comprises: Determine the second current operating characteristic value of the cell in the memory device; A second operational characteristic threshold is identified from a second operational characteristic threshold set, wherein the second current operational characteristic value satisfies a second operational characteristic threshold criterion based on the second operational characteristic threshold. Identify a set of W2R delay time offsets corresponding to the second operating characteristic threshold from a set of multiple W2R delay time offsets, wherein each of the W2R delay time offsets in the set is associated with a corresponding read voltage level; as well as The W2R delay time threshold set is updated based on the W2R delay time offset set.

11. The system of claim 10, wherein updating the W2R delay time threshold set based on the W2R delay time offset set comprises: Each W2R delay time offset in the W2R delay time offset set is added to the corresponding W2R delay time threshold in the W2R delay time threshold set.

12. The system of claim 10, wherein the set of W2R delay time offsets corresponding to the second operational characteristic threshold is identified using a second mapping table that maps operational characteristic thresholds to sets of W2R delay time offsets, wherein the second mapping table maps each operational characteristic threshold to a corresponding set of W2R delay time offsets.

13. The system of claim 10, wherein the second current operating characteristic value includes one or more of the following: operating temperature, layer identifier of the cell of the memory device, electrical distance of the cell of the memory device, or write count of the cell of the memory device.

14. A non-transitory computer-readable medium comprising instructions that, when executed by a processing means, cause the processing means to perform operations including: Identify the current cycle count associated with a cell in the memory device; Identify the loop count range containing the current loop count from the set of loop count ranges; A set of W2R delay time ranges corresponding to the cycle count range is identified from a set of multiple write-to-read W2R delay time ranges, each of which represents a plurality of W2R delay times and is associated with a corresponding read voltage level for performing a read operation on a cell of the memory device having a W2R delay time within the W2R delay time range; Identify the W2R delay time of the cell of the memory device, wherein the identified W2R delay time is based on the time difference between a write operation and a read operation performed by the cell of the memory device; Identify the W2R delay time range containing the W2R delay time of the cell of the memory device from the W2R delay time range set; Identify the read voltage level corresponding to the identified W2R delay time range; as well as A read operation is performed at the cell of the memory device based on the identified read voltage level.

15. The non-transitory computer-readable medium of claim 14, wherein the set of W2R delay time ranges is identified using a first mapping table that maps cycle count ranges to the set of W2R delay time ranges, wherein the first mapping table maps each cycle count range to a corresponding set of W2R delay time ranges.

16. The non-transitory computer-readable medium of claim 15, wherein the first mapping table comprises a plurality of records, each record comprising a cycle count range and a corresponding set of W2R delay time ranges, and wherein identifying the set of W2R delay time ranges corresponding to the cycle count range from the plurality of W2R delay time range sets comprises: The first mapping table identifies records that include the range of the current cycle count, wherein the records further include the identified set of W2R delay time ranges.

17. The non-transitory computer-readable medium of claim 15, wherein the first mapping table further maps each W2R delay time range in each W2R delay time range set to a corresponding read voltage level, and the read voltage level associated with the identified W2R delay time range is identified using the first mapping table.

18. The non-transitory computer-readable medium of claim 14, wherein the operation further comprises: Measure the current temperature associated with the memory device; Identify the temperature range that includes the current temperature associated with the memory subsystem from the temperature range set; Identify a set of W2R delay time offsets corresponding to the current temperature associated with the memory subsystem from a set of multiple W2R delay time offsets, wherein each W2R delay time offset in the set of W2R delay time offsets is associated with a corresponding read voltage level; as well as The W2R delay time range set is adjusted based on the identified W2R delay time offset set.

19. The non-transitory computer-readable medium of claim 18, wherein adjusting the W2R delay time range set based on the identified W2R delay time offset set comprises: Each W2R delay time offset in the identified W2R delay time offset set is added to each endpoint of each W2R delay time range in the identified W2R delay time range set.

20. A method comprising: Determine the first current operating characteristic value of a cell in the memory device; A first operational characteristic threshold is identified from a first operational characteristic threshold set, wherein the first current operational characteristic value satisfies a first operational characteristic threshold criterion based on the first operational characteristic threshold. Identify a set of W2R delay time thresholds corresponding to the first operating characteristic threshold from a set of multiple write-to-read W2R delay time thresholds, wherein each of the W2R delay time thresholds in the set is associated with a corresponding read voltage level; W2R latency thresholds are identified from the set of W2R latency thresholds, and for each W2R latency threshold, the current W2R latency of the cell in the memory device satisfies an associated W2R latency threshold criterion; and Identify the read voltage level associated with the identified W2R delay time threshold.

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