Adaptive throughput monitoring

Abstract

This application relates to adaptive throughput monitoring. In some examples, a memory system can be associated with one or more clocks each associated with a respective subcomponent. When the memory system receives a plurality of commands, the memory system can determine a throughput of the commands. Based on the determined throughput, the memory system can adjust a rate of one or more of the clocks.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 396,117, entitled “Adaptive Throughput Monitoring,” filed August 6, 2021, by BASU et al., which is assigned to the assignee and is expressly incorporated herein by reference. Technical Field

[0003] The technical field involves adaptive throughput monitoring. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, user devices, wireless communication devices, cameras, digital displays, and so on. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless they are periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long time, even in the absence of an external power supply. Summary of the Invention

[0006] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may include: storing code comprising instructions that, when executed by a processor of a memory device, cause the memory device to: receive a plurality of commands at a controller of the non-volatile memory device, wherein the non-volatile memory device includes a plurality of clocks, each of the plurality of clocks being associated with a corresponding sub-component of the non-volatile memory device; determine a throughput of the plurality of commands based at least in part on the receipt of the plurality of commands; and adjust the rate of at least one of the plurality of clocks based at least in part on the determination of the throughput of the plurality of commands.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may include: storing code comprising instructions that, when executed by a processor of a memory device, cause the memory device to: receive a command at the memory device while operating in an idle mode, wherein the memory device includes a plurality of clocks, and wherein each of the plurality of clocks is associated with a corresponding sub-component of the memory device; transition the memory device from the idle mode to an analysis mode based at least in part on receiving the command; determine whether one or more characteristics of the plurality of commands received while the memory device is operating in the analysis mode satisfy a threshold; and adjust the rate of at least one of the plurality of clocks based at least in part on the determination that the one or more characteristics of the plurality of commands received while the memory device is operating in the analysis mode satisfy the threshold.

[0008] Describe an apparatus. The apparatus may include: a non-volatile memory device including a plurality of clocks, each of the plurality of clocks being associated with a corresponding sub-component of the non-volatile memory device; and a controller coupled to the non-volatile memory device, the controller being configured to: receive a plurality of commands; determine a throughput of the plurality of commands at least in part based on the receipt of the plurality of commands; and adjust the rate of at least one of the plurality of clocks at least in part based on the determination of the throughput of the plurality of commands. Attached Figure Description

[0009] Figure 1 Examples of systems supporting adaptive throughput monitoring are shown, based on the examples disclosed herein.

[0010] Figure 2 Examples of systems supporting adaptive throughput monitoring are shown, based on the examples disclosed herein.

[0011] Figure 3 Examples of memory systems that support adaptive throughput monitoring are shown, based on the examples disclosed herein.

[0012] Figure 4 An example of a block diagram illustrating support for adaptive throughput monitoring based on the examples disclosed herein is shown.

[0013] Figure 5 A block diagram of a memory system supporting adaptive throughput monitoring, based on an example disclosed herein, is shown.

[0014] Figure 6 and 7 The flowcharts shown below, based on examples disclosed herein, illustrate one or more methods for supporting adaptive throughput monitoring. Detailed Implementation

[0015] Operations on the memory system can be performed using a clock rate set based on the host system's bandwidth. For example, the host system can be configured to set the speed at which it communicates with the memory system. In some cases, the host system may be configured to set its bandwidth requirements at a relatively high speed, which could result in the memory system's clock being set to its maximum rate. However, in other cases, the memory system's clock can be set to its maximum rate even though the actual throughput between the host system and the memory system is low. Because the memory system has a relatively low power budget, it may be necessary to adjust the rate of one or more clocks of the memory system based on the actual throughput between the host system and the memory system.

[0016] This document describes a memory system configured to determine the throughput of commands received from a host system. In some examples, the memory system may include components (e.g., frequency dividers) for setting the operating rates (e.g., frequencies) of individual clocks. For example, the memory system may include a system clock, an interface (e.g., an Open NAND Flash Interface (ONFI)) clock, and a CPU clock, etc. The memory system may receive one or more commands from the host system and may switch to a mode for determining command throughput (e.g., a second mode, an analysis mode). When operating in the second mode, the memory system may set the rate of each clock to its maximum value to predict the host system requiring the maximum bandwidth. When calculating the throughput of the commands, the memory system may adjust the rates of one or more clocks (e.g., adjust the rates downward). Adjusting the clock rates based on the calculated throughput can save power that might otherwise be incurred due to the clocks operating at unnecessarily or undesirably high rates.

[0017] The features of this disclosure are firstly in reference to Figures 1 to 2 The features of this disclosure are described in the context of systems, devices, and circuits. Figure 3 and 4 The memory system and block diagrams described herein. These and other features of this disclosure are further illustrated in the references. Figure 5-7Device diagrams and flowcharts involving adaptive throughput monitoring are shown and described in the context of the device diagrams and flowcharts.

[0018] Figure 1 An example of a system 100 supporting adaptive throughput monitoring is shown, based on the examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0019] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0020] System 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked business device), or any other computing device that includes memory and processing devices.

[0021] System 100 may include a host system 105 that can be coupled to memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a controller or control component configured to cause host system 105 to perform various operations according to instances described herein. Host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, host system 105 may include an application configured to communicate with memory system 110 or devices therein. The processor chipset may include one or more chips, one or more caches (e.g., memory local to host system 105 or included in host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 105 may use memory system 110, for example, to write data to memory system 110 and read data from memory system 110. Although in Figure 1The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0022] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., exchanging or otherwise transmitting control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Double Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Double Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be contained in host system controller 106 of host system 105 and memory system controller 115 of memory system 110 or otherwise supported between them. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110 or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0023] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0024] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130—and other such operations—collectively referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with a command from the host system 105). For example, the memory system controller 115 may translate responses associated with the memory device 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0025] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0026] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations described herein belonging to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry system.

[0027] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory capable of storing operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions belonging to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory available for internal storage or computation by the memory system controller 115, for example, internal storage or computation related to the functions belonging to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may be used as a cache for the memory system controller 115. For example, if data is read from or written to memory device 130, then data may be stored in local memory 120, and the data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 (e.g., with reduced latency relative to memory device 130) according to a caching strategy.

[0028] although Figure 1 An example of memory system 110 has been shown to include memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, which may be located within memory device 130 to perform the functions described herein as belonging to memory system controller 115. Generally, one or more functions described herein as belonging to memory system controller 115 may actually be performed in some cases by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130 that is at least partially managed by memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0029] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0030] In some instances, memory device 130 may include (e.g., on the same die or within the same package) a local controller 135 that can operate on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions belonging to memory system controller 115 herein. For example, as Figure 1 As shown, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0031] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a single piece of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0032] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information. If configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density than SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity in the supporting circuitry.

[0033] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may be performed within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, provided that the different blocks 170 are in different planes 165. In some cases, a single block 170 may be referred to as a physical block, and a virtual block 180 may refer to a group of blocks 170 within which parallel operations can be performed. For example, parallel operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d located respectively in planes 165-a, 165-b, 165-c, and 165-d, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual block 180. In some cases, a virtual block may contain blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory devices 130-a and 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be “block 0” of plane 165-a, block 170-b may be “block 0” of plane 165-b, and so on). In some cases, performing parallel operations in different planes 165 may have one or more restrictions, such as parallel operations being performed on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0034] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may be alternatively referred to as a bit line) (e.g., coupled thereto).

[0035] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., partially parallel programmed or read as a single programming or read operation), and block 170 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., partially parallel erased as a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, used page 175 may not be updated until the entire block 170 containing page 175 is erased.

[0036] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, cleanup, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in block 170 to have invalid data in order to erase and reuse block 170, an algorithm called “garbage collection” may be invoked, causing block 170 to be erased and freed up as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting block 170 containing valid and invalid data, selecting pages 175 in the block containing valid data, copying the valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170), marking the data in the previously selected pages 175 as invalid, and erasing the selected block 170. Therefore, the number of erased blocks 170 can be increased, so that more blocks 170 can be used to store subsequent data (e.g., data subsequently received from the host system 105).

[0037] System 100 may include any number of non-transitory computer-readable media that support adaptive throughput monitoring. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise access one or more non-transitory computer-readable media that store instructions (e.g., firmware) for performing the functions described herein that pertain to host system 105, memory system controller 115, or memory device 130. For example, if such instructions are executed by host system 105 (e.g., host system controller 106), memory system controller 115, or memory device 130 (e.g., local controller 135), they may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions described herein.

[0038] In some cases, memory system 110 may use memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0039] In some instances, memory system 110 may include one or more clocks for various sub-components. For example, memory die 160 may be associated with a system clock, and memory system controller 115 may include a processor (e.g., CPU) associated with a CPU clock and a data path associated with an interface clock. The operating rate of the clock (e.g., the clock frequency) may be set or adjusted by memory system controller 115. For example, memory system 110 may receive one or more commands from host system 105. Upon receiving a command, memory system controller 115 may determine the throughput of the command, which may be calculated using various factors as described herein. Based on the calculated throughput, memory system controller 115 may maintain or adjust (e.g., up or down) the rate of any one or more clocks. Adjusting the clock rate based on the calculated throughput can save power that might otherwise be incurred due to the clock operating at unnecessarily high rates.

[0040] Figure 2 An example of a system 200 supporting adaptive throughput monitoring is shown, based on the examples disclosed herein. System 200 may be a reference. Figure 1 The described system 100 or an example thereof. System 200 may include a memory system 210 configured to store data received from host system 205 and send data to host system 205 when requested by host system 205 using an access command (e.g., a read command or a write command). System 200 may implement reference Figure 1The described aspects of system 100. For example, memory system 210 and host system 205 may be instances of memory system 110 and host system 105, respectively.

[0041] Memory system 210 may include memory device 240 for storing data transferred between memory system 210 and host system 205, for example, in response to receiving an access command from host system 205, as described herein. Memory device 240 may include references. Figure 1 The memory device 240 may include one or more memory devices as described. For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-point memory, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0042] Memory system 210 may include memory controller 230 for controlling the direct transfer of data to and from memory device 240, such as storing data, retrieving data, and determining the memory location from which data is to be stored and retrieved. Memory controller 230 may communicate with memory device 240 directly or via bus 275 (e.g., ONFI bus) using a protocol specific to each type of memory device 240. In some cases, a single memory controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, memory system 210 may include multiple memory controllers 230, such as different memory controllers 230 for each type of memory device 240. In some cases, memory controller 230 may implement a reference... Figure 1 The local controller 135 is described in various aspects.

[0043] The memory system 210 may additionally include an interface 220 for communicating with the host system 205 and a buffer 225 for temporary storage of data transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 can be used to convert data between the host system 205 and the memory device 240, for example, as shown by data path 250, and can be collectively referred to as the data path components.

[0044] Using buffer 225 to temporarily store data during transmission allows data to be buffered as commands are processed, thereby reducing latency between commands and allowing for arbitrary data sizes associated with commands. This also allows for handling command bursts, and buffered data can be stored or transmitted (or both) immediately after the burst ends. Buffer 225 may contain relatively fast memory (e.g., certain types of volatile memory such as SRAM or DRAM) or hardware accelerators or both to allow for fast storage and retrieval of data to and from buffer 225. Buffer 225 may include data path switching components for bidirectional data transfer between buffer 225 and other components.

[0045] Temporary storage of data within buffer 225 can refer to data being stored in buffer 225 during the execution of an access command. That is, after the access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., it can be overwritten with data from an additional access command). Additionally, buffer 225 can be a non-cached buffer. This means that data can be read directly from buffer 225 without the host system 205. For example, a read command can be added to a queue without requiring an address to be matched against an address already in buffer 225 (e.g., no cached address matching or lookup operation is needed).

[0046] The memory system 210 may additionally include a memory system controller 215 for executing commands received from the host system 205 and controlling data path components when moving data. The memory system controller 215 may be a reference... Figure 1 An example of the described memory system controller 115. Bus 235 can be used for data transfer between system components.

[0047] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and storage queue 270) can be used to control the processing of access commands and the movement of corresponding data. This can be advantageous, for example, when more than one access command from host system 205 is processed in parallel by memory system 210. As an example of a possible implementation, command queue 260, buffer queue 265, and storage queue 270 are depicted at interface 220, memory system controller 215, and memory controller 230, respectively. However, if used, the queues can be located anywhere within memory system 210.

[0048] Data transferred between host system 205 and memory device 240 may use a path in memory system 210 different from that of non-data information (e.g., command status information). For example, system components in memory system 210 may communicate with each other using bus 235, while data may use data path 250 via data path components instead of bus 235. Memory system controller 215 may control how and whether data is transferred between host system 205 and memory device 240 by communicating with data path components on bus 235 (e.g., using a protocol specific to memory system 210).

[0049] If host system 205 transmits an access command to memory system 210, the command can be received by interface 220, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). Therefore, interface 220 can be considered the front end of memory system 210. Upon receiving each access command, interface 220 can transmit the command to memory system controller 215, for example, via bus 235. In some cases, each command can be added to command queue 260 via interface 220 to transmit the command to memory system controller 215.

[0050] The memory system controller 215 can determine that an access command has been received based on a transmission from interface 220. In some cases, the memory system controller 215 can determine that the access command has been received by retrieving the command from command queue 260. The command can be removed from command queue 260 after it has been retrieved, for example, through the memory system controller 215. In some cases, the memory system controller 215 can cause interface 220 to remove the command from command queue 260, for example, via bus 235.

[0051] After confirming that an access command has been received, the memory system controller 215 may execute the access command. For a read command, this may refer to obtaining data from the memory device 240 and transferring the data to the host system 205. For a write command, this may refer to receiving data from the host system 205 and moving the data to the memory device 240.

[0052] In either case, the memory system controller 215 may use the buffer 225 to temporarily store data received from or sent to the host system 205, and for other purposes. The buffer 225 may be considered as an intermediate part of the memory system 210. In some cases, buffer address management (e.g., addressing pointers to locations in the buffer 225) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0053] In order to process a write command received from host system 205, memory system controller 215 may first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space within buffer 225 available for storing the data associated with the write command, for example via firmware (e.g., controller firmware).

[0054] In some cases, buffer queue 265 can be used to control the flow of commands associated with data stored in buffer 225, including write commands. Buffer queue 265 may contain access commands associated with data currently stored in buffer 225. In some cases, commands in command queue 260 can be moved to buffer queue 265 via memory system controller 215 and can remain in buffer queue 265 while the associated data is stored in buffer 225. In some cases, each command in buffer queue 265 may be associated with an address at buffer 225. That is, a pointer indicating where the data associated with each command is stored in buffer 225 can be maintained. Using buffer queue 265, multiple access commands can be received sequentially from host system 205, and at least some of the access commands can be processed in parallel.

[0055] If buffer 225 has sufficient space to store the write data, then memory system controller 215 may cause interface 220 to transmit an availability indication (e.g., a "ready to transfer" indication) to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). When interface 220 subsequently receives data associated with the write command from host system 205, interface 220 may transfer the data to buffer 225 for temporary storage using data path 250. In some cases, interface 220 may obtain the location of the stored data within buffer 225 from buffer 225 or buffer queue 265. Interface 220 may indicate to memory system controller 215, for example, via bus 235 whether the data transfer to buffer 225 has been completed.

[0056] Once written data has been stored in buffer 225 via interface 220, the data can be transferred outside buffer 225 and stored in memory device 240. This can be accomplished using memory controller 230. For example, memory system controller 215 can cause memory controller 230 to retrieve data outside buffer 225 using data path 250 and transfer the data to memory device 240. Memory controller 230 can be considered as the back-end of memory system 210. Memory controller 230 can, for example, indicate to memory system controller 215 via bus 235 that data transfer to memory device 240 has been completed.

[0057] In some cases, memory queue 270 can be used to assist in the transfer of write data. For example, memory system controller 215 can (e.g., via bus 235) push write commands from buffer queue 265 to memory queue 270 for processing. Memory queue 270 may contain entries for each access command. In some instances, memory queue 270 may additionally contain: a buffer pointer (e.g., an address) indicating where the data associated with the command is stored in buffer 225; and a memory pointer (e.g., an address) indicating the location in memory device 240 associated with the data. In some cases, memory controller 230 can obtain the location within buffer 225 from which data is obtained, either from buffer 225, buffer queue 265, or memory queue 270. Memory controller 230 can manage the location of stored data within memory device 240 (e.g., perform wear leveling, garbage collection, etc.). Entries can be added to memory queue 270, for example, via memory system controller 215. For example, entries can be removed from memory queue 270 via memory controller 230 or memory system controller 215 after data transfer is complete.

[0058] In order to process a read command received from host system 205, memory system controller 215 may first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space within buffer 225 available for storing the data associated with the read command, for example via firmware (e.g., controller firmware).

[0059] In some cases, buffer queue 265 can be used to assist in buffering data associated with read commands in a manner similar to that discussed above regarding write commands. For example, if buffer 225 has sufficient space to store read data, then memory system controller 215 can instruct memory controller 230 to retrieve the data associated with the read command from memory device 240 and store the data in buffer 225 for temporary storage using data path 250. When data transfer to buffer 225 is complete, memory controller 230 can, for example, indicate this to memory system controller 215 via bus 235.

[0060] In some cases, the storage queue 270 can be used to assist in the transfer of read data. For example, the memory system controller 215 can push a read command to the storage queue 270 for processing. In some cases, the storage controller 230 can obtain the location of the data to be retrieved from the buffer 225 or the storage queue 270 within the memory device 240. In some cases, the storage controller 230 can obtain the location of the data stored in the buffer 225 from the buffer queue 265. In some cases, the storage controller 230 can obtain the location of the data stored in the buffer 225 from the storage queue 270. In some cases, the memory system controller 215 can move a command processed by the storage queue 270 back to the command queue 260.

[0061] Once data has been stored in buffer 225 by storage controller 230, it can be transferred outside buffer 225 and sent to host system 205. For example, storage system controller 215 may enable interface 220 to retrieve data outside buffer 225 using data path 250 and transfer it to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). For example, interface 220 may process commands from command queue 260 and may indicate to storage system controller 215, for example, via bus 235, that data transfer to host system 205 has been completed.

[0062] The memory system controller 215 can execute received commands according to a certain order (e.g., first-in-first-out order, according to the order of command queue 260). For each command, the memory system controller 215 can move the data corresponding to the command into and out of buffer 225, as discussed above. While the data is moved into and stored in buffer 225, the command can remain in buffer queue 265. If the processing of the command has been completed (e.g., if the data corresponding to the access command has been moved out of buffer 225), then the command can be removed from buffer queue 265, for example, by the memory system controller 215. If the command is removed from buffer queue 265, then the address where the data associated with the command was previously stored can be used to store the data associated with the new command.

[0063] The memory system controller 215 may be additionally configured for operations associated with the memory device 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling, garbage collection, error control operations such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue commands indicating one or more LBAs, and the memory system controller 215 may recognize one or more physical block addresses indicated by the LBAs. In some cases, one or more consecutive LBAs may correspond to non-consecutive physical block addresses. In some cases, the memory controller 230 may be configured to perform one or more of the above operations in conjunction with or instead of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the memory controller 230, and the memory controller 230 may be omitted.

[0064] In some instances, system 200 may include one or more clocks for various sub-components. For example, the memory die of memory device 240 may be associated with an interface clock, memory system controller 215 may include a processor (e.g., CPU) associated with a CPU clock, and data paths (e.g., including interface 220, buffer 225, and memory controller 230) may be associated with a system clock. The operating rate of the clock (e.g., the clock frequency) may be set or adjusted by memory system controller 215. For example, system 200 may receive one or more commands from host system 205. Upon receiving a command, memory system controller 215 may determine the throughput of the command, which may be calculated using various factors as described herein. Based on the calculated throughput, memory system controller 215 may maintain or adjust (e.g., up or down) the rate of any one or more clocks. Adjusting the clock rate based on the calculated throughput can save power that might otherwise be incurred due to the clock operating at unnecessarily high rates.

[0065] Figure 3 An example of a memory system 300 supporting adaptive throughput monitoring is shown, according to the examples disclosed herein. The memory system 300 may include a controller 305 (e.g., a memory controller 305), a processor 310 (e.g., a CPU 310), and one or more memory dies 315. The controller 305 and memory dies 315 may be coupled to a bus 320, which may be an example of an ONFI bus 320. The processor 310 may be included in or associated with the firmware layer of the controller 305. Furthermore, the controller 305 and memory dies 315 may be references... Figure 2Examples of the memory system controller 215 and memory device 240 described herein.

[0066] Alternatively, controller 305 may include queue 325, accelerator 335, system clock divider 340, interface clock divider 345, and CPU clock divider 350. As described herein, accelerator 335 may be configured to determine the throughput associated with commands received from the host device. Based on the determined throughput, system clock divider 340, interface clock divider 345, and CPU clock divider 350 may be configured to adjust the rate (e.g., clock rate) of the corresponding clock of memory system 300. Adjusting the rate of the corresponding clock based on the throughput of received commands can save power in the memory system 300 that would otherwise be incurred due to the clock operating at unnecessarily high rates, and has other benefits.

[0067] In some instances, the memory system 300 may be connected to a host system (e.g., reference...). Figure 2 The host system 205 is coupled to the memory system 300. The host system can transmit commands (e.g., access commands) to the memory system 300, which can be received by an interface (not shown). See reference... Figure 2 As described, commands can be received by the interface according to a protocol (e.g., UFS protocol or eMMC protocol). In some cases, each received command can be added to command queue 325 via the interface, and the command can be transmitted to accelerator 335 for determining the throughput of the command.

[0068] The host system can be configured to set specific bandwidth requirements. For example, the host system can be configured to set the speed at which it communicates with the memory system 300. In some examples, the host system can be configured to set its bandwidth requirements at different levels (e.g., speeds) within the range of G1 to G4. When operating at G4, the host system can have relatively high bandwidth requirements and therefore can communicate with the memory system 300 at a relatively high rate. Alternatively, when operating at G1, the host system can have relatively low bandwidth requirements and therefore can communicate with the memory system 300 at a relatively low rate. As described herein, even if the host system sets bandwidth requirements, the accelerator 335 can adjust the rate of one or more clock cycles based on the throughput of received commands, which can reduce the overall power consumption of the memory system 300.

[0069] In some examples, when operating in an analysis mode (e.g., a second mode), accelerator 335 can determine the throughput of received commands. Memory system 300 can operate in different modes (e.g., different states) based on whether queue 325 contains any commands. For example, memory system 300 can operate in analysis mode, low-power mode, idle mode (e.g., a first mode), or another mode (e.g., a third mode). When queue 325 is empty, memory system 300 can enter idle mode, and when queue 325 contains one or more commands, memory system 300 can transition to analysis mode. In some instances, memory system 300 can transition from any other mode (e.g., from low-power mode, idle mode, etc.) to analysis mode. When operating in analysis mode, accelerator 335 may not have sufficient information to adjust memory system 300 (or a specific clock of memory system 300) to a specific power distribution. Therefore, memory system 300 can operate in analysis mode until accelerator 335 is able to make a decision regarding the power distribution.

[0070] When operating in analysis mode, accelerator 335 can calculate the throughput of commands received from the host system. As used herein, determining the “throughput” of received commands may refer to determining the number of commands received during a duration, determining the type of one or more of the received commands, determining the amount of data associated with one or more of the received commands, determining the depth of queue 325, determining the address of one or more of the received commands, or a combination thereof.

[0071] For example, accelerator 335 can determine the throughput of received commands by determining the number of commands received during a given period. For example, accelerator 335 (or another component of controller 305) can initiate a timer after switching to analysis mode. Accelerator 335 can then determine the number of commands received before the timer expires. Based on the throughput (e.g., the number of commands), accelerator 335 can adjust the rate of one or more clocks of memory system 300.

[0072] Alternatively, the accelerator can determine the throughput of received commands by identifying the type of one or more of the received commands. For example, the accelerator 335 can adjust the rate of one or more clocks of the memory system 300 based on whether the command is a read command, a write command, a random read command, a random write command, or a mixed workload.

[0073] Alternatively, the accelerator can determine the throughput of the received commands by determining the amount of data associated with one or more of the received commands. For example, the accelerator can determine the amount of data associated with each received command and can adjust the rate of one or more clocks of the memory system 300 based on the amount of data.

[0074] Alternatively, the accelerator can determine the throughput of received commands by determining the number of commands in queue 325. For example, the accelerator can determine the number of commands in queue 325 and adjust the rate of one or more clocks of memory system 300 based on the number of commands.

[0075] Alternatively, the accelerator can determine the throughput of received commands by determining the addresses of one or more received commands. For example, the accelerator can determine that an address is associated with a specific processor or a specific memory die 315, and can adjust the rate of one or more clocks of the memory system 300 based on the address.

[0076] In some examples, memory system 300 may include different clocks associated with corresponding sub-components of memory system 300. In some instances, controller 305 (or another component) may include an oscillator (e.g., a voltage-controlled oscillator (VCO) or a phase-locked loop (PLL)) to generate the clock for memory system 300, or memory system 300 may receive a clock from a host. Controller 305 may include corresponding frequency dividers that set different frequencies for sub-components. For example, controller 305 may include a system clock divider 340 configured to set the frequency (e.g., rate) of the data path to memory die 315 within memory system 300. Controller 305 may also include an interface clock divider 345 configured to set the frequency (e.g., rate) of bus 320 and a CPU clock divider 350 configured to set the frequency (e.g., rate) of processor 310, which manages commands in queue 325. Although Figure 3 A memory system 300 containing three (3) clock dividers is shown, but the memory system 300 may contain any number of clock dividers associated with the clocks of the respective sub-components.

[0077] To set or adjust the clock rate of the memory system 300, the accelerator 335 may communicate with a corresponding clock divider. Alternatively, the accelerator 335 may store or access tables, such as Table 1 reproduced below. The table may contain categories of commands associated with indexed clock rate ranges. For example, after receiving multiple commands, the accelerator 335 may categorize the commands into one or more categories, as shown below.

[0078]

[0079]

[0080] Table 1

[0081] For example, after receiving multiple commands, the memory system 300 can switch to analysis mode. When operating in analysis mode, the system clock divider 340, interface clock divider 345, and CPU clock divider 350 can set their respective clocks to maximum rates, as shown in Table 1 (e.g., 500, 800, and 400, respectively). The accelerator 335 can then classify the commands into one or more categories, such as read, write, random read, random write, etc., as shown in Table 1. The accelerator 335 can then calculate the throughput using one of the criteria described herein (e.g., the number of commands received during a duration, the type of one or more of the received commands, etc.).

[0082] Based on the category of the received command and the calculated throughput, accelerator 335 can (e.g., from an indexed range) select an index corresponding to the rate of each clock. For example, the received command can be classified as a random read, and the throughput of the command (e.g., a random read) can be calculated. Using this example, system clock divider 340, interface clock divider 345, and CPU clock divider 350 can set the corresponding clocks to 500, 600, and 200 or 300, 400, and 200 based on the calculated throughput. In some examples, the received command may belong to more than one category. Therefore, in such examples, accelerator 335 can select an index (for each corresponding clock) from more than one category corresponding to the highest rate of the clock.

[0083] Alternatively, each clock may be associated with an indexed frequency range (e.g., an indexed clock rate range). Each indexed frequency range may contain the same number of clock frequencies, but at least one clock (or each clock) in one or more categories may be selected with a different index. Thus, the system clock divider 340, the interface clock divider 345, and the CPU clock divider 350 may be set to their respective frequencies based on the calculated throughput.

[0084] In some instances, the clock rate can also be adjusted based on the number of maintenance operations to be performed on the memory system 300. For example, when the memory system 300 is idle (e.g., operating in an idle mode, i.e., a first mode), the memory controller 305 can determine the number of garbage collection operations to be performed on the memory die 315. Depending on the number, the rate of one or more clocks can be adjusted (e.g., increased or decreased). For example, if the number of garbage collection operations to be performed is relatively low, the rate of one or more clocks can be maintained or decreased (e.g., decreased). Conversely, if the number of garbage collection operations to be performed is relatively large, the rate of one or more clocks can be increased (e.g., increased), which increases the bandwidth of the memory system 300. Therefore, by adjusting the rate of one or more clocks of the memory system 300 based on the throughput of received commands or garbage collection operations, the memory system 300 can save power that would otherwise be incurred due to the clock operating at unnecessarily high rates, and there are other benefits.

[0085] Figure 4 An example of block diagram 400 supporting adaptive throughput monitoring is shown, based on the examples disclosed herein. Block diagram 400 may illustrate a memory system (e.g., reference 1). Figure 3 The memory system 300 described has different operating modes. For example, block diagram 400 may show idle mode 405, analysis mode 410, other modes 415, and low-power mode 420. Furthermore, block diagram 400 may show transitions between different modes. Based on the associated operating mode of the memory system, the rate of the corresponding clock can be adjusted based on the throughput of received commands, which allows the memory system to save power that would otherwise be incurred due to the clock operating at unnecessarily high rates.

[0086] In some instances, the memory system may operate in idle mode 405. The memory system may operate based on the absence of data from the host system (e.g., reference 405) for a given period of time. Figure 2 The described host system 205 receives commands and operates in idle mode 405. In other words, when the queue (e.g., refer to...) Figure 2 When the described queue 325 is empty (e.g., when its depth is equal to zero (0)), the memory system can operate in idle mode 405.

[0087] At 425, the memory system can transition from idle mode 405 to analytical mode. The memory system can transition based on receiving one or more commands from the host system. In some examples, the transition at 425 can be based on a single command being stored in a queue of the memory system (e.g., when the queue depth is greater than zero (0)).

[0088] When operating in analysis mode 410, the memory system (e.g., reference) Figure 3 The accelerator 335 of the described memory system 300 may not have enough information to adjust the rate of all clocks. Therefore, the memory system may operate in analysis mode 410 until the accelerator can make a decision about what rate to set a particular clock. As described herein, when in analysis mode 410, the accelerator may determine the throughput of received commands. When determining the throughput of received commands, if it is predicted that ensuring power distribution will require high bandwidth, the clock rate of the memory system may be set to a relatively high (or maximum) rate. In some examples, the accelerator may calculate the throughput of received commands over an interval (e.g., a duration), which may be configurable. After determining the throughput of received commands, the accelerator may adjust the rate of one or more clocks, and the memory system may switch to another mode (e.g., shown as another mode 415).

[0089] At 430, the memory system can transition from analysis mode 410 to another mode (e.g., shown as other mode 415). The other mode 415 may correspond to one or more of the categories shown in Table 1. Therefore, transitioning to the other mode 415 effectively sets the clock rate of the corresponding clock. In some examples, the command mode can be categorized into more than one category. Therefore, in such instances, each clock from any of more than one category can be set at the highest rate. Alternatively, the rate of at least one clock can be set according to a category (e.g., a single category), and the rates of other clocks with higher rates in another category categorized by the command mode can be increased accordingly.

[0090] When operating in the other mode 415, the memory system can process commands received from the host system, and its clock rate can be maintained at a rate set by the category associated with the other mode 415. In some examples, the memory system can continue to operate in this mode until it transitions to idle mode 405 or returns to analysis mode 410. For example, at 435, the memory system can transition to idle mode 405 based on an empty queue.

[0091] Alternatively, at 440, the memory system can switch to an analysis mode based on different patterns of received commands. For example, the accelerator can set one or more clock rates based on the receipt of multiple read commands. However, after switching from analysis mode 410, the memory system can receive multiple write commands. Therefore, the memory system can continue to analyze the received commands in other modes 415. If the clock category changes, the memory system can switch directly from one category to another, and thus the accelerator can adjust the clock rate.

[0092] Alternatively, the memory system may operate in low-power mode 420. The memory system may operate in low-power mode 420 based on commands received from the host system (e.g., hibernation commands, sleep commands, etc.). Therefore, when operating in low-power mode 420, the memory system may receive relatively few commands or no commands from the host system for a given duration. At 445, the memory system may transition from low-power mode 420 to analysis mode 410. The memory system may transition based on receiving one or more commands from the host system. In some examples, the transition at 445 may be based on a single command being stored in a queue of the memory system (e.g., when the queue depth is greater than zero (0)).

[0093] Therefore, refer to Figure 4 The described modes can be used in conjunction with adjusting the rate of one or more clocks of the memory system based on the throughput of the received commands. Therefore, the memory system can save power that would otherwise be incurred due to unnecessarily high clock speeds, among other benefits.

[0094] Figure 5 A block diagram 500 illustrates a memory system 520 supporting adaptive throughput monitoring according to an example disclosed herein. The memory system 520 may be a reference... Figures 1 to 4 Examples of aspects of the described memory system. Memory system 520 or its various components may be examples of constructs for performing the various aspects of adaptive throughput monitoring described herein. For example, memory system 520 may include receiving component 525, determining component 530, rate adjustment component 535, mode switching component 540, mode operation component 545, index selection component 550, throughput calculation component 555, classification component 560, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0095] The receiving component 525 may be configured or otherwise support means for receiving a plurality of commands at a controller of a non-volatile memory device, wherein the non-volatile memory device includes a plurality of clocks, each of which is associated with a corresponding sub-component of the non-volatile memory device. In some instances, the receiving component 525 may be configured or otherwise support means for receiving commands at the memory device when the memory device is operating in an idle mode, wherein the memory device includes a plurality of clocks, and each of which is associated with a corresponding sub-component of the memory device.

[0096] In some instances, receiving component 525 may be configured or otherwise supported for receiving the plurality of commands when the memory device is operating in analysis mode.

[0097] The determining component 530 may be configured or otherwise supported to support means for determining the throughput of the plurality of commands, at least in part, based on the receipt of the plurality of commands. In some instances, the determining component 530 may be configured or otherwise supported to support means for determining the number of maintenance operations to be performed on the non-volatile memory device when the non-volatile memory device is operating in a first mode. In some instances, to support the determination of the throughput of the plurality of commands, the determining component 530 may be configured or otherwise supported to support means for determining, at least in part, that a subset of the plurality of commands is associated with a first category and a second category of the one or more categories, based on the classification of the plurality of commands.

[0098] In some instances, determining component 530 may be configured or otherwise supported to support means for determining whether one or more characteristics of a plurality of commands received while the memory device is operating in analysis mode satisfy a threshold. In some instances, determining component 530 may be configured or otherwise supported to support means for determining that a first subset of the plurality of received commands satisfies the threshold. In some instances, determining component 530 may be configured or otherwise supported to support means for determining that a second subset of the plurality of received commands satisfies a second threshold.

[0099] The rate adjustment component 535 may be configured or otherwise support means for adjusting the rate of at least one of the plurality of clocks at least partially based on determining the throughput of the plurality of commands. In some instances, the rate adjustment component 535 may be configured or otherwise support means for adjusting the rate of each of the plurality of clocks to a first rate at least partially based on a transition from a first mode to a second mode. In some instances, the rate adjustment component 535 may be configured or otherwise support means for adjusting the rate of at least one of the plurality of clocks to a second rate lower than the first rate at least partially based on determining the throughput of the plurality of commands.

[0100] In some instances, the rate adjustment component 535 may be configured or otherwise supported to adjust the rate of at least one of the plurality of clocks at least in part based on determining the number of maintenance operations to be performed on the non-volatile memory device. In some instances, the rate adjustment component 535 may be configured or otherwise supported to adjust the rate of at least one of the plurality of clocks at least in part based on determining that one or more characteristics of the plurality of commands received while the memory device is operating in analysis mode satisfy the threshold.

[0101] In some instances, when the memory device is operating in analysis mode, the rate of each of the plurality of clocks is set to a first rate, and the rate adjustment component 535 may be configured or otherwise support components for adjusting the rate of at least one of the plurality of clocks to a second rate lower than the first rate, based at least in part on determining that one or more characteristics of the plurality of commands received while the memory device is operating in analysis mode satisfy the threshold. In some instances, the rate adjustment component 535 may be configured or otherwise support components for adjusting the rate of at least one of the plurality of clocks to a third rate, based at least in part on determining that a first subset of the plurality of received commands satisfies the threshold and that a second subset of the plurality of received commands satisfies a second threshold, wherein the threshold is associated with the third rate and the second threshold is associated with a fourth rate lower than the third rate.

[0102] In some instances, mode switching component 540 may be configured or otherwise support means for switching a non-volatile memory device from a first mode to a second mode, at least in part based on receiving at least one of the plurality of commands. Mode switching component 540 may be configured or otherwise support means for switching a memory device from an idle mode to an analysis mode, at least in part based on receiving a command.

[0103] In some instances, when the memory device is operating in analysis mode, the rate of each of the plurality of clocks is set to a first rate, and the mode transition component 540 may be configured or otherwise supported to transition the memory device from analysis mode to a mode different from idle mode based at least in part on adjusting the rate of at least one of the plurality of clocks to a second rate.

[0104] In some instances, the mode operation component 545 may be configured or otherwise support means for operating the non-volatile memory device in a first mode prior to receiving the plurality of commands. In some instances, the mode operation component 545 may be configured or otherwise support means for operating the non-volatile memory device in a third mode after adjusting the rate of at least one of the plurality of clocks to a second rate.

[0105] In some instances, to support adjusting the rate of at least one of the plurality of clocks, the index selection component 550 may be configured or otherwise support a means for selecting a first index corresponding to a third rate from a first indexing range for a first clock. In some instances, to support adjusting the rate of at least one of the plurality of clocks, the index selection component 550 may be configured or otherwise support a means for selecting a second index corresponding to a fourth rate from a second indexing range for a second clock. In some instances, to support adjusting the rate of at least one of the plurality of clocks, the index selection component 550 may be configured or otherwise support a means for selecting a third index corresponding to a fifth rate from a third indexing range for a third clock.

[0106] In some instances, to support the determination of the throughput of the plurality of commands, the index selection component 550 may be configured or otherwise support the following: for a given clock among the plurality of clocks, selecting an index corresponding to the highest rate of the respective clock from a fourth index associated with a first category and a fifth index associated with a second category.

[0107] In some instances, the throughput calculation component 555 may be configured or otherwise support means for calculating the throughput of the plurality of received commands based at least in part on the one or more characteristics, wherein the rate of adjustment of at least one of the plurality of clocks is based at least in part on the calculated throughput.

[0108] In some instances, to support the determination of the throughput of the plurality of commands, the classification component 560 may be configured or otherwise supported to include means for classifying the plurality of commands into one or more categories based at least in part on characteristics associated with each of the plurality of commands, wherein each of the one or more categories is associated with a corresponding index in a first index range, a second index range, or a third index range.

[0109] In some instances, a first clock of the plurality of clocks is associated with a data path of the non-volatile memory device, a second clock of the plurality of clocks is associated with a processor of the non-volatile memory device, and a third clock of the plurality of clocks is associated with a data bus coupled to the non-volatile memory device. In some instances, determining the throughput of the plurality of commands includes determining the number of commands received during a duration, determining the type of one or more of the received commands, determining the amount of data associated with one or more of the received commands, determining the depth of a queue containing one or more of the received commands, determining the address of one or more of the received commands, or a combination thereof.

[0110] In some instances, the one or more characteristics include the number of commands received during a duration, the type of one or more of the received commands, the amount of data associated with one or more of the received commands, the depth of the queue containing one or more of the received commands, the address of one or more of the received commands, or a combination thereof. In some instances, a first clock of the plurality of clocks is associated with a data path of the memory device, a second clock of the plurality of clocks is associated with a processor of the memory device, and a third clock of the plurality of clocks is associated with a data bus coupled to the memory device.

[0111] Figure 6 A flowchart illustrating an example disclosed herein demonstrates a method 600 supporting adaptive throughput monitoring. Operation of method 600 may be implemented by the memory system or its components described herein. For example, operation of method 600 may be provided by reference to... Figures 1 to 5 The described memory system performs the function. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the function. Alternatively, the memory system may use dedicated hardware to perform aspects of the function.

[0112] At 605, the method may include receiving multiple commands at a controller of the non-volatile memory device, wherein the non-volatile memory device includes multiple clocks, each of which is associated with a corresponding sub-component of the non-volatile memory device. Operation 605 may be performed according to the examples disclosed herein. In some examples, aspects of operation 605 may be referenced from... Figure 5 The described receiving component 525 is executed.

[0113] At 610, the method may include determining the throughput of the plurality of commands, at least in part, based on the receipt of the plurality of commands. Operation 610 may be performed according to the examples disclosed herein. In some instances, aspects of operation 610 may be derived from references... Figure 5 The described determination component 530 is executed.

[0114] At 615, the method may include adjusting the rate of at least one of the plurality of clocks based at least in part on determining the throughput of the plurality of commands. Operation 615 may be performed according to the examples disclosed herein. In some instances, aspects of operation 615 may be derived from references... Figure 5 The described rate adjustment component 535 is executed.

[0115] In some instances, the device described herein may perform one or more methods, such as method 600. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a plurality of commands at a controller of a non-volatile memory device, wherein the non-volatile memory device includes a plurality of clocks, each of which is associated with a corresponding sub-component of the non-volatile memory device; determining the throughput of the plurality of commands based at least in part on the receipt of the plurality of commands; and adjusting the rate of at least one of the plurality of clocks based at least in part on the determination of the throughput of the plurality of commands.

[0116] Method 600 and some examples of the device described herein may further include operations, features, circuitry, logic, components, or instructions for: operating the non-volatile memory device in a first mode prior to receiving the plurality of commands; switching the non-volatile memory device from the first mode to a second mode based at least in part on receiving at least one of the plurality of commands; and adjusting the rate of each of the plurality of clocks to a first rate based at least in part on the switch from the first mode to the second mode.

[0117] In some instances of method 600 and the apparatus described herein, the method, apparatus, and non-transitory computer-readable medium may further include operations, features, circuit systems, logic, components, or instructions for adjusting the rate of at least one of the plurality of clocks to a second rate that may be lower than a first rate, at least in part based on determining the throughput of the plurality of commands.

[0118] Method 600 and some examples of the device described herein may further include operations, features, circuitry, logic, components, or instructions for operating the non-volatile memory device in a third mode after adjusting the rate of at least one of the plurality of clocks to a second rate.

[0119] Method 600 and some examples of the device described herein may further include operations, features, circuitry, logic, components, or instructions for: determining the number of maintenance operations to be performed on the non-volatile memory device when the non-volatile memory device is operable in a first mode, and adjusting the rate of at least one of the plurality of clocks based at least in part on the determined number of maintenance operations to be performed on the non-volatile memory device.

[0120] In some instances of method 600 and the apparatus described herein, adjusting the rate of at least one of the plurality of clocks may include operations, features, circuitry, logic, components, or instructions for: selecting a first index corresponding to a third rate from a first indexing range for a first clock; selecting a second index corresponding to a fourth rate from a second indexing range for a second clock; and selecting a third index corresponding to a fifth rate from a third indexing range for a third clock.

[0121] In some instances of method 600 and the device described herein, determining the throughput of the plurality of commands may include operations, features, circuitry, logic, components, or instructions that classify the plurality of commands into one or more categories, at least in part based on characteristics associated with each of the plurality of commands, wherein the one or more categories may each be associated with a corresponding index in a first index range, a second index range, or a third index range.

[0122] In some instances of method 600 and the device described herein, determining the throughput of the plurality of commands may include operations, features, circuitry, logic, components, or instructions for: determining, at least in part, based on classifying the plurality of commands, that a subset of the plurality of commands may be associated with a first category and a second category of the one or more categories; and, for a given clock among the plurality of clocks, selecting an index corresponding to the highest rate of the respective clock from a fourth index associated with the first category and a fifth index associated with the second category.

[0123] In some instances of method 600 and the device described herein, a first clock of the plurality of clocks may be associated with a data path of the non-volatile memory device, a second clock of the plurality of clocks may be associated with a processor of the non-volatile memory device, and a third clock of the plurality of clocks may be associated with a data bus coupled to the non-volatile memory device.

[0124] Method 600 and some examples of the device described herein may further include operations, features, circuitry, logic, components, or instructions for determining the throughput of the plurality of commands, including determining the number of the plurality of commands received during a duration, determining the type of one or more of the plurality of commands received, determining the amount of data associated with one or more of the plurality of commands received, determining the depth of a queue containing one or more of the plurality of commands received, determining the address of one or more of the plurality of commands received, or a combination thereof.

[0125] Figure 7A flowchart illustrating an example disclosed herein demonstrates a method 700 supporting adaptive throughput monitoring. The operation of method 700 can be implemented by the memory system or its components described herein. For example, the operation of method 700 can be provided by reference to... Figures 1 to 5 The described memory system performs the function. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the function. Alternatively, the memory system may use dedicated hardware to perform aspects of the function.

[0126] At 705, the method may include receiving a command at the memory device when the memory device is operating in an idle mode, wherein the memory device includes a plurality of clocks, and each of said plurality of clocks is associated with a corresponding sub-component of the memory device. Operation 705 may be performed according to the examples disclosed herein. In some examples, aspects of operation 705 may be referenced from... Figure 5 The described receiving component 525 is executed.

[0127] At 710, the method may include at least in part switching the memory device from an idle mode to a profiling mode based on a received command. Operation 710 may be performed according to the examples disclosed herein. In some instances, aspects of operation 710 may be derived from references... Figure 5 The described mode-shifting component 540 is executed.

[0128] At 715, the method may include determining whether one or more characteristics of a plurality of commands received while the memory device is operating in analysis mode satisfy a threshold. Operation 715 may be performed according to the examples disclosed herein. In some instances, aspects of operation 715 may be referenced... Figure 5 The described determination component 530 is executed.

[0129] At 720, the method may include adjusting the rate of at least one of the plurality of clocks based at least in part on determining that one or more characteristics of the plurality of commands received while the memory device is operating in analysis mode satisfy the threshold. Operation 720 may be performed according to the examples disclosed herein. In some instances, aspects of operation 720 may be referenced from... Figure 5 The described rate adjustment component 535 is executed.

[0130] In some instances, the device described herein may perform one or more methods, such as method 700. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a command at the memory device while the memory device is operating in an idle mode, wherein the memory device includes a plurality of clocks, and each of said plurality of clocks is associated with a corresponding sub-component of the memory device; transitioning the memory device from an idle mode to an analysis mode based at least in part on the received command; determining whether one or more characteristics of the plurality of commands received while the memory device is operating in analysis mode satisfy a threshold; and adjusting the rate of at least one of the plurality of clocks based at least in part on the determination that said one or more characteristics of said plurality of commands received while the memory device is operating in analysis mode satisfy said threshold.

[0131] Method 700 and some examples of the device described herein may further include operations, features, circuitry, logic, components, or instructions for receiving the plurality of commands when the memory device is operable in an analysis mode, and calculating the throughput of the plurality of received commands based at least in part on one or more of the features, wherein adjusting the rate of at least one of the plurality of clocks may be based at least in part on the calculated throughput.

[0132] In some instances of method 700 and the device described herein, the one or more characteristics include the number of the plurality of commands received during a duration, the type of one or more of the plurality of received commands, the amount of data associated with one or more of the plurality of received commands, the depth of the queue containing one or more of the plurality of received commands, the address of one or more of the plurality of received commands, or a combination thereof.

[0133] In some instances of method 700 and the apparatus described herein, the rate of each of the plurality of clocks may be set to a first rate when the memory device is operable in an analysis mode, and the method, apparatus, and non-transitory computer-readable medium may include other operations, features, circuitry, logic, components, or instructions for: adjusting the rate of at least one of the plurality of clocks to a second rate that may be lower than the first rate, based at least in part on determining that one or more characteristics of the plurality of commands received when the memory device is operable in an analysis mode satisfy the threshold; and transitioning the memory device from the analysis mode to a mode different from the idle mode, based at least in part on adjusting the rate of at least one of the plurality of clocks to the second rate.

[0134] Method 700 and some examples of the device described herein may further include operations, features, circuitry, logic, components, or instructions for: determining that a first subset of the plurality of received commands satisfies the threshold, determining that a second subset of the plurality of received commands satisfies the second threshold, and adjusting the rate of at least one of the plurality of clocks to a third rate, at least in part based on determining that the first subset of the plurality of received commands satisfies the threshold and determining that the second subset of the plurality of received commands satisfies the second threshold, wherein the threshold may be associated with the third rate and the second threshold may be associated with a fourth rate that may be lower than the third rate.

[0135] In some instances of method 700 and the device described herein, a first clock of the plurality of clocks may be associated with a data path of the memory device, a second clock of the plurality of clocks may be associated with a processor of the memory device, and a third clock of the plurality of clocks may be associated with a data bus coupled to the memory device.

[0136] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods may be combined.

[0137] Describe an apparatus. The apparatus may include: a non-volatile memory device including a plurality of clocks, each of the plurality of clocks being associated with a corresponding sub-component of the non-volatile memory device; and a controller coupled to the non-volatile memory device, the controller being configured to: receive a plurality of commands; determine a throughput of the plurality of commands at least in part based on the receipt of the plurality of commands; and adjust the rate of at least one of the plurality of clocks at least in part based on the determination of the throughput of the plurality of commands.

[0138] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may show a signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0139] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that supports the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0140] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. If, for example, one component of a controller couples other components together, then that component triggers a change that allows signals to flow through conductive paths between those other components, paths that were previously not permitted to allow signal flow.

[0141] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, they are isolated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. If a controller isolates two components, the controller achieves the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0142] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, these terms are used interchangeably if they describe the connection between conditional actions, conditional processes, or process parts.

[0143] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a prior condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the occurrence of the prior condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0144] Additionally, the terms "directly in response to" or "directly in response to" can refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) be performed "directly in response to" or "directly in response to" such other condition or action.

[0145] The devices containing memory arrays discussed herein can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals containing (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0146] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. Terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "off" or "deactivated."

[0147] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "advantageous" over other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0148] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral to differentiate them. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0149] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions can be stored as one or more instructions or codes on or transmitted over a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that different parts of the functions are implemented in different physical locations.

[0150] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components or any combination thereof. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0151] As used herein (included in the claims), the word "or" in a list of items (e.g., a list of items ending with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a set of closing conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0152] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. For example, and without limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0153] The description provided herein enables those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, the invention is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A non-transitory computer-readable medium storing code, the code comprising instructions that, when executed by a processing circuitry system of a memory system, cause the memory system to: When the memory system is operated in the first mode, at least one of a plurality of received commands is stored in a queue, wherein the memory system includes a plurality of clocks, each of which is associated with a corresponding sub-component of the memory system. The memory system is switched from operating in the first mode to a second mode to determine the throughput of the plurality of received commands, at least in part, based on storing at least one of the plurality of received commands in the queue. When operating in the second mode, the rate of at least one of the plurality of clocks is adjusted to the maximum rate; When operating in the second mode, the throughput of the plurality of received commands is determined at least in part based on the plurality of received commands; as well as Based at least in part on the determined throughput of the plurality of received commands, the rate of at least one of the plurality of clocks is adjusted to a second rate lower than the maximum rate.

2. The non-transitory computer-readable medium of claim 1, wherein the instructions, when executed by the processing circuitry of the memory system, further cause the memory system to: After adjusting the rate of at least one of the plurality of clocks to the second rate, the memory system is operated in the third mode.

3. The non-transitory computer-readable medium of claim 1, wherein the instructions, when executed by the processing circuitry of the memory system, further cause the memory system to: Determine the number of maintenance operations to be performed on the memory system when it is operating in the first mode; and The rate of at least one of the plurality of clocks is adjusted, at least in part, based on the number of maintenance operations to be performed on the memory system.

4. The non-transitory computer-readable medium of claim 1, wherein, in order to adjust the rate of at least one of the plurality of clocks, the instruction, when executed by the processing circuitry of the memory system, further causes the memory system to: For the first clock, select the first index corresponding to the third rate from the first index range; For the second clock, select the second index corresponding to the fourth rate from the second index range; and For the third clock, select the third index corresponding to the fifth rate from the third index range.

5. The non-transitory computer-readable medium of claim 4, wherein, in order to determine the throughput of the plurality of commands, the instructions, when executed by the processing circuitry of the memory system, further cause the memory system to: The received commands are classified into one or more categories, at least in part, based on characteristics associated with each of the plurality of received commands, wherein each of the one or more categories is associated with a corresponding index in the first index range, the second index range, or the third index range.

6. The non-transitory computer-readable medium of claim 5, wherein, in order to determine the throughput of the plurality of commands, the instructions, when executed by the processing circuitry of the memory system, further cause the memory system to: At least in part, based on classifying the plurality of received commands, a subset of the plurality of received commands is determined to be associated with a first category and a second category of the one or more categories; and For a given clock among the plurality of clocks, the index corresponding to the highest rate of the given clock is selected from the fourth index associated with the first category and the fifth index associated with the second category.

7. The non-transitory computer-readable medium of claim 1, wherein a first clock of the plurality of clocks is associated with a data path of the memory system, a second clock of the plurality of clocks is associated with the processing circuitry of the memory system, and a third clock of the plurality of clocks is associated with a data bus coupled to the memory system.

8. The non-transitory computer-readable medium of claim 1, wherein determining the throughput of the plurality of received commands includes determining the number of the plurality of received commands received during a duration, determining the type of one or more of the plurality of received commands, determining the amount of data associated with one or more of the plurality of received commands, determining the depth of a queue containing one or more of the plurality of received commands, determining the address of one or more of the plurality of received commands, or a combination thereof.

9. A non-transitory computer-readable medium storing code, the code comprising instructions that, when executed by a processing circuitry system of a memory system, cause the memory system to: When the memory system is operating in idle mode, at least one of a plurality of received commands is stored in a queue, wherein the memory system includes a plurality of clocks, and each of the plurality of clocks is associated with a corresponding subcomponent of the memory system. The memory system is switched from the idle mode to the analysis mode to determine the throughput of the plurality of received commands, at least in part, based on storing at least one of the plurality of received commands. When the memory system operates in the analysis mode, the rate of at least one of the plurality of clocks is adjusted to the maximum rate; When the memory system operates in the analysis mode, it determines whether one or more characteristics of the plurality of received commands meet a threshold. as well as At least in part, based on determining that one or more characteristics of the plurality of received commands satisfy the threshold, the rate of at least one of the plurality of clocks is adjusted to a second rate lower than the maximum rate.

10. The non-transitory computer-readable medium of claim 9, wherein the memory system receives the plurality of received commands when operating in the analysis mode, the idle mode, or both, and wherein the instructions, when executed by the processing circuitry of the memory system, further cause the memory system to: The throughput of the plurality of received commands is calculated based at least in part on one or more of the characteristics, wherein the rate at which at least one of the plurality of clocks is adjusted is based at least in part on the calculated throughput.

11. The non-transitory computer-readable medium of claim 10, wherein the one or more characteristics include the number of the plurality of received commands received during a duration, the type of one or more of the plurality of received commands, the amount of data associated with one or more of the plurality of received commands, the depth of the queue containing one or more of the plurality of received commands, the address of one or more of the plurality of received commands, or a combination thereof.

12. The non-transitory computer-readable medium of claim 9, wherein the instructions, when executed by the processing circuitry of the memory system, further cause the memory system to: The memory system is switched from the analysis mode to a mode different from the idle mode, at least in part, by adjusting the rate of at least one of the plurality of clocks to the second rate.

13. The non-transitory computer-readable medium of claim 9, wherein the instructions, when executed by the processing circuitry of the memory system, further cause the memory system to: Determine that a first subset of the plurality of received commands satisfies the threshold; Determine that a second subset of the plurality of received commands satisfies a second threshold; as well as At least in part, based on determining that a first subset of the plurality of received commands satisfies the threshold and determining that a second subset of the plurality of received commands satisfies the second threshold, the rate of at least one of the plurality of clocks is adjusted to a third rate, wherein the threshold is associated with the third rate and the second threshold is associated with a fourth rate lower than the third rate.

14. The non-transitory computer-readable medium of claim 9, wherein a first clock of the plurality of clocks is associated with a data path of the memory system, a second clock of the plurality of clocks is associated with the processing circuitry of the memory system, and a third clock of the plurality of clocks is associated with a data bus coupled to the memory system.

15. An apparatus comprising: A memory system including multiple clocks, each of which is associated with a corresponding sub-component of the memory system; as well as A controller, coupled to the memory system, is configured to: When the memory system is operated in the first mode, at least one of the multiple received commands is stored in a queue; The memory system is switched from operating in the first mode to a second mode to determine the throughput of the plurality of received commands based at least in part on storing at least one of the plurality of received commands; When operating in the second mode, the rate of at least one of the plurality of clocks is adjusted to the maximum rate; When operating in the second mode, the throughput of the plurality of received commands is determined at least in part based on the plurality of received commands; as well as Based at least in part on the determined throughput of the plurality of received commands, the rate of at least one of the plurality of clocks is adjusted to a second rate lower than the maximum rate.

16. The device of claim 15, wherein the controller is further configured to: After adjusting the rate of at least one of the plurality of clocks to the second rate, the memory system is operated in the third mode.

17. The device of claim 15, wherein the controller is further configured to: Determine the number of maintenance operations to be performed on the memory system when it is operating in the first mode; and The rate of at least one of the plurality of clocks is adjusted, at least in part, based on the number of maintenance operations to be performed on the memory system.

18. The device of claim 15, wherein, in order to adjust the rate of at least one of the plurality of clocks, the controller is configured to: For the first clock, select the first index corresponding to the third rate from the first index range; For the second clock, select the second index corresponding to the fourth rate from the second index range; and For the third clock, select the third index corresponding to the fifth rate from the third index range.

19. The device of claim 18, wherein, in order to determine the throughput of the plurality of received commands, the controller is configured to: The received commands are classified into one or more categories, at least in part, based on characteristics associated with each of the plurality of received commands, wherein each of the one or more categories is associated with a corresponding index in the first index range, the second index range, or the third index range.

20. The device of claim 19, wherein, in order to determine the throughput of the plurality of received commands, the controller is configured to: At least in part, based on classifying the plurality of received commands, a subset of the plurality of received commands is determined to be associated with a first category and a second category of the one or more categories; and For a given clock among the plurality of clocks, the index corresponding to the highest rate of the given clock is selected from the fourth index associated with the first category and the fifth index associated with the second category.

21. The device of claim 15, wherein a first clock of the plurality of clocks is associated with a data path of the memory system, a second clock of the plurality of clocks is associated with a processing circuitry of the memory system, and a third clock of the plurality of clocks is associated with a data bus coupled to the memory system.

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