Data storage device with data checking circuitry

Abstract

A data storage device includes a non-volatile memory device including a memory block having a plurality of memory dies, and a controller coupled to the memory device. A memory access command is received and a memory access operation based on the received command is performed. A number of bytes transferred during the memory access operation is determined, and the determined number of bytes is analyzed to determine whether the number of transferred bytes equals a predetermined number. If the number of transferred bytes does not equal the predetermined number, a transfer status fault bit is set.

Description

Technical Field

[0001] This patent application relates generally to data storage devices, and more specifically to data storage devices having data verification circuitry. Background Technology

[0002] Memory devices typically contain various data checking algorithms and / or circuitry to ensure the accuracy of data read from or written to memory. However, in some cases, read or write operations may deliver data to / from a memory device that fails to include the expected number of bytes, potentially leading to memory device failure. For example, the controller and / or memory read / write circuitry may miss clock pulses, causing data to be shifted by one or more bytes (referred to herein as a "byte shift"). Typically, these shifted / missing bytes are not detected by the memory controller or read / write circuitry and can therefore constitute a failure that the memory device cannot handle. For example, a byte shift / missing failure may require the user to cycle power to the memory device, or in some cases, may lead to complete failure of the memory device. Summary of the Invention

[0003] Error detection and correction circuitry typically does not detect or mitigate the effects of byte shifts (e.g., an incorrect number of bytes transferred for a given operation). By detecting that an incorrect number of bytes have been transferred in a given operation (e.g., a read or write operation), memory devices using data verification circuitry can perform various actions to prevent failures caused by an incorrect number of bytes being transferred. Furthermore, by using this data verification circuitry to determine that a byte shift has occurred, one or more status bits or other indications can be provided to the memory controller, user, etc. By detecting and mitigating byte shift events, read and write performance, as well as the performance and lifespan of general-purpose memory devices, can be improved.

[0004] One embodiment of this disclosure includes a data storage device comprising a non-volatile memory device, the non-volatile memory device including a controller and a memory block. The memory block includes a plurality of memory dies and data verification circuitry. The data verification circuitry is configured to receive a memory access instruction from the controller and perform a memory access operation based on the memory access instruction. The data verification circuitry is further configured to determine the number of bytes transferred during the memory access operation, determine whether the number of bytes is equal to a predetermined number of bytes, and, in response to determining that the number of bytes is not equal to the predetermined number of bytes, set a transfer status fault bit indicating that the number of bytes is not equal to the predetermined number of bytes.

[0005] Another embodiment of this disclosure includes a method performed by a data storage device having a controller coupled to a non-volatile memory device. The method includes receiving a memory access command from an external device and performing a memory access operation based on the memory access command. The method further includes determining whether a certain number of bytes are transferred during the memory access operation and determining whether the number of bytes is equal to a predetermined number of bytes. In response to determining that the number of bytes is not equal to the predetermined number of bytes, a transfer status fault bit indicating that the number of bytes is not equal to the predetermined number of bytes is set.

[0006] Another embodiment of this disclosure includes an apparatus comprising means for receiving a memory access command from a controller, and means for performing a memory access operation based on the memory access command. The apparatus further includes means for determining the number of bytes transferred during the memory access operation, and means for determining whether the number of bytes is equal to a predetermined number of bytes. The apparatus further includes means for setting a transfer status bit in response to determining that the number of bytes is not equal to the predetermined number of bytes, the transfer status bit indicating that the number of bytes is not equal to the predetermined number of bytes.

[0007] Various aspects of this disclosure provide data storage devices with data verification circuitry. This disclosure can be embodied in various forms, including hardware or circuitry controlled by software, firmware, or a combination thereof. The foregoing summary is intended only to give a general idea of ​​various aspects of this disclosure and is not intended to limit the scope of this disclosure in any way. Attached Figure Description

[0008] Figure 1 This is a block diagram of an example system including a data storage device according to some implementation schemes.

[0009] Figure 2 This is a flowchart illustrating the byte shift mitigation process during a read operation, based on some implementation schemes.

[0010] Figure 3 This is a flowchart illustrating the byte shift mitigation process during a write operation, based on some implementation schemes. Detailed Implementation

[0011] In the following description, numerous details, such as data storage device configuration, controller operation, etc., are set forth in order to provide an understanding of one or more aspects of this disclosure. It will be apparent to those skilled in the art that these specific details are merely exemplary and are not intended to limit the scope of this application. Specifically, the functions associated with the controller may be performed by hardware (e.g., analog or digital circuitry), a combination of hardware and software (e.g., program code or firmware stored in a non-transitory computer-readable medium and executed by a processor or control circuitry), or any other suitable means. The following description is intended only to give a general conception of various aspects of this disclosure and is not intended to limit the scope of this disclosure in any way. Furthermore, it will be apparent to those skilled in the art that although this disclosure relates to NAND flash memory, the concepts discussed herein are applicable to other types of solid-state memories, such as NOR, PCM (“phase-change memory”), ReRAM, MRAM, DRAM, etc.

[0012] Figure 1 This is a block diagram of an example of a system 100 including byte shift detection and mitigation functions according to some embodiments of this disclosure. Figure 1 In this example, system 100 includes a data storage device 102 that communicates with host device 108. The data storage device 102 includes a memory device 104 (e.g., non-volatile memory) coupled to controller 106.

[0013] exist Figure 1 An example of the structural and functional features provided by controller 106 is shown. However, controller 106 is not limited to those provided by controller 106. Figure 1 The controller 106 provides structural and functional features. The controller 106 may include... Figure 1 Fewer or additional structural and functional features not shown in the diagram.

[0014] Data storage device 102 and host device 108 are operatively coupled via a connection such as a bus or wireless link (e.g., communication path 110). In some examples, data storage device 102 may be embedded within host device 108. Alternatively, in other examples, data storage device 102 may be removed from host device 108 (i.e., "removably" coupled to host device 108). For example, data storage device 102 may be removably coupled to host device 108 according to a removable universal serial bus (USB) configuration. In some implementations, data storage device 102 may include or correspond to a solid-state drive (SSD) that can be used as an embedded storage drive (e.g., a mobile embedded storage drive), an enterprise storage drive (ESD), a client storage device, a cloud storage drive, or other suitable storage drive.

[0015] Data storage device 102 may be configured to be coupled to host device 108 using communication path 110 (such as a wired communication path and / or a wireless communication path). For example, data storage device 102 may include interface 120 (e.g., a host interface) that enables communication between data storage device 102 and host device 108 using communication path 110, such as when interface 120 is communicatively coupled to host device 108.

[0016] Host device 108 may include a processor and memory. The memory may be configured to store data and / or instructions executable by the processor. The memory may be a single memory, or may include one or more memories, such as one or more non-volatile memories, one or more volatile memories, or combinations thereof. Host device 108 may issue one or more commands to data storage device 102, such as one or more requests to erase data at memory device 104 of data storage device 102, read data from the memory device, or write data to the memory device. For example, host device 108 may be configured to provide data to be stored at memory device 104 (such as user data 132) or request data to be read from memory device 104. Host device 108 may include a mobile smartphone, music player, video player, game console, e-book reader, personal digital assistant (PDA), computer (such as a laptop computer or notebook computer), any combination thereof, or other suitable electronic device.

[0017] Host device 108 communicates using a memory interface that enables reading from and writing to memory device 104. In some examples, host device 108 may operate according to industry specifications such as the Universal Flash Storage (UFS) Host Controller Interface Specification. In other examples, host device 108 may operate according to one or more other specifications such as the Secure Digital (SD) Host Controller Specification or other suitable industry specifications. Host device 108 may also communicate with memory device 104 according to any other suitable communication protocol.

[0018] The memory device 104 of the data storage device 102 may include non-volatile memory (e.g., NAND, NOR, BiCS series memory, or other suitable memory). In some examples, the memory device 104 may be any type of flash memory. For example, the memory device 104 may be a two-dimensional (2D) memory or a three-dimensional (3D) flash memory. The memory device 104 may include one or more memory dies 103. Each memory die 103 may include one or more memory blocks 112 (e.g., one or more erase blocks). Each memory block 112 may include one or more sets of memory elements, such as a set of representative memory elements 107A-107N. The set of memory elements 107A-107N may be configured as word lines. The set of memory elements 107A-107N may include multiple memory elements (e.g., memory cells referred to herein as a “string” or “array”), such as representative memory elements 109A and 109N, respectively.

[0019] Memory device 104 may include supporting circuitry such as read / write circuitry 140, read data verification circuitry, write data verification circuitry 144, and error correction circuitry 146. Although depicted as a single component, read / write circuitry 140 may be divided into separate components of memory device 104, such as read circuitry and write circuitry. Read / write circuitry 140 may be external to one or more memory dies 103 of memory device 104. Alternatively, one or more individual memory dies 103 may include corresponding read / write circuitry 140 operable to read from and / or write to storage elements within individual memory dies independently of any other read and / or write operations at any other memory die. For example, read / write circuitry 140 may be configured to perform various read / write operations, such as initial writes to volatile memory, array commit functionality, and other functions required by a given application. Memory device 104 may further include one or more latches (e.g., a set of latches 111 including latches 113, 115, and 117).

[0020] Read data verification circuit 142 and write data verification circuit 144 are shown as separate circuits, but in some embodiments, they may be combined into a single data verification circuit. In other examples, read data verification circuit 142 and write data verification circuit 144 are incorporated into read / write circuit 140. In other examples, read data verification circuit 142 and write verification circuit 144 may be incorporated into controller 106. Read data verification circuit 142 and write data verification circuit 144 may be configured to perform one or more data verification operations to ensure that the data associated with the read and / or write operation is valid, i.e., includes the expected number of bytes. These verification operations are described in more detail below. Error correction circuit 146 is configured to perform one or more error correction operations, such as cyclic redundancy check (“CRC”), to verify the content of the data processed by read / write circuit 140.

[0021] The controller 106 uses a bus 105, an interface (e.g., interface circuitry), another structure, or a combination thereof, to couple to the memory device 104 (e.g., one or more memory dies 103). For example, the bus 105 may include multiple different channels to enable the controller 106 to communicate with each of the one or more memory dies 103, in parallel with and independently of communication with the other memory dies 103.

[0022] Controller 106 is configured to receive data and instructions from host device 108 and to send data to host device 108. For example, controller 106 may use interface 120 to send data to host device 108, and controller 106 may use interface 120 to receive data from host device 108. Controller 106 is configured to send data and commands (e.g., memory operation 136, which may be a loop operation of a memory block of memory device 104) to memory device 104 and to receive data from memory device 104. For example, controller 106 is configured to send data and a program or write command to cause memory device 104 to store data at a specified address on memory device 104. The write command may specify the physical address of the portion of data to be stored on memory device 104 (e.g., the physical address of a word line on memory device 104), and the size of the data to be written (e.g., 2k, 4k, etc.).

[0023] Controller 106 is configured to send a read command to memory device 104 to access data from a specified address of memory device 104. The read command may specify the physical address of a region of memory device 104 (e.g., the physical address of a word line of memory device 104) and the size of the data to be read (e.g., 2k, 4k, etc.). Controller 106 may also be configured to send data and commands to memory device 104 associated with background scan operations, garbage collection operations and / or wear leveling operations, or other suitable memory operations.

[0024] Controller 106 may include processor 124, memory 126, and other associated circuitry. Memory 126 may be configured to store data and / or instructions executable by processor 124. Memory 126 may include data transfer error application 130 and other applications or programs. Data transfer error application 130 may be hardware circuitry or instructions executable by processor 124. Although shown as stored in memory 126, in some examples, data transfer error application 130 may be configured as circuitry within memory device 104.

[0025] The data transmission error application 130 can be configured to perform one or more data transmission error operations. For example, the data transmission error application 130 can store data transmission errors for later review. The stored transmission errors can then be accessed later by one or more users or monitoring controllers for further analysis.

[0026] Turn now Figure 2 The following flowchart illustrates a byte shift mitigation process 200 during a read operation, according to some embodiments. In one embodiment, the byte shift mitigation process 200 is performed by a read data verification circuit 142. In some embodiments, the byte shift mitigation process 200 is performed by the read data verification circuit 142 in conjunction with a read / write circuit 140. In still other embodiments, the read / write circuit 140 may perform the byte shift mitigation process 200.

[0027] At block 202, a read request is received at memory 104. In one example, the read request may be transmitted from controller 106 to memory 104. As described above, controller 106 may receive a read request from host device 108. At block 204, a read operation is performed. In one embodiment, the read operation reads the requested data from memory 104. In one embodiment, read / write circuitry 140 facilitates the read request and accesses data within memory die 103. In some embodiments, data is read from memory die 103 and latched into latch 111, which can then be read by controller 106.

[0028] At block 206, a determination is made regarding whether a read operation has stopped. In some embodiments, the read operation stops when multiple bytes associated with the read operation have been accessed (e.g., read). In some embodiments, a read duration timer associated with the read operation is accessed to determine whether the read operation has stopped or should have stopped. For example, the read operation is considered stopped once the read duration timer has expired. In one embodiment, the read duration timer is within the read / write circuitry 140. In one embodiment, the read duration timer is a time value associated with a given read command. For example, the time value may be based on the size of the data requested in the read request. The time value may be the time required to perform a given read operation on a given data storage device 102. Furthermore, additional delays (such as 10%) may be added to the time value to allow for the delay in performing the associated read operation. Additionally, time delay values ​​exceeding or falling short of 10% required by a given application are also considered. In one embodiment, the time value may have values ​​from 10 nanoseconds to 50 nanoseconds. However, values ​​less than 10 nanoseconds and greater than 50 nanoseconds are also considered. In some embodiments, the time delay value depends on the type of memory device. In one implementation, a device such as controller 106 will request the read operation to stop for a period of time (e.g., a read duration timer) so that the data count can be verified as described below. In yet another example, one or more read completion bits can be set once the read is complete. For example, read / write circuitry 140 can set the read completion bit when the read operation stops.

[0029] In response to determining that the read operation has not stopped, the read operation continues at block 204. In response to determining that the read operation has stopped, the amount of data read is counted at block 208. In one embodiment, the number of bytes associated with the read operation is determined and / or counted. In one embodiment, read data verification circuitry 142 determines the amount of data read. However, in other examples, read / write circuitry 140 determines the amount of read data transmitted. The amount of data expected by the requested read operation can be based on the read request. For example, a read request may request 4096 bytes of data (e.g., 4k data read). Other data read sizes, such as 1k, 2k, 8k, etc., may also be associated with the read request.

[0030] At block 210, a determination is made regarding whether the transmitted data equals a predetermined number of data. In one embodiment, read data verification circuitry 142 performs the verification. However, in other embodiments, read / write circuitry 140 performs the verification. The determination is made that the data equals a predetermined number of data, where the amount of data transmitted equals the predetermined number of data. For example, as described above, a 4K data read has an expected (e.g., predetermined) number of bytes equal to 4096. Therefore, if it is determined that 4096 bytes were transmitted during a read operation, the transmitted data is determined to be equal to the predetermined value. However, if it is determined that 4095 bytes were transmitted during a read operation, the transmitted data is determined not to be equal to the predetermined value. In some examples, the predetermined number of bytes may be specific to a given data storage device 102. For example, while a 4K transfer typically includes 4096 bytes of data, some data storage devices and associated protocols may include more data to specify error correction bits, address bits, and / or other information required by a given application. Therefore, data storage device 102 may have a defined value for the predetermined number of bytes.

[0031] In response to determining that the transmitted data equals a predetermined value, a read operation is completed at block 212. In response to determining that the transmitted data does not equal a predetermined value, a transmission fault bit is set at block 214. The transmission fault bit can be stored in the data transmission error application 130. However, in other embodiments, the transmission fault bit can be stored in the read / write circuit 140 and / or the read data verification circuit 142.

[0032] At block 216, additional data is added to the transmitted data to ensure that the amount of transmitted data equals a predetermined value. For example, in the case where the transmitted data for a 4k read request is only equal to 4095 bytes, an additional 1 byte can be appended to the transmitted data to ensure that the transmitted data includes the predetermined number of bytes. More than 1 byte can be appended to the transmitted data as needed to ensure that the transmitted data includes the predetermined number of bytes. In one embodiment, read data verification circuitry 142 adds the required additional data to the transmitted data. In other embodiments, read / write circuitry 140 adds the required additional data to the transmitted data. In one embodiment, the appended data can always be the same, such as logic 1 or logic 0. However, in other examples, the appended data can be random, such as data generated based on atmospheric noise. In one example, the clock signal can be switched to be equal to the required number of missing bytes, thereby allowing random data to fill the remaining bytes in the transmitted data. Regardless of what data is appended, the setting of the transmission fault bit at block 214 ensures that the data is interpreted as invalid. Once the additional data has been added to the transmitted data, the read operation is completed at block 212.

[0033] By appending missing data to the transmitted data, the transmitted data includes a predetermined data value (e.g., a allowed number of bytes). As described above, byte shifting (e.g., non-allowed data byte values) can cause data storage devices (such as data storage device 102) to malfunction or "blow up." In some cases, data storage device 102 can be reset by power recirculation, but in other cases, data storage device 102 or parts thereof may be irreparable. Byte shifting can cause one or more requested commands to fail to complete because the correct number of bytes were never received. This can cause one or more monitoring routines to indicate a failure, thus causing data storage device 102 to malfunction.

[0034] Byte shifting is not typically a common occurrence in data storage devices; however, as mentioned above, its occurrence can cause significant, and in some cases irreversible, damage to the data storage device. Byte shifting can occur as the device ages due to factors such as copper trace degradation in word lines, breakdown in the silicon matrix, voltage instability within the data storage device 102, device aging, and alpha particle degradation. Furthermore, timing issues between the controller and one or more memories can lead to missing clock pulses, which in turn can cause byte shifting.

[0035] Turn now Figure 3 According to some embodiments, a flowchart illustrating a byte offset verification process 300 during a write operation is shown. In one embodiment, the byte offset verification process 300 is performed by a write data verification circuit 144. In some embodiments, the byte offset verification is performed by the write data verification circuit 144 in conjunction with a read / write circuit 140. Still in other embodiments, the read / write circuit 140 may perform the byte offset verification process 200.

[0036] At block 302, a write request is received at memory 104. In one example, the write request may be transmitted from controller 106 to memory 104. Controller 106 may receive the write request from host device 108, as described above. At block 304, the requested data is written to a volatile portion of the memory, such as volatile latch 111. In one embodiment, read / write circuitry 140 facilitates the write request and transmits the data to volatile latch 111.

[0037] At box 306, the number of received data (e.g., received bytes) is compared to a predetermined value. For example, in the case of a 4k write request, the predetermined value could be 4096 bytes. For a 2k write request, the predetermined value could be 2048 bytes. Predetermined values ​​will exist for all sizes of write requests. In one embodiment, the amount of received data associated with a write operation is determined and / or counted by write data verification circuitry 144. However, in other examples, read / write circuitry 140 determines the amount of received data. As described above, the amount of data expected by the requested write operation can be based on the write request. For example, a write request could request 4096 bits of data (e.g., a 4k data read). Other data write sizes, such as 1k, 2k, 8k, etc., can also be associated with write requests. In some examples, the predetermined number of bytes can be specific to a given data storage device 102. For example, while a 4k transfer typically includes 4096 bytes of data, some data storage devices and associated protocols may include more data to specify error correction bits, address bits, and / or other information required by a given application. Therefore, the data storage device 102 can have a predetermined limit of data storage bytes.

[0038] At block 308, a determination is made regarding whether the received data equals a predetermined number of data. In one embodiment, the write data verification circuit 144 performs the verification. However, in other embodiments, the read / write circuit 140 performs the verification. It is determined that the received data equals a predetermined number of data, where the number of received data equals the predetermined number of data. For example, as described above, a 4k data write has an expected number of bytes equal to 4096. Therefore, if it is determined that 4096 bytes were received during a write operation, data transmission is allowed as the number of received bytes equals the predetermined number of bytes. However, if it is determined that 4095 bytes were received during a write operation, data transmission is not allowed because the number of received bytes does not equal the predetermined number of bytes. In response to the determination that data transmission is not allowed, a transmission fault bit is set at block 310. The transmission fault bit can be stored in the data transmission error application 130. However, in other embodiments, the transmission fault bit can be stored in the read / write circuit 140 and / or the write data verification circuit 144. When the transmission fault bit is set, a program commit delay is initiated at block 312.

[0039] Setting a transfer fault bit during a write operation allows data storage device 102 and therefore controller 106 to understand that a transfer problem has occurred, thereby allowing debugging and / or error management to be performed before attempting to read data, which could result in data corruption during access or failure of data storage device 102 due to incorrect data. Therefore, by providing a transfer fault bit status to data storage device 102, potential failures during subsequent read operations can be reduced or eliminated. Furthermore, the transfer fault bit allows for additional debugging to prevent future transfer errors. For example, one or more arrays (e.g., storage elements 107A-107N) and / or memory dies 103 may be deprecated in response to data transfer errors as described above. In some cases, additional information, such as the number of read / write cycles for a given storage element 107A-107N and / or memory die 103, can be used in conjunction with the transfer fault bit status to determine whether the associated storage element 107A-107N and / or memory die 103 should be deprecated. Additionally, where data storage device 102 is part of an enterprise system, information associated with the transfer fault bit status can be provided to system administrators and / or enterprise controllers. This is an improvement over previous data storage devices that only indicated when a byte shift error occurred, without providing any information or status data indicating that the error was caused by the byte shift error.

[0040] In response to determining that the data transfer is an allowed value (i.e., not equal to a predetermined value), a program commit delay is initiated at block 312. The program commit delay is the delay between writing data associated with a write command to volatile memory (such as latch 111) and committing the data to one or more arrays (e.g., word lines) (such as memory elements 107A-107N). In some embodiments, the commit delay may be a defined time period (e.g., 10 nanoseconds). However, in other examples, the commit delay may be greater than or less than 10 nanoseconds. In other examples, the commit delay may be based on the size of the write request, such that the larger the write request, the greater the program commit delay. In some examples, there may be no commit delay.

[0041] When the program submission delay is completed, a commit operation command is issued in block 314. In one embodiment, the commit operation command is issued by read / write circuitry 140. In other embodiments, one or more other components of data storage device 102 (such as controller 106) issue the commit operation command. The commit operation command instructs read / write circuitry 140 to write received data to one or more static arrays (such as storage elements 107A-107N and / or 109A-109N). When the commit operation command is issued, a determination is made in block 316 regarding whether a transmission fault bit has been set. In one embodiment, read / write circuitry 140 determines whether a transmission fault bit has been set. In other embodiments, one or more of read data verification circuitry 142 and write data verification circuitry 144 determine whether a transmission fault bit has been set. In other embodiments, one or more other components of data storage device 102, such as write data verification circuitry 144, error correction circuitry 146, and / or controller 106, determine whether a transmission fault bit has been set.

[0042] In response to determining that a transmission fault bit has been set, the operation state is set to fault at block 318. In one embodiment, the operation state may be set to fault within data transmission error application 130. In other embodiments, the operation state may be set to fault within error correction circuitry 146. In addition to setting the operation state to fault, additional data may be stored and associated with the operation fault. For example, an indication showing that the transmission fault bit was set based on a received byte not being an allowed value may be provided. Other information, such as write request size, missing byte information, write address, device temperature, and / or the number of read / write operations for a given storage element 107A-107N, may also be stored along with the operation fault state.

[0043] In response to determining that a transmission fault bit is not set, a commit operation is performed at block 320 (e.g., writing received data to one or more static arrays). At block 322, read / write circuitry 140 determines whether the commit operation was successful. In response to determining that the commit operation was unsuccessful, the operation status is set to fault at block 318. In response to determining that the commit operation was successful, the operation is reported as successful at block 324. In one example, read / write circuitry 140 may report a successful operation to one or more components, such as data transmission error application 130, write data verification circuitry 144, and / or controller 106.

[0044] Regarding the processes, systems, methods, heuristics, etc., described herein, it should be understood that although the steps of such processes are described as being performed according to an ordered sequence, such processes can be practiced with the steps performed in a sequence other than that described herein. It should also be understood that some steps may be performed simultaneously, other steps may be added, or some steps described herein may be omitted. In other words, the description of processes herein is provided for the purpose of illustrating certain specific implementations and should in no way be construed as limiting the claims.

[0045] Therefore, it should be understood that the above description is intended to be exemplary and not restrictive. Many embodiments and applications beyond the examples provided will be apparent upon reading the above description. The scope should not be determined by reference to the above description, but rather by reference to the full scope of the appended claims together with the equivalents to which such claims are entitled. It is anticipated and intended that the technology discussed herein will be further developed in the future, and the disclosed systems and methods will be incorporated into such future embodiments. In conclusion, it should be understood that modifications and variations are possible with this application.

[0046] All terms used in the claims are intended to be given their broadest reasonable construction and their common meaning as understood by one skilled in the art described herein, unless expressly indicated otherwise herein. Specifically, the use of singular articles such as “a,” “the,” “the,” etc., should be understood to mean one or more of the elements indicated in the statement, unless expressly limited to the contrary by the statement of the claims.

[0047] A summary of the specification is provided to allow readers to quickly determine the nature of the technical disclosure. It should be understood that the submitted content is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing detailed description, it can be seen that various features are grouped together in various embodiments for the purpose of simplifying this disclosure. This approach of the disclosure should not be construed as reflecting an intention that the claimed embodiments require more features than expressly recited in each claim. Rather, as reflected in the appended claims, the subject matter of the invention lies in fewer than all features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim is independently claimed as a separate subject matter.

Claims

1. A data storage device, the data storage device comprising: A non-volatile memory device, the non-volatile memory device including a controller; A memory block, the memory block comprising a plurality of memory dies; and Data verification circuit, the data verification circuit being configured as follows: Receive memory access commands from the controller. Execute a memory access operation based on the memory access command. Determine the number of bytes transferred during the memory access operation. Determine whether the number of bytes transmitted equals the predetermined number of bytes. In response to determining that the number of bytes transmitted is not equal to the predetermined number of bytes, a second number of additional bytes are appended to the transmitted bytes, wherein the number of the second additional bytes is equal to the difference between the predetermined number of bytes and the number of bytes transmitted. In response to determining that the number of bytes transmitted is not equal to the predetermined number of bytes, a transmission status fault bit indicating that the number of bytes transmitted is not equal to the predetermined number of bytes is set. The second number of additional bytes are randomly generated bytes.

2. The data storage device according to claim 1, wherein the memory access operation is a read operation.

3. The data storage device according to claim 1, wherein the memory access operation is a write operation.

4. The data storage device according to claim 3, wherein the data verification circuit is further configured as follows: A commit operation command is issued to write the transmitted bytes to an array within one or more memory dies in the memory die. Determine whether to set the transmission status fault bit. An indication of a fault in the write operation is generated based on determining the setting of the transmission status fault bit; and In response to determining that the transmission status fault bit is set, a commit operation is prevented.

5. The data storage device of claim 4, wherein the memory block is further configured to transmit the fault indication to the controller.

6. The data storage device of claim 1, wherein the number of predetermined bytes is based on the data size associated with the memory access command.

7. The data storage device of claim 1, wherein the data verification circuit is part of the memory block.

8. A method performed by a data storage device having a controller coupled to a non-volatile memory device, the method comprising: Receive memory access commands from external devices; Execute a memory access operation based on the memory access command; Determine the number of bytes transferred to the memory device during the memory access operation; Determine whether the number of bytes transmitted is equal to the predetermined number of bytes; In response to determining that the number of bytes transmitted is not equal to the predetermined number of bytes, a certain number of additional bytes are appended to the transmitted bytes, wherein the number of additional bytes is equal to the difference between the predetermined number of bytes and the number of bytes transmitted. as well as In response to determining that the number of bytes transmitted is not equal to the predetermined number of bytes, a transmission status fault bit indicating that the number of bytes transmitted is not equal to the predetermined number of bytes is set. The number of additional bytes mentioned therein is one of the randomly generated bytes, logical high bytes, and logical low bytes.

9. The method of claim 8, wherein the memory access operation is a read operation.

10. The method of claim 8, wherein the memory access operation is a write operation.

11. The method according to claim 10, further comprising: A commit operation command is issued to write the bytes to an array within one or more memory dies; Determine whether to set the transmission status fault bit; An indication of a fault in the write operation is generated based on determining the setting of the transmission status fault bit; as well as In response to determining that the transmission status fault bit is set, a submit operation associated with the submit operation command is prevented.

12. The method of claim 11, further comprising storing the instruction in the memory of the controller.

13. The method of claim 12, wherein the number of predetermined bytes is based on the data size associated with the memory access command.

14. An apparatus comprising: A means for receiving memory access commands from a controller; A means for performing memory access operations based on the memory access command; A means for determining the number of bytes transferred during the memory access operation; A means for determining whether the number of bytes transmitted is equal to a predetermined number of bytes; A means for appending a second number of additional bytes to the transmitted bytes in response to determining that the number of transmitted bytes is not equal to the predetermined number of bytes, wherein the number of the second additional bytes is equal to the difference between the predetermined number of bytes and the number of transmitted bytes; and A means for setting a transmission status fault bit indicating that the number of transmitted bytes is not equal to the predetermined number of bytes in response to determining that the number of transmitted bytes is not equal to the predetermined number of bytes. The second number of additional bytes are randomly generated bytes.

15. The apparatus of claim 14, wherein the memory access operation is a read operation.

16. The apparatus of claim 14, wherein the memory access operation is a write operation, the apparatus further comprising: A means for issuing a submit operation command to write the transmitted bytes to an array within one or more memory dies; A device for determining whether to set the transmission status fault bit; A means for generating an indication of a fault in the write operation based on determining the setting of the transmission status fault bit; as well as A means for preventing a submit operation associated with the submit operation command in response to determining to set the transmit bit.

17. The apparatus of claim 16, wherein the number of predetermined bytes is based on the data size associated with the memory access command.

Images