Using register management error control information

Abstract

This application relates to using register management error control information. A memory device can store, at a register, an indication of whether the memory device has detected an error included in or associated with data requested from a host device. The memory device can determine to store the indication based on whether a communication protocol is enabled or disabled and whether an error control configuration is enabled or disabled. The host device can request information from the register of the memory device, and the memory device can output the indication of whether the error was detected in response to the request.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 816,320, filed July 29, 2022, entitled “Managing Error Control Information Using a Register,” and U.S. Provisional Patent Application No. 63 / 234,068, filed August 17, 2021, entitled “Managing Error Control Information Using a Register,” each of which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] This technical field relates to the use of registers to manage error control information. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, often represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write states into the memory device or program states.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, and chalcogenide memory technology. Memory cells can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for a long time, even without external power. For example, volatile memory devices like DRAM may lose their stored state when disconnected from external power. Summary of the Invention

[0006] A method is described. In some instances, the method may include, at a memory device, generating at least in part a first plurality of correctors based on receiving data for storage at the memory device, the first plurality of correctors being associated with an error control operation of the received data, each of the first plurality of correctors including an error correction or error detection corrector bit; at the memory device, generating at least in part a second plurality of correctors based on retrieving the data, the second plurality of correctors being associated with the retrieved data and the error control operation, each of the second plurality of correctors including an error correction or error detection corrector bit; determining whether the first plurality of correctors matches the second plurality of correctors based at least in part on a comparison of the first plurality of correctors and the second plurality of correctors; and storing, at a register of the memory device, an indication of whether the first plurality of correctors matches the second plurality of correctors.

[0007] A method is described. In some instances, the method may include determining at a memory device that a first communication protocol for reporting information to a host device is enabled or disabled; determining at the memory device that a first error control configuration for reporting comparisons of correctors generated by the memory device is enabled or disabled; and configuring registers of the memory device to operate in a first mode, at least in part based on the determination that the first communication protocol is disabled and the first error control configuration is enabled.

[0008] An apparatus is described. In some instances, the apparatus may include an error control circuitry system operable to perform an error control operation on data received and stored at the apparatus, the error control circuitry system further operable to: generate, at least in part based on the received data, a first plurality of correctors associated with the error control operation, each of the first plurality of correctors including an error correction or error detection corrector bit; generate, at least in part based on retrieving the data, a second plurality of correctors associated with the error control operation, each of the second plurality of correctors including an error correction or error detection corrector bit; determine, at least in part based on a comparison of the first plurality of correctors and the second plurality of correctors, whether the first plurality of correctors matches the second plurality of correctors; and generate a signal indicating whether the first plurality of correctors matches the second plurality of correctors; and a register operable to receive the signal from the error control circuitry system and store, at a location in the register, an indication of whether the first plurality of correctors matches the second plurality of correctors, at least in part based on the received signal.

[0009] A device is described. In some instances, the device may include registers; and circuitry operable to: determine whether a first communication protocol for reporting information to a host device is enabled or disabled; determine whether a first error control configuration for reporting comparisons of correctors generated by the device is enabled or disabled; and configure the registers to operate in a first mode, at least in part based on the determination that the first communication protocol is disabled and the first error control configuration is enabled.

[0010] A method is described. In some instances, the method may include a host device writing a first indication to a first register associated with a memory device that a first communication protocol for reporting information from the memory device to the host device is disabled; the host device writing to the first register a second indication that a first error control configuration for reporting comparisons of correctors generated by the memory device is enabled; and at least in part based on the first communication protocol being disabled and the first error control configuration being enabled, transmitting a command to the memory device to read information stored in a second register of the memory device, the information indicating whether a first plurality of correctors matches a second plurality of correctors associated with an error control operation performed at the memory device. Attached Figure Description

[0011] Figure 1 Examples of systems that support the use of registers to manage error control information, based on the examples disclosed herein, are shown.

[0012] Figure 2 Examples of memory dies that support the use of registers to manage error control information, as disclosed herein, are shown.

[0013] Figure 3 Examples of error control circuitry systems that support the use of registers to manage error control information, based on the examples disclosed herein, are shown.

[0014] Figure 4 Examples of memory systems that support the use of registers to manage error control information, based on the examples disclosed herein, are shown.

[0015] Figure 5 A block diagram is shown that supports the use of registers to manage error control information, based on the examples disclosed herein.

[0016] Figure 6 A block diagram is shown illustrating a host device that supports the use of registers to manage error control information, based on the examples disclosed herein.

[0017] Figures 7 to 9 The flowchart illustrates one or more methods for managing error control information using registers, based on the examples disclosed herein. Detailed Implementation

[0018] Memory devices can use error detection and / or correction techniques (e.g., error control techniques) to improve the reliability of stored or transmitted data. Some error control techniques used in memory devices may include Single Bit Error Correction (SBE) (SEC), Double Bit Error Detection (DBE) (DED), and SECDED techniques. In some cases, external devices storing data at the memory device (e.g., a host device) may also use internal error control techniques to verify the reliability of data received from the memory device.

[0019] In some cases, the error control techniques used at the memory device may differ from those used at the host device. For example, the host device may use a more robust error control technique than the memory device. In some situations, using different error control techniques at the host and memory devices can lead to additional errors. For instance, if the memory device applies SECDED to data containing two or more bit errors, the memory device may incorrectly flip the correct bits of the data, potentially increasing the number of errors in the data from two to three. In this scenario, when the memory device transmits data with three bit errors, the host device using SECDED may fail to detect and / or correctly identify the bit errors in the received data, whereas the host device may have already detected the two original bit errors (e.g., no additional errors introduced by the memory device).

[0020] This disclosure provides techniques for improving the reliability of data transmission between a memory device and a host device. For example, the memory device may store an indication in a register (e.g., a mode register) of whether the memory device has detected an error associated with an error control operation using one or more correction bits associated with the error control operation. The memory device may store the indication in a register that is accessible, for example, by the host device. The memory device may determine the storage indication based on multiple criteria. For example, the memory device may determine that a communication protocol (e.g., the DSF+ protocol) for reporting information (e.g., Error Correction Code (ECC) information, correction bit check information) to the host device is disabled, and an error control configuration is enabled (e.g., a configuration for reporting an indication of a detected error). The memory device may store an indication of a detected error in the mode register based on the determination that the communication protocol for reporting information to the host device is disabled and the error control configuration is enabled. The host device may request data from the mode register of the memory device, and the memory device may output an indication of whether an error was detected in response to polling. By accessing an indication of whether an error was detected at the memory device, the host device can avoid using data containing a number of errors that would otherwise exceed the capabilities of the technology used by the host device. For example, a host device using SECDED technology can avoid using data containing three-bit errors.

[0021] The features of this disclosure are first described in the context of a memory system. These features are further described in the context of a correction sub-match checker supporting coordinated error correction and the memory subsystem. These and other features of this disclosure are further illustrated and described with reference to device diagrams, system diagrams, and flowcharts relating to coordinated error correction. While this disclosure generally describes DRAM systems, the techniques described herein are applicable to any memory system implementing error control or detection / correction techniques.

[0022] Figure 1 An example of a system 100 supporting the use of registers to manage error control information is shown according to the examples disclosed herein. System 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 to the memory device 110. System 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0023] System 100 may include portions of electronic devices such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may describe aspects of computers, laptop computers, tablet computers, smartphones, cellular phones, wearable devices, internet-connected devices, vehicle controllers, etc. Memory device 110 may be a component of the system used to store data for one or more other components of system 100.

[0024] At least a portion of system 100 may be an instance of host device 105. Host device 105 may be an instance of a processor or other circuitry within a device that uses memory execution processes, such as within a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, system-on-a-chip (SoC), or other fixed or portable electronic device, and other instances. In some instances, host device 105 may refer to the hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 120. In some instances, external memory controller 120 may be referred to as a host or host device 105. In some instances, host device 105 may use error correction techniques. Host device 105 may request data from registers of memory device 110 (e.g., polling). Host device 105 may access indications of whether an error has been detected at memory device 110 and avoid using data containing a number of errors that would otherwise exceed the capabilities of the error correction techniques used by the host device.

[0025] Memory device 110 may be a separate device or component operable to provide physical memory address / space that can be used or referenced by system 100. In some instances, memory device 110 may be configurable to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be used to support one or more of the following: modulation schemes for modulating signals, various pin configurations for transmitting signals, various form factors for the physical packages of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0026] Memory device 110 may be used to store data for components of host device 105. In some instances, memory device 110 may act as a slave or dependent device of host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0027] The host device 105 may include an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or one or more other components such as one or more peripheral components or one or more input / output controllers. The components of the host device 105 may be coupled to each other via bus 135.

[0028] Processor 125 may be operable to provide control or other functionality for at least a portion of system 100 or host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or SoC, as well as other instances. In some instances, external memory controller 120 may be implemented by processor 125 or be part of said processor.

[0029] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more read-only memory (ROM), flash memory, or other non-volatile memory.

[0030] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more segments), wherein each memory cell can be used to store at least one bit of data. Memory device 110 including two or more memory dies 160 may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package.

[0031] The device memory controller 155 may include circuitry, logic, or components for controlling the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be used to receive, transmit, or execute commands, data, or control information related to components of the memory device 110. The device memory controller 155 may be used to communicate with one or more of an external memory controller 120, one or more memory dies 160, or a processor 125. In some instances, the device memory controller 155 may be used in conjunction with a local memory controller 165 of the memory die 160 to control the operation of the memory device 110 described herein.

[0032] A local memory controller 165 (e.g., local to memory die 160) may include circuitry, logic, or components operable to control the operation of memory die 160. In some instances, the local memory controller 165 is operable to communicate with a device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include a device memory controller 155, and either the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 is operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or combinations thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating the received signals, an encoder for encoding or modulating the signals to be transmitted, or various other circuitry or controllers operable to support the operation of the described device memory controller 155 or the local memory controller 165, or both.

[0033] External memory controller 120 can be used to enable the transfer of one or more of information, data, or commands between components of system 100 or host device 105 (e.g., processor 125) and memory device 110. External memory controller 120 can translate or interpret communications exchanged between components of host device 105 and memory device 110. In some instances, external memory controller 120 or other components of system 100 or host device 105, or the functionality described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125 or other components of system 100 or host device 105. Although external memory controller 120 is depicted as external to memory device 110, in some instances, external memory controller 120 or the functionality described herein may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0034] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths operable to carry signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be operable to act as part of a channel.

[0035] Channel 115 (and associated signal paths and terminals) may be dedicated to transmitting one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, signaling may be transmitted on channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0036] Memory device 110 may support an internal (e.g., on-die) error control scheme configured to detect and, in at least some cases, correct errors in data read from memory array 170 and transmitted to host device 105. Furthermore, memory device 110 may indicate to host device 105 whether the error control scheme at memory device 110 has detected an error associated with the dataset (e.g., by storing the indication so that host device 105 can later poll memory device 110 for the indication, or memory device 110 can later include the indication in an error report). For example, memory device 110 may store the indication in a register of the memory device. Although Figure 1 DRAM systems are typically shown, but this document refers to... Figure 1 The described techniques are applicable to any memory system (e.g., NAND, FeRAM, RRAM, or other memory technologies) that implements error control techniques.

[0037] Figure 2 An example of a memory die 200 supporting register management of error control information, as disclosed herein, is shown. The memory die 200 may be a reference. Figure 1 Examples of memory die 160 described herein. In some instances, memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. Memory die 200 may include one or more memory cells 205, each of which may be programmable to store different logic states (e.g., one programmed state from a set of two or more possible states). For example, memory cell 205 may be operable to store one bit of information at a time (e.g., logic 0 or logic 1). In some instances, memory cell 205 (e.g., a multi-level memory cell) may be used to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some instances, memory cells 205 may be arranged in an array, such as referenced in [reference needed]. Figure 1 The memory array 170 is described.

[0038] Memory cell 205 can store charge representing a programmable state in a capacitor. A DRAM architecture may include a capacitor containing an electrical medium to store charge representing a programmable state. Other memory devices and components are also possible in other memory architectures. For example, a nonlinear electrical medium can be used. Memory cell 205 may include logic storage components, such as capacitor 230 and switching components 235. Capacitor 230 may be an example of an electrical medium capacitor or a ferroelectric capacitor. Nodes of capacitor 230 may be coupled to a voltage source 240, which may be, for example, a cell board reference voltage Vpl, or ground, for example, Vss.

[0039] The memory die 200 may include one or more access lines (e.g., one or more word lines 210 and one or more digital lines 215) arranged in a pattern, such as a grid pattern. Access lines may be wires coupled to memory cells 205 and may be used to perform access operations on memory cells 205. In some instances, word lines 210 may be referred to as row lines. In some instances, digital lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digital lines, or bit lines, or the like, may be interchanged without affecting understanding or operation. Memory cells 205 may be located at the intersection of word lines 210 and digital lines 215.

[0040] Memory cell 205 can be accessed, for example, by activating or selecting one or more access lines, such as word line 210 or digital line 215. A single memory cell 205 can be accessed at its intersection point by biasing word line 210 and digital line 215 (e.g., by applying a voltage to word line 210 or digital line 215). The intersection point of word line 210 and digital line 215 in a two-dimensional or three-dimensional configuration may be referred to as the address of memory cell 205.

[0041] Access to memory cell 205 can be controlled via row decoder 220 or column decoder 225. For example, row decoder 220 can receive row addresses from local memory controller 260 and activate word line 210 based on the received row addresses. Column decoder 225 can receive column addresses from local memory controller 260 and activate digital line 215 based on the received column addresses.

[0042] Selecting or deselecting memory cell 205 can be achieved by activating or deactivating activation switch assembly 235 using word line 210. Capacitor 230 can be coupled to digital line 215 using switch assembly 235. For example, capacitor 230 can be isolated from digital line 215 when switch assembly 235 is deactivated, and can be coupled to digital line 215 when switch assembly 235 is activated.

[0043] Sensing component 245 is operable to detect the state (e.g., charge) stored on capacitor 230 of memory cell 205 and determine the logic state of memory cell 205 based on (e.g., using) the stored state. Sensing component 245 may include one or more sensing amplifiers to amplify or additionally transform signals generated by accessing memory cell 205. Sensing component 245 may compare the signal detected from memory cell 205 with reference 250 (e.g., reference voltage). The detected logic state of memory cell 205 may be provided as an output of sensing component 245 (e.g., to input / output 255) and may indicate the detected logic state to another component of the memory device including memory die 200.

[0044] Sensing component 245 may include various transistors or amplifiers to detect and amplify differences in the signal. The detected logic state of memory cell 205 may be output via I / O 255 ​​through error control block 265 (e.g., ECC block, error control circuitry system, or ECC circuitry system). Error control block 265 may perform error correction operations on the detected logic state of memory cell 205 and output data (e.g., stored data or correction data) via I / O 255. In some other cases, the detected logic state of memory cell 205 may bypass error control block 265 and be output via I / O 255. In some cases, the detected logic state of memory cell 205 may be output to both error control block 265 and I / O 255 ​​simultaneously. Here, while error control block 265 performs error correction operations on the detected logic state of memory cell 205, I / O 255 ​​may output the detected logic state of memory cell 205 from memory die 200. In some cases, sensing component 245 may be part of another component (e.g., column decoder 225, row decoder 220). In some cases, sensing component 245 may be electronically connected to row decoder 220 or column decoder 225.

[0045] Error control block 265 can output error control information, which may represent information for detecting and / or correcting errors introduced when storing data at memory die 200. The error control information may include, for example, ECC information or parity bits, which may indicate the presence of errors in the associated data set. Alternatively or additionally, the error control information may include corrector check information (e.g., reference...). Figure 3 and 4 (As described). The calibrator check information can represent the probability or likelihood of an error existing in the dataset and / or ECC information based on a comparison of a calibrator subset. The calibrator can represent an intermediate result in the error detection or error correction process and can be used by the error control block 265 to estimate whether an error has occurred in the dataset and / or ECC information (e.g., to determine the probability of an error occurring in the dataset and / or ECC information).

[0046] The local memory controller 260 can control the operation of the memory cell 205 through various components (e.g., row decoder 220, column decoder 225, sensing component 245, and error control block 265). The local memory controller 260 can be a reference. Figure 1 An example of a local memory controller 165 is described. In some cases, one or more of the row decoder 220, column decoder 225, sensing component 245, and error control block 265 may be located in the same location as the local memory controller 260. The local memory controller 260 may be configured to receive signals from an external memory controller 105 (or refer to...). Figure 1 The described device memory controller 155 receives commands and / or data, converts the commands and / or data into information usable by the memory die 200, performs one or more operations on the memory die 200, and, in response to performing one or more operations, transfers data from the memory die 200 to an external memory controller 105 (or device memory controller 155). A local memory controller 260 can generate row and column address signals to activate target word lines 210 and target digital lines 215. The local memory controller 260 can also generate and control various voltages or currents used during operation of the memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may be adjusted or varied, and may differ for the various operations discussed in operating the memory die 200.

[0047] In some cases, the local memory controller 260 may be configured to perform write operations (e.g., programming operations) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 may be programmed to store a desired logical state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 260 may identify the target memory cell 205 to which the write operation will be performed. The local memory controller 260 may identify the target word line 210 and target digital line 215 (e.g., the address of the target memory cell 205) that are electrically connected to the target memory cell 205. The local memory controller 260 may activate the target word line 210 and target digital line 215 (e.g., apply a voltage to the word line 210 or digital line 215) to access the target memory cell 205. The local memory controller 260 may apply a specific signal (e.g., voltage) to the digital line 215 during a write operation to store a specific state (e.g., charge) in the capacitor 230 of the memory cell 205, the specific state (e.g., charge) indicating a desired logic state.

[0048] During a write operation, error control block 265 or local memory controller 260 may generate error detection or correction information. For example, error control block 265 may receive data from a host device as part of the write operation. Error control block 265 may determine or generate error detection or correction information associated with the data. In some cases, error control block 265 may include error detection logic, or error detection logic (not shown) may perform the error detection operations described herein. As part of the write operation, error control block 265 may store data and error detection or correction information in one or more memory cells 205. The type of error detection or correction information generated by error control block 265 may correspond to the type of error detection operation performed by error control block 265. For example, if error control block 265 performs a SEC or SECDED error detection operation, error control block 265 may generate a SEC or SECDED codeword as part of the write operation. The SEC or SECDED codeword may correspond to error detection information used by error control block 265 to detect and / or correct errors within the data when performing the SEC or SECDED error detection operations respectively. Alternatively, if the error control block 265 performs an error detection operation based on the parity bit, then the error control block 265 may generate the parity bit as part of the write operation.

[0049] The local memory controller 260 can control access to the memory cell 205 through various components (e.g., row decoder 220, column decoder 225, sensing component 245). The local memory controller 260 can be a reference. Figure 1 An example of a local memory controller 165 is described. In some instances, one or more of the row decoder 220, column decoder 225, and sensing component 245 may be located in the same location as the local memory controller 260. The local memory controller 260 is operable to receive one or more commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with host device 105, another controller associated with memory die 200), translate the commands or data (or both) into information usable by memory die 200, perform one or more operations on memory die 200, and transfer data from memory die 200 to host device 105 based on the performance of said one or more operations. The local memory controller 260 may generate row signals and column address signals to activate target word line 210 and target digital line 215. The local memory controller 260 may also generate and control various voltages or currents used during operation of memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may vary and may differ for the various operations discussed in the operational memory die 200.

[0050] The local memory controller 260 is operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. In some instances, access operations may be performed by the local memory controller 260 in response to various access commands (e.g., from the host device 105) or otherwise coordinated. The local memory controller 260 is operable to perform other access operations not listed herein or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0051] During a read operation, error control block 265 can retrieve data and associated error detection or correction information from memory cell array 205. Error control block 265 can perform error correction operations based on the data and error detection or correction information. Performing error correction operations at the memory device (e.g., via error control block 265 or local memory controller 260) can improve the reliability of the memory device. Error control block 265 can be configured to perform a single type of error detection operation (e.g., SEC or SECDED error detection operation, parity bit-based error detection operation), or it can be configured to perform a combination of error detection operations (e.g., parity bit-based error detection operation and SEC or SECDED error detection operation).

[0052] In some memory architectures, accessing memory cell 205 may degrade or corrupt the logic state stored in memory cell 205. For example, a read operation performed in a DRAM architecture may partially or completely discharge the capacitor of the target memory cell. Local memory controller 260 may perform a rewrite or refresh operation to restore the memory cell to its initial logic state. Local memory controller 260 may rewrite the logic state to the target memory cell after a read operation. In some cases, a rewrite operation may be considered part of a read operation. Additionally, activating a single access line (e.g., word line 210) may interfere with the state stored in some memory cells electrically connected to said access line. Therefore, a rewrite or refresh operation may be performed on one or more memory cells that may not have been accessed yet.

[0053] The memory die 200 may support an internal (e.g., on-die) error control scheme configured to detect and, in at least some cases, correct errors in data read from the memory array 170, as referenced. Figure 1As described. In some cases, the error control scheme can be implemented by error control block 265 or some other on-die error control component (e.g., implemented by an error control circuitry system or ECC component). Furthermore, memory die 200 can indicate to the host device whether the error control scheme at memory die 200 has detected an error associated with the dataset (e.g., by storing the indication, allowing the host device to poll memory die 200 for the indication, or allowing memory die 200 to include the indication in an error report). For example, memory die 200 can store the indication in a register of the memory device. Although Figure 2 DRAM systems are typically shown, but this document refers to... Figure 2 The described techniques are applicable to any memory system that implements error control techniques.

[0054] Figure 3 An example of an error control circuitry system 300 supporting the use of registers to manage error control information is shown, according to the examples disclosed herein. The error control circuitry system 300 may be included in a memory device and may be configured to determine and indicate whether an on-die error control component (e.g., a matching circuit 315) has detected an error (e.g., an error in the data, or an error in the parity bit associated with the data) that is stored in the memory array and requested by the host device.

[0055] Error control circuitry 300 can be configured to detect errors in data stored in memory cells. In some cases, error control circuitry 300 (e.g., or another component of the memory device) can also be configured to correct errors in data by toggling data bits identified as corrupted, for example, changing corrupted data bits from "1" to "0", or vice versa. In some cases, error control circuitry 300 can be configured to detect and correct the SBE in requested data; for example, error control circuitry 300 can be configured to use SEC technology. In other cases, error control circuitry 300 can be configured to detect and correct the DBE in requested data; for example, error control circuitry 300 can be configured to use SECDED technology.

[0056] In other cases, the error control circuitry system 300 may be configured to detect three-bit errors (TBE). The examples described herein are merely illustrative, and the error control circuitry system 300 may be configured to detect up to any first number of errors and correct up to any second number of errors (which may be different from or the same as the first number). The error control circuitry system 300 may be further configured, for example, to provide modified data to an external device (e.g., a host device) after performing one or more error correction techniques on the data. The techniques described herein can be applied to ECC schemes configured to detect and / or correct any number of errors, and any specific number used herein is purely illustrative and non-limiting.

[0057] The error control circuit system 300 may include a storage correction sub-circuit 305, an access correction sub-circuit 310, and a matching circuit 315. When the error control circuit system 300 is configured to detect DBE, compared to when it is configured to implement the SEC scheme, the storage correction sub-circuit 305, access correction sub-circuit 310, and matching circuit 315 may each be configured to output additional correction bits.

[0058] Storage corrector circuit 305 can be configured to generate one or more correctors (e.g., ECCs) for data before storing it in the memory array. In some cases, the corrector generated by storage corrector circuit 305 may be referred to as a "stored ECC," a "stored corrector," or a stored "codeword." Access corrector circuit 310 can be configured to generate one or more other correctors (e.g., another ECC) after reading data from the memory array (e.g., when an external device requests data stored in the memory array). The corrector generated by access corrector circuit 310 may be referred to as a "calculated ECC," a "calculated corrector," or a "calculated codeword." In some cases, access corrector circuit 310 may use the same algorithm as storage corrector circuit 305 to generate the calculated corrector.

[0059] Matching circuit 315 can be configured to compare a stored corrector with a calculated corrector. In some cases, matching circuit 315 can compare the stored and calculated correctors by performing an XOR operation on corresponding bits of the stored and calculated correctors. If every bit of the stored and calculated correctors is the same, for example, if the stored and calculated correctors match, then matching circuit 315 can output all zeros. Otherwise, if the stored and calculated correctors do not match, matching circuit 315 can output one or more non-zero values ​​(e.g., a corresponding non-zero value can be output for each mismatched corrector value or ECC value).

[0060] In some cases, the matching circuit 315 can also be configured to output a set of data or the location of a corrupted bit in the stored corrector based on a comparison between a stored corrector and a calculated corrector. For example, when the matching circuit 315 outputs a non-zero value, each output of the matching circuit can be used to indicate the location of a corresponding bit in the stored codeword that is identified as corrupted by the memory device; for example, the output of the matching circuit 315 can represent up to 256 different bit locations. The error matching circuit 315 can be configured to indicate whether the matching circuit 315 has detected an error in the data requested from the memory array or an error otherwise associated with said data.

[0061] In some cases, if the output of the matching circuit 315 contains all zero values, the matching circuit 315 may output a first signal (e.g., a virtual ground voltage) indicating a match (or "matching signal"). And if the output of the matching circuit 315 contains one or more non-zero values, the matching circuit 315 may output a second signal (e.g., a supply voltage) indicating a mismatch (or "mismatch signal").

[0062] In some cases, when the matching circuit 315 outputs all zero values ​​indicating a match (which can be represented by the virtual ground supply voltage), the matching circuit 315 outputs a Boolean "false". And if the output of the matching circuit contains at least one non-zero value, the matching circuit 315 outputs a Boolean "true", thus indicating a mismatch.

[0063] In other cases, if the output of the matching circuit 315 contains all zero values ​​or non-zero values ​​below a certain threshold amount (e.g., containing a single non-zero value), the matching circuit 315 outputs "false," indicating a match or substantially a match. In some cases, one or some other number of non-zero values ​​below the threshold amount may indicate an error in the corrector bit rather than in the stored data. And if the output of the matching circuit 315 contains a number of non-zero values ​​that meet the threshold (e.g., two or more), the matching circuit 315 outputs "true," indicating a mismatch. In some cases, the error control circuit system 300 may rewrite the stored corrector with the calculated corrector after recognizing that the matching circuit 315 outputs a non-zero value, and the corresponding data may be transmitted to the device requesting the data.

[0064] The output of the matching circuit 315 can be signaled via the memory error line 325. In some cases, the output of the matching circuit 315 is signaled via the memory error line 325 as a "memory corrector flag". In some cases, the memory error line 325 can transmit the output of the matching circuit as a memory corrector flag to one or more externally accessible registers (e.g., mode registers). The output of the matching circuit can be stored in a register and accessed upon request (e.g., polling) by an external device (e.g., a host device). For example, the memory device can receive a command from the host device to read information stored in the register (e.g., a register read command). The memory device can output the information stored in the register (e.g., at least some information) based on the command. In other cases, the data stored in the register can be provided to the external device during some error reporting procedure.

[0065] In some instances, when the error control scheme supported by the error control circuitry 300 is overwhelmed by data containing more bit errors than the maximum number that the error control scheme can detect or correct, the error control circuitry 300 may inappropriately alias (e.g., flip or otherwise alter) bits with correct values, or otherwise introduce errors or fail to correct errors in a set of data read from the memory array. For example, when the error control circuitry 300 is configured with an SEC scheme, it may detect SBEs in requested data that actually contain two or more bit errors. In this case, the error control circuitry 300 may unsuccessfully attempt to correct the detected errors by flipping the undamaged bits in the requested data at the bit positions indicated by the matching circuitry 315, for example, converting a two-bit error to a three-bit error (which may be referred to as "aliasing"). In some cases, the error control circuitry 300 may provide the altered data to an external device (e.g., a host device) requesting the data.

[0066] When the error control circuitry 300 causes aliasing in data requested from the device, it may prevent an external device (e.g., a host device) from detecting errors in the requested data that could otherwise be detected by the external device. For example, an external device using the SECDED scheme that should have detected DBE in the requested data may not reliably detect TBE in the requested data caused by the error control circuitry 300. By identifying and indicating that the error control circuitry 300 has detected and attempted to correct (e.g., indicated and stored by a memory device in a register) errors, the external device can determine whether the memory device detected an error, attempted to correct an error, or otherwise whether aliasing occurred due to the error control circuitry 300's attempt to correct it, as described herein and regarding Figure 4 To be discussed in more detail.

[0067] Figure 4 An example of a memory system 400 supporting the use of registers to manage error control information, according to the examples disclosed herein, is shown. The memory system 400 may include a memory device 405 and a host device 425. The memory device 405 may be configured to store data; for example, the memory device 405 may be configured to store application or other data from the host device 425. The memory device 405 may include a data bus 450, a circuit system 460, an error control circuit system 415, registers 410 and 420. The error control circuit system 415 may be related to reference... Figure 3 The error control circuitry system 300 described is similarly or identically configured, for example, to detect and / or correct errors in the data requested from the host device 425 before delivering the requested data to the host device 425. The error control circuitry system 415 may be configured to store an indication of whether an error was detected in the requested data and / or at an address associated with the requested data, located at register 410.

[0068] The registers of memory device 405 (e.g., registers 410 and 420) may each contain multiple bits, each bit corresponding to a location within the respective register where data or information can be stored. For example, memory device 405 may store bit values ​​at various locations in registers 410 and 420, where each location may be associated with a corresponding type of information (e.g., configuration information, error control information, error reporting information). Memory device 405 may store values ​​(e.g., binary values) in registers 410 and 420 that may indicate or represent information associated with the corresponding location in the register. For example, memory device 405 may store a value indicating whether a communication protocol is enabled or disabled in the first bit (e.g., the first location) of register 420, and may store a value indicating whether error control configuration is enabled or disabled in the second bit (e.g., the second location) of register 420. Similarly, memory device 405 may store a value indicating error control information (e.g., indicating whether memory device 405 detected and / or corrected errors in a set of data based on the result of a corrector check operation) in the first bit (e.g., the first location) of register 410.

[0069] Memory device 405 can configure register 410 to operate in a mode (e.g., configuration) selected from a set of modes. For example, memory device 405 can configure register 410 to operate in a first mode (e.g., corrector check mode register read (MRR) mode, which may be referred to as S-Check). MRRThe memory device 405 may operate in one of these modes (e.g., the main error log mode) based on a communication protocol (e.g., a communication protocol for indicating error control information between the memory device 405 and the host device 425) and an error control configuration (e.g., a corrector check configuration).

[0070] The communication protocol can specify whether the memory device 405 is configured to transmit error control information (e.g., corrector check information associated with error control operations) to the host device 425 (e.g., directly transmitted when error control information is determined). If the communication protocol is enabled, the error control circuitry 415 can transmit error control information, such as corrector check information or results, to the host device 425. For example, the error control circuitry 415 can transmit error control information to the host device 425 via the data bus 450 or via any other communication method or channel (e.g., via circuitry 460 and circuitry 455).

[0071] In other instances, the communication protocol may be disabled, and the error control circuitry 415 may transmit error control information (e.g., corrector check information) to the host device 425 (e.g., error control information may not be transmitted directly or immediately). For example, the error control circuitry 415 may store a value indicating the error control information in register 410. The host device 425 may configure the memory device 405 to operate according to or without the communication protocol, for example, during the startup or configuration process of the host device 425 and the memory device 405. The memory device 405 may store a value in register 420 indicating whether the communication protocol is enabled or disabled (e.g., in the first bit of register 420) based on the configuration indicated by the host device 425.

[0072] Error control configurations specify methods for detecting and / or correcting errors. For example, an error control configuration could be a calibrator check configuration, an error logging configuration, a parity check configuration, or some other error control configuration. Instances of error control configurations (e.g., calibrator check configurations) can be found in references... Figure 3 The described error control circuitry system 300 is implemented. The host device 425 can configure the memory device 405 to operate according to or without the error control configuration, for example, during a startup or configuration procedure of the host device 425 and the memory device 405. The memory device 405 can store a value in register 420 indicating whether the error control configuration is enabled or disabled (e.g., in the second bit of register 420). When the error control configuration is enabled, the memory device 405 can execute one or more error control procedures associated with or indicated by the error control configuration (e.g., execute procedures as described in the reference). Figure 3(The described calibrator check). When the error control configuration is disabled, the memory device 405 can avoid executing one or more error control procedures (e.g., calibrator checks).

[0073] Memory device 405 can configure register 410 to operate in a first mode (e.g., corrector check MRR mode) or a second mode (e.g., master error log mode) based on values ​​stored in register 420. The first mode may represent a mode for storing error control information (e.g., corrector check information) in register 410. The second mode may represent a mode for transmitting error control information (e.g., corrector check information) to host device 425. In some instances, the communication protocol for transmitting error control information to host device 425 can be disabled, and error control configuration (e.g., corrector check) can be enabled. Therefore, memory device 405 (e.g., circuit system 460) can configure register 410 to operate in corrector check MRR mode (e.g., S-Check mode) based on values ​​in register 420 indicating that the communication protocol (e.g., for transmitting error control information to host device 425) is disabled and the error control configuration (e.g., corrector check) is enabled. MRR Operating in either a first mode (e.g., Corrector Check MRR mode) or a second mode (e.g., Master Error Log mode). In some instances, circuitry 460 may determine whether a communication protocol is disabled and whether an error control configuration (e.g., corrector check) is enabled based on values ​​stored in register 420. Circuitry 460 may configure register 410 to operate in either a first mode (e.g., corrector check MRR mode) or a second mode (e.g., master error log mode) based on values ​​stored in register 420. As described herein, circuitry 460 may represent any combination of circuitry within memory device 405, such as communication and control circuitry.

[0074] Memory device 405 may additionally operate according to one or more operating modes, for example, based on whether one or more operating modes are enabled or disabled (e.g., by host device 425 during, for example, a startup or configuration process). In some cases, memory device 405 may operate according to a first operating mode (e.g., master error log mode). In master error log mode, memory device 405 may log one or more errors in an error log. The one or more errors may be associated with the operation of one or more components of memory device 405. Memory device 405 may additionally or alternatively operate according to a second operating mode, which may include indicative actions by memory device 405 indicating whether one or more data pins of memory device 405 are transmitting valid data.

[0075] The memory device 405 may further configure register 410 to operate in either the first or second operating mode based on whether a first and / or second operating mode of the memory device 405 is enabled or disabled. For example, the memory device 405 may configure register 410 to operate in a corrector check MRR mode based on the determination that both the first and second operating modes of the memory device 405 are disabled. In some instances, the circuit system 460 may determine whether one or more operating modes are enabled or disabled. For example, the circuit system 460 may determine whether a first operating mode and a second operating mode are enabled or disabled.

[0076] In some instances, memory device 405 may store an indication of the output of an error control operation performed by error control circuitry system 415 at a bit or location within register 410. For example, error control circuitry system 415 may perform one or more corrector check operations (e.g., as referenced). Figure 3 (Description), and may store the result of one or more corrector check operations or an indication of the output of one or more corrector check operations in bits or positions within register 410 (e.g., when operating in corrector check MRR mode or first mode). Bits or positions within register 410 may store values ​​corresponding to the result of the corrector check operation. For example, error control circuitry 415 may pass an output signal to register 410, and register 410 may use bits or positions to store an indication of the output signal. The output signal may be as described in the reference... Figure 3 The described memory calibrator flag (e.g., an indication of whether an error has been corrected by memory device 405). For example, if memory device 405 does not correct an error (e.g., if a calibrator check operation indicates a calibrator match), the bit or position may store the value '0', and if memory device 405 corrects at least one error (e.g., if a calibrator detection operation indicates a calibrator mismatch), the bit or position may store the value '1'.

[0077] As described herein, register 410 can operate according to a mode selected from a set of modes. For example, register 410 can operate according to a first mode (e.g., corrector check MRR mode) or a second mode (e.g., master error log mode). In master error log mode, memory device 405 can indicate that one or more errors associated with the operation of one or more components of memory device 405 are recorded in an error log. For example, when operating in master error log mode, register 410 can store one or more values ​​corresponding to the error log at one or more bits of register 410, as shown in Tables 1A and 1B. Tables 1A and 1B may correspond to instances of different modes of register 410, and corresponding values ​​of bits or positions of register 410 that may correspond to different modes.

[0078] Main Error Log Fuse load Unexpected test mode mBIST Temperature sensor <![CDATA[S-Check MRR ]]> Fuse load Unexpected test mode mBIST Temperature sensor

[0079] Table 1A

[0080] Main Error Log Register bits [7] Health monitoring CA Parity Check Main Error Log <![CDATA[S-Check MRR ]]> Register bits [7] Health monitoring CA Parity Check Calibrator check

[0081] Table 1B

[0082] As shown in Tables 1A and 1B, register 410 can operate according to a first or second mode, such as the corrector check MRR mode (e.g., S-Check). MRR (or main error log mode). Each bit of register 410 (e.g., bits 0 to 7) can store information related to error control and can be based on the corresponding mode of register 410. For example, the first bit (e.g., bit [0]) can store a value corresponding to an error control operation. In S-Check MRR When operating in the main error log mode, bit [0] may store a corrector flag indicating the result of a corrector check operation and may be accessible to an external device. In some instances, the output of the error control circuitry 415 may be stored in bit [0] of register 410 and accessed upon request (e.g., polling) by an external device (e.g., host device 425). When operating in the main error log mode, bit [0] may store information associated with one or more error logs.

[0083] Bits [1] to [7] of register 410 may, for example, store additional values ​​corresponding to error information when operating in main error log mode. For example, bits [1] to [7] may each store a corresponding binary value corresponding to the detection of a defined error detected during operation of memory device 405. A binary value '1' may indicate that an error condition has occurred for the associated error, while a binary value '0' may indicate that an error condition has not yet occurred. For example, memory device 405 may use bits [1] to [7] to indicate whether an error has been detected in CA parity, in health monitoring information, via a temperature sensor, in fuse load, in a location or bit of another register (e.g., bit [7]), or whether an unexpected test mode has been detected, and other instances.

[0084] Data bus 450 may be configured to transfer data stored in memory device 405 to error control circuitry 430 (e.g., host device 425). In some cases, data bus 450 may deliver data after receiving a request for data (e.g., a read command) from host device 425. In some instances, data bus 450 may deliver the requested data after error control circuitry 415 has processed the requested data, for example, after a corrector match checker has performed a process of detecting and correcting errors in the requested data. In some instances, register 410 may store an indication of a corrector check flag, which, for example, indicates whether error control circuitry 415 has detected or corrected an error in the data requested by host device 425 by indicating a match or non-match in the corrector and / or the address associated with the requested data. Host device 425 may request the indication of the corrector check flag from memory device 405. For example, circuitry 455 of host device 425 may transmit the request to circuitry 460 of memory device 405 (e.g., a register read command). In response to the request (e.g., a register read command), circuit system 460 can access an indication of the corrector check flag from register 410 and transmit the indication to circuit system 455. In some cases, the indication may contain one or more bits. The bits included in the indication may indicate each corresponding corrector in the first set of correctors that matches the corresponding corrector in the second set of correctors, or a mismatch detected between different sets of correctors.

[0085] In some cases, memory device 405 (e.g., circuit system 460) may reset information stored in register 410 based on a register read command received from host device 425. Alternatively, memory device 405 (e.g., circuit system 460) may reset information stored in register 410 based on a command (e.g., a reset command) received from host device 425 instructing memory device 405 to reset register 410. Resetting information stored in register 410 may involve setting the register value to a corresponding default value (e.g., the value '0'). For example, memory device 405 (e.g., circuit system 405) may set the indication of a corrector check flag to a default value indicating a different corrector match.

[0086] The host device 425 can be configured to access data stored in the memory device 405 to support application functionality. The error control circuitry system 430 can be configured to detect errors in data received from the memory device 405, for example, errors in data received via the data bus 450, and indicate whether an error has been detected in data received via the channel error line 435. The error control circuitry system 430 can also be configured to correct detected errors in the received data. In some cases, the error control circuitry system 430 can be used with a reference... Figure 3 The described error control circuitry system 300 is similarly configured, as are other examples. For instance, error control circuitry system 430 may support online ECC for host device 425. In some cases, error control circuitry system 430 may include an initial correction sub-circuit that calculates the initial ECC of the application data (e.g., as part of a single data burst, which may alternatively be referred to as a data packet, data packet, or data codeword) before host device 425 writes the application data and the initial ECC to memory device 405.

[0087] In some cases, the error control circuitry 430 may also include an access correction sub-circuit that calculates the calculated ECC of the application data after receiving data from the memory device 405 (e.g., by parsing the received data burst corresponding to a previously written data burst, for a first sub-group of data bursts (the initial ECC of the payload) previously calculated (generated) by the host device 425, and a second sub-group of data bursts corresponding to parity information). Alternatively, the error control circuitry 430 may include a matching circuit for comparing the initial ECC and the calculated ECC to determine if an error exists in the received data; and an error indication circuit for indicating whether an error exists in the received data. In some cases, the error correction / detection circuitry included in the error control circuitry 430 may be configured to detect DBE and correct individual errors in the received data (e.g., the error control circuitry 430 may use SECDED technology), and each of the stored correction sub-circuit, access correction sub-circuit, and matching circuitry may be configured to output an additional correction bit.

[0088] Channel error line 435 can be configured to pass an output signal generated by error control circuitry 430 to logic component 440. In some instances, channel error line 435 may pass a "channel corrector flag" indicating whether error control circuitry 430 detected an error in a received version of data requested from memory device 405. In some cases, channel error line 435 is a conductive trace. In other cases, channel error line 435 is a wireless link. Similarly, logic component 440 may be coupled to circuitry 455, which may support communication of a "memory corrector flag" (e.g., received by circuitry 455 from memory device 405, based on register reads) from circuitry 455 to logic component 440.

[0089] Logic component 440 can be configured to determine whether one or both of error control circuitry system 430 or error control circuitry system 415 have detected an error in a processed set of data. In some cases, if a memory corrector flag (e.g., output by error control circuitry system 415 or retrieved from register 410) and a channel corrector flag (e.g., output by error control circuitry system 430) indicate that an error has been detected, logic component 440 outputs a multi-bit error (MBE) flag. For example, when both the memory corrector flag and the channel corrector flag indicate a mismatch, logic component 440 can output an MBE flag indicating that an MBE has occurred.

[0090] Data error line 445 may be configured to transmit an output signal generated by logic component 440. In some instances, logic component 440 may output an MBE flag indicating that requested data stored in memory device 405 contains multiple corrupted bits. For example, one or more other components of host device 425 may use the output on data error line 445 to determine whether to use, correct, or discard data received from the memory device. For example, if a correctable MBE occurs, host device 425 may correct the MBE. In other instances, if an uncorrectable MBE (e.g., TBE or higher) occurs, host device 425 may determine to discard the data. In some other instances, if no error occurs, or if host device 425 determines that an error has been detected or corrected, host device 425 may use the data.

[0091] The host device 425 can use the outputs of the error control circuitry system 415, register 410, error control circuitry system 430, and logic component 440 to detect errors (including MBE) in the received data, as shown in Table 2. Table 2 may correspond to an example where the memory device 405 uses SEC technology and the host device 425 uses SECDED technology, although both the memory device 405 and the host device 425 may use other error control technologies (e.g., the host device 425 may use dual error correction (DEC), triple error detection (TED), or triple error correction (TEC)) without departing from the scope of this disclosure.

[0092]

[0093] Table 2

[0094] In some instances, as shown in Table 2, the requested data (e.g., before ECC at memory device 405) may contain SBE, DBE without aliasing, DBE with aliasing, MBE, or no error. If the requested data does not contain errors, host device 425 can detect that there are no errors in the received data. If the requested data contains SBE, host device 425 can detect that the SBE has been corrected by memory device 405 (e.g., based on a “memory correction flag” received from register 410 of memory device). If the requested data contains DBE without aliasing, host device 425 can detect DBE in the received data (e.g., based on the “memory correction flag”). If the requested data contains DBE with aliasing, host device 425 can detect MBE in the received data (e.g., based on the “memory correction flag”) and may not consider the detected error as an SBE. If the requested data contains MBE, host device 425 can detect MBE in the received data and may not consider the MBE as an SBE. For example, host device 425 can detect higher-order errors (e.g., DBE and MBE) that might otherwise be undetectable because memory device 405 can indicate whether an error has been detected or corrected at memory device 405 (e.g., using error control circuitry system 415). In some instances, when a DBE or MBE is detected, host device 425 can determine that the data associated with the error should not be used.

[0095] The host device 425 can also use the outputs of register 410, error control circuitry 430, and logic component 440 to manage the processing of data received from the memory. In some instances, after receiving an indication from register 410 that no error was detected in the requested data, the host device 425 may abandon the execution of the error detection procedure for the received data. For example, if error control circuitry 415 is operating using a SEC scheme and / or link protection (e.g., Cyclic Redundancy Check (CRC) or link ECC) to transmit data over the memory channel, and error control circuitry 430 is using a SECDED scheme, the host device 425 may avoid performing ECC in some cases, as depicted in Table 3.

[0096]

[0097] Table 3

[0098] In some cases (e.g., if the host device 425 uses a corrector matching checker), if the memory corrector flag indicates that a defined type of error (e.g., SBE) has been corrected, the host device 425 further avoids performing ECC calculations.

[0099] In some instances, as shown in Table 3, the requested data (e.g., prior to ECC at memory device 405) may contain SBE, DBE without aliasing, DBE with aliasing, MBE, or no error. If the requested data does not contain an error or SBE (e.g., as indicated by the "Memory Correction Flag"), host device 425 may not calculate ECC. If the requested data contains a DBE without aliasing (e.g., as indicated by both the "Memory Correction Flag" and the "Host Correction Flag"), host device 425 may calculate ECC and detect the DBE in the received data. If the requested data contains a DBE with aliasing (e.g., as indicated by both the "Memory Correction Flag" and the "Host Correction Flag"), host device 425 may calculate ECC and detect the MBE in the received data. If the requested data contains an MBE, host device 425 may detect the MBE in the received data (e.g., as indicated by both the "Memory Correction Flag" and the "Host Correction Flag"). Based on the indication of the "memory correction flag", the host device 425 can detect higher-order errors (e.g., DBE and MBE) that might otherwise be undetectable and abandon the execution of other error detection procedures (e.g., unnecessary procedures). In some instances, when a DBE or MBE is detected, the host device 425 can determine not to use the data associated with the error.

[0100] In another instance, if the error control circuitry 415 is operating with the SECDED scheme and / or link protection (e.g., CRC or link ECC) to transmit data over the memory channel, and the error control circuitry 430 is using the SECDED scheme, the host device 425 may avoid performing ECC in some cases, as depicted in Table 4.

[0101]

[0102] Table 4

[0103] In some cases, if the memory correction flag indicates that a defined type of error has been corrected (e.g., SBE), the host device 425 further avoids performing ECC calculations.

[0104] In some instances, as shown in Table 4, the requested data (e.g., prior to ECC in memory device 405) may contain SBE, DBE, MBE, or no error. If the requested data does not contain an error or SBE (e.g., as indicated by the “Memory Correction Flag”), host device 425 may not calculate ECC. If the requested data contains a DBE (e.g., as indicated by both the “Memory Correction Flag” and the “Host Correction Flag”), host device 425 may calculate ECC and detect the DBE in the received data. If the requested data contains an MBE (e.g., as indicated by both the “Memory Correction Flag” and the “Host Correction Flag”), host device 425 may detect the MBE in the received data. Based on the indication from the correction flags in memory device 405, host device 425 may detect higher-order errors (e.g., DBE and MBE) that might otherwise be undetectable and may abandon the execution of other error detection procedures (e.g., unnecessary procedures). In some instances, when a DBE or MBE is detected, the host device 425 can determine not to use the data associated with the error.

[0105] The host device 425 can also use the outputs of register 410, error control circuitry system 430, and logic component 440 to manage data storage in memory. In some instances, after identifying that data stored in memory device 405 contains multiple bit errors, the host device 425 can blacklist the memory address associated with said data. That is, the host device 425 can instruct memory device 405 not to store its application data at the blacklisted memory address in the memory array of memory device 405.

[0106] Alternatively, host device 425 or memory device 405 may use information to perform "intelligent cleanup" of the memory array in memory device 405. Error correction techniques involving periodically reading the contents of the memory array, performing error correction on the contents of the memory array, and rewriting data identified as corrupted with the correct version of the data can be referred to as "cleanup". That is, host device 425 may trigger memory device 405 to cleanup, or memory device 405 may cleanup (e.g., only) data located at memory addresses that have been identified and / or indicated as corrupted by memory device 405. During a relevant period of time (e.g., throughout the entire operating history of the device, or after the last cleanup procedure), the cleanup procedure may skip (e.g., ignore) pages or other sets of memory cells that are not related to the identified errors.

[0107] In some instances, the host device 425 may not include the error control circuitry 430; for example, the host device 425 may not generate a host corrector flag. In this case, the host device 425 may use the output of register 410 to detect or assist in detecting errors in the received data.

[0108] For example, if the error control circuitry 415 is operating with SEC scheme and / or link protection (e.g., CRC or link ECC) to transmit data through the memory channel, and the host device 425 does not contain the error control circuitry 430, the host device 425 may avoid performing ECC in some cases, as depicted in Table 5.

[0109]

[0110] Table 5

[0111] In some instances, as shown in Table 5, the requested data (e.g., prior to ECC in memory device 405) may contain SBE, DBE without aliasing, DBE with aliasing, MBE, or no error. If the requested data does not contain an error, host device 425 may not calculate ECC. If the requested data contains an SBE, host device 425 may calculate ECC and may not detect an error. If the requested data contains a DBE without aliasing, host device 425 may calculate ECC and detect a DBE in the received data. If the requested data contains a DBE with aliasing, host device 425 may calculate ECC and detect a SBE in the received data. If the requested data contains an MBE, host device 425 may calculate ECC and may treat the ratio as an SBE. Host device 425 may detect higher-order errors (e.g., DBE and MBE) that might otherwise be undetectable. In some instances, when an error is detected, host device 425 may determine not to use the data associated with the error.

[0112] In another instance, if the error control circuitry 415 is operating with the SECDED scheme and / or link protection (e.g., CRC or link ECC) to transmit data over the memory channel, and the host device 425 does not contain the error control circuitry 430, then the host device 425 may avoid performing ECC in some cases, as depicted in Table 6.

[0113]

[0114] Table 6

[0115] In some instances, as shown in Table 6, the requested data (e.g., prior to ECC in memory device 405) may contain SBE, DBE, MBE, or no error. If the requested data does not contain an error, host device 425 may not calculate ECC. If the requested data contains an SBE, host device 425 may calculate ECC and may not detect an error. If the requested data contains a DBE, host device 425 may calculate ECC and detect a DBE in the received data. If the requested data contains an MBE, host device 425 may calculate ECC and may treat the ratio as an SBE. Host device 425 may detect higher-order errors (e.g., DBE and MBE) that might otherwise be undetectable. In some instances, when an error is detected, host device 425 may determine not to use the data associated with the error.

[0116] Figure 5 A block diagram 500 is shown illustrating a memory device 520 that supports the use of registers to manage error control information, according to an example disclosed herein. The memory device 520 may be a reference... Figures 1 to 4 Examples of aspects of the described memory device. Memory device 520 or its various components may be examples of the means described herein for performing various aspects of error control information using registers. For example, memory device 520 may include error control component 525, corrector matching component 530, register access component 535, device configuration component 540, register configuration component 545, register read component 550, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0117] Error control component 525 may be configured or otherwise support means for: generating a first set of multiple correctors at a memory device based on receiving data for storage at the memory device, the first set of multiple correctors being associated with an error control operation on the received data, each corrector in the first set containing an error correction or error detection corrector bit. In some instances, error control component 525 may be configured or otherwise support means for: generating a second set of multiple correctors at a memory device based on retrieved data, the second set of multiple correctors being associated with the retrieved data and an error control operation, each corrector in the second set containing an error correction or error detection corrector bit. Corrector matching component 530 may be configured or otherwise support means for: determining whether the first set of multiple correctors matches the second set of multiple correctors based on a comparison of the first set of multiple correctors and the second set of multiple correctors. Register access component 535 may be configured or otherwise support means for: storing an indication at a register of the memory device whether the first set of multiple correctors matches the second set of multiple correctors.

[0118] In some instances, device configuration component 540 may be configured or otherwise support means for determining that a first communication protocol for reporting information to a host device is disabled. In some instances, device configuration component 540 may be configured or otherwise support means for determining that a first error control configuration for reporting comparisons of correctors generated by a memory device according to error control operations is enabled, wherein storing an indication at a register is based on determining that the first communication protocol is disabled and the first error control configuration is enabled.

[0119] In some instances, register access component 535 may be configured or otherwise support means for accessing a second register of a memory device storing the state of a first communication protocol and the state of a first error control configuration, wherein determining that the first communication protocol is disabled and the first error control configuration is enabled is based on accessing the second register.

[0120] In some instances, device configuration component 540 may be configured or otherwise support a device for determining that an operating mode of the memory device is disabled, the operating mode comprising logging one or more errors associated with the operation of one or more components of the memory device in an error log, wherein an indication stored at a register is based on the determination that the operating mode is disabled.

[0121] In some instances, device configuration component 540 may be configured or otherwise support a device for determining that a second operating mode of the memory device is disabled, the second operating mode being used to indicate whether one or more data pins of the memory device are transmitting valid data, wherein the indication stored at the register is based on the determination that the second operating mode is disabled.

[0122] In some instances, the register read component 550 may be configured or otherwise support means for receiving commands from a host device for reading information stored in a register. In some instances, the register read component 550 may be configured or otherwise support means for outputting instructions to a host device based on the received command.

[0123] In some instances, register access component 535 may be configured or otherwise support means for resetting information stored in a register based on a command received from a host device, wherein the reset information includes setting an indication to a default value indicating a different corrector match.

[0124] In some instances, register access component 535 may be configured or otherwise support means for receiving a command from a host device to reset information stored in a register. In some instances, register access component 535 may be configured or otherwise support means for resetting information stored in a register based on a command received from a host device, wherein the reset information includes setting an indication to a default value indicating a different corrector match.

[0125] In some instances, the register is configured to operate in a mode selected from a set of modes, the set of modes including a first mode for reporting whether a first set of multiple correctors matches a second set of multiple correctors, and a second mode for logging one or more errors associated with the operation of one or more components of the memory device in an error log.

[0126] In some instances, the indication includes one or more bits, and the value of the one or more bits indicates that each of the first set of multiple correctors matches the corresponding corrector in the second set of multiple correctors.

[0127] In some instances, the indication includes one or more bits, and the value of the one or more bits indicates that at least one of the first group of multiple correctors does not match the corresponding corrector in the second group of multiple correctors.

[0128] Device configuration component 540 may be configured or otherwise support means for: determining at the memory device that a first communication protocol for reporting information to the host device is enabled or disabled. In some instances, device configuration component 540 may be configured or otherwise support means for: determining at the memory device that a first error control configuration for reporting comparisons of correctors generated by the memory device is enabled or disabled. Register configuration component 545 may be configured or otherwise support means for: configuring the registers of the memory device to operate in a first mode based on determining that the first communication protocol is disabled and the first error control configuration is enabled.

[0129] In some instances, register access component 535 may be configured or otherwise support means for accessing a second register of a memory device storing the state of a first communication protocol and the state of a first error control configuration, wherein determining that the first communication protocol is enabled and the first error control configuration is enabled is based on accessing the second register.

[0130] In some instances, device configuration component 540 may be configured or otherwise support a device for determining that an operating mode of the memory device is disabled, the operating mode including logging one or more errors associated with the operation of one or more components of the memory device in an error log, wherein configuring registers to operate in a first mode is based on determining that the operating mode is disabled.

[0131] In some instances, device configuration component 540 may be configured or otherwise support a device for determining that a second operating mode of the memory device is disabled, the second operating mode being used to indicate whether one or more data pins of the memory device are transmitting valid data, wherein the configuration register to operate in the first mode is based on determining that the second operating mode is disabled.

[0132] In some instances, the location of one or more bits within the first mode indicator register is used to store the result of an error control operation performed by the memory device.

[0133] In some instances, the registers are configured to operate in a mode selected from a set of modes, which includes a first mode and a second mode for logging one or more errors associated with the operation of one or more components of the memory device in an error log.

[0134] In some instances, error control component 525 may be configured or otherwise support means for performing error control operations to detect or correct one or more errors in data stored at a memory device. In some instances, corrector matching component 530 may be configured or otherwise support means for determining whether a first set of multiple correctors associated with an error control operation matches a second set of multiple correctors associated with the error control operation. In some instances, register access component 535 may be configured or otherwise support means for storing, at a register, an indication of whether a first set of multiple correctors matches a second set of multiple correctors based on configuring the register to operate in a first mode.

[0135] Figure 6 A block diagram 600 is shown illustrating a host device 620 that supports the use of registers to manage error control information according to an example disclosed herein. The host device 620 may be a reference... Figures 1 to 4 Examples of aspects of the described host device. Host device 620 or its various components may be examples of the means described herein for performing various aspects of error control information management using registers. For example, host device 620 may include memory device configuration component 625, register read component 630, error control component 635, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0136] The memory device configuration component 625 may be configured or otherwise support means for: writing a first indication by the host device to a first register associated with the memory device that a first communication protocol for reporting information from the memory device to the host device is disabled. In some instances, the memory device configuration component 625 may be configured or otherwise support means for: writing a second indication by the host device to a first register that a first error control configuration for reporting comparisons of correctors generated by the memory device is enabled. The register read component 630 may be configured or otherwise support means for: transmitting a command to the memory device to read information stored in a second register of the memory device based on the first communication protocol being disabled and the first error control configuration being enabled, the information indicating whether a first set of multiple correctors matches a second set of multiple correctors associated with an error control operation performed at the memory device.

[0137] In some instances, the memory device configuration component 625 may be configured or otherwise support means for: writing a third indication from the host device to a first register of the memory device that an operating mode of the memory device is disabled, the operating mode including recording one or more errors in an error log associated with the operation of one or more components of the memory device, wherein the transmission command is based on determining that the operating mode is disabled.

[0138] In some instances, the error control component 635 may be configured or otherwise support means for: determining information from a memory device that requests an indication of the result of an error control operation, wherein the transmission command is based on the determined request information.

[0139] Figure 7 A flowchart illustrating a method 700 for managing error control information using registers, based on an example disclosed herein, is shown. The operation of method 700 can be implemented by a memory device or its components as described herein. For example, it can be implemented by reference to... Figures 1 to 5 The described memory device performs the operation of method 700. In some instances, the memory device may execute an instruction set to control the functional elements of the device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0140] At 705, the method may include, at a memory device, generating a first set of multiple correctors based on receiving data for storage at the memory device, the first set of multiple correctors being associated with error control operations on the received data, each corrector in the first set including an error correction or error detection corrector bit. Operation of 705 may be performed according to the examples disclosed herein. In some examples, aspects of the operation of 705 may be referenced from... Figure 5 The error control component 525 described is executed.

[0141] At 710, the method may include, at a memory device, generating a second set of multiple correctors based on retrieved data, the second set of multiple correctors being associated with the retrieved data and error control operations, each corrector in the second set containing an error correction or error detection corrector bit. Operation of 710 may be performed according to the examples disclosed herein. In some examples, aspects of the operation of 710 may be referenced from... Figure 5 The error control component 525 described is executed.

[0142] At 715, the method may include determining whether the first set of multiple correctors matches the second set of multiple correctors based on a comparison of a first set of multiple correctors and a second set of multiple correctors. The operation of 715 may be performed according to the examples disclosed herein. In some instances, aspects of the operation of 715 may be referenced. Figure 5 The described correction matching component 530 is executed.

[0143] At 720, the method may include storing an indication at a register of the memory device whether a first set of multiple correctors matches a second set of multiple correctors. Operation of 720 may be performed according to the examples disclosed herein. In some examples, aspects of the operation of 720 may be referenced... Figure 5 The register access component 535 described is executed.

[0144] In some instances, the apparatus described herein may perform one or more methods, such as method 700. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following: at a memory device, generating a first set of multiple correctors based on receiving data for storage at the memory device, the first set of multiple correctors being associated with an error control operation on the received data, each corrector in the first set including an error correction or error detection corrector bit; at the memory device, generating a second set of multiple correctors based on retrieving data, the second set of multiple correctors being associated with the retrieved data and an error control operation, each corrector in the second set including an error correction or error detection corrector bit; determining whether the first set of multiple correctors matches the second set of multiple correctors based on a comparison of the first set of multiple correctors and the second set of multiple correctors; and storing an indication at a register of the memory device that the first set of multiple correctors matches the second set of multiple correctors.

[0145] Method 700 and some examples of the devices described herein may further include operations, features, circuitry, logic, means, or instructions for performing the following: determining that a first communication protocol for reporting information to a host device may be disabled; and determining that a first error control configuration for reporting comparisons of correctors generated by a memory device according to error control operations may be enabled, wherein storing an indication at a register may be based on determining that the first communication protocol may be disabled and the first error control configuration may be enabled.

[0146] Method 700 and some examples of the devices described herein may further include operations, features, circuitry, logic, means, or instructions for performing the following: accessing a second register of a memory device storing the state of a first communication protocol and the state of a first error control configuration, wherein determining that the first communication protocol can be disabled and the first error control configuration can be enabled may be based on accessing the second register.

[0147] Method 700 and some examples of the devices described herein may further include operations, features, circuitry, logic, means, or instructions for performing the following: determining that an operating mode of the memory device can be disabled, the operating mode comprising recording one or more errors in an error log associated with the operation of one or more components of the memory device, wherein an indication stored at a register may be based on determining that the operating mode can be disabled.

[0148] Method 700 and some examples of the devices described herein may further include operations, features, circuitry, logic, means, or instructions for performing the following: determining that a second operating mode of the memory device can be disabled, the second operating mode being used to indicate whether one or more data pins of the memory device are transmitting valid data, wherein an indication stored in a register may be based on the determination that the second operating mode can be disabled.

[0149] Method 700 and some examples of the devices described herein may further include operations, features, circuit systems, logic, means, or instructions for performing the following: receiving a command from a host device for reading information stored in a register; and outputting an indication to the host device based on the received command.

[0150] Method 700 and some instances of the devices described herein may further include operations, features, circuit systems, logic, means, or instructions for performing the following: resetting information stored in a register based on a command received from a host device, wherein the reset information includes setting an indication to a default value indicating a different corrector match.

[0151] Method 700 and some instances of the device described herein may further include operations, features, circuitry, logic, means, or instructions for performing: receiving from a host device a command for resetting information stored in a register; and resetting the information stored in the register at least in part based on the command received from the host device, wherein the reset information includes setting an indication to a default value indicating a different corrector match.

[0152] In some instances of method 700 and the device described herein, the register may be configured to operate in a mode selected from a set of modes, the set of modes including a first mode for reporting an indication of whether a first set of multiple correctors matches a second set of multiple correctors, and a second mode for logging in an error log one or more errors associated with the operation of one or more components of the memory device.

[0153] In some instances of method 700 and the device described herein, the indication includes one or more bits, and the value of the one or more bits indicates that each of the first set of multiple correctors matches the corresponding corrector in the second set of multiple correctors.

[0154] In some instances of method 700 and the device described herein, the indication includes one or more bits, and the value of the one or more bits indicates that at least one of the first set of multiple correctors does not match the corresponding corrector in the second set of multiple correctors.

[0155] Figure 8A flowchart illustrating a method 800 for managing error control information using registers, based on an example disclosed herein, is shown. The operation of method 800 can be implemented by a memory device or its components as described herein. For example, it can be implemented by reference to... Figures 1 to 5 The described memory device performs the operation of method 800. In some instances, the memory device may execute an instruction set to control the functional elements of the device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0156] At 805, the method may include determining at the memory device whether a first communication protocol for reporting information to the host device is enabled or disabled. Operation of 805 may be performed according to the examples disclosed herein. In some instances, aspects of the operation of 805 may be referenced... Figure 5 The device configuration component 540 described is executed.

[0157] At 810, the method may include determining at the memory device whether a first error control configuration for reporting comparisons of correctors generated by the memory device is enabled or disabled. Operation of 810 may be performed according to the examples disclosed herein. In some instances, aspects of the operation of 810 may be referenced... Figure 5 The device configuration component 540 described is executed.

[0158] In step 815, the method may include configuring registers of the memory device to operate in a first mode based on determining that a first communication protocol is disabled and a first error control configuration is enabled. Operation of step 815 may be performed according to the examples disclosed herein. In some instances, aspects of operation of step 815 may be referenced... Figure 5 The described register configuration component 545 is executed.

[0159] In some instances, the device described herein may perform one or more methods, such as method 800. The device may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following: determining at a memory device that a first communication protocol for reporting information to a host device is enabled or disabled; determining at a memory device that a first error control configuration for reporting comparisons of correctors generated by the memory device is enabled or disabled; and configuring registers of the memory device to operate in a first mode based on the determination that the first communication protocol is disabled and the first error control configuration is enabled.

[0160] Method 800 and some examples of the devices described herein may further include operations, features, circuitry, logic, means, or instructions for performing the following: accessing a second register of a memory device storing the state of a first communication protocol and the state of a first error control configuration, wherein determining that the first communication protocol can be enabled and the first error control configuration can be enabled may be based on accessing the second register.

[0161] Method 800 and some examples of the devices described herein may further include operations, features, circuitry, logic, means, or instructions for performing the following: determining that an operating mode of the memory device can be disabled, the operating mode including recording one or more errors in an error log associated with the operation of one or more components of the memory device, wherein configuring registers to operate in a first mode may be based on determining that the operating mode can be disabled.

[0162] Method 800 and some examples of the devices described herein may further include operations, features, circuitry, logic, means, or instructions for performing the following: determining that a second operating mode of the memory device can be disabled, the second operating mode being used to indicate whether one or more data pins of the memory device are transmitting valid data, wherein configuring a register to operate in the first mode may be based on determining that the second operating mode can be disabled.

[0163] In some instances of method 800 and the devices described herein, the location of one or more bits within the first mode indicator register is used to store the result of an error control operation performed by the memory device.

[0164] In some instances of method 800 and the device described herein, the register may be configured to operate in a mode selected from a set of modes, the set of modes including a first mode and a second mode for logging one or more errors associated with the operation of one or more components of the memory device in an error log.

[0165] Method 800 and some examples of the devices described herein may further include operations, features, circuitry, logic, means, or instructions for performing: performing an error control operation to detect or correct one or more errors in data stored in a memory device; determining whether a first set of multiple correctors associated with the error control operation matches a second set of multiple correctors associated with the error control operation; and storing, at a register and at least in part based on configuring the register to operate in a first mode, an indication of whether the first set of multiple correctors matches the second set of multiple correctors.

[0166] Figure 9A flowchart illustrating a method 900 for managing error control information using registers, based on an example disclosed herein, is shown. The operation of method 900 can be implemented by a host device or its components as described herein. For example, it can be implemented by reference to... Figures 1 to 4 The host device described in section 6 performs the operation of method 900. In some instances, the host device may execute an instruction set to control the functional elements of the device to perform the described functions. Alternatively, the host device may use dedicated hardware to perform aspects of the described functions.

[0167] In 905, the method may include a host device writing a first indication to a first register associated with a memory device that a first communication protocol for reporting information from the memory device to the host device is disabled. Operation of 905 may be performed according to the examples disclosed herein. In some examples, aspects of the operation of 905 may be referenced from... Figure 6 The memory device configuration component 625 described is executed.

[0168] In 910, the method may include writing a second indication, by the host device, to a first register, for reporting that a first error control configuration for a comparison of a corrector generated by a memory device is enabled. Operation of 910 may be performed according to the examples disclosed herein. In some instances, aspects of the operation of 910 may be referenced... Figure 6 The memory device configuration component 625 described is executed.

[0169] In 915, the method may include transmitting a command to the memory device to read information stored in a second register of the memory device, based on a first communication protocol being disabled and a first error control configuration being enabled. This information indicates whether a first set of multiple correctors matches a second set of multiple correctors associated with an error control operation performed at the memory device. Operation of 915 may be performed according to the examples disclosed herein. In some examples, aspects of operation of 915 may be referenced from... Figure 6 The register read component 630 described is executed.

[0170] In some instances, the device described herein can perform one or more methods, such as method 900. The device may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following: writing a first indication by a host device to a first register associated with a memory device that a first communication protocol for reporting information from the memory device to the host device is disabled; writing a second indication by the host device to the first register that a first error control configuration for reporting comparisons of correctors generated by the memory device is enabled; and, based on the first communication protocol being disabled and the first error control configuration being enabled, transmitting a command to the memory device to read information stored in a second register of the memory device, the information indicating whether a first set of multiple correctors matches a second set of multiple correctors associated with an error control operation performed at the memory device.

[0171] Method 900 and some examples of the devices described herein may further include operations, features, circuitry, logic, means, or instructions for performing the following: writing a third indication from the host device to a first register of the memory device that an operating mode of the memory device can be disabled, the operating mode including recording one or more errors in an error log associated with the operation of one or more components of the memory device, wherein the transmission command may be based on determining that the operating mode can be disabled.

[0172] Method 900 and some examples of the devices described herein may further include operations, features, circuit systems, logic, means, or instructions for performing the following: determining information from the memory device indicating the result of an error control operation, wherein the transmission command may be based on the determined request information.

[0173] It should be noted that the methods described herein describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0174] Describing another device. The device may include an error control circuitry system operable to perform an error control operation on data received and stored at the device, the error control circuitry system further operable to: generate a first set of multiple correctors associated with the error control operation based on the received data, each corrector in the first set including an error correction or error detection corrector bit; generate a second set of multiple correctors associated with the error control operation based on retrieved data, each corrector in the second set including an error correction or error detection corrector bit; determine whether the first set of multiple correctors matches the second set of multiple correctors based on a comparison of the first set of multiple correctors and the second set of multiple correctors; and generate a signal indicating whether the first set of multiple correctors matches the second set of multiple correctors; and a register operable to receive the signal from the error control circuitry system and store, at a location in the register, an indication of whether the first set of multiple correctors matches the second set of multiple correctors based on the received signal.

[0175] In some instances, the circuitry may be further operable to determine that a first communication protocol for reporting information to a host device can be disabled; and to determine that a first error control configuration for reporting comparisons of correctors generated by the device according to error control operations can be enabled, wherein registers are operable to receive signals and store indications based on the determination that the first communication protocol can be disabled and the first error control configuration can be enabled.

[0176] In some instances, the device may include a second register operable to store the state of a first communication protocol and the state of a first error control configuration, the circuitry operable to access information stored in the second register to determine if the first communication protocol can be disabled and the first error control configuration can be enabled.

[0177] In some instances, the circuitry may be further operable to determine that an operating mode of the device can be disabled, the operating mode comprising recording one or more errors associated with the operation of one or more components of the device in an error log, wherein registers are operable to receive signals and store indications based on the determination that the operating mode can be disabled.

[0178] In some instances, the circuitry may be further operable to determine whether a second operating mode of the device can be disabled, the second operating mode being used to indicate whether one or more data pins of the device are transmitting valid data, wherein a register is operable to receive a signal and store the indication based on the determination that the second operating mode can be disabled.

[0179] In some instances, the circuitry may be further operable to receive commands from the host device for reading information stored in a register; and to output instructions to the host device based on the received commands.

[0180] In some instances, the circuitry may be further operable to reset information stored in a register based on a command received from a host device, wherein the reset information includes setting an indication to a default value indicating a different corrector match.

[0181] In some instances, the circuitry may be further operable to receive a command from a host device for resetting information stored in a register; and to reset the information stored in the register based on the command received from the host device, wherein the reset information includes setting an indication to a default value indicating a different corrector match.

[0182] In some instances of the device, the registers may be configured to operate in a mode selected from a set of modes, the set of modes including a first mode for reporting an indication of whether a first set of multiple correctors matches a second set of multiple correctors, and a second mode for logging one or more errors in an error log associated with the operation of one or more components of the device.

[0183] In some instances of the device, the indication includes one or more bits, and a first value of the one or more bits indicates that each of the first set of multiple correctors matches the corresponding corrector in the second set of multiple correctors.

[0184] In some instances of the device, the indication includes one or more bits, and a second value of the one or more bits indicates that at least one of the first set of multiple correctors does not match the corresponding corrector in the second set of multiple correctors.

[0185] Another device is described. The device may include registers and circuitry operable to: determine whether a first communication protocol for reporting information to a host device is enabled or disabled; determine whether a first error control configuration for reporting comparisons of correctors generated by the device is enabled or disabled; and configure registers to operate in a first mode based on the determination that the first communication protocol is disabled and the first error control configuration is enabled.

[0186] In some instances, the circuitry may be further operable to receive indications from the host device of the status of the first communication protocol and the status of the first error control configuration; and to store the status of the first communication protocol and the status of the first error control configuration.

[0187] In some instances, the circuitry may be further operable to access the state of the first communication protocol and the state of the first error control configuration at a second register, wherein determining that the first communication protocol can be enabled and the first error control configuration can be enabled can be based on accessing the state of the first communication protocol and the state of the first error control configuration.

[0188] In some instances, the circuitry may be further operable to determine that an operating mode of the device can be disabled, the operating mode comprising logging one or more errors associated with the operation of one or more components of the device in an error log, wherein configuration registers for operation in a first mode may be based on the determination that the operating mode can be disabled.

[0189] In some instances, the circuitry may be further operable to determine whether a second operating mode of the device can be disabled, the second operating mode being used to indicate whether one or more data pins of the device are transmitting valid data, wherein the configuration register to operate in the first mode may be based on the determination that the second operating mode can be disabled.

[0190] In some instances of the device, the first mode indicator register contains the location of one or more bits used to store the result of an error control operation performed by the device.

[0191] In some instances of the device, the registers may be configured to operate in a mode selected from a set of modes, including a first mode and a second mode for logging one or more errors associated with the operation of one or more components of the device in an error log.

[0192] In some instances, the circuitry may be further operable to perform error control operations operable to correct one or more errors in data stored at the device; determine whether a first set of multiple correctors associated with the error control operations matches a second set of multiple correctors associated with the error control operations; and output to a register and, based on configuring the register to operate in a first mode, an indication of whether the first set of multiple correctors matches the second set of multiple correctors, wherein the register may be configured to store the indication based on being configured to operate in the first mode.

[0193] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, signals may represent buses of signals, which may have various bit widths.

[0194] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that can support the flow of signals between them at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or it can be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0195] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. When a component, such as a controller, couples other components together, it initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0196] The term "isolation" refers to the relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller separates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0197] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0198] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped, such as degenerate, semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be called a p-type FET. The channel may be sealed by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the gate, the transistor may be “turned on” or “activated.” When a voltage less than the threshold voltage of the transistor is applied to the gate, the transistor may be “turned off” or “deactivated.”

[0199] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description," not "preferred" or "superior to other instances." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0200] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0201] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or codes on or transmitted over a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed configurations such that portions of the functions are implemented in different physical locations.

[0202] For example, the various illustrative blocks and modules described in connection with this disclosure may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0203] As used herein, the word "or," as used in the claims, such as in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of"), indicates a list containing endpoints such that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0204] Computer-readable media includes both non-transitory computer-readable storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically copy data magnetically, while optical discs use lasers to copy data optically. Combinations of these are also included within the scope of computer-readable media.

[0205] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: At the memory device, a first plurality of correctors are generated at least in part based on receiving data for storage at the memory device, the first plurality of correctors being associated with error control operations on the received data, each of the first plurality of correctors including an error correction or error detection corrector bit; At the memory device, a second plurality of correctors are generated at least in part based on the retrieved data, the second plurality of correctors being associated with the retrieved data and the error control operation, each of the second plurality of correctors including an error correction or error detection corrector bit; The determination of whether the first plurality of correctors matches the second plurality of correctors is based at least in part on a comparison of the first plurality of correctors and the second plurality of correctors; and Output an indication to the host device as to whether the first plurality of correctors match the second plurality of correctors.

2. The method according to claim 1, further comprising: It was determined that a first communication protocol used to report information to the host device was disabled; as well as A first error control configuration for reporting comparisons of correctors generated by the memory device according to the error control operation is enabled, wherein the output of the indication is based at least in part on the determination that the first communication protocol is disabled and the first error control configuration is enabled.

3. The method according to claim 2, further comprising: Accessing registers of the memory device that store the state of the first communication protocol and the state of the first error control configuration, wherein determining that the first communication protocol is disabled and the first error control configuration is enabled is at least in part based on accessing the registers.

4. The method of claim 2, further comprising: The operating mode of the memory device is determined to be disabled, the operating mode including logging one or more errors associated with the operation of one or more components of the memory device in an error log, wherein the output of the indication is based at least in part on the determination that the operating mode is disabled.

5. The method of claim 2, further comprising: A second operating mode of the memory device is determined to be disabled, the second operating mode being used to indicate whether one or more data pins of the memory device are transmitting valid data, wherein the output of the indication is based at least in part on the determination that the second operating mode is disabled.

6. The method of claim 1, wherein outputting the instruction to the host device comprises: The instruction is stored in a register of the memory device; Receive a command from the host device for reading information stored in the register; as well as The instruction is output to the host device at least in part based on the receipt of the command.

7. The method of claim 6, further comprising: The information stored in the register is reset at least in part based on the command received from the host device, wherein resetting the information includes setting the indication to a default value indicating different compensator matching.

8. The method of claim 1, further comprising: Receive a command from the host device to reset the information stored in the register; as well as The information stored in the register is reset at least in part based on the command received from the host device, wherein resetting the information includes setting the register to indicate different compensator matching.

9. The method of claim 1, wherein the registers of the memory device are configured to operate in a mode selected from a set of modes, the set of modes including a first mode for reporting whether the indication of the first plurality of correctors matches the second plurality of correctors, and a second mode for logging in an error log one or more errors associated with the operation of one or more components of the memory device.

10. The method of claim 1, wherein the indication comprises one or more bits, and the value of the one or more bits indicates that each of the first plurality of correctors matches a corresponding corrector in the second plurality of correctors.

11. The method of claim 1, wherein the indication comprises one or more bits, and the value of the one or more bits indicates that at least one of the first plurality of correctors does not match a corresponding corrector in the second plurality of correctors.

12. A method comprising: At the memory device, determine whether a first communication protocol used to report information to the host device is enabled or disabled; At the memory device, it is determined whether a first error control configuration for reporting whether a first plurality of correctors matches a second plurality of correctors is enabled or disabled, wherein the first plurality of correctors are generated at least in part based on receiving data for storage at the memory device, and the second plurality of correctors are generated at least in part based on retrieving the data; as well as The registers of the memory device are configured to operate in a first mode, based at least in part on the determination that the first communication protocol is disabled and the first error control configuration is enabled.

13. The method of claim 12, further comprising: Accessing a second register of the memory device that stores the state of the first communication protocol and the state of the first error control configuration, wherein determining that the first communication protocol is disabled and the first error control configuration is enabled is at least in part based on accessing the second register.

14. The method of claim 12, further comprising: An operating mode of the memory device is determined to be disabled, the operating mode including logging one or more errors in an error log associated with the operation of one or more components of the memory device, wherein configuring the register to operate in the first mode is at least in part based on the determination that the operating mode is disabled.

15. The method of claim 12, further comprising: A second operating mode of the memory device is determined to be disabled, the second operating mode being used to indicate whether one or more data pins of the memory device are transmitting valid data, wherein configuring the register to operate in the first mode is at least in part based on the determination that the second operating mode is disabled.

16. The method of claim 12, wherein the first mode indicates the location of one or more bits in the register for storing the result of an error control operation performed by the memory device.

17. The method of claim 16, wherein the register is configured to operate in a mode selected from a set of modes, the set of modes including a first mode and a second mode for logging in an error log one or more errors associated with the operation of one or more components of the memory device.

18. The method of claim 12, further comprising: The register stores an indication of whether the first plurality of correctors match the second plurality of correctors, at least in part based on configuring the register to operate in the first mode.

19. An apparatus comprising: An error control circuitry system operable to perform error control operations on data received and stored at the device, the error control circuitry system further operable to: At least in part based on the received data, a first plurality of correctors associated with the error control operation are generated, each of the first plurality of correctors including an error correction or error detection corrector bit; A second plurality of correctors associated with the error control operation are generated, at least in part based on the retrieved data, each of the second plurality of correctors including an error correction or error detection corrector bit; Whether the first plurality of correctors matches the second plurality of correctors is determined at least in part based on a comparison of the first plurality of correctors and the second plurality of correctors; as well as Generate a signal indicating whether the first plurality of correctors match the second plurality of correctors; as well as A register operable to receive the signal from the error control circuitry and, at least in part, output an indication to the host device as to whether the first plurality of correctors match the second plurality of correctors based on the receipt of the signal.

20. The device of claim 19, wherein the device further comprises a circuit system operable to: It was determined that the first communication protocol used to report information to the host device was disabled; and A first error control configuration for reporting comparisons of correctors generated by the device according to the error control operation is determined to be enabled, wherein the register is operable to receive the signal and output the indication based at least in part on the determination that the first communication protocol is disabled and the first error control configuration is enabled.

21. The device according to claim 20, further comprising: A second register is operable to store the state of the first communication protocol and the state of the first error control configuration, and the circuitry is operable to access the information stored in the second register to determine that the first communication protocol is disabled and the first error control configuration is enabled.

22. The device of claim 20, wherein the circuitry is further operable to: The operating mode of the device is determined to be disabled, the operating mode including logging one or more errors associated with the operation of one or more components of the device in an error log, wherein the register is operable to receive the signal and output the indication at least in part based on the determination that the operating mode is disabled.

23. The device of claim 20, wherein the circuitry is further operable to: The device is determined to have a second operating mode disabled, the second operating mode being used to indicate whether one or more data pins of the device are transmitting valid data, wherein the register is operable to receive the signal and output the indication at least in part based on the determination that the second operating mode is disabled.

24. The device of claim 19, wherein the register is further operable to: The instruction is stored at the location of the register; Receive a command from the host device for reading information stored in the register; and The instruction is output to the host device at least in part based on the receipt of the command.

25. The device of claim 24, wherein the register is further operable to: The information stored in the register is reset at least in part based on the command received from the host device, wherein resetting the information includes setting the indication to a default value indicating different compensator matching.

26. The device of claim 19, wherein the register is further operable to: Receive a command from the host device for resetting information stored in the register; and The information stored in the register is reset at least in part based on the command received from the host device, wherein resetting the information includes setting the indication to a default value indicating different compensator matching.

27. The device of claim 19, wherein the register is configured to operate in a mode selected from a set of modes, the set of modes including a first mode for reporting whether the indication of the first plurality of correctors matches the second plurality of correctors, and a second mode for logging in an error log one or more errors associated with the operation of one or more components of the device.

28. The device of claim 19, wherein the indication comprises one or more bits, and a first value of the one or more bits indicates that each of the first plurality of correctors matches a corresponding corrector in the second plurality of correctors.

29. The device of claim 19, wherein the indication comprises one or more bits, and a second value of the one or more bits indicates that at least one of the first plurality of correctors does not match a corresponding corrector in the second plurality of correctors.

30. An apparatus comprising: register; as well as A circuit system that can operate as follows: Determine whether the first communication protocol used to report information to the host device is enabled or disabled; A first error control configuration for reporting whether a first plurality of correctors matches a second plurality of correctors is enabled or disabled, wherein the first plurality of correctors is generated at least in part based on receiving data for storage at the device, and the second plurality of correctors is generated at least in part based on retrieving the data; as well as The register is configured to operate in a first mode, based at least in part on the determination that the first communication protocol is disabled and the first error control configuration is enabled.

31. The device of claim 30, wherein the device further comprises a second register operable to: Receive from the host device an indication of the status of the first communication protocol and the status of the first error control configuration; and Store the state of the first communication protocol and the state of the first error control configuration.

32. The device of claim 31, wherein the circuit system is further operable to: Accessing the state of the first communication protocol and the state of the first error control configuration at the second register, wherein determining that the first communication protocol is disabled and the first error control configuration is enabled is at least in part based on accessing the state of the first communication protocol and the state of the first error control configuration.

33. The device of claim 30, wherein the circuit system is further operable to: It is determined that the operating mode of the device is disabled, the operating mode including logging one or more errors in an error log associated with the operation of one or more components of the device, wherein configuring the register to operate in the first mode is at least in part based on the determination that the operating mode is disabled.

34. The device of claim 30, wherein the circuitry is further operable to: It is determined that a second operating mode of the device is disabled, the second operating mode being used to indicate whether one or more data pins of the device are transmitting valid data, wherein configuring the register to operate in the first mode is at least in part based on the determination that the second operating mode is disabled.

35. The device of claim 30, wherein the first mode indicates the location of one or more bits in the register for storing the result of an error control operation performed by the device.

36. The device of claim 35, wherein the register is configured to operate in a mode selected from a set of modes, the set of modes including a first mode and a second mode for logging one or more errors associated with the operation of one or more components of the device in an error log.

37. The apparatus of claim 30, wherein the apparatus further comprises an error control circuitry system operable to: The register outputs an indication of whether the first plurality of correctors match the second plurality of correctors, at least in part based on the register being configured to operate in the first mode, wherein the register is configured to store the indication at least in part based on being configured to operate in the first mode.

38. A method comprising: The host device writes a first indication to a first register associated with the memory device, indicating that a first communication protocol for reporting information from the memory device to the host device is disabled; The host device writes a second indication to the first register for reporting whether a first plurality of correctors match a second plurality of correctors, wherein the first plurality of correctors are generated at least in part based on receiving data for storage in the memory device, and the second plurality of correctors are generated at least in part based on retrieving the data; as well as At least in part based on the first communication protocol being disabled and the first error control configuration being enabled, a command is transmitted to the memory device to read information stored in a second register of the memory device, the information indicating whether the first plurality of correctors match a second plurality of correctors associated with an error control operation performed at the memory device.

39. The method of claim 38, further comprising: The host device writes a third indication to the first register of the memory device that an operating mode of the memory device is disabled, the operating mode including logging one or more errors associated with the operation of one or more components of the memory device in an error log, wherein the transmission of the command is based at least in part on determining that the operating mode is disabled.

40. The method of claim 38, further comprising: Determine information from the memory device indicating the result of the error control operation, wherein transmitting the command is at least in part based on determining the requested information.

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