Semiconductor package device and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor packaging device and a manufacturing method thereof. The semiconductor packaging device comprises a first chip, a second chip, a heat conducting member between the first chip and the second chip, and a heat sink above the first chip and the second chip. The semiconductor packaging device can avoid the internal structure of the semiconductor packaging device from being broken, and is beneficial to improve the product yield.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging technology, and more specifically to semiconductor packaging apparatus and manufacturing methods thereof. Background Technology

[0002] Today, electronic devices are constantly evolving towards miniaturization, which in turn places higher demands on the miniaturization of packaging device dimensions.

[0003] In existing fan-out layer-on-substrate (RDL) packaging structures, the redistribution layer (RDL) is typically placed on the substrate. On one hand, the input / output (I / O) pitch of the redistribution layer matches the I / O pitch of the substrate, resulting in a typically larger pitch. On the other hand, the I / O pitch of the chip is typically smaller. Therefore, the inconsistent I / O pitches between the redistribution layer and the chip make direct interconnection difficult. For these reasons, chips can usually only be placed side-by-side or stacked on one side of the redistribution layer, leading to an increase in package size and hindering miniaturization of the packaged device.

[0004] Therefore, it is necessary to propose a new technical solution to solve at least one of the above-mentioned technical problems. Summary of the Invention

[0005] This disclosure provides a semiconductor packaging apparatus and a method for manufacturing the same.

[0006] In a first aspect, this disclosure provides a semiconductor packaging apparatus, comprising:

[0007] The substrate has an accommodating space;

[0008] A redistribution layer is located on the substrate, wherein a first electronic component is disposed on a first surface of the redistribution layer, and a second electronic component is disposed on a second surface of the redistribution layer, the second electronic component being located within the accommodating space.

[0009] In some alternative embodiments, the redistribution layer is recessed relative to the substrate to expose a first conductive element on the surface of the substrate, the first conductive element being electrically connected to the redistribution layer.

[0010] In some optional embodiments, the second surface of the redistribution layer is provided with an outer ring conductive element and an inner ring conductive element, the outer ring conductive element being located outside the inner ring conductive element, the inner ring conductive element being electrically connected to the second electronic component via a connecting wire, and the outer ring conductive element being electrically connected to the substrate via solder.

[0011] In some alternative embodiments, the planar dimension of the outer conductive element is larger than the planar dimension of the inner conductive element.

[0012] In some optional embodiments, adjacent outer conductive elements have a first preset interval, and adjacent inner conductive elements have a second preset interval.

[0013] In some alternative embodiments, the accommodating space is provided with filler material.

[0014] In some optional embodiments, the semiconductor packaging device further includes:

[0015] A sealing material that covers the first surface and sidewalls of the redistribution layer.

[0016] In some alternative embodiments, at least a portion of the surface of the first electronic component is exposed outside the sealing material.

[0017] In some alternative embodiments, the substrate and the redistribution layer are electrically connected by solder and / or connecting wires.

[0018] In some alternative implementations, the number of the first electronic component and / or the second electronic component is at least two;

[0019] The at least two first electronic components are stacked together, and / or the at least two second electronic components are stacked together.

[0020] Secondly, this disclosure provides a method for manufacturing a semiconductor packaging device, including:

[0021] The second surface of the redistribution layer is electrically connected to the first surface of the substrate by solder, wherein the substrate has an accommodating space, and a second electronic component is disposed on the second surface of the redistribution layer, the second electronic component being located within the accommodating space;

[0022] A filler material is formed within the accommodating space;

[0023] The first surface of the redistribution layer is electrically connected to the first surface of the substrate via a connecting line;

[0024] The first electronic component is fixed to the first surface of the redistribution layer;

[0025] A sealing material is formed on the first surface of the substrate to obtain the semiconductor package device, wherein the sealing material covers the first surface and sidewalls of the redistribution layer.

[0026] In some alternative embodiments, after forming a sealing material on the substrate to obtain the semiconductor package device, the method further includes:

[0027] An external connector is provided on the second surface of the substrate.

[0028] In the semiconductor packaging apparatus and manufacturing method disclosed herein, a first electronic component is disposed on a first surface of a redistribution layer, and a second electronic component is disposed on a second surface of the redistribution layer and located within the accommodating space of a substrate. Compared to existing chip-side-by-side or chip-stack arrangements, the second electronic component in this disclosure is embedded in the substrate, thus reducing the thickness of the packaging apparatus, which is beneficial for miniaturizing the packaging apparatus and consequently miniaturizing the electronic device. Attached Figure Description

[0029] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0030] Figure 1 This is a schematic diagram of a semiconductor packaging device in the prior art;

[0031] Figures 2-8 These are first to seventh schematic diagrams of a semiconductor packaging apparatus according to embodiments of the present invention;

[0032] Figures 9-13 This is a schematic diagram of a method for manufacturing a semiconductor packaging device according to an embodiment of the present invention.

[0033] Symbol explanation:

[0034] 11. Packaging substrate; 12. Fan-out layer; 13. Upper chip; 100. Substrate; 110. First conductive element; 120. Second conductive element; 130. Accommodation space; 200. Redundancy layer; 210. Inner ring conductive element; 220. Outer ring conductive element; 310. First electronic component; 320. Second electronic component; 400. Filler material; 500. Connecting wire; 600. Solder; 700. Sealing material; 710. Conductive post; 800. External electrical connection component; 910. Carrier; 920. Bonding head; 930. Injection part; 940. Wire bonding part. Detailed Implementation

[0035] The specific embodiments of the present invention will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by the present invention and the resulting technical effects from the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0036] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the invention. They are not intended to limit the scope of the invention and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and objectives of the invention, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity and not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention's implementation.

[0037] It should also be noted that the longitudinal section corresponding to the embodiments of this disclosure can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0038] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0039] Figure 1 This is a schematic diagram of a semiconductor packaging device in the prior art. For example... Figure 1 As shown, the semiconductor packaging device includes a packaging substrate 11, a fan-out layer 12, and multiple upper chips 13. The fan-out layer 12 is disposed on the packaging substrate 11. The input and output linewidths of the bottom surface of the fan-out layer 12 are the same as the input and output linewidths of the packaging substrate 11. The multiple upper chips 13 are stacked on the fan-out layer 12. The input and output linewidths of the upper chips 13 are different from the input and output linewidths of the fan-out layer 12. In this semiconductor packaging device, because the multiple upper chips 13 are stacked, the vertical dimension of the structure is relatively large, which is not conducive to miniaturizing the packaging device.

[0040] Figures 2-7 These are first to sixth schematic diagrams of a semiconductor packaging apparatus according to embodiments of the present invention.

[0041] Figure 2 A longitudinal cross-section of a semiconductor packaging device according to an embodiment of the present invention is shown. Figure 2 As shown, the semiconductor packaging device in this embodiment includes a substrate 100, a redistribution layer 200, a first electronic component 310, and a second electronic component 320. The substrate 100 has an accommodating space 130. The redistribution layer 200 is located on the substrate 100. The first electronic component 310 is located on the first surface of the redistribution layer 200 (i.e., Figure 2The second electronic component 320 is located on the second surface of the redistribution layer 200 (i.e., the upper surface of the redistribution layer 200). Figure 2 (The lower surface of the substrate). The second electronic component 320 is located within the accommodating space 130 of the substrate 100.

[0042] like Figure 2 As shown, the second surface of the redistribution layer 200 is provided with an outer ring conductive element 220 and an inner ring conductive element 210. The inner ring conductive element 210 is electrically connected to the second electronic component 320 via a connecting line 500, and the outer ring conductive element 220 is electrically connected to the substrate 100 via solder 600.

[0043] like Figure 2 As shown, a first conductive element 110 and a second conductive element 120 are disposed on the upper surface of the substrate 100. The first conductive element 110 is electrically connected to the conductive element on the upper surface of the redistribution layer 200 via a connecting line 500. The second conductive element 120 is electrically connected to the outer ring conductive element 220 on the lower surface of the redistribution layer 200 via solder 600. The redistribution layer 200 is recessed relative to the substrate 100 to expose the first conductive element 110 on the surface of the substrate 100, and the width of the redistribution layer 200 is smaller than the width of the substrate 100. An external electrical connection element 800 is also disposed on the lower surface of the substrate 100.

[0044] like Figure 2 As shown, there are two second electronic components 320, and the two second electronic components 320 are stacked. In other embodiments, the number of second electronic components 320 may be one, three, or five, etc., and this disclosure does not limit this. Similarly, there may be multiple first electronic components 310, and they may also be stacked.

[0045] like Figure 2 As shown, a filler material 400 is provided within the accommodating space 130 to enhance structural strength and protect the second electronic component 320 within the accommodating space 130. The filler material 400 can be a molding compound or an underfill, etc.

[0046] like Figure 2 As shown, the semiconductor packaging device also includes a sealing material 700. The sealing material 700 covers the first surface and sidewalls of the redistribution layer 200. The upper surface of the first electronic component 310 is exposed to achieve better heat dissipation.

[0047] Figure 3 A bottom view (viewed from the bottom up) of a redistribution layer 200 of a semiconductor packaging apparatus according to an embodiment of the present invention is shown. Figure 3As shown, the second surface of the redistribution layer 200 is provided with an outer ring conductive element 220 and an inner ring conductive element 210, with the outer ring conductive element 220 located outside the inner ring conductive element 210. The planar dimension of the outer ring conductive element 220 is larger than the planar dimension of the inner ring conductive element 210. The aforementioned planar dimension can be width, perimeter, or diagonal length, etc., and this disclosure does not limit it.

[0048] In this embodiment, adjacent outer conductive elements 220 are spaced by a first preset interval, and adjacent inner conductive elements 210 are spaced by a second preset interval. In one example, the first preset interval can be determined based on the planar dimensions of the outer conductive elements 220, and the second preset interval can be determined based on the planar dimensions of the inner conductive elements 210. The correspondence between the first preset interval and the planar dimensions of the outer conductive elements 220, and the correspondence between the second preset interval and the planar dimensions of the inner conductive elements 210, can be referred to the correspondence between line width and line spacing in the art, and this disclosure does not limit this.

[0049] Figure 4 A top view (viewed from the top of the substrate 100) of a semiconductor packaging apparatus according to an embodiment of the present invention is shown. Figure 4 As shown, a first conductive element 110 and a second conductive element 120 are disposed on the upper surface of the substrate 100, with the first conductive element 110 located outside the second conductive element 120. A receiving space 130 is disposed in the middle of the substrate 100. The opening of the receiving space 130 faces upward.

[0050] Figure 5 for Figure 2 One variation of the semiconductor packaging device shown herein will Figure 2 The connection between the right side of the heavy wiring layer 200 and the right side of the substrate 100 via the connecting line 500 is changed to a connection via solder 600, specifically a flip chip connection.

[0051] Figure 6 for Figure 2 This is a variation of the semiconductor packaging device shown. Figure 2 In the semiconductor packaging device shown, the sealing material 700 is a molding compound, while... Figure 6 In the semiconductor packaging device shown, the sealing material 700 is potting compound.

[0052] Figure 7 for Figure 2 This is a variation of the semiconductor packaging device shown. Figure 2 In the semiconductor packaging device shown, the upper surface of the redistribution layer 200 and the upper surface of the substrate 100 are electrically connected by a connecting line 500. Figure 7In the semiconductor packaging device shown, conductive pillars 710 are respectively provided on the upper surface of the redistribution layer 200 and the upper surface of the substrate 100. The conductive pillars 710 are further connected to the uppermost conductive line, thereby realizing the electrical connection between the upper surface of the redistribution layer 200 and the upper surface of the substrate 100.

[0053] Figure 8 for Figure 2 This is a variation of the semiconductor packaging device shown. Figure 8 In the semiconductor packaging device shown, the substrate 100 has a plurality of accommodating spaces 130, and a corresponding second electronic component 320 is disposed in each accommodating space 130. This facilitates the coordination between the lateral dimensions (i.e., XY size) and the vertical dimensions (i.e., Z height) of the semiconductor packaging device.

[0054] In the semiconductor packaging apparatus and manufacturing method disclosed herein, a first electronic component 310 is disposed on a first surface of a redistribution layer 200, and a second electronic component 320 is disposed on a second surface of the redistribution layer 200 and located within the accommodating space 130 of the substrate 100. Compared to the existing chip-side-by-side or chip-stacked arrangement, the second electronic component 320 in this disclosure is disposed in the substrate in an embedded manner, thus reducing the thickness of the packaging apparatus, which is beneficial for miniaturizing the packaging apparatus and thereby achieving miniaturization of electronic devices.

[0055] This embodiment also provides a method for manufacturing a semiconductor packaging device. For example... Figures 8-12 As shown, the method includes the following steps:

[0056] First step, such as Figure 9 As shown, the redistribution layer 200 on the carrier 910 is connected by the bonding head 920, and the second surface of the redistribution layer 200 is electrically connected to the first surface of the substrate 100 by solder 600. The substrate 100 has a receiving space 130, and a second electronic component 320 is disposed on the second surface of the redistribution layer 200, which is located within the receiving space 130.

[0057] The second step, as Figure 10 As shown, filler material 400 is formed in the accommodating space 130 by injection part 930.

[0058] The third step, as Figure 11 As shown, the first surface of the redistribution layer 200 is electrically connected to the first surface of the substrate 100 via a bonding wire 500 using a bonding tool (e.g., a soldering pin) 940.

[0059] Step four, as Figure 12 As shown, the first electronic component 310 is fixed to the first surface of the redistribution layer 200.

[0060] Fifth step, as Figure 13 As shown, a sealing material 700 is formed on the first surface of the substrate 100 to obtain a semiconductor packaging device, wherein the sealing material 700 covers the first surface and sidewalls of the redistribution layer 200.

[0061] In one example, after step five above, an external connector can be provided on the second surface of the substrate 100 to obtain, as shown below. Figure 2 The semiconductor packaging device shown.

[0062] The manufacturing method of the semiconductor packaging device in this embodiment can achieve the technical effects of the semiconductor packaging device described above, and will not be repeated here.

[0063] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual equipment due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor packaging device, comprising: A substrate having an accommodating space located inside the substrate; A redistribution layer is located on the substrate, wherein a first electronic component is disposed on the upper surface of the redistribution layer, and a second electronic component is disposed on the lower surface of the redistribution layer, the second electronic component being located within the accommodating space and embedded in the substrate; The lower surface of the redistribution layer is further provided with an outer ring conductive element and an inner ring conductive element. The outer ring conductive element is located outside the inner ring conductive element, and the inner ring conductive element is electrically connected to the second electronic component through a connecting wire. The upper surface of the substrate is provided with a first conductive element and a second conductive element. The first conductive element is electrically connected to the conductive element on the upper surface of the redistribution layer through a connecting line, and the second conductive element is electrically connected to the outer ring conductive element on the lower surface of the redistribution layer through solder. The redistribution layer is recessed relative to the substrate to expose the first conductive element, and the width of the redistribution layer is smaller than the width of the substrate.

2. The semiconductor packaging apparatus according to claim 1, wherein, The planar dimension of the outer conductive element is larger than the planar dimension of the inner conductive element.

3. The semiconductor packaging apparatus according to claim 2, wherein, The adjacent outer conductive elements have a first preset interval, and the adjacent inner conductive elements have a second preset interval; the accommodating space is provided with a filler material.

4. The semiconductor packaging apparatus according to claim 1, wherein, The semiconductor packaging apparatus further includes: A sealing material is used to cover the upper surface and sidewalls of the redistribution layer.

5. The semiconductor packaging apparatus according to claim 4, wherein, At least a portion of the surface of the first electronic component is exposed outside the sealing material.

6. The semiconductor packaging apparatus according to claim 1, wherein, The number of the first electronic component and / or the second electronic component is at least two; The at least two first electronic components are stacked together, and / or the at least two second electronic components are stacked together.

7. A method for manufacturing a semiconductor packaging device, comprising: The lower surface of the redistribution layer is electrically connected to the upper surface of the substrate using solder. The substrate has an accommodating space located within it. A second electronic component is disposed on the lower surface of the redistribution layer, located within the accommodating space and embedded in the substrate. The lower surface of the redistribution layer also has an outer conductive element and an inner conductive element. The outer conductive element is located outside the inner conductive element, and the inner conductive element is electrically connected to the second electronic component via a connecting wire. The upper surface of the substrate has a first conductive element and a second conductive element. The second conductive element is electrically connected to the outer conductive element on the lower surface of the redistribution layer via solder. The redistribution layer is recessed relative to the substrate to expose the first conductive element, and the width of the redistribution layer is smaller than the width of the substrate. A filler material is formed within the accommodating space; The conductive element on the upper surface of the redistribution layer is electrically connected to the first conductive element on the upper surface of the substrate via a connecting line. The first electronic component is fixed to the upper surface of the redistribution layer; A sealing material is formed on the upper surface of the substrate to obtain the semiconductor package device, wherein the sealing material covers the upper surface and sidewalls of the redistribution layer.

8. The method according to claim 7, wherein, After forming a sealing material on the substrate to obtain the semiconductor package device, the method further includes: An external connector is provided on the lower surface of the substrate.

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