Semiconductor structure and method of fabricating the same

Abstract

A semiconductor structure and a method of fabricating the same are disclosed. The semiconductor structure includes a first dielectric layer on a substrate, a conductive structure in the first dielectric layer and including an end portion and an extension portion connected to the end portion and extending away from the end portion. A second dielectric layer is on the first dielectric layer. A conductive plug passes through the second dielectric layer and directly contacts the extension portion of the conductive structure. A dummy plug passes through the second dielectric layer and directly contacts the end portion of the conductive structure. In a cross-section, a width of the dummy plug is less than 50% of a width of the conductive plug.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for manufacturing the same, and more particularly to a semiconductor structure including a dummy plug disposed at the end of a conductive structure and a method for manufacturing the same. Background Technology

[0002] Chemical mechanical polishing (CMP) is widely used in semiconductor manufacturing to create conductive structures, such as metal contact plugs for vertical electrical connections. However, during CMP, the metal material exposed to the polishing slurry may undergo Galvanic corrosion (or potential difference corrosion) due to the active potential difference, resulting in over-removal and pitting, causing defects such as poor subsequent contact. Summary of the Invention

[0003] The present invention aims to provide a semiconductor structure and its fabrication method, which provides a small-sized dummy plug at the end of the conductive structure, thereby reducing the problem of excessive removal of the metal material of the conductive plugs on other parts of the conductive structure during chemical mechanical polishing, resulting in dents.

[0004] An embodiment of the present invention provides a semiconductor structure including a first dielectric layer on a substrate, a conductive structure located in the first dielectric layer and including an end portion and an extension portion connected to the end portion and extending away from the end portion, a second dielectric layer on the first dielectric layer, a conductive plug passing through the second dielectric layer and in direct contact with the extension portion of the conductive structure, and a dummy plug passing through the second dielectric layer and in direct contact with the end portion of the conductive structure. In cross-section, the width of the dummy plug is less than 50% of the width of the conductive plug.

[0005] Another embodiment of the present invention provides a method for fabricating a semiconductor structure, comprising the following steps: First, a conductive structure is formed in a first dielectric layer, wherein the conductive structure includes an end and an extension connected to the end and extending away from the end. Next, a second dielectric layer is formed on the first dielectric layer. Next, a first opening is formed through the second dielectric layer directly above the extension, and a second opening is formed through the second dielectric layer directly above the end, wherein in cross-section, the width of the second opening is less than 50% of the width of the first opening. Next, a conductive material layer is formed to cover the second dielectric layer and fill the first opening and the second opening. Then, a chemical mechanical polishing process is performed to remove the conductive material layer outside the first opening and the second opening, obtaining a conductive plug located in the first opening and a dummy plug located in the second opening. Attached Figure Description

[0006] Figure 1 , Figure 2 , Figure 3 , Figure 5 , Figure 6 , Figure 7 , Figure 8 This is a cross-sectional schematic diagram of a semiconductor structure according to an embodiment of the present invention at various stages of the manufacturing process;

[0007] Figure 4 A semiconductor structure according to an embodiment of the present invention is Figure 3 A schematic diagram of another implementation of the stage shown;

[0008] Figure 9 This is a cross-sectional schematic diagram of a semiconductor structure according to another embodiment of the present invention;

[0009] Figure 10 , Figure 11 and Figure 12 This is a planar schematic diagram of a semiconductor structure according to some embodiments of the present invention.

[0010] Explanation of main component symbols

[0011] 10 base

[0012] 12 First dielectric layer

[0013] 14. Conductive Structure

[0014] 14a end

[0015] 14b Extension

[0016] 16 Etching Stop Layer

[0017] 18 Dielectric material layers

[0018] 18S surface

[0019] 20 Second dielectric layer

[0020] 22 First opening

[0021] 24 Second opening

[0022] 25. Conductive material layer

[0023] 26 First metal layer

[0024] 28 Second metal layer

[0025] 30 Conductive plugs

[0026] 32. Feigned plug

[0027] 40 Memory Stack

[0028] 42 Bottom electrode material layer

[0029] 44 Storage Layer

[0030] 46 Top electrode material layer

[0031] 48. Memory cell structure

[0032] 52 Protective Layer

[0033] 26A Liner

[0034] 26B Second Filler Metal

[0035] 28A First Filler Metal

[0036] 30S surface

[0037] 32S surface

[0038] P1 Chemical Mechanical Polishing Process

[0039] P2 Patterning Process

[0040] W1 First Width

[0041] W2 Second Width Detailed Implementation

[0042] Figure 1 , Figure 2 , Figure 3 , Figure 5 , Figure 6 , Figure 7 , Figure 8 The diagram shown is a cross-sectional schematic of a semiconductor structure at various stages of the manufacturing process according to an embodiment of the present invention. Figure 4 The illustrated semiconductor structure is based on an embodiment of the present invention. Figure 3 Another implementation of the stage shown.

[0043] Please refer to Figure 1 First, a substrate 10 is provided. Then, a first dielectric layer 12 is formed on the substrate 10, and a conductive structure 14 is formed in the first dielectric layer 12. The conductive structure 14 includes an end portion 14a and an extension portion 14b connected to one side of the end portion 14a and extending away from the end portion 14a. In other words, the conductive structure 14 extends along a horizontal plane and terminates at the end portion 14a.

[0044] The substrate 10 may be, for example, a silicon substrate, an epitaxial silicon substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. The substrate 10 may contain insulating structures, active regions, and semiconductor elements formed in the active regions, such as transistors, diodes, memory, light-emitting elements, resistors, capacitors, or inductors, which are not shown in the figure for simplicity.

[0045] The first dielectric layer 12 may include silicon oxide or a low-k dielectric material with a dielectric constant less than that of silicon oxide (approximately 3.9). An interlayer dielectric layer and conductive structures formed in the interlayer dielectric layer may be provided between the first dielectric layer 12 and the substrate 10, which are not shown in the figures for simplicity.

[0046] The conductive structure 14 can be any conductive structure used to achieve a horizontal electrical connection, such as conductive wires or conductive plates of various sizes. The conductive structure 14 may include metallic materials, such as cobalt (Co), copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), platinum (Pt), tantalum (Ta), titanium (Ti), compounds, composite layers, or alloys of the above materials, but is not limited thereto. According to one embodiment of the present invention, the conductive structure 14 includes copper.

[0047] Please continue to refer to this. Figure 1 Then, a second dielectric layer 20 is formed comprehensively on the first dielectric layer 12. According to one embodiment of the present invention, the second dielectric layer 20 may include an etch stop layer 16 and a dielectric material layer 18 located on the etch stop layer 16. The dielectric material layer 18 may include silicon oxide or a low-k dielectric material with a dielectric constant less than that of silicon oxide (approximately 3.9). The etch stop layer 16 may include a dielectric material different from that of the dielectric material layer 18, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or nitrogen-doped silicon carbide (NDC), but is not limited thereto.

[0048] Please refer to Figure 1 Next, a patterning process (e.g., photolithography and etching) can be performed to form a first opening 22 and a second opening 24 that penetrate the second dielectric layer 20 and are located directly above the extension 14b and end 24 of the conductive structure 14, respectively. Figure 1As shown, the first opening 22 has a first width W1, and the second opening 24 has a second width W2, wherein the second width W2 is less than 50% of the first width W1, for example, it may be between 20% and 40% of the first width W1. For example, when the second width W2 is approximately 55 nm, the first width W1 is less than 27 nm, for example, it may be between 11 nm and 22 nm.

[0049] Please refer to Figure 3 Next, a conductive material layer 25 can be formed on the second dielectric layer 20 using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). According to one embodiment of the present invention, the conductive material layer 25 includes first forming a first metal layer 26, which covers and fills most or completely the space of the second opening 24 along the surface of the second dielectric layer 20 (i.e., the surface of the dielectric material layer 18), the sidewalls of the first opening 22, and the bottom surface; then forming a second metal layer 28 on the first metal layer 26, and filling the first opening 22 with the second metal layer 28. According to one embodiment of the present invention, the material of the first metal layer 26 may include titanium nitride (TiN), and the material of the second metal layer 28 may include tungsten (W).

[0050] In some embodiments, such as Figure 4 As shown, an etching process can be performed after the formation of the first metal layer 26 to remove the first metal layer 26 located outside the first opening 22 and the second opening 24, exposing the surface of the second dielectric layer 20 (i.e. the surface of the dielectric material layer 18), and then the second metal layer 28 can be formed.

[0051] Please refer to Figure 5 Next, a chemical mechanical polishing process P1 is performed to remove the conductive material layer 25 outside the first opening 22 and the second opening 24 until the surface of the second dielectric layer 20 (i.e., the surface 18S of the dielectric material layer 18) is exposed, thereby obtaining a conductive plug 30 located in the first opening 22 and a dummy plug 32 located in the second opening 24. The size of the conductive plug 30 is determined by the size of the first opening 22, for example, it may have a first width W1. The size of the dummy plug 32 is determined by the size of the second opening 24, for example, it may have a second width W2. The second width W2 of the dummy plug 32 is less than 50% of the first width W1 of the conductive plug 30.

[0052] like Figure 5 As shown, the conductive plug 30 includes a first filler metal 28A and a liner 26A located between the first filler metal 28A, the second dielectric layer 20, and the conductive structure 14, wherein the first filler metal 28A is composed of a second metal layer 28, and the liner 26A is composed of a first metal layer 26. The dummy plug 32 includes a second filler metal 26B, and the second filler metal 26B is composed of a first metal layer 26.

[0053] It is worth noting that the metal materials of the conductive plug 30 and the dummy plug 32 are electrically connected to each other through the conductive structure 14. When both are simultaneously exposed to the polishing slurry in the chemical mechanical polishing process P1, an electrochemical system involving electron flow and chemical reaction (oxidation of the metal materials by the oxidant in the polishing slurry) is actually formed. The present invention provides a dummy plug 32 at the end 14a of the conductive structure 14, and makes the size of the dummy plug 32 sufficiently smaller than the size of the conductive plug 30 (the second width W2 is less than 50% of the first width W1), which can concentrate electrons (e as indicated in the figure). - This reduces the number of electrons flowing to the conductive plug 30, thereby reducing the problem of excessive galvanic corrosion and pitting in the metal material of the conductive plug 30. As a result, such as Figure 5 As shown, the surface 30S of the conductive plug 30 (the surface of the first filler metal 28A) is generally flush with or slightly lower than the surface of the second dielectric layer 20 (i.e., the surface 18S of the dielectric material layer 18). The dummy plug 32 undergoes more significant galvanic corrosion due to electron aggregation, therefore its surface 32S (i.e., the surface of the second filler metal 26B) is lower than the surface 30S of the conductive plug 30 and has a recessed profile.

[0054] Please refer to Figure 6 Next, a memory stack 40 is formed to completely cover the second dielectric layer 20, the conductive plug 30, and the dummy plug 32. According to one embodiment of the present invention, the memory stack 40 may include a bottom electrode material layer 42, a memory layer 44 on the bottom electrode material layer 42, and a top electrode material layer 46 on the memory layer 44, wherein the bottom electrode material layer 42 directly contacts the conductive plug 30 and the dummy plug 32. The bottom electrode material layer 42 and the top electrode material layer 46 respectively contain conductive materials, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or combinations thereof, but are not limited thereto. The memory layer 44 may include a magnetic tunneling junction layer (MTJ) of a magnetoresistive memory (MRAM), a variable resistance layer of a resistive memory (RRAM), or other types of memory material layers. According to one embodiment of the present invention, the memory layer 44 includes a magnetic tunneling junction layer (MTJ).

[0055] Please refer to Figure 7 Next, a patterning process P2 is performed on the memory stack 40 to form a memory cell structure 48 directly above each conductive plug 30, and the memory stack 40 directly above the dummy plug 32 is removed to expose the opening of the second opening 24. In some embodiments, such as Figure 7As shown, a remaining portion of the bottom electrode material layer 42 will fill the second opening 24 directly above the dummy plug 32, covering the surface 32S of the dummy plug 32 (i.e. the surface of the second filler metal 26B).

[0056] Please refer to Figure 8 Next, a protective layer 52 can be formed on the second dielectric layer 20 using a chemical vapor deposition (CVD) process, conformally covering the surface of the second dielectric layer 20, the sidewalls of the memory cell structure 48, and the top surface, and completely covering the dummy plug 32. The material of the protective layer 52 may include insulating materials such as silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbide nitride (SiCN), but is not limited to these.

[0057] By providing a dummy plug 32 at the end 14a of the conductive structure 14, the present invention can reduce the problem of excessive denting of the metal material of the conductive plug 30 due to galvanic corrosion. As a result, the surface of the first filler metal 28A of the conductive plug 30 can be approximately flush with or slightly lower than the surface of the second dielectric layer 20 (i.e., the surface of the dielectric material layer 18), thus obtaining a preferred electrical connection quality with the bottom electrode material layer 42.

[0058] Figure 9 The diagram shown is a cross-sectional schematic of a semiconductor structure according to another embodiment of the present invention. The difference from the foregoing embodiment is that the bottom electrode material layer 42 covering the dummy plug 32 is patterned using process P2 (see reference). Figure 7 The protective layer 52 formed thereafter can be completely removed from the dummy plug 32, so that it will fill the second opening 24 directly above the dummy plug 32 and directly contact the surface of the second filler metal 26B of the dummy plug 32.

[0059] Figure 10 , Figure 11 and Figure 12 The diagram shown is a planar schematic of a semiconductor structure according to some embodiments of the present invention. It should be understood that the number of dummy plugs and conductive plugs shown may be adjusted as needed and is not limited to the examples shown in the figure.

[0060] Please refer to Figure 10 The conductive structure 14 may be part of a conductive winding, including an end 14a and an extension 14b connected to one side of the end 14a and extending away from the end 14a. A plurality of conductive plugs 30 are disposed on the extension 14b. A plurality of dummy plugs 32 are disposed on the end 14a.

[0061] Please refer to Figure 11The conductive structure 14 may be part of a conductive plate, with the portion near the edge being the end 14a, and the portion surrounded by the end 14a being the extension 14b. A plurality of conductive plugs 30 are disposed on the extension 14b. A plurality of dummy plugs 32 may be disposed along the edge of the conductive structure 14.

[0062] Please refer to Figure 12 In some embodiments, if the distance between the conductive plug 30 and the edge of the conductive structure 14 is insufficient to accommodate the dummy plug 32, an outwardly extending portion can be designed at the edge of the conductive structure 14, i.e. Figure 12 The end 14a is marked, and then a dummy plug 32 is placed on the end 14a. Similarly, electrons can be gathered in the chemical mechanical polishing process, thereby avoiding the problem of the conductive plug 30 being excessively removed due to galvanic corrosion, resulting in a dent.

[0063] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor structure, comprising: The first dielectric layer is located on the substrate; A conductive structure is located in the first dielectric layer and includes an end and an extension connected to the end and extending in a direction away from the end; The second dielectric layer is located on the first dielectric layer; A conductive plug passes through the second dielectric layer and makes direct contact with the extension of the conductive structure; as well as A dummy plug passes through the second dielectric layer and directly contacts the end of the conductive structure, wherein in cross-section, the width of the dummy plug is less than 50% of the width of the conductive plug, and the top surface of the dummy plug is lower than the top surface of the conductive plug.

2. The semiconductor structure of claim 1, wherein the width of the dummy plug is between 20% and 40% of the width of the conductive plug.

3. The semiconductor structure of claim 1, wherein the top surface of the conductive plug is flush with or below the surface of the second dielectric layer.

4. The semiconductor structure as claimed in claim 1, further comprising: The memory cell structure is located on the conductive plug; as well as A protective layer is located on the second dielectric layer and the dummy plug, and covers the top surface and sidewalls of the memory cell structure.

5. The semiconductor structure of claim 4, wherein the protective layer is in direct contact with the top surface of the dummy plug.

6. The semiconductor structure of claim 4, further comprising a bottom electrode material layer located on the top surface of the dummy plug, wherein the protective layer is in direct contact with the top surface of the bottom electrode material layer.

7. The semiconductor structure of claim 1, wherein the conductive plug includes a first filler metal, the dummy plug includes a second filler metal, the first filler metal is separated from the second dielectric layer and the conductive structure by a liner and does not directly contact them, the second filler metal is in direct contact with the second dielectric layer and the conductive structure, and the second filler metal and the liner are made of the same material.

8. The semiconductor structure of claim 7, wherein the first filler metal comprises tungsten (W), the second filler metal and the substrate comprise titanium nitride (TiN).

9. The semiconductor structure of claim 7, wherein the top surface of the first filler metal is lower than the top surface of the second filler metal.

10. A method for fabricating a semiconductor structure, comprising: A conductive structure is formed in a first dielectric layer, wherein the conductive structure includes an end and an extension connected to the end and extending in a direction away from the end; A second dielectric layer is formed on the first dielectric layer; A first opening is formed through the second dielectric layer directly above the extension, and a second opening is formed through the second dielectric layer directly above the end, wherein in cross-section, the width of the second opening is less than 50% of the width of the first opening; A conductive material layer is formed to cover the second dielectric layer and fill the first opening and the second opening; as well as A chemical mechanical polishing process is performed to remove the conductive material layer outside the first opening and the second opening, thereby obtaining a conductive plug in the first opening and a dummy plug in the second opening.

11. The method of fabricating a semiconductor structure as claimed in claim 10, wherein the top surface of the dummy plug is lower than the top surface of the conductive plug.

12. The method of fabricating a semiconductor structure as claimed in claim 11, wherein the top surface of the conductive plug is flush with or below the surface of the second dielectric layer.

13. The method for fabricating a semiconductor structure as claimed in claim 10, wherein the step of forming the conductive material layer comprises: A first metal layer is formed, which covers the surface of the second dielectric layer, the sidewalls of the first opening, and the bottom surface, and fills the second opening. as well as A second metal layer is formed on top of the first metal layer and fills the first opening.

14. The method of fabricating a semiconductor structure as claimed in claim 13, wherein the first metal layer comprises titanium nitride (TiN) and the second metal layer comprises tungsten (W).

15. The method of fabricating a semiconductor structure as claimed in claim 13, further comprising removing the first metal layer outside the first opening and the second opening before forming the second metal layer.

16. The method for fabricating a semiconductor structure as described in claim 10, further comprising: A memory stack is formed on the second dielectric layer and covers the conductive plug and the dummy plug, wherein the memory stack includes: Bottom electrode material layer; The storage layer is located on the bottom electrode material layer; and The top electrode material layer is located on the storage layer; The memory stack is patterned to form a memory cell structure directly above the conductive plug, and the memory stack directly above the dummy plug is removed; and A protective layer is formed, covering the second dielectric layer and the sidewalls and top surface of the memory cell structure, and covering the dummy plug.

17. The method of fabricating a semiconductor structure as claimed in claim 16, wherein the remaining portion of the bottom electrode material layer is located on the dummy plug, and the top surface of the remaining portion is in direct contact with the protective layer.

18. The method of fabricating a semiconductor structure as claimed in claim 16, wherein the protective layer is in direct contact with the top surface of the dummy plug.

19. The method of fabricating a semiconductor structure as claimed in claim 10, wherein the width of the second opening is between 20% and 40% of the width of the first opening.

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