Semiconductor packaging

Abstract

This invention discloses a semiconductor package comprising: a bottom package including an application processor die surrounded by a molding compound; a top package mounted on the bottom package; a top redistribution layer structure disposed between the top package and the bottom package; a plurality of through-holes disposed in the molding compound for electrically connecting the top package to the application processor die, wherein each of the plurality of through-holes has an elliptical or rectangular shape when viewed from above; and a bottom redistribution layer structure wherein the application processor die and the plurality of through-holes are interconnected to the bottom redistribution layer structure. The present invention features smaller spacing between the through-holes, bringing them closer to the center, thus shortening the path for the pads on the application processor die to connect to the through-holes, thereby reducing the connection length to the memory package.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a semiconductor package. Background Technology

[0002] The rapid growth of emerging markets for mobile applications has made packaging technology more challenging than ever, driving advanced silicon (Si) node, finer bump pitch, and finer line width and pitch substrate manufacturing capabilities to meet the growing demands of mobile devices.

[0003] Package-on-Package (PoP) technology has been used to combine discrete packages. A PoP typically consists of two packages; for example, a top package containing memory chips is mounted on a bottom package containing logic chips. The top package can be connected to the bottom package via an interposer.

[0004] The industry urgently needs a novel PoP packaging structure, in which the length of the connection path between the logic chip and the memory chip needs to be further shortened to improve electrical performance. Summary of the Invention

[0005] In view of this, the present invention provides a semiconductor package with a reduced connection length to solve the above problems.

[0006] According to a first aspect of the present invention, a semiconductor package is disclosed, comprising:

[0007] Bottom package, including the application processor die surrounded by molding compound;

[0008] Top package, mounted on the bottom package;

[0009] A top redistribution layer structure is disposed between the top package and the bottom package;

[0010] Multiple through-holes are disposed in the molding compound for electrically connecting the top package to the application processor die, wherein each of the multiple through-holes has an elliptical or rectangular shape when viewed from above; and

[0011] A bottom redistribution layer structure in which the application processor die and the plurality of through-hole molded vias are interconnected to the bottom redistribution layer structure.

[0012] According to a second aspect of the present invention, a semiconductor package is disclosed, comprising:

[0013] Bottom packaging, comprising two top substrate layers, a middle molding compound, and a bottom multilayer substrate, is used to package the application processor die.

[0014] Top package, mounted on the bottom package;

[0015] Multiple through-holes are disposed in the intermediate molding compound for electrically connecting the top package to the application processor die, wherein each of the multiple through-holes has an elliptical or rectangular shape when viewed from above.

[0016] According to a third aspect of the present invention, a semiconductor package is disclosed, comprising:

[0017] At least one logic chip is surrounded by the molding compound;

[0018] A memory device disposed near the at least one logic die;

[0019] Multiple vias surround the at least one logic die for electrically connecting the at least one logic die to the memory device, wherein each of the multiple vias has an elliptical or rectangular shape when viewed from above.

[0020] The semiconductor package of the present invention comprises: a bottom package including an application processor die surrounded by a molding compound; a top package mounted on the bottom package; a top redistribution layer structure disposed between the top package and the bottom package; a plurality of through-holes disposed in the molding compound for electrically connecting the top package to the application processor die, wherein each of the plurality of through-holes has an elliptical or rectangular shape in plan view; and a bottom redistribution layer structure wherein the application processor die and the plurality of through-holes are interconnected to the bottom redistribution layer structure. Each through-hole is shaped as an ellipse or rectangle, with the width of the ellipse or rectangle being smaller than its length. This makes the spacing between through-holes smaller than the spacing between circular through-holes in the prior art. Consequently, the width (or size) occupied by the same number of through-holes is smaller, and these through-holes are brought closer to the center. This shortens the path when the pads on the application processor die are connected to the through-holes, thereby reducing the connection length between the application processor die and the through-holes, as well as the connection to the memory package. Attached Figure Description

[0021] Figure 1 This is a schematic cross-sectional view showing an exemplary semiconductor package according to an embodiment of the present invention;

[0022] Figure 2 This is a partial top view of the TMV layout around the AP grain according to an embodiment of the present invention.

[0023] Figure 3 The interleaved TMVs are displayed as a 3x2 array;

[0024] Figure 4 An example HBPoP is shown;

[0025] Figure 5 An exemplary semiconductor package is shown;

[0026] Figure 6 Another exemplary semiconductor package is shown; and

[0027] Figure 7 This illustrates yet another exemplary semiconductor package. Detailed Implementation

[0028] In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form part of the invention, and which illustrate specific preferred embodiments in which the invention can be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice them, and it should be understood that other embodiments may be utilized, and mechanical, structural, and procedural changes may be made, without departing from the spirit and scope of the invention. Therefore, the following detailed description should not be construed as limiting, and the scope of the embodiments of the invention is defined only by the appended claims.

[0029] It will be understood that although the terms “first,” “second,” “third,” “primary,” “secondary,” etc., may be used herein to describe various components, parts, regions, layers, and / or portions, these components, parts, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one component, part, region, layer, or portion from another. Therefore, without departing from the teachings of the inventive concept, the first or primary component, part, region, layer, or portion discussed below may be referred to as a second or secondary component, part, region, layer, or portion.

[0030] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “under,” “above,” and “above” may be used herein to describe the relationship of a component or feature to it. Another component or feature is shown in the figure. In addition to the orientation described in the figure, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly. Additionally, it will be understood that when a “layer” is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more intermediate layers.

[0031] The terms “about,” “roughly,” and “about” generally mean a range of ±20%, ±10%, ±5%, ±3%, ±2%, ±1%, or ±0.5% of a specified value. The specified values ​​in this invention are approximate. Unless otherwise specified, the specified values ​​include the meanings of “about,” “roughly,” and “about.” The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular terms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0032] What will be understood is that when a “component” or “layer” is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another component or layer, it can be directly on, connected to, coupled to, or adjacent to the other component or layer, or there may be intermediate components or layers. Conversely, when a component is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another component or layer, there are no intermediate components or layers.

[0033] Note: (i) the same features will be represented by the same reference numerals throughout the figures and will not necessarily be described in detail in every figure in which they appear, and (ii) a series of figures may show different aspects of a single item, each of which is associated with various reference labels that may appear throughout the series or only in selected figures of the series.

[0034] This invention relates to semiconductor packages with reduced (or shorter) connection lengths, suitable for applications including, but not limited to, fan-out package-on-package (PoP) and high-bandwidth package-on-package (HBPoP).

[0035] Fan-out packaging can be defined as any package that has connections fanned out from the chip surface, thus supporting more external I / O (input / output). Traditional fan-out packages use epoxy molding compounds to fully embed the die, rather than placing them on a substrate or interposer. Fan-out packaging typically involves dicing chips on a silicon wafer, then precisely positioning the known good chips onto a thin "reconstruction" or carrier wafer, molding it, forming a redistribution layer (RDL) on top of the molded area (chip and fan-out area), and then forming solder balls on top. HBPoP typically includes a top 2-layer substrate, middle molding, and a bottom 3-layer substrate (three-layer substrate) to package an application processor (AP) chip. Compared to fan-out PoP, HBPoP AP packaging is less expensive.

[0036] Figure 1 This is a schematic cross-sectional view showing an exemplary semiconductor package according to an embodiment of the present invention. Figure 1 As shown, the semiconductor package 1 can be a fan-out PoP, but is not limited thereto. According to one embodiment, the semiconductor package 1 may include a bottom package 10 and a top package 20 mounted on the bottom package 10. For example, the bottom package 10 includes an application processor (AP) die 100 surrounded by molding compound 110. A dielectric layer DL may be disposed on the active surface (active surface) 100 of the AP die 100. A plurality of conductive bumps or pillars 101 may be disposed in the dielectric layer DL and may be electrically coupled to the active surface 100a. After performing a grinding or chemical mechanical polishing (CMP) process, the top surface (upper surface) S1 of the dielectric layer DL may be coplanar (or flush) with the top surface (upper surface) S2 of the surrounding molding compound 110.

[0037] According to one embodiment of the present invention, a redistributed layer (RDL) structure RS can be disposed on the top surface (upper surface) S1 of the dielectric layer DL and the top surface S2 of the surrounding molding compound 110. The RDL structure RS may include multilayer interconnects IS. According to one embodiment of the present invention, a plurality of ball pads PB can be distributed on the top surface S3 of the RDL structure RS. Solder balls SB can be mounted on each ball pad PB for further interconnection. Optionally, passive components PD, such as decoupling capacitors or any suitable surface mount device (SMD), can be disposed on the top surface S3 of the RDL structure RS between the solder balls SB.

[0038] According to one embodiment of the present invention, a plurality of through molding vias (TMVs) 110v are disposed in molding compound 110 to electrically connect an RDL structure RS to an overlying redistribution layer (RDL) structure RT (RDL structures RS and RT are respectively disposed on opposite sides of molding compound 110). According to one embodiment, the RDL structure RT may include at least a plurality of bump pads PI and metal traces PT for connecting the bump pads PI and the TMVs 110v. A top package 20 is mounted on the bump pads PI via bumps ST, such as microbumps. According to one embodiment of the present invention, the top package 20 may be, for example, a DRAM package, such as a DDR DRAM package. In some embodiments, the TMVs 110v may be insert pillars or solder joints. The top package 20 may be a memory package.

[0039] Please refer to Figure 2 . Figure 2 This is one embodiment of the present invention. Figure 1 A partial top-view diagram of the TMV 110v surrounding the AP grain 100. (See diagram below.) Figure 2 As shown, when viewed from above, each TMV 110v can have an elliptical or rectangular shape. Each TMV 110v extends along the second direction D2 or the direction from the via to the grain 100. The maximum length (dimension) of each TMV 110v is L, and the maximum width (dimension) of each TMV 110v is W, where L is greater than W; the above description of shape and size applies to elliptical or rectangular shapes.

[0040] According to one embodiment, the TMV 110v in an exemplary 3x2 array may have a horizontal spacing P1 of W+Sh along a first direction D1 (i.e., a direction parallel to the adjacent side edges of the AP grain 100), where Sh is the spacing between two adjacent TMV 110v along the first direction D1. According to one embodiment, the TMV 110v in the 3x2 array may have a vertical spacing P2 of L+Sv along a second direction D2, where Sv is the spacing between two adjacent TMV 110v along the second direction D2. According to one embodiment, the first direction D1 and the second direction D2 are orthogonal. According to one embodiment of the invention, the vertical spacing P2 of the TMV 110v is greater than the horizontal spacing P1.

[0041] By providing this configuration, the TMV 110v can be arranged more tightly around the AP die 100 than in the prior art. Due to the elliptical shape of the TMV 110v, especially those located in the peripheral or corner areas of the semiconductor package 1, the connection length between the memory package (top package) 20 and the AP die 100 can be reduced. Specifically, as... Figure 2 As shown, each TMV 110v is configured as an ellipse or rectangle, with the width of the ellipse or rectangle being smaller than its length. This makes the spacing P1 between TMV 110v smaller than the spacing between circular TMV 110v in the prior art. This results in a smaller width (or size) occupied by the same number of TMV 110v (ellipse or rectangle), causing these TMV 110v to be closer to the center. This shortens the path when the pads on the AP die 100 connect to the TMV 110v (ellipse or rectangle), thereby reducing the connection length between the AP die 100 and the TMV 110v (ellipse or rectangle), as well as the connection to the memory package (top package) 20. Figure 2 In the example shown, the pads mentioned above can be pads located on the side of AP die 100 adjacent to or close to TMV 110v. For TMV 110v located on different sides of AP die 100 (close to or adjacent to), the direction extending perpendicular to the corresponding side of AP die 100 is the length direction of TMV 110v (second direction), while the direction extending parallel to the corresponding side of AP die 100 is the width direction of TMV 110v (first direction). The width of TMV 110v is set to be smaller than its length. This allows for a smaller distance occupied in the width direction when the same TMV 110v is placed on the corresponding side of AP die 100, meaning the TMV 110v (array) is arranged more compactly in the width direction. This allows the pads on the corresponding side of AP die 100 to be connected to TMV 110v with a shorter path (shorter wiring length), reducing the connection path.

[0042] For simplicity, a single 3x2 array of TMV 110v is shown in the figure. According to one embodiment of the invention, two rows of TMV 110v can be aligned with each other in the second direction D2. According to another embodiment, as... Figure 3 As shown, the 3x2 array of TMV 110v can be staggered, meaning the front and back rows are offset. This approach allows for different design requirements and increases design flexibility.

[0043] like Figure 2 and Figure 3 The elliptical TMV 110v shown can be used in other types of semiconductor packages, such as HBPoP. Figure 4 An exemplary HBPoP is illustrated. (As shown) Figure 4 As shown, HBPoP 2 has a bottom package 30 and a top package 40, such as a DRAM package mounted on the bottom package 30. The bottom package 30 includes a top two-layer (two-layer or two-layer) substrate 310, an intermediate molding compound (intermediate molded part or molding compound) 320, and a bottom multilayer substrate 330 for packaging an application processor (AP) die 300. Similarly, a plurality of TMVs 320v are disposed around the AP die 300. The TMVs 320v are disposed in the molding compound 320 and are used for electrical connection between the top two-layer (two-layer or two-layer) substrate 310 and the bottom multilayer substrate 330. The TMVs 320v disposed in the intermediate molding compound electrically connect the top package to the AP die, wherein each of the plurality of TMVs has an elliptical shape, a rectangular shape, or a combination thereof. Figure 2-3The TMV 110v shown is disposed on the upper side of AP die 100. At this time, the first direction D1 is the width direction of AP die 100. In order to reduce the size occupied in the width direction when arranging the same TMV 110v, according to the above embodiment of the present invention, the size of TMV 110v in the first direction D1 (that is, the width direction of AP die 100 at this time, or the width direction of the side of AP die 100 that is close to or adjacent to the TMV 110v) can be reduced (for example, set as an ellipse or rectangle in this embodiment), so that the width (or size) of each TMV 110v in the first direction D1 is smaller than the length (or size) of each TMV 110v in the second direction D2, wherein the second direction D2 is perpendicular to the first direction D1. For the other sides of the AP die 100, the dimensions can be configured accordingly as described above. Specifically, in the width direction (parallel to that side) of the corresponding AP die 100, the size of each TMV 110v is smaller (the size of each TMV 110v in the width direction is smaller than the size of each TMV 110v in the direction perpendicular to that width direction (i.e., perpendicular to that side)). By employing the above embodiments of the present invention, the size of each TMV 110v in the direction parallel to the corresponding side of the AP die 100 (i.e., the width direction) can be reduced (smaller than the size in the direction perpendicular to the corresponding side of the AP die 100 (i.e., the length direction)). This results in a smaller width direction occupied by the same number of TMV 110v, leading to a more compact arrangement of the TMV 110v. Consequently, the line length connecting the pads on the corresponding side of the AP die 100 to the TMV 110v will be shorter, significantly reducing the signal transmission path and improving the electrical performance of the semiconductor package.

[0044] Figure 5 An exemplary semiconductor package is shown. Figure 5 As shown, semiconductor package 3 includes an AP die 500 encapsulated by molding compound 520 and surrounded by a via substrate 522 having multiple vias 522v. The AP die 500 and a memory device 600, such as a DRAM package, are mounted side-by-side on substrate 530. A top bridge substrate 510 is disposed on the via substrate 522 and molding compound 520. The signal path PP shows that signals from the AP die 500 are transmitted through the left substrate 530, the via substrate 522 and vias 522v, the top bridge substrate 510, the right via (or through-hole) substrate 522 and vias 522v, and substrate 530 to the memory die 600. Figure 2 and Figure 3The rectangular or elliptical vias (or through-holes) shown 522v can significantly reduce the connection length of the signal transmission path PP (reduce the wiring length), thus improving the electrical performance of the semiconductor package 3.

[0045] Figure 6 Another exemplary semiconductor package is shown. (e.g.) Figure 6 As shown, semiconductor package 4 includes a fan-out chip package 70 mounted on substrate 80. The fan-out chip package 70 and a memory package (top package), such as a DRAM package, 90 are mounted side-by-side on the substrate. According to some embodiments, the fan-out chip package 70 may include two logic dies 701 and 702 interconnected to a bridging via substrate 703 and a peripheral via structure 704 surrounding the bridging via substrate 703. An RDL structure 705 is disposed between the bridging via substrate 703 and substrate 80, and between the peripheral via structure 704 and substrate 80. Figure 2 and Figure 3 The rectangular or elliptical vias shown 704v can significantly improve the electrical performance of semiconductor package 4 because the connection can reduce the length of the signal transmission path.

[0046] Figure 7 This illustrates yet another exemplary semiconductor package. For example... Figure 7 As shown, the semiconductor package 5 may include logic dies 1001 and 1002, and a memory die 1003 interconnected via an RDL structure 1004. The RDL structure 1004 is further interconnected to a through-silicon via (TSV) die 1005 surrounded by a molding compound 1006. The TSV die 1005 includes a plurality of TSVs 1005v passing through it. A plurality of TMVs 1006v are disposed in the molding compound 1006 for signal transmission. The TMVs 1006v can be electrically connected to the TSV die 1005 via a bottom RDL structure 1007. Furthermore, the TSV die 1005 can be electrically connected to the logic dies 1001 and 1002 and the memory die 1003 via the bottom RDL structure 1007, the TMVs 1006v, and the RDL structure 1004. Figure 2 and Figure 3 The rectangular or elliptical vias (or through holes) shown can significantly improve the electrical performance of the semiconductor package 5 because they can reduce the connection length of the signal transmission path.

[0047] Those skilled in the art will readily observe that numerous modifications and alterations can be made to the apparatus and method while maintaining the teachings of this invention. Therefore, the foregoing disclosure should be interpreted as being limited only by the scope and limits of the appended claims.

Claims

1. A semiconductor package, characterized by, Comprising: a bottom package including an application processor die surrounded by a molding compound; a top package mounted on the bottom package; a top redistribution layer structure disposed between the top package and the bottom package; a plurality of through-mold vias disposed in the molding compound for electrically connecting the top package with the application processor die, wherein each of the plurality of through-mold vias has an elliptical or rectangular shape when viewed from above; and a bottom redistribution layer structure, wherein the application processor die and the plurality of through-mold vias are interconnected to the bottom redistribution layer structure; wherein the plurality of through-mold vias have a horizontal pitch along a first direction and a vertical pitch along a second direction, wherein the vertical pitch is greater than the horizontal pitch.

2. The semiconductor package of claim 1, wherein, The plurality of through-mold vias are arranged along the second direction.

3. The semiconductor package of claim 1, wherein, The plurality of through-mold vias are arranged in a staggered manner.

4. The semiconductor package of claim 1, wherein, A plurality of solder balls are disposed on a surface of the bottom redistribution layer structure.

5. A semiconductor package, characterized by, Comprising: a bottom package including a top two-layer substrate, an intermediate molding compound, and a bottom multi-layer substrate for packaging an application processor die; a top package mounted on the bottom package; a plurality of through-mold vias disposed in the intermediate molding compound for electrically connecting the top package with the application processor die, wherein each of the plurality of through-mold vias has an elliptical or rectangular shape when viewed from above; wherein the plurality of through-mold vias have a horizontal pitch along a first direction and a vertical pitch along a second direction, wherein the vertical pitch is greater than the horizontal pitch.

6. A semiconductor package, characterized by, Comprising: at least one logic die surrounded by a molding compound; a memory device disposed adjacent to the at least one logic die; a plurality of vias surrounding the at least one logic die for electrically connecting the at least one logic die to the memory device, wherein each of the plurality of vias has an elliptical or rectangular shape when viewed from above; wherein the plurality of vias have a horizontal pitch along a first direction and a vertical pitch along a second direction, wherein the vertical pitch is greater than the horizontal pitch.

7. The semiconductor package of claim 6, wherein the semiconductor package is a flip chip semiconductor package. Further comprising: a top bridge substrate interconnected with the plurality of vias.

8. The semiconductor package of claim 6, wherein the semiconductor package is a flip chip semiconductor package. Further comprising: a bridge via substrate interconnected with the at least one logic die.

9. The semiconductor package of claim 6, wherein, Further comprising: a through-silicon via die surrounded by the molding compound, wherein the plurality of vias are disposed in the molding compound.

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