Select gate transistor with segmented channel fin

Abstract

The present disclosure relates to select gate transistors with segmented channel fins. Various applications can include memory devices designed to provide enhanced gate-induced drain leakage (GIDL) current during memory erase operations. Enhanced operations can be provided to strings of memory cells by enhancing the electric field in the channel structure of a select gate transistor. The channel structure can be implemented as a segmented portion for the drain and a portion opposite the gate. The segmented portion includes one or more fins and one or more non-conductive regions, where both the fins and non-conductive regions extend vertically from the portion opposite the gate. Variations of the boundary region of the portion opposite the gate with the segmented portion can include a sharp corner region extending from the fins to the portion opposite the gate or a rounded boundary region under the non-conductive regions. Such select gate transistors can be formed using a single photomask process. Additional devices, systems, and methods are discussed.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory devices and operations of memory devices, and more specifically, to structures and methods related to erase operations of memory devices. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory requires power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), as well as other types of memory. Non-volatile memory retains stored data when no power is applied and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistive variable memory, such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), or three-dimensional (3D) XPoint. TM Memory, and other types of memory. 3D X-point memory is a non-volatile memory (NVM) technology with a stackable cross-grid data access array, where bit storage is based on changes in volume resistance.

[0003] Flash memory is used as non-volatile memory for a wide range of electronic applications. Flash memory devices typically contain one or more sets of single-transistor, floating-gate, or charge-trapping memory cells that allow for high memory density, high reliability, and low power consumption. Two common types of flash memory array architectures include NAND and NOR architectures, named after the logical form of the basic memory cell configuration in which each is arranged. The memory cells of a memory array are typically arranged in a matrix. In one example, the gate of each floating-gate memory cell in a row of the array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drain of each memory cell in a string of the array is coupled together in source-to-drain series between the source line and the data line.

[0004] Using a 3D architecture for memory devices (such as NAND memory devices) can provide increased capacity beyond that of planar structures. Memory arrays for 3D structures can comprise memory cells stacked vertically as strings of memory cells. When one or more strings are selected to access a given memory cell, gating structures can be located at the top and bottom of these strings, with memory cells storing data between them. The gating structure can include a select-gate transistor located at one end of the string whose drain is coupled to a data line, such as a bit line, and at the other end of the string whose source is coupled to a source line.

[0005] In many NAND flash memory devices, the erase operation on a string of memory cells is performed by applying a high positive voltage to the string body. In the case of a 3D NAND architecture, with the string body of the memory cells electrically isolated, holes can be generated and implanted in the string body to maintain a positive potential in the string during the erasure of memory cells. Gate-induced drain leakage (GIDL) is a technique for achieving high-performance and reliable erase operations. It is a leakage mechanism in devices such as insulated-gate field-effect transistors (IGFETs), which is attributed to the large field effect in the drain junction. Existing methods for enhancing GIDL operation in 3D NAND flash memory devices involve attempting to optimize the device doping distribution of the select transistor for a string of memory cells to cause abrupt junction changes in the select transistor. As the number of memory cell layers in a vertical string in a 3D NAND flash memory device increases to hundreds or more, providing sufficient GIDL current during the erase operation becomes crucial. Summary of the Invention

[0006] According to an aspect of this disclosure, a memory device is provided. The memory device includes: a vertical memory cell pillar; a data line; a transistor coupling the data line to the vertical memory cell pillar, the transistor having a channel structure and a gate, the channel structure being separate from the gate; a first portion of the channel structure of the transistor coupled to and extending vertically from a channel material of the vertical memory cell pillar; and a segmented portion of the channel structure extending vertically from the first portion, the segmented portion having fins contacting and extending vertically therefrom the first portion of the channel structure and a non-conductive region contacting and extending vertically therefrom the first portion of the channel structure, the first portion having a boundary with the non-conductive region, wherein the boundary decreases from the fins to a position below the lowest level of the fins.

[0007] According to another aspect of this disclosure, a memory device is provided. The memory device includes: a vertical memory cell pillar; a data line; a transistor coupling the data line to the vertical memory cell pillar, the transistor having a channel structure and a gate, the channel structure being separate from the gate; a first portion of the channel structure of the transistor coupled to and extending vertically from a channel material of the vertical memory cell pillar; a segmented portion of the channel structure extending vertically from the first portion, the segmented portion having fins contacting and extending vertically therefrom the first portion of the channel structure and a non-conductive region contacting and extending vertically therefrom the first portion of the channel structure; and a sharp corner region extending from the fins into the first portion of the channel structure.

[0008] According to another aspect of this disclosure, a memory system is provided. The memory system includes: a plurality of memory devices, wherein one or more of the memory devices include: data lines; a memory array having vertical strings of memory cells, wherein each vertical string is arranged as a pillar coupled to a transistor that couples the string to a data line in the data lines, the transistor having: a channel structure and a gate, the channel structure being separate from the gate; a first portion of the channel structure coupled to and extending vertically from the channel material of the vertical string; and segmented portions of the channel structure extending vertically from the first portion, the segmented portions having fins contacting and extending vertically therefrom the first portion of the channel structure and non-conductive regions contacting and extending vertically therefrom the first portion of the channel structure; and a corner region extending from the fins into the first portion of the channel structure; and a memory controller including a processing circuitry system configured to perform an operation comprising: performing an erase operation on the selected string by applying an erase voltage to the gate of the transistor that couples the selected string of the memory array to the data line associated with the selected string.

[0009] According to another aspect of this disclosure, a method of forming a memory device is provided. The method includes: forming a vertical memory cell string; forming a transistor to couple a data line to the vertical string, comprising: forming the transistor having a channel structure and a gate, wherein the channel structure is separate from the gate; forming a first portion of the channel structure of the transistor, which is coupled to and extends vertically from the channel material of the vertical memory cell string; forming a segmented portion of the channel structure, which extends vertically from the first portion, the segmented portion having fins that contact the first portion of the channel structure and extend vertically therefrom, and a non-conductive region that contacts the first portion of the channel structure and extends vertically therefrom; forming a sharp corner region that extends from the fins into the first portion of the channel structure; and forming the data line to couple to the transistor. Attached Figure Description

[0010] The diagrams, which may not be drawn to scale, are generally intended to illustrate the various embodiments discussed in this document in an exemplary rather than restrictive manner.

[0011] Figures 1A to 1D This describes a set of example channel structures that can be implemented in a transistor to couple data lines to vertical memory cell pillars according to various embodiments.

[0012] Figures 2A to 2C The block diagrams illustrate different instances of channel structures in various embodiments where the dielectric region in the transistor is separated from the gate.

[0013] Figure 3A This section describes example channel structures of transistors according to various embodiments, wherein the transistors are arranged in a channel material for coupling data lines to vertical memory cell pillars of a memory device.

[0014] Figure 3B Demonstration of various embodiments Figure 3A A cross-sectional view of the channel structure, where the gate is relative to... Figure 3A The first part of the trench structure is arranged.

[0015] Figures 4 to 47 This describes an example method for forming a memory device having an array of memory cell strings according to various embodiments, wherein each string is formed as a vertical column coupled to a drain-side selected gate transistor of the string.

[0016] Figures 48 to 90 This describes another example method for forming a memory device having an array of memory cell strings according to various embodiments, wherein each string is formed as a vertical column coupled to a drain-side selected gate transistor of the string.

[0017] Figure 91The illustration describes a functional block diagram of an instance memory device according to various embodiments, the instance memory device including a memory array having a plurality of memory cells, and one or more circuits or components for providing communication with the memory array or performing one or more memory operations on the memory array.

[0018] Figure 92 This is a flowchart illustrating the features of an example method for forming a memory device having a drain-side select gate coupled to a string of memory cells to a data line, according to various embodiments.

[0019] Figure 93 This is a block diagram of an example machine having one or more memory devices according to various embodiments, the memory devices being structured to enhance interband tunneling in select-gate transistors during erase operations, the select-gate transistors coupling data lines to a string of memory cells in a memory array of one or more memory devices. Detailed Implementation

[0020] The following detailed description, with reference to the accompanying drawings, illustrates various possible embodiments by way of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to practice these and other embodiments. Other embodiments may be utilized, and structural, logical, mechanical, and electrical changes may be made to these embodiments. As used herein, the term "horizontal plane" is defined as a plane parallel to a conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term "vertical" refers to a direction perpendicular to the horizontal plane as defined above. The various embodiments are not necessarily mutually exclusive, as some embodiments may be combined with one or more other embodiments to form new embodiments. Therefore, the following detailed description should not be construed in a limiting sense.

[0021] Both NOR and NAND flash memory arrays are accessed via a decoder that activates a specific memory cell by selecting an access line (WL) coupled to the gate of that specific memory cell. In a NOR array, once activated, the selected memory cell places its data value on the data line, causing different currents to flow according to the programmed state of the specific cell. In a NAND array, a relatively high bias voltage is applied to the drain-side selected gate (SGD) line. An access line coupled to the gate of each group of unselected memory cells is driven with a specified pass voltage (e.g., Vpass) to operate each group of unselected memory cells as a pass transistor (e.g., to pass current without being limited by the data value they store). The current then flows through each series-coupled group in the line between the source line and the data line, limited only by the selected memory cell of each group, placing the currently encoded data value of the selected memory cell on the data line.

[0022] In a NOR or NAND architecture semiconductor memory array, each flash memory cell can be individually or collectively programmed into one or more programmed states. For example, a single-level cell (SLC) can represent one of two programmed states (e.g., 1 or 0), representing one data bit. Flash memory cells can also represent more than two programmed states, allowing for the fabrication of higher-density memories without increasing the number of memory cells, since each cell can represent more than one binary digit (e.g., more than one bit). Such cells may be referred to as multi-state memory cells, multi-digit cells, or multi-level cells (MLCs). In some instances, MLCs have been referred to as memory cells that can store two data bits per cell (e.g., one of four programmed states). In the broader context herein, MLC is used to refer to any memory cell that can store more than one data bit per cell (i.e., it can represent more than two programmed states). In this document, a memory cell that can store two data bits per cell (e.g., one of four programmed states) is referred to as a dual-level cell (DLC). A three-level cell (TLC) refers to a memory cell that can store three data bits per cell (e.g., one of eight programmed states). A four-level cell (QLC) can store four data bits per cell, and a five-level cell (PLC) can store five data bits per cell. In a string of memory cells in a 3D memory device, such as a 3D NAND memory, access to the string to operate on the memory cells in the string can be controlled by a gating selector device, such as a selector gate transistor, which is connected in series with the memory cells of the string.

[0023] In various embodiments, the generation of inter-band charge in the transistor channel of the select-gate transistor at the data line side of the 3D NAND flash pillar of the memory cell can be increased based on the segmentation of the channel structure of the select-gate transistor. The pillar may comprise a string of memory cells coupled to a source line via one or more source-side select-gate (SGS) transistors coupled to the pillar at one end, wherein the string of memory cells is arranged in series to the source line. At the other end, the string of memory cells may be coupled to a data line via one or more SGD transistors coupled to the pillar and arranged to couple the string of memory cells to the data line. The channel structure of the SGD transistor may comprise two parts. A first part of the channel structure of the SGD transistor may be coupled to the channel material of the vertical memory cell pillar and extend vertically from the coupling member to the channel material of the vertical pillar. The first part is the channel region of the SGD transistor operating relative to the gate of the SGD transistor, wherein the gate is dielectrically separated from the first part. The second part of the channel structure is a segmented portion of the channel structure of the SGD transistor. The segmented portion may extend vertically from the first portion, wherein the segmented portion has one or more fins extending vertically from the first portion of the contact channel structure and one or more non-conductive regions extending vertically from the first portion of the contact channel structure. The first portion provides a transistor channel region to the drain, wherein the one or more fins of the segmented portion are structured into one or more drain channels, thereby providing a drain interface for the first portion. In various embodiments, the memory cell pillars in the 3D NAND memory array may be coupled to a data line using an SGD and coupled to a source line using an SGS.

[0024] Based on the structural interface between the segmented portion and the first portion of the topmost SGD, the increased interband charge generation further enhances the drain-side current GIDL during the erase operation. This structural interface between the segmented portion and the first portion provides a different approach to doping optimization between the contacts and the channel structure of the SGD. The interband tunneling field that generates the GIDL current is enhanced by using the segmented portion coupled to the first portion of the channel structure. The cross-segmentation segmented portion, provided by the non-conductive regions of the fins and the segmented portion, disrupts the uniformity of the electric field and allows the electric field lines to concentrate in the segmented region, thereby enhancing the interband offset.

[0025] In various embodiments, SGD transistors for vertical NAND memory cell strings can be implemented using a segmented structure of fins that interface with the channel region of the SGD transistor, wherein sharp corner regions extend from the fins into the channel region. SGD transistors with segmented fins and sharp corners can be implemented in various arrangements. In one arrangement, thin, low-capacitance drain contacts can be constructed in situ with the segmentation module. The drain contacts can be, but are not limited to, tungsten drain contacts. In another arrangement, the drain contacts can be configured to contact a conductive landing pad downwards. The drain contacts can be, but are not limited to, tungsten drain contacts, and the conductive landing pad can be, but is not limited to, an n+ drain landing pad. High GIDL de-integration single-photomask processes can be used to construct SGD transistors with segmented fins and sharp corners for vertical memory strings in memory arrays of memory devices (e.g., NAND memory devices). Single-photomask processes can form small-form-factor segmented SGD transistors for high GIDL operation of vertical NAND drains.

[0026] In segmented SGD single-light-level processes, a single-light layer can be used to form SGD transistors, enabling self-aligned dicing and block partitioning in the memory array. The process may involve positive overlap between the interfaces of the control gate and channel region of the SGD transistor and the segmented fins of the drain of the SGD transistor. This positive overlap can be controlled by sacrificing material layering during the construction of the drain and transistor channel segments. The control gate can be configured to positively overlap with the top layer of the channel material of the memory cells used to form the memory string of the SGD transistor, which improves performance. The channel material can be polysilicon. Other semiconductor materials can be used for the channel material.

[0027] There are numerous options for designing the configuration and shape of the interface between the channel region of an SGD transistor and the segmented fins that overlap for the drain and gate to improve performance. The segmented fins for the drain can be more heavily doped than the channel region. For example, the segmented fins for the drain can be an n+ region and the channel region can be an n- region. Using single-layer photolithography and wet etching to process these regions can also reduce manufacturing costs. Furthermore, the self-aligned and autonomous drain contacts provided by these processes should mitigate many failure modes associated with current SGD module processes.

[0028] Figures 1A to 1DThis describes a set of example channel structures 102A, 102B, 102C, and 102D that can be implemented in transistors according to various embodiments to couple data lines to vertical memory cell pillars. The transistor coupling the data lines to the vertical memory cell pillars can be implemented, for example, as an SGD transistor in a memory array of a NAND memory device. Each of the channel structures 102A, 102B, 102C, and 102D includes a first portion of channel material to couple to and from the vertical memory cell pillar. The first portion provides a transistor channel region for transistor operation and is separated from the transistor gate by a dielectric material providing the transistor gate dielectric. Each of the channel structures 102A, 102B, 102C, and 102D further includes a segmented portion extending vertically from the first portion, wherein the segmented portion is more heavily doped than the first portion, thereby providing an interface for the drain region. The segmented portion has one or more fins that contact the first portion and extend vertically from the first portion, and one or more non-conductive regions that contact the first portion and extend vertically from the first portion.

[0029] Figure 1AA channel structure 102A is shown, having fins 105-1A, 105-2A, 105-3A, and 105-4A, and non-conductive regions 107-1A, 107-2A, and 107-3A, wherein the fins 105-1A, 105-2A, 105-3A, and 105-4A, and the non-conductive regions 107-1A, 107-2A, and 107-3A extend vertically from a first portion 110A of the channel structure 102A. Although not shown, non-conductive regions exist between fins 105-1A and fins 105-2A. Although the non-conductive regions 107-1A, 107-2A, and 107-3A are shown as voids, these non-conductive regions may contain dielectric material. The interface between the non-conductive region 107-1A and the first portion 110A has a rounded corner 108-1A extending from the lower corner of fin 105-1A to the lower corner of fin 105-4A, which forms the circular boundary of the first portion 110A. The interface between the non-conductive region 107-2A and the first portion 110A has a rounded corner 108-2A extending from the lower corner of fin 105-2A to the lower corner of fin 105-3A, which forms the circular boundary of the first portion 110A. The interface between the non-conductive region 107-3A and the first portion 110A has a rounded corner 108-3A extending from the lower corner of fin 105-3A to the lower corner of fin 105-4A, which forms the circular boundary of the first portion 110A. The non-conductive region between fins 105-1A and fins 105-2A may also have rounded corners as the circular boundary of the first portion 110A. The rounded corners of the channel structure 102A may be structured as a region that is more heavily doped than the first portion 110A. For example, if the first portion 110A is doped as an n-structure, n+ doping may be added to the rounded corners of the channel structure 102A. The structure 102A, implemented in the SGD transistor of a memory string for a memory array of a memory device, may be disposed around the dielectric region.

[0030] Figure 1BA channel structure 102B is shown, having fins 105-1B, 105-2B, 105-3B, and 105-4B, and non-conductive regions 107-1B, 107-2B, 107-3B, and 107-4B, wherein the fins 105-1B, 105-2B, 105-3B, and 105-4B, and the non-conductive regions 107-1B, 107-2B, 107-3B, and 107-4B extend vertically from a first portion 110B of the channel structure 102B. Although the non-conductive regions 107-1B, 107-2B, 107-3B, and 107-4B are shown as voids, these non-conductive regions may contain dielectric material. The interface between the non-conductive region 107-1B and the first portion 110B has a rounded corner 108-1B extending from the lower corner of fin 105-1B to the lower corner of fin 105-4B, which forms the circular boundary of the first portion 110B. The interface between the non-conductive region 107-2B and the first portion 110B has a rounded corner 108-2B extending from the lower corner of fin 105-1B to the lower corner of fin 105-2B, which forms the circular boundary of the first portion 110B. The interface between the non-conductive region 107-4B and the first portion 110B has a rounded corner 108-3B extending from the lower corner of fin 105-3B to the lower corner of fin 105-4B, which forms the circular boundary of the first portion 110B. The interface between the non-conductive region 107-3B and the first portion 110B can also have rounded corners, serving as the circular boundary of the first portion 110B between fins 105-2B and fins 105-3B. The rounded corners of the channel structure 102B can be structured into regions that are more heavily doped than the first portion 110B. For example, if the first portion 110B is doped into an n-structure, n+ doping can be added to the rounded corners of the channel structure 102B.

[0031] Additionally, emitter 109-1B can be structured to extend from fillet 108-1B into the first portion 110B. Emitter 109-1B can be positioned within the first portion 110B, extending downward from approximately the center of fillet 108-1B, and can have a width along fillet 108-1B equal to the width of the portion of fillet 108-1B. Emitter 109-2B can be structured to extend from fillet 108-3B into the first portion 110B. Emitter 109-2B can be positioned within the first portion 110B, extending downward from approximately the center of fillet 108-3B, and can have a width along fillet 108-3B equal to the width of the portion of fillet 108-3B. Although not shown, emitters can be structured into the first portion 110B, which extends from other fillets at the interface between the non-conductive region and the first portion 110B. The emitter of the channel structure 102B can be structured to be more heavily doped than the first portion 110B. For example, if the first portion 110B is doped to an n-structure, the emitter can be an n+ emitter. The structure 102B implemented in the SGD transistor of the memory string of a memory array for a memory device can be disposed around the dielectric region.

[0032] Figure 1C A channel structure 102C is shown, having fins 105-1C, 105-2C, 105-3C, and 105-4C, and non-conductive regions 107-1C, 107-2C, 107-3C, and 107-4C, wherein the fins 105-1C, 105-2C, 105-3C, and 105-4C, and the non-conductive regions 107-1C, 107-2C, 107-3C, and 107-4C extend vertically from a first portion 110C of the channel structure 102C. Although the non-conductive regions 107-1C, 107-2C, 107-3C, and 107-4C are shown as voids, these non-conductive regions may contain dielectric material. The interface between the non-conductive region 107-1C and the first portion 110B has a rounded corner 108-1C extending from the lower corner of fin 105-1C to the lower corner of fin 105-4C, which forms the circular boundary of the first portion 110C. The interface between the non-conductive region 107-2C and the first portion 110C has a rounded corner 108-2C extending from the lower corner of fin 105-1C to the lower corner of fin 105-2C, which forms the circular boundary of the first portion 110C. The interface between the non-conductive region 107-4C and the first portion 110C has a rounded corner 108-3C extending from the lower corner of fin 105-3C to the lower corner of fin 105-4C, which forms the circular boundary of the first portion 110C. The interface between the non-conductive region 107-3C and the first part 110C may also have rounded corners, serving as the rounded boundary of the first part 110C between fins 105-2C and fins 105-3C.

[0033] Emitter 109-1C may be structured to extend from fillet 108-1C into the first portion 110C. Emitter 109-1C may be positioned within the first portion 110C and extend downward from approximately the center of fillet 108-1C, having a width along fillet 108-1C equal to the width of the portion of fillet 108-1C. Emitter 109-2C may be structured to extend from fillet 108-2C into the first portion 110C. Emitter 109-2C may be positioned within the first portion 110C and extend downward from approximately the center of fillet 108-2C, having a width along fillet 108-2C equal to the width of the portion of fillet 108-2C. Emitter 109-3C may be structured to extend from fillet 108-3C into the first portion 110C. Emitter 109-3C may be positioned within the first portion 110C extending downward from approximately the center of fillet 108-3C, and may have a width along fillet 108-3C equal to the width of the portion of fillet 108-3C. Although not shown, other emitters may be similarly structured at the interface between the non-conductive region and the first portion 110C, extending from other fillets of channel structure 102C into the first portion 110C. The emitters of channel structure 102C may be structured to be more heavily doped than the first portion 110C. For example, if the first portion 110C is doped into an n-structure, the emitter may be an n+ emitter. Figure 1C The channel structure 102C and Figure 1B The difference between the channel structure 102B and the channel structure 102C is that, except for the emitter, the rounded corners of the first portion 110C of the channel structure 102C are not charged with respect to the first portion 110C. The structure 102C implemented in the SGD transistor of the memory string for the memory array of the memory device can be structured around the dielectric region.

[0034] Figure 1DA channel structure 102D is shown, having fins 105-1D, 105-2D, 105-3D, and 105-4D, and non-conductive regions 107-1D, 107-2D, 107-3D, and 107-4D, wherein the fins 105-1D, 105-2D, 105-3D, and 105-4D, and the non-conductive regions 107-1D, 107-2D, 107-3D, and 107-4D extend vertically from a first portion 110D of the channel structure 102D. Although the non-conductive regions 107-1D, 107-2D, 107-3D, and 107-4D are shown as voids, these non-conductive regions may contain dielectric material. The interface between the non-conductive region 107-1D and the first portion 110D has a rounded corner 108-1D extending from the lower corner of fin 105-1D to the lower corner of fin 105-4D, which forms the circular boundary of the first portion 110D. The interface between the non-conductive region 107-3D and the first portion 110D has a rounded corner 108-2D extending from the lower corner of fin 105-2D to the lower corner of fin 105-3D, which forms the circular boundary of the first portion 110D. The interface between the non-conductive region 107-4D and the first portion 110D has a rounded corner 108-3D extending from the lower corner of fin 105-3D to the lower corner of fin 105-4D, which forms the circular boundary of the first portion 110D. The interface between the non-conductive region 107-2D and the first part 110D may also have rounded corners, serving as the circular boundary of the first part 110D between fins 105-1D and fins 105-2D.

[0035] The fillet 108-1D portion of the channel structure 102D can be structured to be more heavily doped than the first portion 110A, without fully doping the fillet 108-1D more heavily than the first portion 110D. The partially doped fillet 108-1D being more heavily doped than the first portion 110D can structure two sharp corner regions 112-1D and 112-2D into the first portion 110D. Sharp corner region 112-1D extends from the lower corner of fin 105-1D along fillet 108-1D towards the lower corner of fin 105-4D. Sharp corner region 112-2D extends from the lower corner of fin 105-4D along fillet 108-1D towards the lower corner of fin 105-1D. Sharp corner regions 112-1D and 112-2D are separated from each other by the region of fillet 108-1D. In the first part 110D, the doping is carried out to form an n- structure, and the sharp corners of the channel structure 102D may have n+ doping, wherein the region between the sharp corners is below the non-conductive region with the n- structure. Figure 1DThe diagram also shows a pointed corner region 112-3D extending from the lower end of fin 105-2D along rounded corner 108-2D. Although not shown, each fin of channel structure 102D may be structured to have two pointed corner regions extending into the first portion 110D, wherein each pointed corner region is positioned along a portion of the corresponding rounded corner of the first portion 110D. Figure 1D The channel structure 102D and Figure 1A The difference between channel structure 102A and channel structure 102D is that the rounded corners between the fins and below the non-conductive region have two more heavily doped sharp-corner regions than the first part of the channel structure, wherein the region between the sharp corners is part of the first part of the channel structure, while Figure 1A The fillets in the channel structure 102A are more heavily doped from one fin to the adjacent fin. The structure 102D, implemented in the SGD transistor of a memory string for a memory array of a memory device, can be structured around the dielectric region.

[0036] Figures 2A to 2C Block diagrams illustrate different examples of channel structures where the dielectric region in the transistor is separated from the gate. The channel structures can be implemented similarly to, but not limited to, any of channel structures 102A, 102B, 102C, or 102D. For ease of discussion, Figures 2A to 2C The cross-section of each channel structure shown in the diagram only displays a single fin extending from the interface to a first portion, which is structured as the channel region of the associated transistor. The interface provides a junction between the transistor channel region and a more heavily doped region of the transistor drain.

[0037] Figure 2A A vertical channel structure 202A with fins 205A is described, the fins extending vertically from interface 213A to a first portion 210A that is lighter-doped than fin 205A. The vertical channel structure 202A is separated from the gate 215A by a dielectric region 214A. The top of the gate 215A is at a layer such that the gate 215A vertically overlaps with interface 213A and is vertically terminated at its top, at a layer corresponding to the layer in fin 205A.

[0038] Figure 2B A vertical channel structure 202B with fins 205B is described, the fins extending vertically from interface 213B to a first portion 210B, wherein the first portion 210B is less doped than the fins 205B. The vertical channel structure 202B is separated from the gate 215B by a dielectric region 214B. The top of the gate 215B is at a layer such that the gate 215B vertically negatively overlaps with interface 213B and is vertically terminated at its top, at a layer corresponding to the layer in the first portion 210B.

[0039] Figure 2CA vertical channel structure 202C with fins 205C is described, the fins extending vertically from interface 213C to a first portion 210C, wherein the first portion 210C is lightly doped compared to the fins 205C. The vertical channel structure 202C is separated from the gate 215C by a dielectric region 214C. The top of the gate 215C is vertically aligned at a layer corresponding to interface 213C, such that the gate 215C is vertically terminated at its top at the layer aligned with interface 213C.

[0040] In a channel structure with segmented fins extending from a first portion, serving as part of an SGD transistor in a memory string within a memory array for a memory device, the channel structure can influence the GIDL operation of the memory string. This influence can depend on numerous factors, such as the channel structure itself and the relationship between portions of the channel structure and the gate of the SGD transistor. Simulations can demonstrate the relationship between GIDL operation and... Figures 1A to 1D The relationship between channel structures 102A, 102B, 102C and 102D and Figures 2A to 2C The gate-junction relationship.

[0041] Simulations indicate that deeper cuts provide improved GIDL operation, independent of gate-junction positive overlap. Gain can be achieved with any n+ fin-gate positive overlap, but GIDL variability is generally greater than in cases where the cut is deeper than the junction line (the interface between the segmented fin and the first part of the channel structure). In channel structure arrangements... Figure 1A With a channel structure 102A and the junction aligned with the top of the associated gate, adding n+ to the fillet relative to the doping of the first portion 110A helps improve the GIDL current at lower bias voltages. In a channel structure arrangement of... Figure 1A In the case of a 102A channel structure with positive overlap between the junction and the top of the gate, doping of the rounded corners does not appear to offer any advantage. When the junction and the top of the gate have negative overlap, doping of the rounded corners appears to be advantageous. However, using a small positive overlap without doping the rounded corners may be appropriate.

[0042] The trench structure is arranged as follows Figure 1B In the case of the 102B channel structure, the emitter helps to make the GIDL current less dependent on the junction variant. The emitter can increase the GIDL current at lower bias voltages, even more than the doped fillets that provide an n+ region at the boundary of the first section 110B of the 102B channel structure. The GIDL current can fall back at higher bias voltages, but is still higher than in a segmented structure without fillets.

[0043] The trench structure is arranged as follows Figure 1CIn the case of a 102C channel structure, implementing an emitter with undoped rounded corners provides the greatest enhancement. However, due to the high dependence on gate-junction positive overlap, a standalone emitter may not be desirable. In a channel structure arrangement of... Figure 1D In the case of a 102D channel structure, rounded corners with sharp corner regions can provide a larger current than rounded corners with only n+ doping.

[0044] Figure 3A An embodiment of an example channel structure 302 for a transistor is described, wherein the transistor is arranged with channel material 301 to couple data lines 325 to vertical memory cell pillars of a memory device. The transistor for the channel structure 302 may be structured as an SGD transistor of a vertical memory cell pillar. The channel material 301 may be arranged around a dielectric 303, and the transistor having the channel structure 302 may be positioned such that its structure is horizontally shifted relative to the pillars.

[0045] The channel structure 302 may be structured as a first portion 310 and segmented portions. The first portion 310 of the channel structure 302 for transistors may be coupled to and extend vertically from the channel material 301 of the vertical memory cell pillar. The segmented portions of the channel structure 302 may extend vertically from the first portion 310, wherein the segmented portions have one or more fins and one or more non-conductive regions. Figure 3A In the example, the segmented portion of the channel structure 302 has four fins 305-1, 305-2, 305-3, and 305-4 and four non-conductive regions 307-1, 307-2, 307-3, and 307-4. Each of the fins 305-1, 305-2, 305-3, and 305-4 contacts the first portion 310 of the channel structure 302 and extends vertically therefrom. Each of the non-conductive regions 307-1, 307-2, 307-3, and 307-4 contacts the first portion 310 of the channel structure 302 and extends vertically therefrom. The segmented portion of the channel structure 302 may further include sharp corner regions 312-1 and 312-2, sharp corner regions 312-3 and 312-4, sharp corner regions 312-5 and 312-6, and sharp corner regions 312-7 and 312-8 extending from fins 305-1, 305-2, 305-3, and 305-4 into the first portion 310 of the channel structure 302. The channel structure 302 can be connected with... Figure 1D The channel structure 102D is implemented in a similar or identical manner.

[0046] Fins 305-1, 305-2, 305-3, and 305-4 may extend from the first portion 310 to the drain 320 of the transistor. Drain contacts 323, disposed on and in contact with the drain 320, may be coupled to the data line 325 via a conductive structure 324. The conductive structure 324 may be a metal contact. The metal contact may include, but is not limited to, tungsten, titanium nitride, a combination of tungsten and titanium nitride, or other suitable metals. The conductive structure 324 may be disposed on and in contact with titanium silicide between the conductive structure 324 and the drain contacts. The conductive structure 324 provides additional drain contacts coupled to the fins of the channel structure 302, wherein the conductive structure 324 may have a width equal to or less than the width of the data line 325. The fins 305-1, 305-2, 305-3, and 305-4, the sharp corner regions 312-1, 312-2, 312-3, 312-4, 312-5, 312-6, 312-7, and 312-8, the drain contact 323, and the drain 320 may be heavily doped relative to the first portion 310. The first portion 310 may be n- doped, and these other doped regions may be n+ doped.

[0047] Figure 3B exhibit Figure 3A A cross-sectional view of the channel structure 302, wherein the gate 315 is arranged relative to the first portion 310. The first portion 310 provides a transistor channel for the drain 320, wherein the first portion 310 is separated from the gate 315. The drain 320 may be integrated with segmented portions of fins 305-1 and 305-2 and a non-conductive region 307. The non-conductive region 307 may be a void region or a solid dielectric region. Sharp corner regions 312-1 and 312-2 extend from fins 305-1 and 305-2 into the first portion 310.

[0048] In this example, the top of the gate 315 is aligned with the bottom of fins 305-1 and 305-2. In other embodiments, the top of the gate 315 positively overlaps with the interface between the first portion 310 and fins 305-1 and 305-2, or negatively overlaps with the interface between the first portion 310 and fins 305-1 and 305-2. The top of the first portion 310 has a circular boundary 308 between fins 305-1 and 305-2, wherein the circular boundary 308 decreases from fins 305-1 and 305-2 toward the lower boundary of the first portion 310 and the non-conductive region 307. Fins 305-1 and 305-2, as well as the sharp corner regions 312-1 and 312-2, are portions more heavily doped than the circular boundary 308 between the sharp corner regions 312-1 and 312-2.

[0049] Figures 4 to 47Examples of methods for forming a memory device with an array of memory cell strings are illustrated, wherein each string is formed as a vertical column of SGD transistors coupled to the string. Features associated with the stages of forming the SGD transistors coupled to the memory cell strings are shown in some of the figures in these figures. In this embodiment, the SGD transistors with segmented fins and sharp corners are formed with thin, low-capacitance drain contacts that are built in situ together with the segmentation module. For the procedures discussed herein, the choice of processing materials may depend on the materials selected to form the various components of the device of the memory array and the contacts to said device. Processing materials may be selected to allow the removal of one or more materials while retaining one or more other materials. Additionally, deposition techniques typical of the material being formed, the size of the material being formed, and the architecture of the material being formed may be used.

[0050] Figure 4 The image shows material layer 430 and oxide layer 432 after etching to form openings 431 in material layer 430 and oxide layer 432. Pillars for memory cells are formed in openings 431. Oxide layer 432 may be a silicon oxide layer. Dielectric materials other than oxides may be used in oxide layer 432. Material layer 430 may comprise a stack of alternating layers of insulating dielectrics and sacrificial regions, where the sacrificial regions form the gates of memory cells, and where each insulating dielectric separates adjacent memory cell layers. The number of material layers 430 depends on the number of memory cell layers to be formed in openings 431. The number of layers can range from a few to thousands or even more, depending on the number of memory cells in the string.

[0051] Figure 5 This diagram shows a cross-sectional view of one of the openings 431 after the unit membrane and channel material have been formed and oxide 539 has been formed on the material used for the unit membrane. For the material used, a suitable deposition process can be used for formation. Suitable deposition techniques may include, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), variations of CVD and ALD, or other techniques. Figure 4Each opening 431 can be filled in the same manner to form a similar, identical structure. Each cell formed in the opening 431 may contain elements of a transistor to store charge. For example, each cell may contain a channel region in which current can flow during the operation of the memory device, a tunnel region separating the channel from a charge-trapping region for storing charge, and a dielectric barrier region separating the gate from the charge-trapping region. In various embodiments, a dielectric barrier region structured as a thin region may be disposed between the dielectric barrier region and the gate, thereby implementing an enhanced tunneling barrier that prevents electrons from tunneling backward from the gate through the dielectric barrier region to the charge-trapping region. The material of the cell film formed in the opening 431 may include a dielectric barrier material 534, a charge-trapping material 536, a tunneling material 538, and a channel material 501.

[0052] In embodiments using a dielectric barrier, although Figure 5 Not shown, but a dielectric barrier material can be deposited on the surface of opening 431. The dielectric barrier material can be realized as an alumina region or a dielectric region having a higher dielectric constant than alumina. For example, the dielectric barrier material may comprise alumina, hafnium oxide, zirconium oxide, or a mixture of hafnium oxide and / or zirconium oxide with one or more of alumina, silicon oxide, titanium oxide, gadolinium oxide, niobium oxide, or tantalum oxide. Other high-κ dielectrics can be used in the dielectric barrier material, where κ is the dielectric constant. A high-κ dielectric is a dielectric with a dielectric constant greater than that of silicon dioxide. The dielectric barrier material can be formed in the region as a nanolayer of multiple different compounds, the nanolayer located in each sub-region of the region forming the nanolayer, wherein the formed region has a total thickness in the nano-region. The term "nanolayer" refers to a composite film of two or more ultrathin layers of materials in a layered stack. Typically, each layer in a nanolayer has a thickness on the order of nanometers. Furthermore, each individual layer of the nanolaminated material can have a thickness as low as a single layer or as high as 5 nanometers. The dielectric barrier material can be formed with walls having a thickness in the range of 20 to 50 angstroms from the opening 431. The transition of the dielectric barrier material from one layer of nanolaminated material to another further disrupts the tendency of the ordered structure in the nanolaminated material stack, reducing or eliminating the occurrence of conventional reverse tunneling paths.

[0053] As in Figure 5As shown, dielectric barrier material 534 can be formed on the surface of opening 431, or formed on the dielectric barrier material after such dielectric barrier material is formed on the surface of opening 431. Dielectric barrier material 534 can be silicon oxide, a high-k dielectric, or a combination of silicon oxide or one or more high-k dielectric materials. When a dielectric barrier material is used, the material of the dielectric barrier material 534 interfaced with the dielectric barrier material is selected to be different from the material of the dielectric barrier material at the interface.

[0054] After forming the dielectric barrier material 534, a charge trapping material 536 may be formed on the dielectric barrier material 534. The charge trapping material 536 may be structured from materials capable of retaining electrons received from the channel region of the corresponding memory cell during operation. For example, the charge trapping material 536 may be a dielectric material capable of storing charge. The charge trapping material 536 may be a dielectric nitride region, such as a region containing dielectric silicon nitride. Other dielectric materials for the charge trapping material 536 may be used to trap charge. Depending on the memory cell design, materials operating as a floating gate structure may be used for the charge trapping material 536.

[0055] After forming the charge trapping material 536, a tunneling material 538 may be formed on the charge trapping material 536. The tunneling material 538 may be constructed as an engineered region to meet selected criteria, such as, but not limited to, the equivalent oxide thickness (EOT). The EOT quantifies the electrical properties, such as capacitance, of the tunneling material 538 of the dielectric based on a representative physical thickness. For example, the EOT may be defined as the thickness of a theoretical SiO2 layer, which will be required to have the same capacitance density as a given dielectric (tunneling material 538), disregarding leakage current and reliability considerations. The tunneling material 538 may contain oxides and nitrides. The tunneling material 538 may contain a high-κ dielectric. The tunneling material 538 may contain a set of dielectric regions. The tunneling material 538 may be a three-region structure. Such a three-region structure may be arranged as a dielectric oxide region followed by a dielectric nitride region, and then another dielectric oxide region. The tunneling material 538 may be a two-region tunnel structure or a one-region tunnel structure. Furthermore, the tunneling material 538 may have four or more regions, wherein the choice of material and thickness depends on the ability of a material with a given thickness to function as a tunneling region in charge trapping.

[0056] After forming the tunneling material 538, a channel material 501 can be formed on the tunneling material 538. The channel material 501 can be structured as semiconductor material pillars arranged vertically from the source line for an array of memory cell strings and arranged to couple with the SGD transistor to be formed. The channel material 501 can be implemented as a polysilicon channel structure. Other semiconductor types and materials can be used for the channel material 501.

[0057] Figure 6Displayed after several processing stages have been executed Figure 5 A cross-sectional view of the structure. Chemical mechanical planarization (CMP) has been performed on oxide 539, and oxide 539 has been recessed. The recess has been filled with semiconductor material 641. Semiconductor material 641 may be, but is not limited to, the same as channel material 501. For example, semiconductor material 641 may be polysilicon. After filling the recess, a CMP process has been applied to the surface such that a portion of the channel material 501, which has been horizontally formed on top of tunnel material 538, has been removed, leaving the channel material 501, semiconductor material 641, and tunnel material 538 surrounding the channel material 501 and semiconductor material 641 exposed as the top surface.

[0058] Figure 7 The image shows the result after removing the dielectric barrier material 534, charge trapping material 536, and tunneling material 538 formed horizontally on top of the oxide layer 432. Figure 6 A cross-sectional view of the structure. Removal may involve creating a recess in oxide layer 432. Removal can be performed by wet etching.

[0059] Figure 8 Displayed after other processing stages have been performed. Figure 7 A cross-sectional view of the structure. Carbon nitride 842 has been formed on top of the recessed oxide layer 432, the dielectric barrier material 534, the charge trapping material 536 and the tunneling material 538, the channel material 501, and the semiconductor material 641. A suitable deposition technique can be used to perform the formation of carbon nitride 842. After the formation of carbon nitride 842, a CMP procedure is applied to remove carbon nitride 842 from the top of the channel material 501 and the semiconductor material 641, exposing the channel material 501 and the semiconductor material 641. The carbon nitride has been reduced, leaving carbon nitride 842 on top of the oxide layer 432 and the dielectric barrier material 534, charge trapping material 536, and tunneling material 538 for the memory cell.

[0060] Figure 9 Displayed after other processing stages have been performed. Figure 8 A cross-sectional view of the structure. The portion of semiconductor material 641 and the channel material 501 above oxide 539 is removed. Removal can be performed by wet etching. After removing the portion of semiconductor material 641 and channel material 501, [the following text is incomplete and likely refers to further details about the process]. Figure 8 Another semiconductor material 941 is formed on the surface of the structure. Semiconductor material 941 may be, but is not limited to, the same as channel material 501 or semiconductor material 641. For example, semiconductor material 941 may be polycrystalline silicon. Suitable deposition techniques can be used to perform the formation of semiconductor material 941.

[0061] Figure 10The demonstration shows the process of applying a CMP procedure to semiconductor material 941 and removing semiconductor material 941 from above carbon nitride 842. Figure 9 A cross-sectional view of the structure. The CMP process leaves a channel material 501 on oxide 539, a semiconductor material 941 on oxide 539, and carbon nitride 842 as a planarization top surface. Unit films 534, 536, and 538, channel material 501, and oxide 539 below carbon nitride 842 form structure 1045, which is substantially the same as the additional process applied to carbon nitride 842.

[0062] Figure 11 Shown Figure 4 Formed in the previous opening 431 Figure 10 Cross-sectional views of the structure of carbon nitride, channel material, and semiconductor material planarization. Figure 11 It also shows a thicker oxide 1146 formed across the array of structure 1045 and carbon nitride 842 between these unit membrane pillars. Figure 11 The structure can be removed appropriately Figure 4 A portion of the material layer 430 is processed to form the gate of the memory cell. Removal may be included in an etching process to form the gate during a gate replacement procedure. The processing of the material layer 430 results in a set of memory cell layers 1130 having gates coupled to the cell film of structure 1045. These procedures can be performed using known techniques for forming vertical memory cell arrays. During the subsequent processing discussed below, the configuration of layers 1130 and structure 1045 remains unchanged for the SGD transistor.

[0063] Figure 12 Display after forming a treatment layer on oxide 1146 Figure 11 A cross-sectional view of the assembly layers 1130, structure 1045, carbon nitride 842, semiconductor material 941, and oxide 1146 in an example of a series of pillars. The processing layers may comprise nitride 1251, oxide 1252, nitride 1253, oxide 1254, nitride 1255, and oxide 1256. These processing layers can be formed using one or more suitable deposition techniques. The oxide used may be, but is not limited to, silicon oxide, and the nitride used may be, but is not limited to, silicon nitride.

[0064] Figure 13A The display shows the formation of opening 1360 through oxide 1256, nitride 1255, oxide 1254, nitride 1253 and oxide 1252 to nitride 1251. Figure 12 A cross-sectional view of the structure. In this example, circular and elliptical patterns are etched through the top of oxide 1256, nitride 1255, oxide 1254, nitride 1253 and oxide 1252 to nitride 1251. Figure 13BA top view of the possible resist patterns for the circular pattern 1362 and the elliptical patterns 1363-1, 1363-2, and 1363-3 used for etching pattern 1361 is shown on the surface of the pillar structure 1345. This single set of patterns can be used for the subsequent formation of SGD transistors for the memory cell array in layer 1130. Figure 13A The cross-sectional view is along Figure 13B The cross-sectional line. The pattern allows for the design of gaps between the downwardly etched patterns to form keyholes, which remain free of deposited material in subsequent stages. The narrow gaps between the resist patterns of circular pattern 1362 and elliptical patterns 1363-1, 1363-2, and 1363-3 and the etched pattern 1361 form the star-shaped ends of the etched pattern 1361. The etched points in and between the fins are formed by the narrow gaps between the resist patterns of circular pattern 1362 and elliptical patterns 1363-1, 1363-2, and 1363-3 and the etched pattern 1361. The number of points in the star-shaped pattern 1361 corresponds to the number of fins to be formed.

[0065] Figure 13C exhibit Figure 13A The opening 1360 is relative to Figure 13B A top view of the star-shaped pattern 1361. The opening 1361 between the circle and the ellipse is centered for positioning the contacts of the forming SGD. Multiple such openings are arranged on the surface of the pillar structure 1345 and between the circles and ellipses across the surface of the pillar structure 1345, such that the center of the opening is positioned for contact with the multiple SGD transistors of the pillar structure 1345. The center of the opening 1360 is relative to... Figure 13A The vertical column structure was horizontally shifted by 1045.

[0066] Figure 14 After oxide 1466 is formed on the surface of opening 1360. Figure 13A A cross-sectional view of the structure. The cross-sectional view is along... Figure 13B The cross-sectional line. Oxide 1466 can be formed through the surfaces of nitrides 1255, 1253, and 1251 exposed in the oxide opening 1360. Oxide 1466 can be a thermally grown oxide. Oxide 1466 serves to protect the void area from etching chemicals used to etch nitride 1255 penetrating downwards through the voids formed by the resist and the etching pattern and eroding nitrides 1253 and 1251.

[0067] Figure 15AExamples of embodiments are shown for forming openings 1560 for contacts relative to unit posts 1545. The different patterns may include circular patterns 1562 and elliptical patterns 1563 of different sizes. Patterns may be generated for sub-blocks of the memory array across boundaries 1564-1 and 1564-2. Figure 15B An embodiment showing another example of a pattern used for opening 1560B.

[0068] Figure 16A An embodiment of a combination 1662 of pattern 1661 used to form fins is shown. Pattern 1661 is used for six fins. Figure 16B An embodiment of a pattern combination 1663 for forming a structure with four fins is shown. Figure 16A and 16B The example pattern provides a mechanism for patterning and air gaps for segmented fins. The segmented fins can be n+ fins. Fin formation can be based on providing sufficient air gaps and space for the SGD transistor, wherein the space is uniform and properly positioned. Other patterns can be used to form SGD transistors with channel structures having segmented portions having N fins, where N is a positive integer. The number N can be limited by the number of separate fins that can be formed in a designated area of ​​the SGD transistor.

[0069] Figure 17 exhibit Figure 14 The structure is shown in the cross-sectional view after the deposition and etching of oxide spacers 1766 to bridge the circular and elliptical patterns together to form sharp corners. The oxide spacers 1766 are formed sufficiently non-conformally to deposit more on the surface of oxide 1256 than on the sidewalls and bottom of opening 1360, so that after the spacers are etched, the oxide is removed from the bottom of opening 1360 but remains on the surface to protect the gaps between the patterns. The formation of large gaps between the circular and elliptical features is desirable. The cross-sectional view is along... Figure 13B The cross-sectional line. Oxide spacer 1766 may contain oxide 1466.

[0070] Figure 18 Displayed after other processing stages have been performed. Figure 17 A cross-sectional view of the structure. The cross-sectional view is along... Figure 13BThe cross-sectional line is shown. Using opening 1360, nitride 1251 has been selectively etched. The etching results in a square pattern being etched into a circle. After etching nitride 1251, oxide 1146 is etched onto a portion of the top of semiconductor material 941 and channel material 501, wherein the portion of the top of channel material 501 has been removed by an etchant. Semiconductor material 1810 has been deposited in the opening 1460 formed by removing the portion of channel material 501, on top of the surface of oxide spacer 1766, and on the top surface of oxide 1256. Semiconductor material 1810 may be, but is not limited to, the same as channel material 501, semiconductor material 641, or semiconductor material 941. For example, semiconductor material 1810 may be polysilicon. The deposited semiconductor material 1810 may be an n-semiconductor material used to form the transistor channel region of the SGD transistor to be formed.

[0071] Figure 19 Displayed after further processing stages have been performed. Figure 18 A cross-sectional view of the structure. The cross-sectional view is along... Figure 13B The cross-sectional line. Oxide 1903 has formed in Figure 18 In the opening 1460 shown, and on the top surface of the semiconductor material 1810, the semiconductor material is on top of the surface of the oxide spacer 1766 and on the oxide 1256. A suitable deposition technique can be used to perform the formation of oxide 1903. Oxide 1903 fills the opening 1460 to fill the area of ​​the SGD transistor. A CMP process has been applied to the surface of oxide 1903, resulting in the semiconductor material 1810 being exposed on oxide 1256 and the top surface of the oxide 1903 filling the opening 1460 with the exposed semiconductor material 1810.

[0072] Figure 20 The image shows the opening 2060 after the oxide 1903 has been recessed and demarcated by the semiconductor material 1810. Figure 19 A cross-sectional view of the structure. The cross-sectional view is along... Figure 13B The cross-sectional line.

[0073] Figure 21 After semiconductor material 2120 is formed on oxide 1903 in semiconductor material 1810 and opening 2060. Figure 20 The cross-sectional view of the structure reduces the size of the opening 2060. The cross-sectional view is along... Figure 13BThe cross-sectional line is shown. A suitable deposition technique can be used to form semiconductor material 2120. Semiconductor material 2120 may be, but is not limited to, the same as channel material 501, semiconductor material 641, or semiconductor material 941. For example, semiconductor material 2120 may be polycrystalline silicon. However, semiconductor material 2120 is formed to be more heavily doped than semiconductor material 1810. For example, the deposited semiconductor material 2120 may be n+ polycrystalline silicon. Semiconductor material 2120 is subsequently processed to form the drain of the SGD transistor being formed.

[0074] Figure 22 Displayed after further processing stages have been performed. Figure 21 A cross-sectional view of the structure. The cross-sectional view is along... Figure 13B The cross-sectional line. Conductive regions 2220 have been formed on the semiconductor material 2120 within the reduced opening 2060 and on... Figure 21 The conductive region 2220 is on the semiconductor material 1810 and semiconductor material 2120 in the structure. The conductive region 2220 can be a metallic material suitable for use as a drain contact of a transistor. For example, the conductive region 2220 can comprise titanium, titanium nitride, tungsten, titanium, titanium nitride, or a combination of tungsten, or other metals. After forming the conductive region 2220, a CMP process is applied to obtain... Figure 22 The structure has semiconductor material 1810, semiconductor material 2120 and conductive region 2220 removed on the top layer of oxide spacer 1766 and oxide 1256, thereby leaving conductive region 2220 delimited by semiconductor material 2120 on oxide 1903.

[0075] Figure 23 The conductive region 2220, defined by semiconductor material 2120, is recessed on oxide 1903 to form an opening 2360. Figure 22 A cross-sectional view of the structure. The cross-sectional view is along... Figure 13B The cross-sectional line.

[0076] Figure 24 Displayed after the executed processing phase Figure 23 A cross-sectional view of the structure. The cross-sectional view is along... Figure 13B The cross-sectional line. A portion of semiconductor material 2120 and semiconductor material 1810 has been selectively removed. Removal can be performed by selective dry etching of semiconductor material 2120 and semiconductor material 1810, thereby expanding an opening 2360 around the conductive region 2220 on the remaining portion of semiconductor material 2120 located on oxide 1903. Carbon nitride 2442 has been formed in the expanded opening 2360 and on the top surface of oxide 1256. The formation of carbon nitride 2442 can be performed using a suitable deposition technique. Voids 2443 can be formed in the formation of carbon nitride 2442.

[0077] Figure 25 Displayed after further processing stages have been performed. Figure 24 A cross-sectional view of the structure. The cross-sectional view is along... Figure 13B The cross-sectional line is shown. The CMP process has removed the carbon nitride 2442 formed on the surface of oxide 1256, and has removed portions of oxide 1256 and oxide spacers 1766, as well as the carbon nitride 2442 on the top layer of oxide 1256. Nitride 1256 has been removed, leaving conductive regions 2220 and carbon nitride 2442, where voids 2443 are demarcated by oxide spacers 1766. This removal of nitride 1256 can be performed using wet etching.

[0078] Figure 26 The image shows the semiconductor material 1810 after removing oxide 1254 and sufficient oxide spacers 1766 to blow the oxide out of the void region and expose the ends of the void region. Figure 25 A cross-sectional view of the structure. Wet etching can be used to remove this type of oxide. The cross-sectional view is along... Figure 13B The cross-sectional line indicates the non-void region 2671.

[0079] Figure 27A The image shows the semiconductor material 1810 after removing oxide 1254 and sufficient oxide spacers 1766 to blow oxide out of void region 2772 and expose the end of corner void region 2772. Figure 26 Different cross-sectional views of the structure. Cross-sectional views are for... Figure 13B The star pattern 1361, the circular pattern 1362, and the oval patterns 1363-1, 1363-2, and 1363-3 shown in the image are along the... Figure 27B The cross-sectional line, and used for instance formation. Figures 4 to 14 And SGD transistors for memory cell pillars 17 to 41. Figure 27C It is a top view highlighting the corner gap area 2772 formed between the etched patterns 1362, 1363-1, 1363-2 and 1363-3 and the star pattern 1361.

[0080] Figure 28A The exposed semiconductor material 1810 is shown after removing the corner void region 2772 at the end of a distance below the top surface of carbon nitride 2442 to nitride 1251. Figure 27A A cross-sectional view of the structure. The cross-sectional view is along the star pattern 1361, the circular pattern 1362, and the elliptical patterns 1363-1, 1363-2, and 1363-3. Figure 27B and Figure 28B The cross-sectional line. Figure 28BThe enhancement of the corner gap area 2772 is indicated. Figure 28C It is a top view highlighting the increased corner gap area 2772 formed between the etchant patterns 1362, 1363-1, 1363-2 and 1363-3 and the star pattern 1361.

[0081] Figure 29 The demonstration was conducted during the subsequent mining of Nitride 1253. Figure 28A Oxide 2986 forms on top of the structure to protect the nitride 1251 thereafter. Figure 28A A cross-sectional view of the structure. The cross-sectional view is along... Figure 28B The cross-sectional line.

[0082] Figure 30 Displayed after further processing stages have been performed. Figure 29 A cross-sectional view of the structure. The cross-sectional view is along... Figure 28B The cross-sectional line. The top of oxide 2986 on carbon nitride 2442 and oxide 1253 has been removed. Removal can be performed by etching away the top portion of oxide 2986, thereby exposing oxide 1253 and carbon nitride 2442, leaving the remaining portion of oxide 2986 surrounding semiconductor material 2120 and oxide 1903. The exposed nitride 1253 is removed, which can be performed by etching. After removing nitride 1253, the remaining portions of oxide 2986 and oxide 1252 are removed, thereby causing Figure 29 The structure has a small opening on the semiconductor material 1810 relative to the top of nitride 1251. The remaining portions of oxide 2986 and oxide 1252 can be removed by etching.

[0083] Figure 31 The oxide 3186 has been formed in Figure 30 After the top of the structure Figure 30 A cross-sectional view of the structure. The cross-sectional view is along... Figure 28B The cross-sectional line. Oxide 3186 can be deposited using a suitable deposition technique to cover the top of nitride 1251 delimited by oxide 1903, nitride 1251, and semiconductor material 1810, as well as the horizontal surface of carbon nitride 2442, semiconductor material 2120, oxide 1903, nitride 1251, and small openings on semiconductor material 1810. In the case where semiconductor material 1810 is to be processed to form the channel region of an SGD transistor, semiconductor material 1810 can be an n-type semiconductor material.

[0084] Figure 32 Displayed after oxide 3186 has been removed from the horizontal surface covered with carbon nitride 2442, semiconductor material 2120, oxide 1903 and nitride 1251. Figure 31 The structure along Figure 28B A cross-sectional view of the cross-sectional line. Oxide 3186 is recessed in a small opening on top of semiconductor material 1810 relative to nitride 1251 and demarcated by oxide 1903, nitride 1251, and semiconductor material 1810. Oxide 3186 is recessed in the gap on semiconductor material 1810, thereby leaving sufficient coating on semiconductor material 1810 to block subsequent processing of more heavily doped material at the bottom of the notch rather than on the sides. Semiconductor material 1810 may be n-doped, with the upper region being doped with n+.

[0085] Figure 33 Demonstrating the formation of semiconductor material 3305, which is heavily doped relative to semiconductor material 1810. Figure 32 The structure along Figure 13B A cross-sectional view of the cross-sectional line. Semiconductor material 3305 is a portion of material 1810, which has n+ dopants implanted or diffused therein. Along Figure 13B The cross-sectional line indicates the non-void region 2671. Semiconductor material 3305 may be, but is not limited to, the same as semiconductor material 2120, semiconductor material 1810, semiconductor material 941, semiconductor material 641, or channel material 501 used in previous processing stages. For example, semiconductor material 3305 may be polysilicon. In the case where semiconductor material 1810 is an n-semiconductor material, the semiconductor region may be an n+ material formed to produce an abrupt n+ junction. In the case where semiconductor material 1810 is polysilicon, semiconductor material 3305 is polysilicon with an n+ dopant implanted or diffused therein. This can be accomplished by phosphorus-rich oxide or plasma doping (PLAD) implantation, which has a heating step to drive the dopant into a portion of the polysilicon of semiconductor material 1810 and activate the implanted material in the polysilicon. Doping occurs only on the exposed 1810 polysilicon, with a small amount diffusing from the exposed portion of polysilicon 1810 into the polysilicon. A abrupt junction is formed between the n+ polysilicon of semiconductor material 3305 and the n- polysilicon of semiconductor material 1810. Residues from phosphorus-rich oxide processes, PLAD processes, or other processes are removed after the desired n+ region is formed. The thickness of nitride 1251 can be configured for positive / negative gate overlap. If a slightly larger distance from the n+ of semiconductor material 3305 to the gate edge is desired, a small amount of nitride 1251 can be removed after the n+ dopant process has been cleared to adjust this length.

[0086] Figure 34A exhibit Figure 31 The structure along Figure 13B Cross-sectional views of different cross-sectional lines of a star-shaped pattern. Figure 34A The cross-sectional line of the star-shaped pattern 1361 is in Figure 34BThe image is shown as a star-shaped pattern 1361 along the column structure 1345. Figure 34A The non-void region 2671 and void 2772 are indicated. A segmented channel structure is shown extending from semiconductor material 1810, wherein the segmented channel structure includes n+ semiconductor material 3305 structured as fins and a non-conductive region formed by void 2772. The n+ semiconductor material 3305 is formed from a portion of the n+ doped semiconductor material 1810, wherein the semiconductor material 1810 may be polycrystalline silicon. A sharp corner region 3412 extends from the n+ semiconductor material 3305 (shown as a fin on the upper left) toward another n+ semiconductor material 3305 shown as a fin on the right, but does not intersect with it. The sharp corner region 3412 can be doped to the doping level of the semiconductor material 3305, which is provided to form the fins. The sharp corner region provides high GIDL operation. Between the two sharp corner regions is a rounded corner 3408 of the vertical boundary of the semiconductor material 1810. The rounded corner 3408 provides the n-bottom of the cut region between the n+ sharp corners, where the dopant is blocked by the oxide above the rounded corner 3408. The n+ dopant will diffuse into any exposed silicon and dop it into n+, until it reaches the oxide at the bottom of the rounded region. The oxide at the bottom prevents n+ from diffusing into the polysilicon below.

[0087] Figure 34C This demonstrates the semiconductor material extending from structure 1045. Figure 34A The representation of the SGD transistor structure in the diagram. Figure 34C The structure includes a channel region 1810 adjacent to the gate 3415 and includes a drain 2120 coupled to the channel region 1810 via fins 3305, the fins having a sharp corner region 3412 extending below the interface between the fins 3305 and the channel region 1810, wherein the channel region 1810 has rounded corners 3408 between the fins 3305.

[0088] Figure 35 Displayed after further processing stages have been performed. Figure 33 A cross-sectional view of the structure. The cross-sectional view is along... Figure 13B The cross-sectional line indicates the non-porous region 2671. Carbon nitride 3542 has formed a covering. Figure 33 The top surface of the structure allows carbon nitride 2442 to extend and cover the top surfaces of semiconductor material 3305 and nitride 1251. Carbon nitride 3542 can be formed using a suitable deposition technique. Carbon nitride 3542 has been etched with spacers to expose the top surface of nitride 1251 and to maintain portions of carbon nitride 3542 around conductive region 2220 and semiconductor material 3305.

[0089] Figure 36Demonstrated after removal of nitride 1251 and exposure of oxide 1146 Figure 35 A cross-sectional view of the structure. Nitride 1251 can be removed by wet etching. The cross-sectional view is along... Figure 13B The cross-sectional line indicates the non-void region 2671.

[0090] Figure 37 Demonstrated after removal of nitride 1251 and exposure of oxide 1146 Figure 35 Another cross-sectional view of the structure. The cross-sectional view is along... Figure 27B The cross-sectional line indicates the corner gap area 2772.

[0091] Figure 38A Displayed after removal of oxide 1146 Figure 37 A cross-sectional view of the structure. The cross-sectional view is along... Figure 27B The cross-sectional line indicates the corner void region 2772. This view shows the small sharp corner region 3812, which can be implemented as the n+ polysilicon sharp corner at the bottom of the n+ channel (fin) chamfered void region 2772. Figure 38B The fin 3305 has a sharp corner 3812 and is separated from the non-conductive region 3307. The fin 3305 couples the semiconductor material 1810 to the n+ drain contact 3823, forming the fin 3305 as a drain channel.

[0092] Figure 39A Displayed after removal of oxide 1146 Figure 37 Another cross-sectional view of the structure. The cross-sectional view is along... Figure 13B The cross-sectional line indicates the non-void region 2671. Figure 39B The diagram describes a fin 3305 separated by a non-conductive region 3307, wherein the fin 3305 contacts a semiconductor material 1810 at an interface 3913. Interface 3913 may be formed from an n+ polysilicon channel that contacts an n-channel at the bottom of the n+ fin. The fin 3305 couples the semiconductor material 1810 to an n+ drain contact 3823, thus forming the drain channel region.

[0093] Figure 40 Display in forming a coverage Figure 39A After the surface oxide 4014 of the structure Figure 39A A cross-sectional view of the structure. Oxide 4014 can be formed using a suitable deposition technique. Further processing of oxide 4014 is performed in a subsequent stage to form the gate oxide for the SGD transistor being constructed. The cross-sectional view is along... Figure 13B The cross-sectional line shows the non-void region 2671.

[0094] Figure 41 Displayed in Coverage Figure 40After forming conductive material 4115 on the surface oxide 4014 of the structure Figure 40 A cross-sectional view of the structure, showing structure 4100 formed on pillar structure 1045 for memory cell layer 1130 group. Conductive material 4115 can be formed by a suitable deposition technique. The cross-sectional view is along... Figure 13B The cross-sectional line indicates the non-void region 2671. Conductive material 4115 will be processed to form the gate of the SGD transistor. Titanium, titanium nitride, tungsten, or combinations thereof may be deposited to form the SDG gate. Other conductive materials with sufficient properties for use as transistor gates may be used for the SDG gate. The thickness of the gate provided by conductive material 4115 may be designed to be thick enough to bridge the SGD transistors between each sub-block of the memory array being constructed, but not thick enough to bridge the sub-blocks together. Ideally, sufficient space will exist between the sub-blocks to deposit the gate conductor and oxide spacers. This space allows for dry etching of the oxide spacers, thereby allowing the conductive material 4115 to be wet-etched away from the bottom of the trenches forming it and off the surface. This will allow portions of the oxide 4014 and semiconductor material 941 on top of the channel material 501 of pillar 405 to remain undamaged, and the SGD gate oxide to be deposited directly on top of the channel material 501 and semiconductor material 941 of pillar 405. If the conductive material 4115 is removed using dry etching, these layers may be damaged.

[0095] Figure 42 Showing from Figure 41 A cross-sectional view of multiple structures 4100 of two sub-blocks 4291 and 4293 for a memory array after further processing stages have been performed. A thin spacer oxide 4242 has been formed on the top surface of the multiple structures 4100 and on the surface of the trench 4221 separating the two sub-blocks. The thin spacer oxide 4242 can be formed using a suitable deposition technique. After the formation of the thin spacer oxide 4242, it has been dry etched, leaving the thin spacer oxide 4242 on the vertical walls and bottom corners of the trench 4221, exposing the conductive material 4115 at the top surface of the multiple structures 4100 and the bottom of the trench 4221.

[0096] Figure 43 exhibit Figure 42 The two sub-blocks 4291 and 4293 of the structure are cross-sectional views after further processing to modify the multiple structures 4100 that form the multiple structures 4300. The conductive material 4115 on the top surface of the multiple structures 4100 has been wet-etched from the top surface of the oxide 4014 of the multiple structures 4100 and from... Figure 42Conductive material 4115 is removed from the region of oxide 4014 in the trench 4221 of the structure. Conductive material 4115 has also been recessed between the multiple structures 4100 to form multiple structures 4300. Oxide 4346 has been formed on the top surface of the multiple structures 4300. Figure 42 The oxide 4014 is deposited in the exposed areas of the trench 4221 and in the recesses of the conductive material 4115 between the multiple structures 4300. Suitable deposition techniques can be used to deposit the oxide 4346.

[0097] Figure 44 exhibit Figure 43 The cross-sectional view of the two sub-blocks 4291 and 4293 of the structure after the further processing stage has been performed to modify the multiple structures 4300 into multiple structures 4400. Figure 43 The top of the structure has been subjected to a CMP process to planarize oxide 4346 downwards to carbon nitride 3542. After the CMP process, the remaining oxide 4346 between the carbon nitride 3542 in adjacent structures 4300 in each sub-block has been removed, exposing conductive material 4115, forming multiple structures 4400.

[0098] Figure 45 exhibit Figure 44 The two sub-blocks 4291 and 4293 of the structure are cross-sectional views after further processing stages have been performed to modify the plurality of structures 4400 into a plurality of structures 4500. Exposed conductive material 4115 adjacent to carbon nitride 3542 has been recessed into a layer near the top of semiconductor material 1810 in each of the plurality of structures 4400, wherein semiconductor material 1810 will form the transistor channel region of the SGD transistor. The openings from which the exposed conductive material 4115 is recessed have been filled with oxide 4546, and the surfaces of the plurality of structures have been planarized by CMP on the top of conductive region 2220, thereby producing the plurality of structures 4500.

[0099] Figure 46 exhibit Figure 45 The structure is shown in cross-sectional views of two sub-blocks 4291 and 4293 after patterning and etching opening 4621. Opening 4621 will be processed to fill with conductive material to form contacts with SGD transistors and other components of the memory device.

[0100] Figure 47 exhibit Figure 46 The cross-sectional view of the two sub-blocks 4291 and 4293 of the structure after the further processing stage has been performed. Figure 46The opening 4621 of the structure has been filled with conductive material 4724, followed by a CMP process. The CMP process involves forming oxide 4746 on a planarized surface, patterning oxide 4746, and removing portions of oxide 4746 based on the patterning to form the contactable opening 4721.

[0101] Figures 48 to 90 Another embodiment of an example method for forming a memory device with an array of memory cell strings is illustrated, wherein each string is formed as a vertical column coupled to an SGD transistor. Features associated with the stage of forming the SGD transistor coupled to the memory cell strings are shown in some of the figures in these figures. In this embodiment, after forming the SGD transistor, the SGD transistor with segmented fins and sharp corners is formed with drain contacts configured to contact downward conductive landing pads. The conductive landing pads may be, but are not limited to, n+ drain landing pads. For the procedures discussed herein, the choice of processing material may depend on the materials selected to form the various components of the device of the memory array and the contacts to the device. Processing materials may be selected to allow the removal of one or more materials while retaining one or more other materials. Alternatively, deposition techniques typical of the material being formed, the size of the material being formed, or the architecture of the material being formed may be used.

[0102] Figure 48 The diagram shows a material layer 4830 after etching to form openings 4831 in the material layer 4830 and in the carbon nitride layer 4842 for forming memory cells in the openings 4831, and a carbon nitride layer 4842 on the material layer 4830. Dielectric materials other than the carbon nitride layer may be used for the carbon nitride layer 4842. The material layer 4830 may comprise a stack of alternating layers of insulating dielectrics and sacrificial regions, wherein the sacrificial regions are used to form the gates of the memory cells, and each insulating dielectric separates adjacent memory cell layers. The number of material layers 4830 depends on the number of memory cell layers to be formed in the openings 4831. The number of layers can range from a few to thousands or even more, depending on the number of memory cells in the string.

[0103] Figure 49 The image shows the process after oxide 4939 has been deposited on the material of the unit membrane and channel material. Figure 48 A cross-sectional view of one of the openings 4831. Figure 48Each opening 4831 can be structured and processed in the same manner. Each cell may contain elements of a transistor to store charge. For example, each cell may contain a channel region in which current can flow during the operation of the memory device, a tunnel region separating the channel from a charge-trapping region for storing charge, and a dielectric barrier region separating the gate from the charge-trapping region. In various embodiments, a dielectric barrier region structured as a thin region may be disposed between the dielectric barrier region and the gate, thereby implementing an enhanced tunneling barrier that prevents electrons from tunneling backward from the gate through the dielectric barrier region to the charge-trapping region. Figure 49 The material of the unit membrane in the opening 4831 may include dielectric barrier material 4934, charge trapping material 4936, tunneling material 4938, and channel material 4901.

[0104] In embodiments using a dielectric barrier, although Figure 49 Not shown, but a dielectric barrier material may be deposited on the surface of opening 4831. The dielectric barrier material may be realized as an alumina region or a dielectric region having a higher dielectric constant than alumina. For example, the dielectric barrier material may comprise alumina, hafnium oxide, zirconium oxide, or one or more mixtures of hafnium oxide and / or zirconium oxide with one or more of alumina, silicon oxide, titanium oxide, gadolinium oxide, niobium oxide, or tantalum oxide. Other high-κ dielectrics may be used for the dielectric barrier. The dielectric barrier material may be formed in the region as a nanolayer of multiple different compounds, said nanolayer located in each sub-region of the region, wherein the formed region has a total thickness in the nano-region. The dielectric barrier material may be formed with a thickness in the range of 20 to 50 angstroms from the wall of opening 4831.

[0105] As in Figure 49 As shown, dielectric barrier material 4934 can be formed on the surface of opening 4831, or formed on the dielectric barrier material after such dielectric barrier material is formed on the surface of opening 4831. Dielectric barrier material 4934 can be silicon oxide, a high-k dielectric, or a combination of silicon oxide or one or more high-k dielectric materials. When a dielectric barrier material is used, the material of the dielectric barrier material 4934 that interfaces with the dielectric barrier material is selected to be different from the material of the dielectric barrier material at the interface.

[0106] After forming the dielectric barrier material 4934, a charge trapping material 4936 may be formed on the dielectric barrier material 4934. The charge trapping material 4936 may be structured from materials capable of retaining electrons received from the channel region of the corresponding memory cell during operation. For example, the charge trapping material 4936 may be a dielectric material capable of storing charge. The charge trapping material 4936 may be a dielectric nitride region, such as a region containing dielectric silicon nitride. Other dielectric materials for the charge trapping material 4936 may be used to trap charge. Depending on the memory cell design, materials operating as a floating gate transistor structure may be used for the charge trapping material 4936.

[0107] After forming the charge trapping material 4936, a tunneling material 4938 may be formed on the charge trapping material 4936. The tunneling material 4938 may be configured as an engineered region to meet selected criteria, such as, but not limited to, a selected EOT. The tunneling material 4938 may contain oxides and nitrides. The tunneling material 4938 may contain a high-k dielectric. The tunneling material 4938 may contain a set of dielectric regions. The tunneling material 4938 may be a three-region structure. Such a three-region structure may be arranged as a dielectric oxide region followed by a dielectric nitride region, and then another dielectric oxide region. The tunneling material 4938 may be a two-region tunnel structure or a single-region tunnel structure. Furthermore, the tunneling material 4938 may have four or more regions, wherein the selection of materials and thickness depends on the ability of a material with a given thickness to perform as a tunneling region in charge trapping.

[0108] After forming the tunneling material 4938, a channel material 4901 can be formed on the tunneling material 4938. The channel material 4901 can be structured as semiconductor material pillars arranged vertically from the source line for an array of memory cell strings and arranged to couple with the SGD transistor to be formed. The channel material 4901 can be implemented as a polysilicon channel structure. Other semiconductor types and materials can be used for the channel material 4901.

[0109] Figure 50 Displayed after several processing stages have been executed Figure 49 A cross-sectional view of the structure. A CMP procedure has been performed on oxide 4939 to expose the top surface of channel material 4901, which is formed on carbon nitride 4842 located on material layer 4830. Oxide 4939 has been recessed to form opening 5031.

[0110] Figure 51 The image shows the channel material 4901, tunneling material 4938, charge trapping material 4936, and dielectric barrier material 4934 after the removal of carbon nitride 4842. Figure 50A cross-sectional view of the structure. The removal of these materials can be performed using a suitable wet etching technique. Horizontal removal of these materials is achieved by recessing the material of the unit film into a notch in opening 5031, which can extend to a layer below the top of carbon nitride 4842.

[0111] Figure 52 Demonstrating the formation of semiconductor material 5241 on the top surface of the structure Figure 51 A cross-sectional view of the structure. Semiconductor material 5241 can be formed using appropriate deposition techniques. Semiconductor material 5241 can be, but is not limited to, the same as channel material 4901. For example, semiconductor material 5241 can be polycrystalline silicon.

[0112] Figure 53 exhibit Figure 52 The cross-sectional view of the structure after the CMP process has been applied to the surface shows that the semiconductor material 5241 previously formed on the top surface of the carbon nitride 4842 has been removed, leaving portions of the semiconductor material 5241 on the top surfaces of the oxide 4939, channel material 4901, tunneling material 4938, charge trapping material 4936, and dielectric barrier material 4934. The top surface of the semiconductor material 5241 has been planarized to lie on the top surface of the carbon nitride 4842.

[0113] Figure 54 Display in processing Figure 48 The opening 4831 was formed during the processing. Figure 53 The structure after Figure 48 A cross-sectional view of the structure. After the semiconductor material 5241 has been formed and the top of the cell film has undergone a CMP process, appropriate removal of portions of the material layer 4830 group has been performed to form the gate for the memory cell. Removal may include etching in a gate replacement process to form the gate. A thicker oxide layer may be deposited during gate formation. The processing of the material layer 4830 group results in a set of memory cell layers 4830 having gates coupled to the cell film of structure 5445. During the subsequent processing discussed below, the configuration of layers 4830 and structure 5445 remains substantially unchanged for the SGD transistor. Structure 5445 comprises a vertical string of memory cells having a dielectric barrier material 4934, a charge trapping material 4936, a tunneling material 4938, and a channel material 4901 that can be disposed around oxide 4939.

[0114] Figure 55 Shown Figure 54 After forming a processing layer on top of the structure Figure 54A cross-sectional view of a set of layers 4830, region 5545, carbon nitride 4842, semiconductor material 5241, and oxide 5546 in an example string pillar. The processed layers may comprise oxide 5546, nitride 5551, oxide 5552, nitride 5553, and oxide 5554. The formation of these processed layers can be performed using one or more suitable deposition techniques.

[0115] Figure 56A The display shows the formation of opening 5660 through oxide 5554, nitride 5553, and oxide 5552 to nitride 5551. Figure 55 A cross-sectional view of the structure. In this example, circular and elliptical patterns are etched through the top of oxide 5554, nitride 5553, and oxide 5552 to nitride 5551. A resist pattern has been formed, and circular and wavy patterns have been etched through oxide 5554, nitride 5553, and oxide 5552. Figure 56B A top view showing the possible resist patterns of circular pattern 5662 and elliptical patterns 5663-1, 5663-2 and 5663-3 used for etching pattern 5661 on the surface of column structure 5645. Figure 56A The cross-sectional view is along Figure 56B The cross-sectional line. The pattern allows for the design of gaps between the downwardly etched patterns to form keyholes, which remain free of deposited material in subsequent stages. The narrow gaps between the resist patterns of circular pattern 5662 and elliptical patterns 5663-1, 5663-2, and 5663-3 and the etched pattern 5661 form the star-shaped ends of the etched pattern 5661. The etched points in and between the fins are formed by the narrow gaps between the resist patterns of circular pattern 5662 and elliptical patterns 5663-1, 5663-2, and 5663-3 and the etched pattern 5661. The number of points in the star-shaped pattern 5661 corresponds to the number of fins to be formed.

[0116] A star-shaped opening 5661 between the circle and the ellipse is centered to position the contacts of the forming SGD. Multiple such openings are arranged on the surface of the pillar structure 5645 and between the circle and the ellipse spanning the surface of the pillar structure 5645, such that the center of the opening is positioned for contact with the multiple SGD transistors of the pillar structure 5645. The center of the opening 5660 is relative to... Figure 56A The vertical column structure 5645 was horizontally shifted.

[0117] Figure 57 exhibit Figure 56AThe cross-sectional view of the structure after the formation of oxide spacers 5766 to bridge the circular and elliptical patterns together to form sharp corners is shown. Appropriate deposition techniques can be used to form the oxide spacers 5766. The oxide spacers 5766 are formed sufficiently non-conformally to deposit more on the surface of the oxide 5554 than on the sidewalls and bottom of the opening 5660, so that after the spacers are etched, the oxide is removed from the bottom of the opening 5660 but remains on the surface to protect the gaps between the patterns. The cross-sectional view is along... Figure 56B The cross-sectional line. Sufficient clearance should be made between the circular and elliptical features.

[0118] Figure 58 The images shown are of each material selectively etched on top of nitride 5551, oxide 5546, semiconductor material 5241, and structure 5445. Figure 57 A cross-sectional view of the structure. Carbon nitride 4842 is used as an etch stop layer to prevent damage to access line 4830. This selective etching results in the formation of opening 5860. The cross-sectional view is along... Figure 56B The cross-sectional lines. The etching process caused the square pattern to be etched into a circle.

[0119] Figure 59 Demonstrating the formation of semiconductor material 5910 in opening 5860 Figure 58 A cross-sectional view of the structure. The cross-sectional view is along... Figure 56B The cross-sectional line. Semiconductor material 5910 can be formed using appropriate deposition techniques. Semiconductor material 5910 can be, but is not limited to, the same as channel material 4901 or semiconductor material 5241. For example, semiconductor material 5910 can be polycrystalline silicon. The deposited semiconductor material 5910 can be an n-semiconductor material used to form the transistor channel region of the SGD transistor to be formed.

[0120] Figure 60 The oxide 6003 has been formed in Figure 59 The opening 5860 shown is located on top of the surface of the oxide spacer 5766 and on the top surface of the semiconductor material 5910 on the oxide 5554. Figure 59 A cross-sectional view of the structure. The cross-sectional view is along... Figure 56B The cross-sectional line is shown. A suitable deposition technique can be used to perform the formation of oxide 6003. Oxide 6003 fills the opening 5860 to fill the area of ​​the SGD transistor.

[0121] Figure 61 Demonstrated after applying a CMP process to the surface of oxide 6003 Figure 60 A cross-sectional view of the structure. The cross-sectional view is along... Figure 56BThe cross-sectional line. The CMP process results in the exposure of semiconductor material 5910 on oxide 5554 and the top surface of oxide 6003 is structured with the top surface of the exposed semiconductor material 5910, which fills the previous opening 5860.

[0122] Figure 62 Displayed after the oxide 6003 has been recessed to form the opening 6221 Figure 61 A cross-sectional view of the structure. The cross-sectional view is along... Figure 56B The cross-sectional line.

[0123] Figure 63 The image shows the material after semiconductor material 6320 has been formed and CMP process has been applied to planarize the top of semiconductor material 6320, oxide spacers 5766 and oxide 5554 and remove the material of channel 5910 from the surface. Figure 62 A cross-sectional view of the structure. The cross-sectional view is along... Figure 56B The cross-sectional line is shown. A suitable deposition technique can be used to form the semiconductor material 6320. The semiconductor material 6320 may be, but is not limited to, the same as the channel material 5910 or the semiconductor material 5241. For example, the semiconductor material 6320 may be polycrystalline silicon. However, the semiconductor material 6320 is formed to be more heavily doped than the semiconductor material 5910. For example, the deposited semiconductor material 6320 may be n+ polycrystalline silicon. The semiconductor material 6320 is subsequently processed to form the drain of the SGD transistor being formed.

[0124] Figure 64 Displayed after the 6320 semiconductor material has been recessed. Figure 63 A cross-sectional view of the structure. The cross-sectional view is along... Figure 56B The cross-sectional line.

[0125] Figure 65 The demonstration shows the process after carbon nitride 6542 has been formed and CMP technology has been applied to carbon nitride 6542, oxide spacer 5766, and oxide 5554 to leave a plug on top of semiconductor material 6320. Figure 64 A cross-sectional view of the structure. This plug provides a landing area for subsequent etching to form contacts to the formed SGD transistor. Materials other than carbon nitride 6542 can be used as contact etching punch materials if such materials can withstand wet etching materials, such as polysilicon, oxides, and nitrides used in the method. The cross-sectional view is along... Figure 56B The cross-sectional line.

[0126] Figure 66 exhibit Figure 65A cross-sectional view of the structure, indicating that after sufficient oxide spacers 5766 have been wet-etched to blow the oxide out of the void regions and expose the semiconductor material 5910 at the ends of the void regions, the non-void regions 6671 are shown. Semiconductor material 5910 is a lighter-doped material than semiconductor material 6320. Semiconductor material 5910 may be, but is not limited to, n-polysilicon. The cross-sectional view is along... Figure 56B The cross-sectional line.

[0127] Figure 67A exhibit Figure 66 Different cross-sectional views of the structure indicate the void region 6772. The cross-sectional views are along... Figure 67B The cross-sectional lines shown in the figure. Figure 67B A top view showing the possible resist patterns of circular pattern 5662 and elliptical patterns 5663-1, 5663-2 and 5663-3 used for etching pattern 5661 on the surface of column structure 5645. Figure 67C It is a top view highlighting the corner gap area 6772 formed between the etched patterns 5662, 5663-1, 5663-2 and 5663-3 and the star pattern 5661.

[0128] Figure 68A After selective wet etching of semiconductor material 5910 at the ends of semiconductor material 6320, oxide 6003, and corner void region 6772. Figure 67A A cross-sectional view of the structure. The cross-sectional view is along... Figure 67B The cross-sectional lines shown in the figure. Figure 68B The extended corner pore region 6772 is shown.

[0129] Figure 69 Shown Figure 68A After oxide 6966 forms on the exposed surface Figure 68A A cross-sectional view of the structure. Oxide 6966 can be formed using appropriate deposition techniques. Porosity 6943 can be formed during the formation of oxide 6966. The cross-sectional view is along... Figure 67B The cross-sectional lines shown in the figure.

[0130] Figure 70 The image shows the portion after removing oxide 6966 and exposing nitride 5553. Figure 69 A cross-sectional view of the structure. A portion of oxide 6966 can be removed using appropriate etching techniques. The cross-sectional view is along... Figure 67B The cross-sectional lines shown in the figure.

[0131] Figure 71 Demonstrated after removal of exposed nitride 5553 and exposure of oxides 6966 and 5552. Figure 70A cross-sectional view of the structure. Exposed nitride 5553 can be removed using appropriate etching techniques. The cross-sectional view is along... Figure 67B The cross-sectional lines shown in the figure.

[0132] Figure 72 Demonstrated after removal of exposed oxides 6966 and 5552 Figure 71 A cross-sectional view of the structure. The exposed oxide 6966 can be removed using appropriate etching techniques. The cross-sectional view is along... Figure 67B The cross-sectional lines shown in the figure.

[0133] Figure 73 Display in formation Figure 72 After the oxide 7386 on the exposed surface of the structure. Figure 72 A cross-sectional view of the structure. Exposed oxide 7386 can be formed using appropriate deposition techniques. The cross-sectional view is along... Figure 67B The cross-sectional lines shown in the figure.

[0134] Figure 74 Displayed after oxide 7386 has been removed from the horizontal surface covered with carbon nitride 6542, semiconductor material 6320, oxide 6003 and nitride 5551. Figure 73 A cross-sectional view of the structure. The remaining oxide 7386 is recessed relative to the top of nitride 5551 in a small opening defined by oxide 6003, nitride 5551, and semiconductor material 5910. The oxide 7386 is recessed in the gaps on semiconductor material 5910, leaving sufficient coating on semiconductor material 5910 to block subsequent processing of more heavily doped material at the bottom of the notch rather than on the sides. Semiconductor material 5910 may be n-doped, where more heavily doped material is formed in the structure as n+ doped. The cross-sectional view is along... Figure 67B The cross-sectional lines shown in the figure.

[0135] Figure 75 Demonstrating the formation of semiconductor material 7505, which is heavily doped relative to semiconductor material 5910. Figure 74 The structure along the non-porous region 6671 Figure 56BA cross-sectional view of the cross-sectional line. Semiconductor material 7505 is a portion of material 5910 having an n+ dopant implanted or diffused therein. Semiconductor material 7505 may be, but is not limited to, the same as semiconductor material 6320, semiconductor material 5910, semiconductor material 5241, or channel material 4901 used in previous processing stages. For example, semiconductor material 7505 may be polysilicon. In the case where semiconductor material 5910 is an n-semiconductor material, semiconductor material 7505 is an n+ material formed to produce abrupt n+ junctions. In the case where semiconductor material 5910 is polysilicon, semiconductor material 7505 may be polysilicon in which an n+ dopant is implanted or diffused. This can be accomplished by phosphorus-rich oxide or plasma doping (PLAD) implantation, which has a heating step to drive the dopant into the polysilicon portion of semiconductor material 5910 and activate the implanted material in the polysilicon. Doping occurs only on the exposed polysilicon 5910, with a small amount diffusing from the exposed portion of polysilicon 5910 into the polysilicon. A abrupt junction is formed between the n+ polysilicon of semiconductor material 7505 and the n- polysilicon of semiconductor material 5910. Residues from phosphorus-rich oxide processes, PLAD processes, or other processes are removed after the desired n+ region is formed. The thickness of nitride 5551 can be set to allow for positive / negative gate overlap. If a slightly larger distance from the n+ of semiconductor material 7505 to the gate edge is desired, a small amount of nitride 5551 can be removed after the n+ dopant process has been cleared to adjust this length.

[0136] Figure 76A Displayed along column structure 5645 Figure 76B The cross-sectional lines of the star pattern 5661 shown in the image Figure 75 A cross-sectional view of the structure. Figure 76A The non-void regions 6671 and voids 6672 are illustrated. A segmented channel structure is shown extending from semiconductor material 5910, comprising n+ semiconductor material 7505 structured as fins and a non-conductive region formed by voids 6672. Sharp corner regions 7612 extend from n+ semiconductor material 7505 (shown as a fin on the upper left) toward n+ semiconductor material 7505 extending as another fin on the right, but do not intersect with it. Sharp corner regions 7612 can be doped to the doping level of the semiconductor material 7505 forming the fins. Sharp corner regions 7612 provide high GIDL operation. Between the two sharp corner regions 7612 is a rounded corner 7608 of the vertical boundary of semiconductor material 5910. The rounded corner 7608 provides an n-bottom of the cleaved region between the n+ sharp corners, where the dopant is blocked by the oxide on the rounded corner 7608. The n+ dopant diffuses into any exposed silicon and dops with n+ until it reaches the oxide at the bottom of the circular region. The oxide at the bottom prevents n+ from diffusing into the polysilicon below.

[0137] Figure 76C The display corresponds to the semiconductor material extending from cell 5445. Figure 76A The representation of the SGD transistor structure in the diagram. Figure 76C The structure includes a channel region 5910 adjacent to a gate 7615 and a drain 6320 coupled to the channel region 5910 via fins 7505, the fins having a sharp corner region 7612 extending below the interface between the fins 7505 and the channel region 5910, wherein the channel region 5910 has rounded corners 7608 between the fins 7505.

[0138] Figure 77 The display shows that a coating has been formed on carbon nitride 7742. Figure 75 After the top surface of the structure is extended, carbon nitride 6542 extends and covers the top surfaces of semiconductor material 7505 and nitride 5551. Figure 75 A cross-sectional view of the structure. Carbon nitride 7742 can be formed using suitable deposition techniques. The cross-sectional view is along... Figure 56B The cross-sectional lines shown in the figure.

[0139] Figure 78 The image shows the portion after carbon nitride 7742 has been etched by spacers, exposing the top surface of carbon nitride 5551, and maintaining carbon nitride 7742 on semiconductor material 6320 and semiconductor material 7505. Figure 77 A cross-sectional view of the structure. The cross-sectional view is along... Figure 56B The cross-sectional lines shown in the figure.

[0140] Figure 79 Demonstrated after removal of nitride 5551 and exposure of oxide 5546 Figure 78 A cross-sectional view of the structure. Nitride 5551 can be removed by wet etching. The cross-sectional view is along... Figure 56B The cross-sectional lines shown in the figure.

[0141] Figure 80 Demonstrated after removal of nitride 5551 and exposure of oxide 5546 Figure 78 A cross-sectional view of the structure, wherein the cross-sectional view is along... Figure 67B The cross-sectional lines shown in the figure.

[0142] Figure 81A Demonstrated after removal of oxide 5546 and exposure of carbon nitride 4842 Figure 80 The cross-sectional view of the structure relative to the corner gap region 6772. For the star pattern 5661 in the column structure 5645, the cross-sectional view is along... Figure 67B The cross-sectional lines shown in the figure. Figure 81CThe fin 7605 has a sharp corner 7612 and is separated from the non-conductive region 8107. The fin 7605 couples the semiconductor material 5910 to the drain 6320 having an n+ drain contact 8123, thus forming the fin 7605 as a drain channel region.

[0143] Figure 82A Demonstrates the removal of oxide 5546 relative to the non-porosity region 6671 and exposure of carbon nitride 4842. Figure 79 A cross-sectional view of the structure. The cross-sectional view is along... Figure 56B The cross-sectional lines shown in the figure. Figure 82B The fin 7605 is described, and the fin is separated by a non-conductive region 8107. The sharp corner 8213 may be formed by an n+ polysilicon channel that contacts an n-channel at the bottom of the n+ fin. The fin 7605 couples semiconductor material 5910 to a drain 6320 having an n+ drain contact 8123, thus forming the fin 7605 as a drain channel region.

[0144] Figure 83 Display in forming a coverage Figure 82A After the surface oxide of the structure 8314 Figure 82A A cross-sectional view of the structure. Oxide 8314 can be formed using a suitable deposition technique. Further processing of oxide 8314 is performed in a subsequent stage to form the gate oxide for the SGD transistor being constructed. The cross-sectional view is relative to the non-void region 6671 along... Figure 56B The cross-sectional line.

[0145] Figure 84 Displayed in Coverage Figure 83 After forming conductive material 8415 on the surface oxide 8314 of the structure. Figure 83 A cross-sectional view of the structure. Conductive material 8415 can be formed using suitable deposition techniques. The cross-sectional view is along... Figure 56BThe cross-sectional line of the conductive material 8415. The result of forming the conductive material 8415 is the structure 8400 formed on the pillar structure 5445 of the layer 4830 group for memory cells. The structure 8400 is formed on multiple pillar regions of the memory cell layer group in the memory array for the memory device being processed. The conductive material 8415 will be processed to form the gate of the SGD transistor. Titanium, titanium nitride, tungsten, or combinations thereof can be deposited to form the SDG gate. Other conductive materials with sufficient properties for use as transistor gates can be used for the SDG gate. The thickness of the gate provided by the conductive material 8415 can be designed to be thick enough to bridge the SGD transistors between each sub-block of the memory array being constructed, but not thick enough to bridge the sub-blocks together. Ideally, there will be enough space between the sub-blocks to deposit the gate conductor and oxide spacers. This space allows for dry etching of the oxide spacers, thereby allowing the conductive material 8415 to be wet-etched away from the bottom of the trenches in which it is formed and away from the surface. This allows the SGD gate oxide to be deposited directly on top of the channel material 4901 and semiconductor material 5241 of the pillar structure 5445, thus allowing the transistor gate to be deposited on top of the semiconductor material of the previously mentioned portion forming the SGD transistor, and allowing the gate material between the sub-blocks to be etched without damaging the underlying gate oxide and semiconductor material.

[0146] Figure 85 This is demonstrated after a thin spacer oxide 8542 is formed on the exposed top surface of the conductive material 8415. Figure 83 The diagram shows a cross-sectional view of the structure 8400 formed at the stage shown. Spacer oxide 8542 can be formed using appropriate deposition techniques. An opening 8521 has been formed between sub-blocks 8591 and 8592.

[0147] Figure 86 The spacer oxide 8542 shown has been from Figure 85 The horizontal surface of the structure was removed, leaving oxide 8542 on the wall of opening 8521. Figure 85 A cross-sectional view of the structure. The thickness of the oxide 8542 on the wall of the opening 8521 can be formed, thus leaving the opening 8521 available for further processing. The removal of the spacer oxide 8542 can be achieved using a suitable dry etching technique.

[0148] Figure 87 Shown Figure 86 The portion of conductive material 8415 with exposed surfaces in the structure has been removed to form structure 8700 from structure 8400. Figure 86A cross-sectional view of the structure. Structure 8700 has oxide 8314 as the top surface. Conductive material 8415 can be removed by appropriate wet etching techniques. Conductive material 8415 has been removed from between sub-blocks 8591 and 8592 up to oxide 8314. The remaining conductive material 8415 will be used for the gate of the SGD transistor being formed.

[0149] Figure 88 Displayed after removal of exposed spacer oxide 8542 Figure 87 A cross-sectional view of the structure. The exposed spacer oxide 8542 can be removed using appropriate vapor phase etching techniques.

[0150] Figure 89 The oxide 8946 has been formed in Figure 88 The exposed top surface of the structure and the CMP procedure has been applied to oxide 8946 afterward. Figure 88 A cross-sectional view of the structure. Oxide 8946 can be formed using appropriate deposition techniques. The oxide material used for oxide 8946 can be the same as that used for oxide 8314.

[0151] Figure 90 Displayed after further processing stages have been performed. Figure 89 A cross-sectional view of the structure. A portion of oxide 8946 has been removed from the conductive material 6320 of structure 8700, and carbon nitride 6542 on the conductive material 6320 has also been removed. This material removal can be performed using appropriate etching techniques. Conductive material 9020 has been filled into the areas where the removed material has been incorporated. Conductive material 9020 provides contacts for the drain of the formed SGD transistor. Conductive material 9020 may comprise, but is not limited to, titanium, titanium nitride, tungsten, titanium, titanium nitride, or combinations thereof, or other suitable metallic materials.

[0152] although Figures 4 to 47 Methods and Figures 48 to 90 The method describes the formation of a structure similar to Figure 1D Examples of SGD transistors with a 102D channel structure are provided, but variations of these methods can be used to form other channel structures. For example, the teachings of these methods can be implemented to form a similar channel structure. Figure 1A , 1B The channel structures of 102A, 102B and 102C are also described.

[0153] Figure 91This illustrates a functional block diagram of an example memory device 9100, which includes a memory array 9102 having a plurality of memory cells 9104, and one or more circuits or components for providing communication with the memory array 9102 or performing one or more memory operations on the memory array. The memory device 9100 may be a memory die, such as a NAND memory die. The memory device 9100 may include a row decoder 9112, a column decoder 9114, a sub-block driver 9109, a sense amplifier 9120, a page buffer 9122, a selector 9124, input / output (I / O) circuitry 9126, and a memory controller 9130. The memory controller 9130 may include a processing circuitry system, including one or more processors 9105, and may be configured to perform operations of the memory device 9100 by executing instructions 9115. The memory controller 9130 may be coupled to a register 9131, which may contain parameter data for the memory controller 9130. For the purposes of this example, instruction 9115 may be executed by memory within memory controller 9130 or by memory dedicated to said memory controller. In other examples, at least some portions of the instructions executed by memory controller 9130 may be stored in other memory structures and, for example, loaded into local (memory controller) memory for execution by memory controller 9130. The operation may include an erase algorithm using SGD transistors that couple memory cell strings to data lines, wherein each SGD transistor has a drain channel structure segmented by one or more fins, the fins being separated by one or more non-conductive regions, wherein the fins and non-conductive regions extend vertically from the transistor channel region of a given SGD transistor, as taught herein. The segmented drain channel structure and transistor channel region of each SGD transistor may be respectively defined by… Figure 1A , 1B It can be implemented using any one of the channel structures 102A, 102B, 102C and 102D of 1C and 1D.

[0154] The memory cells 9104 of the memory array 9102 can be arranged in blocks, such as a first block 9102A and a second block 9102B. Each block can contain sub-blocks. For example, the first block 9102A can contain a first sub-block 9102A0 and a second sub-block 9102A0. N Furthermore, the second 9102B block may include the first sub-block 9102B0 and the second sub-block 9102B. NEach subblock may contain multiple physical pages, and each page contains multiple memory cells 9104. Although described herein as having two blocks, each block having two subblocks, and each subblock having multiple memory cells 9104, in other embodiments, the memory array 9102 may contain more or fewer blocks, subblocks, memory cells, etc. In other embodiments, the memory cells 9104 may be arranged in multiple rows, columns, pages, subblocks, blocks, etc., and accessed using, for example, access lines 9106, first data lines 9110, or one or more select gates, source lines, etc.

[0155] The memory controller 9130 can control the storage operation of the memory device 9100 based on one or more signals or instructions received on the control line 9132 (e.g., control signals including one or more clock signals or indicating the operation to be performed (e.g., write, read, erase, etc.)) or address signals (A0 to AX) received on one or more address lines 9116. One or more devices external to the memory device 9100 can control the values ​​of the control signals on the control line 9132 or the address signals on the address lines 9116. Examples of devices external to the memory device 9100 may include, but are not limited to, a host, an external memory controller, a processor, or... Figure 91 One or more circuits or components not specified in the text.

[0156] The memory device 9100 can use access lines 9106 and first data lines 9110 to transfer data to or from one or more memory cells 9104 (e.g., write or erase) or to transfer data from one or more memory cells (e.g., read). Row decoders 9112 and column decoders 9114 can receive and decode address signals (A0 to AX) from address lines 9116, determine which memory cells 9104 need to be accessed, and provide signals to access lines 9106 (e.g., multiple access lines (WL0 to WL...). M One or more of the data lines 9110 (e.g., one or more of the multiple data lines (BL0 to BLN)) or one or more of the first data lines 9110, as described above.

[0157] The memory device 9100 may include a sensing circuitry system, such as a sensing amplifier 9120, configured to use a first data line 9110 to determine the value of data on (e.g., read) the memory cell 9104, or to determine the value of data to be written to the memory cell. For example, in a selected string of memory cells 9104, one or more of the sensing amplifiers 9120 may read logic levels in the selected memory cells 9104 in response to a read current flowing through the selected string associated with the data line 9110 in the memory array 9102.

[0158] One or more devices external to the memory device 9100 may communicate with the memory device 9100 using I / O lines (DQ0 to DQN) 9108, address lines 9116 (A0 to AX), or control lines 9132. I / O circuitry 9126 may use I / O lines 9108 to transfer data values ​​to or from the memory device 9100, for example, to or from page buffer 9122 or memory array 9102, according to, for example, control lines 9132 and address lines 9116. Page buffer 9122 may store data received from one or more devices external to the memory device 9100 before it is programmed into a relevant portion of memory array 9102, or may store data read from memory array 9102 before it is transmitted to one or more devices external to the memory device 9100.

[0159] The column decoder 9114 can receive address signals (A0 to AX) and decode them into one or more column select signals (CSEL1 to CSEL1). N The selector 9124 (e.g., a selector circuit) can receive column select signals (CSEL1 to CSEL1). N The page buffer 9122 selects data representing the value of data to be read from or programmed into the memory cell 9104. The selected data can be transferred between the page buffer 9122 and the I / O circuitry 9126 using a second data line 9118.

[0160] The memory controller 9130 may receive positive and negative supply signals from an external power source or supply (e.g., an internal or external battery, an AC-to-DC converter, etc.), such as a supply voltage (Vcc) 9134 and a negative supply voltage (Vss) 9136 relative to Vcc (e.g., ground potential). In some instances, the memory controller 9130 may include a regulator 9128 to internally provide positive or negative supply signals.

[0161] To program or write data to a memory cell, a programming voltage (VPGM) (e.g., one or more programming pulses) can be applied to a selected access line (e.g., WL). iA programming voltage is applied to the control gate of each memory cell coupled to a selected access line. The programming pulse may begin, for example, at 15V or close to 15V, and in some instances, may be increased by an order of magnitude during each programming pulse application. When the programming voltage is applied to the selected access line, a potential, for example, ground potential (e.g., Vss), may be applied to the data line and substrate (and thus the channel structure between the source and drain) of the target memory cell for programming, causing charge transfer from the channel structure to the floating gate of the target memory cell (e.g., direct implantation or Fowler-Nordheim (FN) tunneling, etc.).

[0162] A Vpass can be applied to one or more access lines having untargeted memory cells for programming, or a suppressor voltage (e.g., Vcc) can be applied to data lines having untargeted memory cells for programming to, for example, prevent charge transfer from the channel structure to the floating gate of such untargeted memory cells. The pass voltage can be variable, for example, depending on the proximity of the applied pass voltage to the targeted access line for programming. The suppressor voltage can include a supply voltage (Vcc), such as a voltage from an external power source or supply (e.g., a battery, AC-to-DC converter, etc.) relative to ground potential (e.g., Vss).

[0163] As an example, if a programming voltage (e.g., 15V or higher) is applied to a specific access line (e.g., WL4), then a 10V pass voltage can be applied to one or more other access lines, such as WL3, WL5, etc., to prevent programming of non-target memory cells or to preserve the values ​​stored on such memory cells that are not intended for programming. As the distance between the applied programming voltage and the non-target memory cell increases, the pass voltage that inhibits programming of the non-target memory cell can be reduced. For example, when a 15V programming voltage is applied to WL4, a 10V pass voltage can be applied to WL3 and WL5, an 8V pass voltage to WL2 and WL6, a 7V pass voltage to WL1 and WL7, etc. In other examples, the pass voltage or the number of access lines can be higher or lower, more or fewer.

[0164] Between the application of one or more programming pulses (e.g., VPGM), a verification operation can be performed to determine whether a selected memory cell has reached its intended programmed state. If the selected memory cell has reached its intended programmed state, further programming of it can be prevented. If the selected memory cell has not yet reached its intended programmed state, additional programming pulses can be applied. If, after a certain number of programming pulses (e.g., a maximum number), the selected memory cell, or a string, block, or page associated with such selected memory cell, has not reached its intended programmed state, the selected memory cell or such string, block, or page can be marked as defective.

[0165] To erase a memory cell or a group of memory cells (e.g., erasure is typically performed in blocks or sub-blocks), an erase voltage (Vers) (e.g., typically VPGM) can be applied to the substrate of the memory cell targeted for erasure (and thus the channel between the source and drain) (e.g., using one or more data lines, select gates, etc.), while the access line of the target memory cell remains at a potential, such as ground potential (e.g., Vss), thereby causing a charge transfer from the floating gate of the target memory cell to the channel structure (e.g., direct implantation or FN tunneling, etc.).

[0166] When a host device, acting as a user device, sends an address to memory device 9100, it typically has block, page, and column identifiers. The block identifier is used to select the block of interest in the selection operation. The page identifier is used to select the write level (WL) on which the page resides, and also to select a specific sub-block, since the WL is shared among the sub-blocks of a block. The sub-block on which the page resides is decoded and selected. The address provided by the user device is used to open and close the selector device and access memory cells. In typical operation, only one sub-block is selected, making the SGD (SGD) of that sub-block active.

[0167] Based on the address provided by the user device, the memory controller 9130 can select any or all sub-blocks. The memory controller 9130 can generate sub-block addresses for the sub-block driver 9109 and select any or all sub-blocks. The memory controller 9130 can send WL information to the row decoder 9112 and the column address to the column decoder 9114.

[0168] Sub-block driver 9109 may include generating signals to select line 9113SL 0-0 ...SL K-J Multiple independent drivers. These select lines can be coupled to different SGD transistors and different SGS transistors in different blocks. Depending on the different voltages designed for the operation of the respective drivers during erase, program, and read operations, multiple input signals can be assigned to each individual driver. From the sub-block driver 9109, the appropriate operating signal can be transmitted via select line 9113 (SL).(sub-block#)-(SGD#或SGS#) )SL 0-0 ...SL K-J Send to memory array 9102.

[0169] Figure 92 This is a flowchart illustrating the features of an embodiment of a method 9200 for forming a memory device having drain-side select-gate transistors that couple memory cell strings to data lines. At 9210, a vertical memory cell string is formed. Subsequently, drain-side select-gate transistors are formed to couple data lines to the vertical string. At 9220, a transistor having a channel structure and a gate is formed, wherein the channel structure is separate from the gate. At 9230, a first portion of the channel structure of the transistor is formed, which is coupled to and extends vertically from the channel material of the vertical memory cell string. At 9240, segmented portions of the channel structure extending vertically from the first portion are formed, wherein the segmented portions have fins that contact and extend vertically from the first portion of the channel structure, and have non-conductive regions that contact and extend vertically from the first portion of the channel structure. At 9250, sharp corner regions are formed extending from the fins into the first portion of the channel structure. The fins and sharp corner regions may be heavily doped relative to the doping of the first portion. The fins and sharp corner regions can be formed as n+ regions, and the first part can be formed as an n- region. In 9260, data lines are formed to couple to the transistor.

[0170] Variations of method 9200, or methods similar to method 9200, may include several different embodiments, which may be combined depending on the application of such methods and / or the architecture of the memory device in which such memory devices are implemented. Such methods may include using a single photomask to form transistors such that dicing and block partitioning of the memory array for the memory device are self-aligned. Variations may include layering of sacrificial material for forming segmented portions of the channel structure and the drain. Variations may include forming transistors offset from a vertical string, wherein drain contacts are substantially centered on and extend vertically from the drain of the transistor, and forming data lines coupled to the top of the drain contacts. Variations may include forming a gate with a top-level layer having negative overlap with the interface between the first portion and the fin, or forming a gate aligned with the interface. Variations may include forming a gate with a top-level layer having positive overlap with the interface between the first portion and the fin.

[0171] Variations of method 9200 or methods similar to method 9200 may include forming a transistor with a drain contact, the dipole contact being constructed in situ together with a finned module. Forming such a drain contact may include forming a vertical region of a first conductive material extending vertically from a first portion of the channel structure, wherein the first conductive material surrounds a dielectric material region and a portion of the dielectric material region is removed to form an opening to the dielectric material region, wherein the opening is surrounded by the first conductive material. A second conductive material may be formed on the dielectric material region within the opening, wherein the second conductive material extends vertically from the dielectric material region. A portion of the second conductive material may be removed to form an opening to the second conductive material, wherein the opening is surrounded by the remaining portion of the second conductive material. Material for the drain contact may be formed within the opening to the second conductive material. The first conductive material, the dielectric material region, the second conductive material, and the material for the drain contact may be further processed to form the drain contact, fins, a corner portion, and the first portion of the channel structure. The fins and the corner portion may be more heavily doped than the first portion. The material forming the drain contact may include titanium silicide and a combination of titanium nitride and tungsten formed in an opening leading to the second conductive material, wherein the titanium silicide is between the combination of titanium nitride and tungsten and the second conductive material. In an alternative embodiment, the drain contact to the drain region of the transistor may be formed on a landing pad after the transistor is formed.

[0172] In various embodiments, the memory device may include vertical memory cell pillars, data lines, and transistors coupling the data lines to the vertical memory cell pillars. The transistor may have a channel structure and a gate, wherein the channel structure is separate from the gate. The channel structure may have a first portion and segmented portions. The first portion of the transistor's channel structure is coupled to and extends vertically from the channel material of the vertical memory cell pillar. The segmented portions of the channel structure extend vertically from the first portion, wherein the segmented portions have fins contacting the first portion and non-conductive regions. The fins extend vertically from the first portion of the channel structure, and the non-conductive regions contact the first portion of the channel structure and extend vertically from it. The first portion may have a boundary with non-conductive regions, wherein the boundary decreases from the fins to a position below the lowest level of the fins. The boundary may be a circular boundary, wherein the peak of the boundary is symmetrically located below the non-conductive regions. The segmented portions may have one or more fins and one or more non-conductive regions.

[0173] Such memory devices or variations thereof may include a variety of different embodiments, depending on the application of such memory devices and / or the architectural combinations implementing such memory devices. Such memory devices may include a channel structure having a boundary region along a boundary, wherein the boundary region along the boundary is heavily doped relative to the doping of a first portion outside the boundary region. Variations of such memory devices may include a channel structure having an emitter region extending downward from the boundary in a first portion, wherein the emitter region is heavily doped relative to the doping of a first portion outside the emitter region. Other variations may include a channel structure having a boundary region along a boundary, wherein the emitter extends downward from the boundary region, wherein the boundary region along the boundary and the emitter is heavily doped relative to the doping of both the boundary region and the first portion outside the emitter. Yet another variation of such memory devices may include a channel structure having a sharp corner region extending from a fin along the boundary into a first portion of the channel structure, wherein the sharp corner region is heavily doped relative to the doping of a first portion outside the sharp corner region. The memory device may be based on an n-type semiconductor material. In other embodiments, the memory device may be based on a p-type semiconductor material.

[0174] In various embodiments, the memory device may include vertical memory cell pillars, data lines, and transistors coupling the data lines to the vertical memory cell pillars. The transistor may have a channel structure and a gate, wherein the channel structure is separate from the gate. A first portion of the channel structure of the transistor may be coupled to a channel material of the vertical memory cell pillar and may extend vertically from the channel material. Segmented portions of the channel structure may extend vertically from the first portion. The segmented portions may have fins that contact and extend vertically from the first portion of the channel structure, and may have non-conductive regions that contact and extend vertically from the first portion of the channel structure. Sharp corner regions may extend from the fins into the first portion of the channel structure. The fins and sharp corner regions may be heavily doped relative to the doping of the first portion. For example, the fins and sharp corner regions may be n+ regions, wherein the first portion is an n- region. In other embodiments, the memory device may be based on a p-type semiconductor material. The top of the gate may positively overlap with the interface between the first portion and the fins, negatively overlap with the interface, or be aligned at the bottom layer of the fins.

[0175] Such memory devices or variations thereof may include a variety of different embodiments, depending on the application of such memory devices and / or the architectural combinations implementing such memory devices. Such memory devices may include transistors horizontally shifted relative to vertical pillars. The memory device may include drain contacts coupled to fins, wherein the drain contacts have a width equal to or less than the width of the data lines. The drain contacts may contain tungsten.

[0176] Variants of this type of memory device or similar memory device may include a top portion having a first portion with a circular boundary from a fin to a second fin, wherein the second fin is separated from the fin by a non-conductive region. The circular boundary decreases in size from the fin toward the boundary between the first portion and the non-conductive region. The circular boundary may extend below the non-conductive region from the end of a pointed region to the end of a second pointed region, wherein the second pointed region extends from the second fin into the first portion of the channel structure. Variants may include a non-conductive region as a void region.

[0177] In various embodiments, the memory system may include multiple memory devices. One or more of the memory devices may include data lines, a memory array, and a memory controller including a processing circuitry system. The memory array has vertical strings of memory cells, each vertical string being formed as a pillar coupled to a transistor, wherein the transistor couples the string to a data line in the data lines. The transistor may have a channel structure and a gate, wherein the channel structure is separate from the gate. The channel structure has a first portion and segmented portions. The first portion of the channel structure is coupled to and extends vertically from the channel material of the vertical strings. The segmented portions of the channel structure extend vertically from the first portion. The segmented portions have fins that contact the first portion of the channel structure and extend vertically therefrom, and have non-conductive regions that contact the first portion of the channel structure and extend vertically therefrom. Sharp corner regions extend from the fins into the first portion of the channel structure. The memory controller is configured to perform an operation comprising: performing an erase operation on a selected string by applying an erase voltage to the gate of a transistor that couples a selected string of the memory array to a data line associated with the selected string. The fin and sharp corner regions can be n+ regions and the first part can be n- regions.

[0178] Such memory systems or variations thereof may include a variety of different embodiments, which may depend on the application of such memory systems and / or the architectural combinations implementing such memory systems. Such memory systems may include transistors horizontally shifted relative to the string. The top of the gate may positively overlap with the interface between the first portion and the fin, may negatively overlap with the interface, or may be aligned at the bottom layer of the fin. The memory device may include drain contacts coupled to the fins, wherein the drain contacts have a width equal to or less than the width of the data lines.

[0179] A variant may include a top portion of a first section having a circular boundary extending from the end of a pointed region to the end of a second pointed region below a non-conductive region. The second pointed region extends from the second fin into the first section of the channel structure, where the second fin is separated from the fins by the non-conductive region. A variant may include a segmented portion of the channel structure having four fins, where each fin is separated from its adjacent fin by a non-conductive region. Other configurations may include more or fewer than four fins.

[0180] For example, electronic devices for mobile electronic devices (e.g., smartphones, tablets, etc.), electronic devices for automotive applications (e.g., automotive sensors, control units, driver assistance systems, passenger safety or comfort systems, etc.), and appliances or devices connected to the Internet (e.g., Internet of Things (IoT) devices, etc.) have different storage requirements, which depend on the type of electronic device, the environment in which it is used, performance expectations, etc.

[0181] Electronic devices can be broken down into several main components: a processor (e.g., a central processing unit (CPU) or other main processor); memory (e.g., one or more volatile or non-volatile RAM memory devices, such as DRAM, mobile or low-power dual data rate synchronous DRAM (DDR SDRAM), etc.); and storage devices (e.g., NVM devices, such as flash memory, ROM, SSD, multimedia card (MMC) or other memory card structures or assemblies, etc.). In some instances, electronic devices may include a user interface (e.g., a display, touch screen, keyboard, one or more buttons, etc.), a graphics processing unit (GPU), power management circuitry, a baseband processor, or one or more transceiver circuits, etc.

[0182] Figure 93 This is a block diagram of an embodiment of an instance machine having one or more memory devices, which are structured to enhance inter-band tunneling during erase operations in SGD transistors that couple data lines to strings of memory cells in a memory array of one or more memory devices. SGD transistors may be used individually. Figure 1A , 1B It can be constructed using any of the channel structures 102A, 102B, 102C, and 102D of 1C and 1D. A machine 9300 having one or more such memory devices can operate as a standalone machine or can be connected (e.g., networked) to other machines.

[0183] In a network deployment, Machine 9300 can operate as a server machine, a client machine, or both in a server-client network environment. In an example, Machine 9300 can act as a peer-to-peer (P2P) (or other distributed) network environment. Machine 9300 can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, web appliance, IoT device, automotive system, or any machine capable of executing instructions (sequentially or otherwise) that specifies actions to be performed by said machine. Furthermore, although only a single machine is described, the term "machine" should also be considered as any collection of machines that individually or jointly execute one or more sets of instructions to perform any one or more of the methods discussed herein (e.g., cloud computing, Software as a Service (SaaS), other computer cluster configurations). Example Machine 9300 can be arranged to operate with one or more memory devices having SGD transistors. As taught herein, a segmented structure extending vertically from the transistor channel region couples the memory cell strings to the associated data lines in one or more memory devices. Instance machine 9300 may include one or more memory devices, the structure of which is similar to that of... Figure 91 The structure described in the memory device 9100.

[0184] As described herein, an instance may comprise logic, components, devices, packages, or mechanisms, or be operable therefrom. A circuit system is a collection (e.g., a group) of circuits implemented in a tangible entity containing hardware (e.g., simple circuits, gates, logic, etc.). The membership of a circuit system can be flexible over time and due to the variability of the underlying hardware. A circuit system contains members that can perform specific tasks individually or in combination during operation. In an instance, the hardware of a circuit system may be invariably designed to perform specific operations (e.g., hardwired). In an instance, the hardware of a circuit system may contain variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) and computer-readable media that are physically modified (e.g., magnetically, electrically, or with movable placement of massless particles) to encode instructions for specific operations. When connecting physical components, the underlying electrical properties of the hardware may, for example, be changed from an insulator to a conductor, or vice versa. Instructions enable participating hardware (e.g., execution units or loading mechanisms) to form members of a circuit system within the hardware via variable connections to perform specific tasks during operation. Therefore, while the device is operating, it is communicatively coupled to other components of the circuit system via computer-readable media. In this example, any one of the physical components may be used in more than one member of more than one circuit system. For instance, during operation, an execution unit may be used at one point in time in a first circuit of a first circuit system and may be reused at different times by a second circuit in the first circuit system or a third circuit in the second circuit system.

[0185] Machine (e.g., computer system) 9300 may include a hardware processor 9350 (e.g., CPU, GPU, hardware processor core, or any combination thereof), main memory 9354, and static memory 9356, some or all of which may communicate with each other via an interconnect link (e.g., bus) 9358. Machine 9300 may further include a display device 9360, an alphanumeric input device 9362 (e.g., keyboard), and a user interface (UI) navigation device 9364 (e.g., mouse). In an example, the display device 9360, input device 9362, and UI navigation device 9364 may be a touchscreen display. Machine 9300 may additionally include a mass storage device (e.g., drive unit) 9351, a signal generation device 9368 (e.g., speaker), a network interface device 9353, and one or more sensors 9366, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors. Machine 9300 may include output controller 9369, which is connected, for example, serially (e.g., Universal Serial Bus (USB), in parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.)) to communicate with or control one or more peripheral devices (e.g., printer, card reader, etc.).

[0186] Machine 9300 may include machine-readable medium 9352 on which one or more sets of data structures or instructions 9355 (e.g., software) embodied or utilized by machine 9300 are stored to perform any one or more of the techniques or functions designed for machine 9300. Instructions 9355 may also reside wholly or at least partially in main memory 9354, static memory 9356, mass storage device 9351, or hardware processor 9350 during execution by machine 9300. In this example, one or any combination of hardware processor 9350, main memory 9354, static memory 9356, or mass storage device 9351 may constitute machine-readable medium 9352.

[0187] Although machine-readable media 9352 is described as a single medium, the term "machine-readable media" can include a single medium or multiple media (e.g., a centralized or distributed database, or associated cache and server) configured to store one or more instructions 9355. The term "machine-readable media" can include any medium capable of storing or encoding instructions executable by machine 9300 and causing machine 9300 to perform any one or more of the technologies designed for machine 9300, or capable of storing or encoding data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory as well as optical and magnetic media. In examples, massed machine-readable media includes machine-readable media having multiple particles with invariant (e.g., rest) masses. Therefore, massed machine-readable media is not a transient propagating signal. Specific examples of quality machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., EPROM, EEPROM) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and compact optical disc ROMs (CD-ROMs) and digital universal optical disc read-only memory (DVD-ROM) disks.

[0188] Instructions 9355 (e.g., software, programs, operating system (OS), etc.) or other data stored on mass storage device 9351 can be accessed via main memory 9354 for use by processor 9350. Main memory 9354 (e.g., DRAM) is typically faster but volatile, and therefore a different type of memory from mass storage device 9351 (e.g., SSD), suitable for long-term storage, including when in a "shutdown" state. Instructions 9355 or data being used by the user or machine 9300 are typically loaded into main memory 9354 for use by processor 9350. When main memory 9354 is full, virtual space from mass storage device 9351 can be allocated to supplement main memory 9354; however, because mass storage device 9351 is typically slower than main memory 9354, and write speeds are typically at least twice as slow as read speeds, using virtual memory can significantly degrade the user experience (compared to main memory 9354, e.g., DRAM) due to storage device latency. Furthermore, using the mass storage device 9351 for virtual memory can significantly reduce the usable lifespan of the mass storage device 9351.

[0189] Compared to virtual memory, virtual memory compression (e.g., The kernel feature “ZRAM” uses a portion of memory as a compacted block storage device to avoid paging to mass storage device 9351. Paging occurs within the compacted block until it is necessary to write such data to mass storage device 9351. Virtual memory compaction increases the available size of main memory 9354 while reducing wear on mass storage device 9351.

[0190] Storage devices optimized for mobile electronic devices or mobile storage typically include MMC solid-state storage devices (e.g., microSD cards). TM MMC devices contain numerous parallel interfaces (e.g., 8-bit parallel interfaces) with the host device and are typically detachable and separate components from the host device. In contrast, embedded MMC (eMMC)... TM The device is attached to a circuit board and treated as a component of the host device, with read speeds comparable to SSDs based on the Serial Advanced Technology Bus (SATA). However, the demands on mobile device performance are constantly increasing, such as for fully enabling virtual or augmented reality devices and utilizing ever-growing network speeds. In response to this demand, storage devices have transitioned from parallel communication interfaces to serial communication interfaces. Universal Flash Storage (UFS) devices (including the controller and firmware) communicate with the host device using a Low Voltage Differential Signaling (LVDS) serial interface with dedicated read / write paths, thereby further improving read / write speeds.

[0191] The transmission medium can be further used to transmit or receive commands 9355 on the communication network 9359 via a network interface device 9353 that utilizes any of a variety of transmission protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Example communication networks may include local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), conventional telephone (POTS) networks, and wireless data networks (e.g., referred to as…). The Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard series is known as... The network interface device 9353 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connection to the network 9359. In an example, the network interface device 9353 may include multiple antennas for wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmission medium" should be considered to include any tangible medium capable of carrying instructions to and executed by the machine 9300, and includes means for transmitting digital or analog communication signals to facilitate the communication of such instructions, which may be implemented by software.

[0192] The following are example embodiments of the apparatus and methods taught herein.

[0193] Example memory device 1 may include: a vertical memory cell pillar; a data line; a transistor coupling the data line to the vertical memory cell pillar, the transistor having a channel structure and a gate, the channel structure being separate from the gate; a first portion of the channel structure of the transistor coupled to and extending vertically from a channel material of the vertical memory cell pillar; and a segmented portion of the channel structure extending vertically from the first portion, the segmented portion having fins contacting and extending vertically therefrom the first portion of the channel structure and a non-conductive region contacting and extending vertically therefrom the first portion of the channel structure, the first portion having a boundary with the non-conductive region, wherein the boundary decreases from the fins to a position below the lowest level of the fins.

[0194] Example memory device 2 may include the features of example memory device 1 and may include the channel structure, the channel structure including a boundary region along the boundary, wherein the boundary region along the boundary is heavily doped relative to the doping of the first portion outside the boundary region.

[0195] Example memory device 3 may include the features of any of the aforementioned example memory devices and may include: a channel structure comprising an emitter region extending downward from a boundary in the first portion, wherein the emitter region is heavily doped relative to the doping of the first portion outside the emitter region.

[0196] Example memory device 4 may include features of example memory device 3 and any one of the aforementioned example memory devices 1 to 2 and may include the channel structure, the channel structure including a boundary region along the boundary, wherein the emitter extends downward from the boundary region, wherein the boundary region along the boundary is heavily doped relative to the doping of the first portion outside the boundary region.

[0197] Example memory device 5 may include features of any of the aforementioned example memory devices and may include the channel structure, the channel structure including a sharp corner region extending from the fin along the boundary into a first portion of the channel structure, the sharp corner region being heavily doped relative to the doping of the first portion outside the sharp corner region.

[0198] In instance memory device 6, any one of the memory devices in instance memory devices 1 to 5 may include a memory device incorporated into an electronic memory device, and further includes a host processor and a communication bus extending between the host processor and the memory device.

[0199] In instance memory device 7, any one of the memory devices in instance memory devices 1 to 6 may be modified to include any structure presented in another of instance memory devices 1 to 6.

[0200] In instance memory device 8, any device associated with a memory device in instance memory devices 1 to 7 may further include a machine-readable storage device configured to store instructions as a physical state, wherein the instructions can be used to perform one or more operations of the device.

[0201] In instance memory device 9, any one of the memory devices in instance memory devices 1 to 8 can be operated according to any one of the methods in the following instance methods 1 to 14.

[0202] Example memory device 10 may include vertical memory cell pillars; data lines; and transistors coupling the data lines to the vertical memory cell pillars. The transistors have a channel structure and a gate, the channel structure being separate from the gate; a first portion of the channel structure of the transistor coupled to and extending vertically from a channel material of the vertical memory cell pillar; and segmented portions of the channel structure extending vertically from the first portion, the segmented portions having fins contacting and extending vertically therefrom the first portion of the channel structure and non-conductive regions contacting and extending vertically therefrom the first portion of the channel structure; and sharp corner regions extending from the fins into the first portion of the channel structure.

[0203] Instance memory device 11 may include features of instance memory device 10 and may include the transistor horizontally shifted relative to the vertical column.

[0204] Example memory device 12 may include features of any of the aforementioned example memory devices 10 or 11 and may include the fins and the sharp corner regions that are heavily doped relative to the first portion.

[0205] Example memory device 13 may include features of any one of memory devices 10 to 12 and may include the top of the gate, which positively overlaps with the interface between the first portion and the fin, negatively overlaps with the interface, or is aligned at the bottom layer level of the fin.

[0206] Instance memory device 14 may include features of any of the aforementioned instance memory devices 10 to 14 and may include the memory device having a drain contact coupled to the fin, wherein the drain contact has a width equal to or less than the width of the data line.

[0207] Instance memory device 15 may include features of instance memory device 14 and any of the aforementioned instance memory devices 10 to 14 and may include the drain contact, which contains tungsten.

[0208] Instance memory device 16 may include features of any of the aforementioned instance memory devices 10-15 and may include a top of the first portion having a circular boundary from the fin to a second fin separated from the fin by the non-conductive region, wherein the circular boundary decreases from the fin toward the boundary position between the first portion and the non-conductive region.

[0209] The instance memory device 17 may include features of the instance memory device 16 and any of the aforementioned instance memory devices 10 to 15 and may include the circular boundary extending below the non-conductive region from the end of the cusp region to the end of a second cusp region extending from the second fin into the first portion of the channel structure.

[0210] Instance memory device 18 may include features of any of the aforementioned instance memory devices 10 to 17 and may include the non-conductive region that is a void region.

[0211] In instance memory device 19, any of the memory devices in instance memory devices 10 to 18 may include a memory device incorporated into an electronic memory device, the electronic memory device further including a host processor and a communication bus extending between the host processor and the memory device.

[0212] In instance memory device 20, any one of the memory devices in instance memory devices 10 to 19 may be modified to include any structure presented in another of instance memory devices 10 to 19.

[0213] In instance memory device 21, any device associated with a memory device in instance memory devices 10 to 20 may further include a machine-readable storage device configured to store instructions as a physical state, wherein the instructions can be used to perform one or more operations of the device.

[0214] In instance memory device 22, any one of the memory devices in instance memory devices 10 to 21 can be operated according to any one of the methods in the following instance methods 1 to 14.

[0215] Example memory system 1 may include: a plurality of memory devices, wherein one or more of the memory devices include: a data line; a memory array having vertical strings of memory cells, wherein each vertical string is arranged as a pillar coupled to a transistor, the transistor coupling the string to a data line in the data line, the transistor having: a channel structure and a gate, the channel structure being separate from the gate; a first portion of the channel structure coupled to and extending vertically from the channel material of the vertical string; and segmented portions of the channel structure extending vertically from the first portion, the segmented portions having fins contacting and extending vertically therefrom the first portion of the channel structure and non-conductive regions contacting and extending vertically therefrom the first portion of the channel structure; and sharp corner regions extending from the fins into the first portion of the channel structure. The memory system includes a memory controller, which contains processing circuitry and is configured to perform operations including: performing an erase operation on the selected string by applying an erase voltage to the gate of the transistor that couples the selected string of the memory array to the data line associated with the selected string.

[0216] Instance memory system 2 may include features of instance memory system 1 and may include transistors that are horizontally shifted relative to the string.

[0217] The instance memory system 3 may include the features of any of the aforementioned instance memory systems and may include fins, with the pointed corner region being an n+ region and the first portion being an n- region.

[0218] Instance memory system 4 may include features of any of the aforementioned instance memory systems and may include the top of the gate, which positively overlaps with the interface between the first portion and the fin, negatively overlaps with the interface, or is aligned at the bottom level of the fin.

[0219] Instance memory system 5 may include features of any of the aforementioned instance memory systems and may include the memory device, which includes a drain contact coupled to the fin, wherein the drain contact has a width equal to or less than the width of the data line.

[0220] The instance memory system 6 may include features of any of the aforementioned instance memory systems and may include the top of the first portion, which extends below the non-conductive region from the end of the cusp region to the end of the second cusp region, the second cusp region extending from the second fin into the first portion of the channel structure, the second fin being separated from the fin through the non-conductive region.

[0221] The instance memory system 7 may include features of any of the aforementioned instance memory systems and may include segmented portions of a channel structure, the segmented portions comprising four fins, each fin being separated from adjacent fins by a non-conductive region.

[0222] In instance memory system 8, any one of the memory systems in instance memory systems 1 to 7 may include a memory system incorporated into an electronic memory device, the electronic memory device further including a host processor and a communication bus extending between the host processor and the memory system.

[0223] In instance memory system 9, any one of the memory systems in instance memory systems 1 to 8 may be modified to include any structure presented in another of instance memory systems 1 to 8.

[0224] In instance memory system 10, any of the devices associated with the memory systems in instance memory systems 1 to 9 may further include a machine-readable storage device configured to store instructions as physical states, wherein the instructions can be used to perform one or more operations of the device.

[0225] In instance memory system 11, any one of the memory systems in instance memory systems 1 to 10 can be operated according to any one of the methods in the following instance methods 1 to 14.

[0226] Example method 1 for forming a memory device may include: forming a vertical memory cell string; forming a transistor to couple a data line to the vertical string, comprising: forming the transistor having a channel structure and a gate, wherein the channel structure is separate from the gate; forming a first portion of the channel structure of the transistor, which is coupled to and extends vertically from the channel material of the vertical memory cell column; forming a segmented portion of the channel structure, which extends vertically from the first portion, the segmented portion having fins that contact the first portion of the channel structure and extend vertically therefrom, and a non-conductive region that contacts the first portion of the channel structure and extends vertically therefrom; forming a sharp corner region that extends from the fins into the first portion of the channel structure; and forming the data line to couple to the transistor.

[0227] Example method 2 for forming a memory device may include the features of example method 1 for forming a memory device and may include forming a transistor that is vertically shifted from a vertical line, forming a drain contact that is generally centered on and extends vertically from the drain of the transistor, and forming the data line coupled to the top of the drain contact.

[0228] Example method 3 for forming a memory device may include features of any of the aforementioned example methods for forming a memory device, and may include forming the fins and the corner regions as n+ regions and forming the first portion as an n- region.

[0229] Example method 4 for forming a memory device may include features of any of the aforementioned example methods for forming a memory device and may include forming the gate of the top level having negative interface overlap between the first portion and the fin, or forming the gate aligned with the interface.

[0230] Example method 5 for forming a memory device may include features of any of the aforementioned example methods for forming a memory device and may include using a single photomask to form the transistors such that the dicing and block partitioning of the memory array for the memory device are self-aligned.

[0231] Example method 6 for forming a memory device may include features of any of the foregoing example methods for forming a memory device and may include layering of the sacrificial material for the segmented portion and the drain used to form the channel structure.

[0232] Example method 7 for forming a memory device may include features of any of the aforementioned example methods for forming a memory device and may include forming a transistor including forming a drain contact, the drain contact being constructed in situ together with a module containing the fins.

[0233] Example method 8 for forming a memory device may include features of example method 7 for forming a memory device and features of any one of example methods 1 to 6 for forming a memory device, and may include forming a vertical region of a first conductive material extending vertically from the first portion of the channel structure, wherein the first conductive material surrounds a dielectric material region; removing a portion of the dielectric material region to form an opening to the dielectric material region, wherein the opening is surrounded by the first conductive material; forming a second conductive material on the dielectric material region in the opening, the second conductive material extending vertically from the dielectric material region; removing a portion of the second conductive material to form an opening to the second conductive material, wherein the opening is surrounded by the remaining portion of the second conductive material; forming material for the drain contact in the opening to the second conductive material; further processing the first conductive material, the dielectric material region, the second conductive material, and the material for the drain contact to form the drain contact, the fin, the corner portion, and the first portion of the channel structure, wherein the fin and the corner portion are more heavily doped than the first portion.

[0234] Example method 9 for forming a memory device may include features of example method 8 for forming a memory device and features of any one of example methods 1 to 7 for forming a memory device, and may include the material forming the drain contact comprising titanium silicide and a combination of titanium nitride and tungsten formed in the opening leading to the second conductive material, wherein the titanium silicide is between the combination of titanium nitride and tungsten and the second conductive material.

[0235] Example method 10 for forming a memory device may include features of any of the aforementioned example methods for forming a memory device and may include, after forming the transistor, forming a drain contact on a landing pad to the drain region of the transistor.

[0236] In Example 11 of forming a memory device, any of Example 1 to 10 of forming a memory device may be performed when forming an electronic memory device, the electronic memory device further including a main processor and a communication bus extending between the main processor and the memory device.

[0237] In example method 12 for forming a memory device, any one of example methods 1 to 11 for forming a memory device may be modified to include operations described in any other method example of method example 1 to 11 for forming a memory device.

[0238] In example method 13 of forming a memory device, any of example methods 1 to 12 of forming a memory device may be implemented at least in part by using instructions stored as physical states in one or more machine-readable storage devices.

[0239] The example method 14 for forming a memory device may include features of any of the aforementioned example methods 1 to 13 for forming a memory device, and may include functions that perform any features associated with the example memory devices 1 to 22 and the memory systems 1 to 11.

[0240] The instance machine-readable storage device 1 stores instructions that, when executed by one or more processors, cause the machine to perform operations. These instructions may include instructions to perform functions associated with any feature of the instance memory devices 1 to 22 and memory systems 1 to 11, or to perform methods associated with any feature of the instance methods 1 to 14.

[0241] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that any arrangement calculated to achieve the same purpose may replace the specific embodiments shown. Various embodiments utilize arrangements and / or combinations of the embodiments described herein. The above description is intended to be illustrative rather than restrictive, and the wording or terminology used herein is for illustrative purposes. Upon studying the above description, those skilled in the art will readily understand combinations of the above embodiments and other embodiments.

Claims

1. A memory device comprising: Vertical memory cell column; Data cable; A transistor that couples the data line to the vertical memory cell pillar, the transistor having a channel structure and a gate, the channel structure being separate from the gate; A first portion of the channel structure of the transistor is coupled to the channel material of the vertical memory cell pillar and extends vertically from the channel material. and The channel structure has segmented portions that extend vertically from the first portion. The segmented portions have fins that contact the first portion of the channel structure and extend vertically therefrom, and non-conductive regions that contact the first portion of the channel structure and extend vertically therefrom. The first portion and the non-conductive regions have a boundary, wherein the boundary is a circular boundary from the fins toward the first portion below the lowest level of the fins.

2. The memory device of claim 1, wherein the channel structure includes a boundary region along the boundary, wherein the boundary region along the boundary is heavily doped relative to the doping of the first portion outside the boundary region.

3. The memory device of claim 1, wherein the channel structure includes an emitter region extending downward from the boundary in the first portion, wherein the emitter region is heavily doped relative to the doping of the first portion outside the emitter region.

4. The memory device of claim 3, wherein the channel structure includes a boundary region along the boundary, wherein the emitter extends downward from the boundary region, wherein the boundary region along the boundary is heavily doped relative to the doping of the first portion outside the boundary region.

5. The memory device of claim 1, wherein the channel structure includes a sharp corner region extending from the fin along the boundary into the first portion of the channel structure, the sharp corner region being heavily doped relative to the doping of the first portion outside the sharp corner region.

6. A memory device comprising: Vertical memory cell column; Data cable; A transistor that couples the data line to the vertical memory cell pillar, the transistor having a channel structure and a gate, the channel structure being separate from the gate; A first portion of the channel structure of the transistor is coupled to the channel material of the vertical memory cell pillar and extends vertically from the channel material. The channel structure has segmented portions that extend vertically from the first portion, the segmented portions having fins that contact the first portion of the channel structure and extend vertically therefrom, and non-conductive regions that contact the first portion of the channel structure and extend vertically therefrom. and The sharp-cornered region extends from the fin along the rounded corner into the first portion of the channel structure.

7. The memory device of claim 6, wherein the transistor is horizontally displaced relative to the vertical post.

8. The memory device of claim 6, wherein the fins and the sharp corner regions are heavily doped relative to the doping of the first portion.

9. The memory device of claim 6, wherein the top of the gate positively overlaps with the interface between the first portion and the fin, negatively overlaps with the interface, or is aligned at the bottom layer of the fin.

10. The memory device of claim 6, wherein the memory device includes a drain contact coupled to the fin, wherein the drain contact has a width equal to or less than the width of the data line.

11. The memory device of claim 10, wherein the drain contact comprises tungsten.

12. The memory device of claim 6, wherein the top of the first portion has a circular boundary from the fin to the second fin, the second fin being separated from the fin by the non-conductive region, wherein the circular boundary extends downward from the fin and from the second fin to the boundary position between the first portion and the non-conductive region.

13. The memory device of claim 12, wherein the circular boundary extends below the non-conductive region from the end of the pointed region to the end of a second pointed region, the second pointed region extending from the second fin into the first portion of the channel structure.

14. The memory device of claim 6, wherein the non-conductive region is a void region.

15. A memory system comprising: A plurality of memory devices, wherein one or more of the memory devices comprise: Data cable; A memory array having vertical strings of memory cells, wherein each vertical string is arranged as a pillar coupled to a transistor, the transistor coupling the string to a data line in the data line, the transistor having: A channel structure and a gate, wherein the channel structure is separate from the gate; The first portion of the channel structure is coupled to the vertically strung channel material and extends vertically from the channel material; and The channel structure has segmented portions that extend vertically from the first portion, the segmented portions having fins that contact the first portion of the channel structure and extend vertically therefrom, and non-conductive regions that contact the first portion of the channel structure and extend vertically therefrom. and A sharp-cornered region that extends from the fin along a rounded corner into the first portion of the channel structure; and A memory controller comprising a processing circuitry configured to perform an operation comprising: performing an erase operation on a selected string by applying an erase voltage to the gate of a transistor that couples a selected string of the memory array to a data line associated with the selected string.

16. The memory system of claim 15, wherein the transistor is horizontally shifted relative to the string.

17. The memory system of claim 15, wherein the fins and the sharp corner region are n+ regions, and the first portion is an n- region.

18. The memory system of claim 15, wherein the top of the gate positively overlaps with the interface between the first portion and the fin, negatively overlaps with the interface, or is aligned at the bottom layer of the fin.

19. The memory system of claim 15, wherein the memory device includes a drain contact coupled to the fin, wherein the drain contact has a width equal to or less than the width of the data line.

20. The memory system of claim 15, wherein the top of the first portion extends below the non-conductive region from the end of the angular region to the end of the second angular region, the second angular region extending from the second fin into the first portion of the channel structure, the second fin being separated from the fin through the non-conductive region.

21. The memory system of claim 15, wherein the segmented portion of the channel structure comprises four fins, each fin being separated from adjacent fins by a non-conductive region.

22. A method of forming a memory device, the method comprising: Form a vertical memory cell string; A transistor is formed to couple a data line to the vertical string, comprising: The transistor is formed having a channel structure and a gate, wherein the channel structure is separate from the gate; A first portion of the channel structure forming the transistor is coupled to the channel material of the vertical memory cell string and extends vertically from the channel material; The segmented portion forming the channel structure extends vertically from the first portion, the segmented portion having fins that contact the first portion of the channel structure and extend vertically therefrom, and a non-conductive region that contacts the first portion of the channel structure and extends vertically therefrom. and A sharp-cornered region is formed, which extends from the fin along the rounded corner into the first portion of the channel structure; and The data line is formed to couple to the transistor.

23. The method of claim 22, wherein the method comprises forming the transistor shifted from the vertical string, forming a drain contact substantially centered on and extending vertically therefrom the drain of the transistor, and forming the data line coupled to the top of the drain contact.

24. The method of claim 22, wherein the method comprises forming the fins and the pointed corner region as an n+ region and forming the first portion as an n- region.

25. The method of claim 24, wherein the method comprises forming a top-level gate having negative overlap with the interface between the first portion and the fin, or forming the gate aligned with the interface.

26. The method of claim 22, wherein the method comprises using a single photomask to form the transistor such that the dicing and block partitioning of the memory array for the memory device are self-aligned.

27. The method of claim 22, wherein the method comprises layering the sacrificial material used to form the segmented portion of the channel structure and the drain electrode.

28. The method of claim 22, wherein forming the transistor includes forming a drain contact, the drain contact being constructed in situ together with forming a module containing the fins.

29. The method of claim 28, wherein forming the drain contact comprises: A vertical region of a first conductive material is formed extending vertically from the first portion of the channel structure, wherein the first conductive material surrounds the dielectric material region; A portion of the dielectric material region is removed to form an opening to the dielectric material region, wherein the opening is surrounded by the first conductive material; In the opening, a second conductive material is formed on the dielectric material region, the second conductive material extending vertically from the dielectric material region; A portion of the second conductive material is removed to form an opening to the second conductive material, wherein the opening is surrounded by the remaining portion of the second conductive material; Material for the drain contact is formed in the opening leading to the second conductive material; The first conductive material, the dielectric material region, the second conductive material, and the material for the drain contact are further processed to form the drain contact, the fins, the corner portion, and the first portion of the channel structure, wherein the fins and the corner portion are more heavily doped than the first portion.

30. The method of claim 29, wherein the material forming the drain contact comprises forming titanium silicide and a combination of titanium nitride and tungsten in the opening leading to the second conductive material, wherein the titanium silicide is between the combination of titanium nitride and tungsten and the second conductive material.

31. The method of claim 22, wherein the method includes forming a drain contact on a landing pad to the drain region of the transistor after forming the transistor.

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