Semiconductor device

Abstract

A semiconductor device in which characteristics can be easily adjusted is provided. A semiconductor device according to the present invention includes a substrate having an IGBT region and a diode region, a surface electrode provided on an upper surface of the substrate, and a back surface electrode provided on a back surface of the substrate opposite the upper surface, the diode region having a first portion formed thinner than the IGBT region by being recessed from the upper surface of the substrate, and a second portion provided on one side of the first portion and thicker than the first portion.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Background Technology

[0002] Patent Document 1 discloses a semiconductor device having a semiconductor substrate that defines adjacent IGBT regions and diode regions. A trench is disposed on the IGBT surface, and the diode surface in the semiconductor substrate is recessed relative to the IGBT surface in the semiconductor substrate. The distance between the back side of the opposite side of the semiconductor substrate surface and the lower end of the trench corresponds to the distance between the back side of the semiconductor substrate and the diode surface.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2021-28922

[0004] In the case of the semiconductor device in Patent Document 1, the substrate is formed thin throughout the diode region. Therefore, characteristic tuning may become difficult. Summary of the Invention

[0005] The present invention was proposed to solve the above-mentioned problems, and its purpose is to obtain a semiconductor device whose characteristics can be easily adjusted.

[0006] The semiconductor device of the present invention comprises: a substrate having an IGBT region and a diode region; a surface electrode disposed on an upper surface of the substrate; and a back electrode disposed on a back side of the substrate opposite to the upper surface, wherein the diode region has a first portion formed by a recess in the upper surface of the substrate that is thinner than the IGBT region and a second portion disposed on one side of the first portion that is thicker than the first portion.

[0007] The effects of the invention

[0008] Regarding the semiconductor device of the present invention, the diode region has a first portion that is thinner than the IGBT region and a second portion that is thicker than the first portion. Therefore, characteristic adjustment is easy. Attached Figure Description

[0009] Figure 1 This is a cross-sectional view of the semiconductor device according to Embodiment 1.

[0010] Figure 2 This is a cross-sectional view of a semiconductor device involved in a variation of Embodiment 1.

[0011] Figure 3 This is a cross-sectional view of the semiconductor device involved in Embodiment 2.

[0012] Figure 4 This is a cross-sectional view of the semiconductor device involved in Embodiment 3.

[0013] Figure 5 This is a cross-sectional view of the semiconductor device involved in Embodiment 4.

[0014] Figure 6 This is a cross-sectional view of the semiconductor device according to Embodiment 5.

[0015] Figure 7 This is a cross-sectional view of the semiconductor device according to Embodiment 6.

[0016] Figure 8 This is a cross-sectional view of the semiconductor device according to Embodiment 7. Detailed Implementation

[0017] Referring to the accompanying drawings, the semiconductor devices according to various embodiments will be described. The same or corresponding structural elements are labeled with the same reference numerals, and repeated descriptions are sometimes omitted. In the following description, n and p denote the conductivity type of the semiconductor. The conductivity types described in each embodiment may also be opposite. Furthermore, n- indicates a lower impurity concentration than n, and n+ indicates a higher impurity concentration than n. Similarly, p- indicates a lower impurity concentration than p, and p+ indicates a higher impurity concentration than p.

[0018] Implementation Method 1

[0019] Figure 1 This is a cross-sectional view of the semiconductor device 100 according to Embodiment 1. The semiconductor device 100 has a substrate having an IGBT region 10 and a diode region 20. The semiconductor device 100 is an RC-IGBT (Reverse Conducting IGBT). The IGBT region 10 and the diode region 20 are collectively referred to as a cell region. Around the cell region, an end region (not shown) is provided for voltage withstand of the semiconductor device 100.

[0020] An active trench gate 11 and a dumb trench gate 12 are provided in the IGBT region 10. The active trench gate 11 has a gate trench electrode 11a separated by a gate trench insulating film 11b within a trench formed in the substrate. The dumb trench gate 12 has a dumb trench electrode 12a separated by a dumb trench insulating film 12b within a trench formed in the substrate. The gate trench electrode 11a is electrically connected to a gate pad (not shown). The dumb trench electrode 12a is electrically connected to a surface electrode 6 provided on the upper surface of the substrate.

[0021] Surface electrode 6 is the emitter electrode.

[0022] The substrate has an n-type drift layer 1. In the IGBT region 10, the substrate extends from the n+ type source layer 13 and p+ type contact layer 14 to the p-type collector layer 16. In the IGBT region 10, an n-type carrier accumulation layer 2 is disposed on the upper surface side of the n-type drift layer 1. Alternatively, the n-type carrier accumulation layer 2 may not be disposed. The n-type carrier accumulation layer 2 and the n-type drift layer 1 may also be collectively referred to as the drift layer.

[0023] A p-type base layer 15 is disposed on the upper surface of the n-type carrier accumulation layer 2. An n+ type source layer 13 and a p+ type contact layer 14 constitute the upper surface of the substrate. The n+ type source layer 13 is disposed in contact with the gate trench insulating film 11b. A p+ type contact layer 14 is disposed between two adjacent dumb trench gates 12. Alternatively, the p+ type contact layer 14 and the p-type base layer 15 can be collectively referred to as the p-type base layer.

[0024] An n-type buffer layer 3 is disposed on the back side of the n-type drift layer 1. Alternatively, the n-type buffer layer 3 may not be disposed. The n-type buffer layer 3 and the n-type drift layer 1 may be collectively referred to as the drift layer. A p-type collector layer 16 is disposed on the back side of the n-type buffer layer 3. The p-type collector layer 16 constitutes the back side of the substrate. The p-type collector layer 16 is disposed not only in the IGBT region 10 but also in the end region.

[0025] An interlayer insulating film 4 is disposed on the active trench gate 11. A barrier metal 5 is formed on the upper surface of the IGBT region 10, on the area where the interlayer insulating film 4 is not disposed and on the interlayer insulating film 4. The barrier metal 5 has ohmic contact with the n+ type source layer 13, the p+ type contact layer 14, and the dumb trench electrode 12a. A surface electrode 6 is disposed on the barrier metal 5. A back electrode 7 is disposed on the back side of the substrate opposite to the upper surface. The back electrode 7 is a collector electrode. The back electrode 7 has ohmic contact with the p-type collector layer 16.

[0026] The semiconductor device 100 also has an n-type drift layer 1 in the diode region 20. The n-type drift layer 1 of the diode region 20 and the n-type drift layer 1 of the IGBT region 10 are integrally formed. In the diode region 20, the substrate extends from the p+ type contact layer 24 to the n+ type cathode layer 26. A p-type anode layer 25 and a p+ type contact layer 24 are disposed on the upper surface side of the n-type drift layer 1. The p+ type contact layer 24 and the p-type anode layer 25 can also be collectively referred to as the p-type anode layer.

[0027] In diode region 20, an n+ type cathode layer 26 is disposed on the back side of the n-type buffer layer 3. The n+ type cathode layer 26 constitutes the back side of the substrate. In diode region 20, the surface electrode 6 serves as the anode electrode, and the back electrode 7 serves as the cathode electrode.

[0028] The diode region 20 has a first portion 20a that is thinner than the IGBT region 10 and is formed by a recess in the upper surface of the substrate. Furthermore, the diode region 20 has a second portion 20b that is thicker than the first portion 20a and is disposed on one side of the first portion 20a, and a third portion 20c that is thicker than the first portion 20a and is disposed on the other side of the first portion 20a. The second portion 20b is adjacent to the IGBT region 10.

[0029] The p-type anode layer 25 has a portion 25a disposed along the upper surface of the first portion 20a. In addition, the p-type anode layer 25 has portions 25b and 25c disposed along the side surface of the substrate that connects the first portion 20a with the second portion 20b and the third portion 20c.

[0030] In this embodiment, multiple planes exist in the diode region 20 where the surface electrode 6 contacts the p-type anode layer 25. The depth of the first portion 20a is arbitrary and can be selected. The depth of the first portion 20a can be changed by the mask pattern and etching conditions during mask processing. Alternatively, the depth of the first portion 20a can also be adjusted by changing the width of the mask pattern.

[0031] In this embodiment, the diode region 20 has a thin portion and a thick portion. This allows the p-type anode layer 25 to be widely distributed in the depth direction. Consequently, the concentration of each portion of the p-type anode layer 25 can be easily adjusted. The amount of holes injected from the p-type anode layer 25 can be adjusted by adjusting the depth and concentration of the p-type anode layer 25. This allows for adjustment of the forward voltage and recovery characteristics during forward operation. Therefore, in this embodiment, characteristic adjustment can be easily performed.

[0032] Furthermore, when the silicon thickness is thin across the entire diode region, damage may easily occur in the boundary region between the IGBT and diode regions or in areas of current concentration. Areas of current concentration include, for example, the center of the diode region or directly below the conductor. Additionally, chip breakage may occur. Furthermore, large steps may form between the IGBT and diode regions, making manufacturing difficult.

[0033] In contrast, in this embodiment, the thin area of ​​the substrate can be defined. This suppresses wafer warpage. Furthermore, damage or chip breakage caused by current concentration can be suppressed, improving yield. Moreover, by defining the step portion, defocusing during photomask processing can be avoided, reducing residue after etching. Therefore, the manufacture of the semiconductor device 100 becomes easier. In summary, this embodiment simplifies characteristic adjustment, improves damage resistance, and simplifies the manufacturing process.

[0034] In addition, such as Figure 1 As shown, the upper surface of part 20b and the upper surface of IGBT region 10 can also form the same plane. If there is a step in the boundary region between IGBT region 10 and diode region 20, the electric field may locally increase at the step. In this case, the withstand voltage decreases, and damage may easily occur during switching and recovery operations. Since there is no step at the boundary between IGBT region 10 and diode region 20, electric field concentration can be suppressed, and the withstand voltage under reverse bias can be improved.

[0035] exist Figure 1 In this example, an interlayer insulating film 4 is formed on the upper surface of the second part 20b. However, the second part 20b may also be in contact with the surface electrode 6. Alternatively, a p-type anode layer 25 may be formed instead of the p+ type contact layer 24. In this case, a concentration gradient may be provided in the p-type anode layer 25 adjacent to the IGBT region 10. Preferably, the concentration of the p-type anode layer 25 decreases towards the IGBT region. Furthermore, the trench at the boundary between the IGBT region 10 and the diode region 20 may not be present.

[0036] Alternatively, the p-type collector layer 16 disposed on the back side of the substrate in the IGBT region 10 can also extend into the diode region 20. That is, in the diode region 20, the back side of the portion adjacent to the IGBT region can also be a p-type collector layer 16.

[0037] When the back side of the boundary region adjacent to the IGBT region 10 is constructed with an n+ type cathode layer 26, carriers may become trapped in the boundary region during the forward operation of the diode. Therefore, damage may easily occur during recovery. Furthermore, a backlash phenomenon may occur, where electrons flow through the n+ type cathode layer 26 when the IGBT is turned on, making it difficult to inject holes from the p-type collector layer 16, thus preventing the IGBT from turning on. By extending the p-type collector layer 16 towards the diode region, interference between the IGBT and the diode carriers in this manner can be suppressed.

[0038] The extension amount U1 of the p-type collector layer 16 into the diode region 20 is, for example, the same as the wafer thickness. Typically, the current flows within an angle range of 45°. Therefore, as long as the extension amount U1 is ensured to be the same distance as the wafer thickness, current interference can be suppressed. However, the extension amount U1 can be arbitrarily set. The p-type collector layer 16 and the p-type anode layer 25 may or may not overlap when viewed from above.

[0039] The different portions 25a, 25b, and 25c of the p-type anode layer 25 can also have different concentrations. The p-type anode layer 25 can also have a concentration gradient corresponding to its depth.

[0040] Figure 2 This is a cross-sectional view of the semiconductor device 200 according to a variation of Embodiment 1. The portions 25a, 25b, and 25c of the p-type anode layer 25 may also be separate. That is, an anode may be formed on each of the plurality of planes in contact with the p-type anode layer 25 by the surface electrode 6. An anode can be formed on each plane by setting the mask pattern during mask processing or by implantation after etching.

[0041] In this embodiment, the height of the diode region 20 is two steps. However, it is not limited to this; the height of the diode region 20 may also be greater than or equal to three steps.

[0042] In diode region 20, the first portion 20a can be provided in only one location or in multiple locations. The pattern of the first portion 20a when viewed from above can be of any shape. The pattern of the first portion 20a when viewed from above can be strip-shaped, island-shaped, or circular. The shape of the first portion 20a can be appropriately changed by the mask pattern during mask processing. In addition, diode region 20 only needs to have the first portion 20a and a second portion or a third portion provided on one side of the first portion 20a. That is, the portion of diode region 20 that is thicker than the first portion 20a only needs to be provided on at least one side of the first portion 20a.

[0043] In addition, Figure 1 In the example, the first portion 20a is drilled to the same depth as the active trench gate 11. The depth of the first portion 20a is not limited to this. By drilling the first portion 20a to a depth lower than the active trench gate 11, losses can be further suppressed. In addition, by making the upper surface of the first portion 20a the same as the bottom of the active trench gate 11, the substrate is thinned, which can suppress the increase in manufacturing costs.

[0044] Regarding the semiconductor device 100, the substrate may also be formed of a wide-bandgap semiconductor. The wide-bandgap semiconductor is silicon carbide, gallium nitride-based materials, or diamond. According to this embodiment, by appropriately adjusting its characteristics, a high current can be stably flowed through the substrate formed of the wide-bandgap semiconductor.

[0045] These modifications can be appropriately applied to the semiconductor devices involved in the following embodiments. Furthermore, since the semiconductor devices involved in the following embodiments share many similarities with Embodiment 1, the description will focus on the differences between them and Embodiment 1.

[0046] Implementation Method 2

[0047] Figure 3This is a cross-sectional view of the semiconductor device 300 according to Embodiment 2. The structure of the first part 20a of the semiconductor device 300 is different from that of the semiconductor device 100. The other structures are the same as those of the semiconductor device 100. The first part 20a of the semiconductor device 300 has a p-type anode layer 25 and a Schottky contact layer 40 at its uppermost layer. n-type P (phosphorus) may also be implanted into the Schottky contact layer 40.

[0048] In section 1, 20a, the n-type drift layer 1 is thin, making current concentration easier. In section 1, 20a, by setting a portion of the p-type anode layer 25 as the Schottky contact layer 40, the amount of hole injection during forward operation can be suppressed. This reduces recovery losses. Furthermore, by changing the patterns of the p-type anode layer 25 and the Schottky contact layer 40, the trade-off between forward turn-on voltage and recovery losses can be adjusted. Additionally, the width, density, or depth of the p-type anode layer 25 can be adjusted so that the depletion layer extends from the p-type anode layer 25 and covers the Schottky contact layer 40 during reverse bias. This suppresses leakage current.

[0049] The area ratio of the p-type anode layer 25 to the Schottky contact layer 40 is arbitrary. The pattern of the p-type anode layer 25 and the Schottky contact layer 40 when viewed from above can be strip-shaped, island-shaped, honeycomb-shaped, or circular.

[0050] Implementation Method 3

[0051] Figure 4 This is a cross-sectional view of the semiconductor device 400 according to Embodiment 3. The structure of the diode region 20 of the semiconductor device 400 is different from that of the semiconductor device 100. Other structures are the same as those of the semiconductor device 100. In the semiconductor device 400, the first part 20a has a p-type anode layer 25 on its uppermost layer, and the third part 20c has a Schottky contact layer 40 on its uppermost layer.

[0052] Typically, the leakage current of the Schottky contact layer 40 is large when reverse biased. Therefore, as shown in Embodiment 2, the pattern shape may be limited in order to block the leakage current by means of a depletion layer extending from the p-type anode layer 25. In this embodiment, by setting the upper surface of the first portion 20a as the p-type anode layer 25 and the upper surface of the second portion 20b or the third portion 20c as the Schottky contact layer 40, the depletion layer can easily cover the Schottky contact layer 40 when reverse biased. Therefore, the leakage current can be reduced.

[0053] The area ratio of the p-type anode layer 25 to the Schottky contact layer 40 is arbitrary. When viewed from above, the pattern of the p-type anode layer 25 and the Schottky contact layer 40 can be strip-shaped, island-shaped, honeycomb-shaped, or circular. Furthermore, the side surface of the substrate connecting the first part 20a to the second part 20b or the third part 20c can be either the p-type anode layer 25 or the Schottky contact layer 40.

[0054] Implementation Method 4

[0055] Figure 5 This is a cross-sectional view of the semiconductor device 500 according to Embodiment 4. In the semiconductor device 500, the side surface of the substrate connecting the first portion 20a, the second portion 20b, and the third portion 20c is covered by an oxide film 42. Other structures are the same as those of the semiconductor device 400.

[0056] The thickness of the oxide film 42 is arbitrary. The oxide film 42 is formed, for example, by thermal oxidation or CVD (Chemical Vapor Deposition). Alternatively, anisotropic etching can be performed after CVD processing, leaving the oxide film 42 only on the sides of the substrate. Furthermore, the oxide film 42 can also have a composite film structure. In a composite film structure, for example, an oxide film, polysilicon, and an oxide film are stacked.

[0057] In this embodiment, the stepped portion of the substrate is covered by an oxide film 42. Therefore, no current flows through the stepped portion. As a result, the damage resistance during recovery can be improved.

[0058] exist Figure 5 In the example shown, the entire step portion is covered by oxide film 42. However, this is not a limitation; at least a portion of the side surface of the substrate connecting the first part 20a, the second part 20b, and the third part 20c may be covered by oxide film 42. For example, only the upper or lower corner of the side surface of the substrate may be covered by oxide film 42. In this case, current concentration at the corner can be suppressed, improving the resistance to damage during recovery.

[0059] Implementation Method 5

[0060] Figure 6 This is a cross-sectional view of the semiconductor device 600 according to Embodiment 5. In the semiconductor device 600, the side surface of the substrate connecting the first portion 20a and the second portion 20b is formed by an outwardly protruding curved surface. Other structures are the same as those of the semiconductor device 100. The shape of such a stepped portion can be formed, for example, by isotropic etching. Furthermore, the thickness of the mask pattern can be varied according to its position, thereby adjusting the etching depth.

[0061] In this embodiment, compared to Embodiment 1, the thickness of the p-type anode layer 25 can be made nearly uniform. In particular, thinning of the p-type anode layer 25 can be suppressed at the lower corner of the step between the first part 20a and the second part 20b and the third part 20c. Therefore, the voltage drop due to punch-through can be suppressed. In addition, the current concentration at the corner during recovery can be suppressed, and the Reverse Recovery Safe Operation Area (RRSOA) can be improved.

[0062] The curvature of the substrate's side surface is arbitrary. A greater curvature of the substrate's side surface will better suppress thinning of the p-type anode layer 25 at the corners. Sufficient effect will be achieved as long as the curvature of the substrate's side surface is greater than or equal to the curvature of the p-type anode layer 25.

[0063] Implementation Method 6

[0064] Figure 7 This is a cross-sectional view of the semiconductor device 700 according to Embodiment 6. The diode region 20 has an n+ type cathode layer 26 on the back side of the substrate. In the semiconductor device 700, the n+ type cathode layer 26 is spaced out. Furthermore, in... Figure 7 The structure of Embodiment 2 is used as the structure of the upper surface side of the substrate, but other embodiments may also be used.

[0065] Next, the method for forming such an n+ type cathode layer 26 will be described. First, a p-type collector layer 16 is formed by implantation of the entire back side of the substrate. Next, the n+ type cathode layer 26 is formed by selective implantation using a mask pattern. The implantation amount of the n+ type cathode layer 26 is set to be greater than the implantation amount of the p-type collector layer 16. Then, recrystallization is performed by laser annealing. Due to the concentration difference, the p-type collector layer 16 is canceled out in the region where it is implanted as the n+ type cathode layer 26. Thus, a pattern of p-type collector layer 16 and n+ type cathode layer 26 can be formed. The pattern when viewed from above can be strip-shaped, island-shaped, or circular.

[0066] By intermittently removing electrons from the n+ type cathode layer 26, the injection of electrons from the n+ type cathode layer 26 is suppressed. Therefore, the tail current during recovery can be reduced. Furthermore, by changing the pattern ratio of the p-type collector layer 16 to the n+ type cathode layer 26, the trade-off between the forward turn-on voltage and recovery loss can be adjusted.

[0067] Alternatively, the closer to the IGBT region 10, the more the n+ type cathode layer 26 can be spaced out. In this case, the spaced-out removal rate can be tilted towards the IGBT region 10. Alternatively, the n+ type cathode layer 26 can be spaced out significantly only at the boundary region between it and the IGBT region 10. This reduces the carrier concentration on the back side of the substrate on the IGBT region 10 side. Therefore, it can suppress the concentration of recovery current at the corners of the steps in the diode region 20. This improves the RRSOA.

[0068] Implementation Method 7

[0069] Figure 8 This is a cross-sectional view of the semiconductor device 800 according to Embodiment 7. In this embodiment, the structure of the n+ type cathode layer 26 differs from that in Embodiment 6. In the semiconductor device 800, the n+ type cathode layer 26 is disposed away from directly below the p-type anode layer 25 of the first portion 20a. Furthermore, in... Figure 8 The structure of Embodiment 3 is used as the structure of the upper surface side of the substrate, but other embodiments may also be used.

[0070] If an n+ type cathode layer 26 exists below the p-type anode layer 25 in the first portion 20a near the back side of the substrate, the conductivity modulation effect caused by holes injected from the p-type anode layer 25 and electrons injected from the n+ type cathode layer 26 becomes larger. Therefore, recovery loss may increase. In this embodiment, the n+ type cathode layer 26 is not formed directly below the backmost portion of the p-type anode layer 25. This reduces recovery loss.

[0071] Furthermore, in this embodiment, the backmost portion of the p-type anode layer 25, the n-type drift layer 1, and the p-type collector layer 16 form a pnp structure. If the voltage rises during recovery operation, the pnp transistor operates, thus suppressing surge voltage.

[0072] Furthermore, the technical features described in each embodiment can also be used in combination as appropriate.

[0073] Explanation of the label

[0074] 1. n-type drift layer, 2. n-type carrier accumulation layer, 3. n-type buffer layer, 4. interlayer insulating film, 5. barrier metal, 6. surface electrode, 7. back electrode, 10. IGBT region, 11. active trench gate, 11a. gate trench electrode, 11b. gate trench insulating film, 12. dumb trench gate, 12a. dumb trench electrode, 12b. dumb trench insulating film, 13. n+ type source layer, 14. p+ type contact layer, 15. p-type base layer, 16. p-type collector layer, 20. diode region, 20a. part 1, 20b. part 2, 20c. part 3, 24. p+ type contact layer, 25. p-type anode layer, 25a. part 25b, 26. n+ type cathode layer, 40. Schottky contact layer, 42. oxide film, 100, 200, 300, 400, 500, 600, 700, 800 semiconductor devices.

Claims

1. A semiconductor device, characterized in that, have: A substrate having an IGBT region and a diode region adjacent to the IGBT region in a direction along the upper surface of the substrate; A surface electrode is disposed on the upper surface of the substrate; as well as A back electrode is disposed on the back side of the substrate, opposite to the upper surface. The diode region has a first portion that is thinner than the IGBT region and is formed by a recess in the upper surface of the substrate, a second portion that is thicker than the first portion and is disposed on one side of the first portion, and a third portion that is thicker than the first portion and is disposed on the other side of the first portion.

2. The semiconductor device according to claim 1, characterized in that, The anode layer of the diode region is disposed along the upper surface of the first part and the side surface of the substrate that connects the first part and the second part.

3. A semiconductor device, characterized in that, have: A substrate having an IGBT region and a diode region; A surface electrode is disposed on the upper surface of the substrate; as well as A back electrode is disposed on the back side of the substrate, opposite to the upper surface. The diode region has a first portion formed by a recess in the upper surface of the substrate, which is thinner than the IGBT region, and a second portion disposed on one side of the first portion, which is thicker than the first portion. The anode layer of the diode region is disposed along the upper surface of the first portion and the side surface of the substrate that connects the first portion and the second portion. The portion of the anode layer disposed along the upper surface of the first part is separate from the portion disposed along the side surface of the substrate that connects the first part and the second part.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The second part is adjacent to the IGBT region. The upper surface of the second part forms the same plane as the upper surface of the IGBT region.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that, The IGBT region has a collector layer on the back side of the substrate. The collector layer extends into the diode region.

6. A semiconductor device, characterized in that, have: A substrate having an IGBT region and a diode region; A surface electrode is disposed on the upper surface of the substrate; as well as A back electrode is disposed on the back side of the substrate, opposite to the upper surface. The diode region has a first portion formed by a recess in the upper surface of the substrate, which is thinner than the IGBT region, and a second portion disposed on one side of the first portion, which is thicker than the first portion. The first part has an anode layer and a Schottky contact layer on its uppermost layer.

7. A semiconductor device, characterized in that, have: A substrate having an IGBT region and a diode region; A surface electrode is disposed on the upper surface of the substrate; as well as A back electrode is disposed on the back side of the substrate, opposite to the upper surface. The diode region has a first portion formed by a recess in the upper surface of the substrate, which is thinner than the IGBT region, and a second portion disposed on one side of the first portion, which is thicker than the first portion. The first part has an anode layer on its uppermost layer. The second part has a Schottky contact layer on its uppermost layer.

8. The semiconductor device according to any one of claims 1 to 3, 6, and 7, characterized in that, At least a portion of the side surface of the substrate that connects the first part and the second part is covered by an oxide film.

9. A semiconductor device, characterized in that, have: A substrate having an IGBT region and a diode region; A surface electrode is disposed on the upper surface of the substrate; as well as A back electrode is disposed on the back side of the substrate, opposite to the upper surface. The diode region has a first portion formed by a recess in the upper surface of the substrate, which is thinner than the IGBT region, and a second portion disposed on one side of the first portion, which is thicker than the first portion. The side surface of the substrate that connects the first part and the second part is formed by an outwardly convex curved surface.

10. The semiconductor device according to any one of claims 1 to 3, 6, 7, and 9, characterized in that, The diode region has a cathode layer on the back side of the substrate. The cathode layer is removed intermittently.

11. The semiconductor device according to claim 10, characterized in that, The closer to the IGBT region, the more the cathode layer is removed at intervals.

12. A semiconductor device, characterized in that, have: A substrate having an IGBT region and a diode region; A surface electrode is disposed on the upper surface of the substrate; as well as A back electrode is disposed on the back side of the substrate, opposite to the upper surface. The diode region has a first portion formed by a recess in the upper surface of the substrate, which is thinner than the IGBT region, and a second portion disposed on one side of the first portion, which is thicker than the first portion. The diode region has a cathode layer on the back side of the substrate. The cathode layer is disposed away from directly below the anode layer of the first part.

13. The semiconductor device according to any one of claims 1 to 3, 6, 7, 9, and 12, characterized in that, The substrate is formed of a wide-bandgap semiconductor.

14. The semiconductor device according to claim 13, characterized in that, The wide-bandgap semiconductor is silicon carbide, gallium nitride, or diamond.

Images