Power failure protection circuit and power supply circuit

Abstract

This invention discloses a power-down protection circuit and a power supply circuit. The power-down protection circuit includes a delay circuit, a switching circuit, and a threshold circuit. The delay circuit includes a first input terminal, a second input terminal, and an output terminal; the first input terminal of the delay circuit is connected to a power signal, and the second input terminal is grounded; the delay circuit is used to attenuate the power-down bounce pulse in the power signal. The switching circuit includes a control terminal, an input terminal, and an output terminal; the input terminal of the switching circuit is electrically connected to the output terminal of the delay circuit, and the output terminal outputs an enable signal; the switching circuit is used to intercept the power-down bounce pulse when turned off. The threshold circuit includes an input terminal and an output terminal; the input terminal of the threshold circuit is grounded, and the output terminal is electrically connected to the control terminal of the switching circuit; the threshold circuit is used to set a threshold voltage, and the threshold voltage and the output signal of the delay circuit jointly control the conduction or turn-off of the switching circuit. This invention can effectively intercept power-down bounce pulses and improve the reliability of the power-down protection circuit.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuit technology, and in particular to a power-down protection circuit and a power supply circuit. Background Technology

[0002] Currently, power boards supplying power to TV boards may experience power-off bounce. This is especially true when a single TV board is paired with different power boards, as compatibility issues and power board quality problems can easily lead to power-off bounce. When power-off bounce occurs, it may happen during the bounce pulse period, where power is briefly restored to the TV board before it loses power again. This could cause the memory (such as FLASH memory) in the TV board to lose power before all data is written, leading to memory malfunction and consequently, TV board malfunction.

[0003] Existing power-down protection circuits typically employ hardware protection via resistor voltage division or software protection via a control system. However, using resistor voltage division makes it difficult to determine the magnitude of the shutdown voltage, especially when the peak value of the power-down bounce pulse is close to the normal power signal value, thus failing to guarantee reliable interception of the bounce pulse. Conversely, when using a control system for protection, the slow response speed of the protection circuit also fails to guarantee effective interception of the bounce pulse. Therefore, existing power-down protection circuits are ineffective at intercepting power-down bounce pulses and have low reliability. Summary of the Invention

[0004] This invention provides a power-down protection circuit and a power supply circuit to effectively intercept power-down bounce pulses and improve the reliability of the power-down protection circuit.

[0005] In a first aspect, embodiments of the present invention provide a power-off protection circuit, comprising:

[0006] A delay circuit includes a first input terminal, a second input terminal, and an output terminal; the first input terminal of the delay circuit is connected to a power signal, and the second input terminal of the delay circuit is grounded; the delay circuit is used to attenuate the power-down bounce pulse in the power signal.

[0007] A switching circuit includes a control terminal, an input terminal, and an output terminal; the input terminal of the switching circuit is electrically connected to the output terminal of the delay circuit, and the output terminal of the switching circuit outputs an enable signal; the switching circuit is used to intercept power-off bounce pulses when turned off.

[0008] A threshold circuit includes an input terminal and an output terminal; the input terminal of the threshold circuit is grounded, and the output terminal of the threshold circuit is electrically connected to the control terminal of the switching circuit; the threshold circuit is used to set a threshold voltage, and the threshold voltage and the output signal of the delay circuit jointly control the switching circuit to turn on or off.

[0009] Optionally, the delay circuit includes: a first resistor, a second resistor, and a capacitor;

[0010] The first end of the first resistor is connected to the power signal; the second end of the first resistor is electrically connected to the first end of the second resistor and serves as the output of the delay circuit; the first end of the capacitor is electrically connected to the second end of the second resistor, and the second end of the capacitor is grounded.

[0011] Optionally, the power-off protection circuit further includes: a first discharge circuit, including a control terminal, an input terminal, and an output terminal; the control terminal of the first discharge circuit is electrically connected to the output terminal of the switching circuit, the input terminal of the first discharge circuit is electrically connected to the first terminal of the capacitor, and the output terminal of the first discharge circuit is grounded.

[0012] Optionally, the first discharge circuit includes: a first transistor; the control electrode of the first transistor serves as the control terminal of the first discharge circuit, the first electrode of the first transistor serves as the input terminal of the first discharge circuit, and the second electrode of the first transistor serves as the output terminal of the first discharge circuit.

[0013] Optionally, the power-off protection circuit further includes: a second discharge circuit, including an input terminal and an output terminal; the input terminal of the second discharge circuit is electrically connected to the first terminal of the capacitor, and the output terminal of the second discharge circuit is electrically connected to the first terminal of the first resistor.

[0014] Optionally, the second discharge circuit includes a diode; the first terminal of the diode serves as the input terminal of the second discharge circuit, and the second terminal of the diode serves as the output terminal of the second discharge circuit.

[0015] Optionally, the threshold circuit includes: a third resistor and a Zener diode; the first terminal of the Zener diode serves as the input terminal of the threshold circuit, and the second terminal of the Zener diode is electrically connected to the second terminal of the third resistor; the first terminal of the third resistor serves as the output terminal of the threshold circuit.

[0016] Optionally, the switching circuit includes: a second transistor; the control electrode of the second transistor serves as the control terminal of the switching circuit, the second electrode of the second transistor serves as the input terminal of the switching circuit, and the first electrode of the second transistor serves as the output terminal of the switching circuit.

[0017] Optionally, the second transistor is a PNP transistor or a P-type MOS transistor.

[0018] Secondly, embodiments of the present invention also provide a power supply circuit, including: a power conversion chip and a power failure protection circuit as provided in any embodiment of the present invention;

[0019] The power conversion chip has its input terminal connected to the power signal, and its enable terminal is electrically connected to the output terminal of the switching circuit.

[0020] The power-down protection circuit provided by this invention includes a delay circuit, a switching circuit, and a threshold circuit. The threshold voltage set by the threshold circuit, in conjunction with the output signal of the delay circuit, controls the switching state of the switching circuit. The delay circuit can react quickly when a power-down bounce pulse appears in the power signal, performing delay filtering on the bounce pulse. This allows the threshold circuit to set the threshold voltage only based on the weakened peak value of the bounce pulse. Compared to existing technologies, this embodiment provides more margin for setting the threshold voltage. It allows the threshold voltage to be set relatively far from the normal power signal value without affecting the switching circuit's ability to intercept bounce pulses. This allows for ripple in the power signal during normal operation, preventing abnormal shutdown of the switching circuit due to the threshold voltage being too close to the normal power signal value, thus ensuring the stability of the circuit board. Therefore, compared to existing technologies, this embodiment can effectively intercept bounce pulses and improve the reliability of the power-down protection circuit. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a power-off protection circuit provided in an embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of another power-off protection circuit provided in an embodiment of the present invention;

[0023] Figure 3 This is a schematic diagram of another power-off protection circuit provided in an embodiment of the present invention;

[0024] Figure 4 This is a waveform diagram of a power signal provided in an embodiment of the present invention;

[0025] Figure 5 This is a waveform diagram of another power signal provided in an embodiment of the present invention;

[0026] Figure 6 This is a schematic diagram of a power supply circuit provided in an embodiment of the present invention. Detailed Implementation

[0027] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0028] As described in the background section, existing power-down protection circuits are ineffective at intercepting power-down bounce pulses. The problems with existing technologies are explained in detail below. In existing technologies, a power conversion chip is typically required to convert the power signal into the supply voltage needed by the TV board; common power-down protection circuits include:

[0029] 1. A voltage divider resistor is installed between the power signal terminal and the enable terminal of the power conversion chip. By adjusting the value of the voltage divider resistor, the enable signal input to the enable terminal of the power conversion chip is controlled, thereby controlling whether the power conversion chip works or stops working. Specifically, when the power signal decreases, the enable signal obtained after voltage division will also decrease accordingly. When the enable signal decreases below the critical value of the enable voltage for the power conversion chip to operate normally, the power conversion chip stops outputting.

[0030] The advantages of this type of power-down protection circuit are its simple structure and low cost; the disadvantage is that it is difficult to set the shutdown voltage. The shutdown voltage can be understood as the voltage at which the power signal drops to the point where the power conversion chip stops working.

[0031] 2. Based on the first approach, a Zener diode is added between the power signal terminal and the enable terminal of the power conversion chip to facilitate setting the shutdown voltage. However, when the power signal drops to the shutdown voltage, the enable signal obtained after voltage division by the resistor will be less than or equal to the critical value of the enable voltage, causing the power conversion chip to stop working. Therefore, if the shutdown voltage is set close to the normal value of the power signal, the power conversion chip may be falsely shut down during operation due to power signal ripple and other factors. Thus, this method is not suitable for situations where the peak value of the power-down bounce pulse is close to the normal value of the power signal.

[0032] 3. A monitoring module is installed at the power supply end to monitor the power signal status and transmit the monitoring signal to the control system. The control system then protects the TV board based on the monitoring signal. For example, a voltage divider resistor can be used to construct the monitoring module, and the control system can be an embedded multimedia card (EMMC) system. When the monitoring signal indicates that the power signal drops to a certain voltage, the EMMC system performs data protection. However, this method requires software system cooperation, and the overall response of the protection circuit is relatively slow, making it difficult to handle sudden load changes.

[0033] In summary, schemes 1 and 2 are hardware-based protection, while scheme 3 is software-based protection. All of these schemes suffer from the problem of difficulty in effectively intercepting power-off bounce pulses, resulting in low reliability.

[0034] Based on the above research, this invention provides a power-off protection circuit to solve the power-off bounce problem, especially the power-off bounce caused by slow power supply response speed after load change. Figure 1This is a schematic diagram of a power-off protection circuit provided in an embodiment of the present invention. See also... Figure 1 The power-off protection circuit includes: a delay circuit 10, a switching circuit 20, and a threshold circuit 30.

[0035] The delay circuit 10 includes a first input terminal 11, a second input terminal 12, and an output terminal 13. The first input terminal 11 of the delay circuit 10 is connected to the power supply signal VCC, and the second input terminal 12 is grounded. The delay circuit 10 is used to attenuate the power-down bounce pulse in the power supply signal VCC. The switching circuit 20 includes a control terminal 21, an input terminal 22, and an output terminal 23. The input terminal 22 of the switching circuit 20 is electrically connected to the output terminal 13 of the delay circuit 10, and the output terminal 23 outputs an enable signal DCDC_EN. The switching circuit 20 is used to intercept the power-down bounce pulse when turned off. The threshold circuit 30 includes an input terminal 31 and an output terminal 32. The input terminal 31 of the threshold circuit 30 is grounded, and the output terminal 32 is electrically connected to the control terminal 21 of the switching circuit 20. The threshold circuit 30 is used to set a threshold voltage, which, together with the output signal of the delay circuit 10, controls the switching circuit 20 to turn on or off.

[0036] For example, the operation of this power failure protection circuit includes:

[0037] Under normal circumstances, the power signal VCC is output to the input terminal 22 of the switching circuit 20 after passing through the delay circuit 10. The threshold circuit 30 outputs the threshold voltage to the control terminal of the switching circuit 20. Since the difference between the output signal of the delay circuit 10 and the threshold voltage is greater than the conduction threshold voltage of the switching circuit 20, the switching circuit 20 is turned on. At this time, the enable signal DCDC_EN output by the switching circuit 20 is greater than the critical value of the enable voltage of the subsequent power conversion chip. Therefore, the enable signal DCDC_EN controls the power conversion chip to work normally and output the supply voltage.

[0038] When the power signal VCC decreases, i.e., when a power failure occurs, the output signal of the delay circuit 10 decreases. Since the threshold voltage remains unchanged, the difference between the output signal of the delay circuit 10 and the threshold voltage gradually decreases until the difference is less than the conduction threshold voltage of the switching circuit 20, at which point the switching circuit 20 is turned off. At this time, the switching circuit 20 has no signal output, or in other words, the enable signal DCDC_EN is "0", which does not meet the enable condition of the power conversion chip, and the power conversion chip stops working and no longer outputs.

[0039] When the power signal VCC experiences a power-down bounce, the delay circuit 10 immediately filters and delays the power-down bounce pulse to weaken it. This weakens the pulse so that the difference between the peak value and the threshold voltage of the weakened power-down bounce pulse is less than the conduction threshold voltage of the switching circuit 20. As a result, the switching circuit 20 remains off during the power-down bounce, intercepting the power-down bounce pulse and preventing the power conversion chip from being started erroneously.

[0040] The power-down protection circuit provided by this invention includes a delay circuit 10, a switching circuit 20, and a threshold circuit 30. The threshold voltage set by the threshold circuit 30, in conjunction with the output signal of the delay circuit 10, controls the switching state of the switching circuit 20. The delay circuit 10 can react quickly when a power-down bounce pulse appears in the power signal, performing delay filtering on the bounce pulse. This ensures the response speed of the power-down protection circuit while allowing the threshold circuit 30 to set the threshold voltage only based on the weakened peak value of the bounce pulse. Compared to existing technologies, this embodiment provides more margin for setting the threshold voltage. It allows the threshold voltage to be set relatively far from the normal value of the power signal VCC without affecting the switching circuit 20's ability to intercept bounce pulses. This allows for ripple in the power signal VCC during normal operation, preventing abnormal shutdown of the switching circuit 20 due to the threshold voltage being too close to the normal power signal VCC, thus ensuring the stability of the circuit board, especially in high-performance models. Therefore, this embodiment of the invention can effectively intercept bounce pulses and improve the reliability of the power-down protection circuit.

[0041] Figure 2 This is a schematic diagram of another power-down protection circuit provided in an embodiment of the present invention. See also... Figure 2 Based on the above embodiments, optionally, the delay circuit 10 includes: a first resistor R1, a second resistor R2, and a capacitor C1; the first end of the first resistor R1 is connected to the power supply signal VCC; the second end of the first resistor R1 is electrically connected to the first end of the second resistor R2 and serves as the output end of the delay circuit 10; the first end of the capacitor C1 is electrically connected to the second end of the second resistor R2, and the second end of the capacitor C1 is grounded.

[0042] In this embodiment, the first resistor R1, the second resistor R2, and the capacitor C1 together constitute the RC delay circuit 10, making the delay circuit 10 simple in structure, low in cost, and easy to implement. The delay time (denoted as Td) of the delay circuit 10 can be expressed as: Td = (R1 + R2)C1. The delay time Td can be set based on empirical values ​​and the width of the actual power-down bounce pulse tested; for example, the delay time Td can be set to be equal to the width of the power-down bounce pulse, or it can be adjusted according to the actual situation. In practical applications, the required resistor and capacitor values ​​can be calculated based on the delay time Td.

[0043] See also Figure 2 Based on the above embodiments, optionally, the switching circuit 20 includes: a second transistor Q2; the control terminal of the second transistor Q2 serves as the control terminal of the switching circuit 20, the second terminal serves as the input terminal of the switching circuit 20, and the first terminal serves as the output terminal of the switching circuit 20. For example... Figure 2As shown, exemplarily, the second transistor Q2 can be a PNP transistor, with its base as its control electrode, its collector as its first electrode, and its emitter as its second electrode. In this embodiment, a single transistor is used to construct the switching circuit 10, making the switching circuit 10 simple in structure and easy to implement.

[0044] See also Figure 2 Based on the above embodiments, optionally, the threshold circuit 30 includes: a third resistor R3 and a Zener diode D2; the first terminal of the Zener diode D2 serves as the input terminal of the threshold circuit 30, and the second terminal of the Zener diode D2 is electrically connected to the second terminal of the third resistor R3; the first terminal of the third resistor R3 serves as the output terminal of the threshold circuit.

[0045] In this threshold circuit 30, the threshold voltage, i.e., the conduction voltage of the second transistor Q2, can be set by selecting the Zener diode D2. By adjusting the resistance value of the third resistor R3, or by jointly adjusting the resistance values ​​of the first resistor R1 and the third resistor R3, it can be ensured that the Zener diode D2 operates in a steady state, thereby ensuring the stability of the power-down protection circuit.

[0046] Based on the above embodiments, the power-down protection circuit may optionally include a discharge circuit to discharge capacitor C1, preventing capacitor C1 from retaining charge for a long time due to the lack of a discharge circuit after being charged, thus affecting the function of the delay circuit 10 when the power is turned off. The structure of the discharge circuit will be described below, but this is not intended to limit the present invention.

[0047] See also Figure 2 In one embodiment, the power-down protection circuit may optionally include a first discharge circuit 40. The control terminal of the first discharge circuit 40 is electrically connected to the output terminal of the switching circuit 20, the input terminal of the first discharge circuit 40 is electrically connected to the first terminal of capacitor C1, and the output terminal of the first discharge circuit 40 is grounded. In this embodiment, when a power outage occurs, since the switching circuit 20 is open, the control terminal of the first discharge circuit 40 receives no signal input, and the first discharge circuit 40 is turned off, without affecting the normal operation of capacitor C1. However, when power is restored after a power outage, and the switching circuit 20 is turned on, the power signal VCC is transmitted through the delay circuit 10 and the switching circuit 20 to the control terminal of the first discharge circuit 40, causing the first discharge circuit 40 to turn on. Capacitor C1 discharges through the first discharge circuit 40 until the power supply fails again and the switching circuit 20 is turned off again, at which point capacitor C1 can be recharged.

[0048] Based on the above embodiments, optionally, the first discharge circuit 40 includes: a first transistor Q1; the control terminal of the first transistor Q1 serves as the control terminal of the first discharge circuit 40, the first terminal serves as the input terminal of the first discharge circuit 40, and the second terminal serves as the output terminal of the first discharge circuit 40. For example... Figure 2 As shown, exemplarily, the first transistor Q1 can be an NPN transistor, with its base as its control electrode, its collector as its first electrode, and its emitter as its second electrode.

[0049] See also Figure 2 In one embodiment, the power-down protection circuit may optionally further include a second discharge circuit 50. The input terminal of the second discharge circuit 50 is electrically connected to the first terminal of capacitor C1, and the output terminal of the second discharge circuit 50 is electrically connected to the first terminal of the first resistor R1. This discharge circuit is suitable for situations involving fast power-on / off and power-down bounce. When the power signal VCC is high, it charges capacitor C1; when VCC goes low, capacitor C1 can quickly discharge through the second discharge circuit 50, thus ensuring that capacitor C1 is not fully charged each time power is applied.

[0050] Based on the above embodiments, optionally, the second discharge circuit 50 includes: a diode D1; the first terminal of diode D1 serves as the input terminal of the second discharge circuit 50, and the second terminal of diode D1 serves as the output terminal of the second discharge circuit 50. This configuration ensures the unidirectionality of the second discharge circuit 50 and does not affect the normal operation of the delay circuit 10.

[0051] In one embodiment, the power-off protection circuit may optionally include a first discharge circuit 40 and a second discharge circuit 50. The two discharge circuits cooperate with each other to form the discharge circuit of capacitor C1, which can better ensure that capacitor C1 is not fully charged each time it is powered on.

[0052] In summary, as Figure 2 The power-down protection circuit shown is a purely hardware design. Through the cooperation of delay circuit 10 and threshold circuit 30, it can quickly respond to and intercept power-down bounce pulses, making up for the shortcomings of existing power-down protection circuits. Moreover, no component in the entire protection circuit is redundant, making the best use of resources and minimizing costs.

[0053] The above embodiments exemplify the case where both the first transistor Q1 and the second transistor Q2 are bipolar transistors, but are not intended to limit the invention. In other embodiments, the first transistor Q1 and / or the second transistor Q2 may be other types of transistors.

[0054] Figure 3This is a schematic diagram of another power-off protection circuit provided in an embodiment of the present invention. See also... Figure 3 In one embodiment, optionally, the first transistor Q1 is an N-type MOSFET and the second transistor Q2 is a P-type MOSFET. For example, the Zener diode D2 can be constructed using a voltage regulator chip; the A pin of the voltage regulator chip is the input terminal of the Zener diode D2, the K pin is the output terminal of the Zener diode D2, and the NC pin is left floating.

[0055] Figure 4 This is a waveform diagram of a power signal provided in an embodiment of the present invention. The following is in conjunction with... Figure 4 The working principle of the power failure protection circuit will be explained in detail. Figure 4 The horizontal axis represents time T, and the vertical axis represents the voltage value of the power supply signal VCC. See also... Figure 4 Let the normal value of the power signal VCC be denoted as U0, for example, 12V. Power failure occurs from time t0, and the voltage value of the power signal VCC at time t0 is denoted as U1. Power failure bounce occurs from time t1. The waveform between times t1 and t2 can be considered as the power failure bounce pulse, with a pulse width of t2-t1 and a peak value denoted as U21.

[0056] like Figure 4 The power-down bounce pulse shown has a peak value U21 that is close to the normal value U0 of the power supply signal VCC. From time t1, the delay circuit 10 begins to function, filtering and delaying the power-down bounce pulse; the weakened power-down bounce pulse after the delay circuit 10 is as follows: Figure 4 As shown by the dashed line, the weakened pulse peak is reduced to U22. Since the conduction requirement for the second transistor Q2 is that the output signal of the delay circuit 10 minus the threshold voltage is greater than the conduction threshold Vth of the second transistor Q2 (e.g., Vth = 0.7V), the threshold voltage output by the threshold circuit 30 should be greater than U22 - Vth. This allows the delay circuit 10 to filter the voltage peak of the power-down bounce pulse below the threshold voltage, ensuring that the switching circuit 20 remains off during t1-t2. Simultaneously, the threshold voltage output by the threshold circuit 30 should be less than U0 - Vth to ensure that the switching circuit 20 can conduct when the power supply signal VCC is normal. Furthermore, considering the ripple of the power supply signal VCC, to ensure the reliability of the power-down protection circuit, the upper limit of the threshold voltage can be set as small as possible. For example, when U0 = 12V, the threshold voltage can be set within the range of (U22, 10V).

[0057] Figure 5 This is a waveform diagram of another power signal provided in an embodiment of the present invention. See also... Figure 5 ,and Figure 4The difference is that the peak value U23 of the power-down bounce pulse in the power signal VCC is much farther from the normal value U0 of the power signal VCC. Therefore, regarding... Figure 5 In such cases, the role of the delay circuit 10 in the power-down protection circuit can be weakened, or even omitted entirely. The power-down bounce pulse can be intercepted solely by setting the threshold voltage, thereby accelerating the response speed of the power-down protection circuit. For example, when U0 = 12V, the threshold voltage can be set within the range of (U23, 10V).

[0058] This invention also provides a power supply circuit, including the power-off protection circuit provided in any embodiment of this invention, which has corresponding beneficial effects. Figure 6 This is a schematic diagram of a power supply circuit according to an embodiment of the present invention. See also... Figure 6 The power supply circuit includes a power conversion chip UD1 and a power-down protection circuit. The input terminal IN of the power conversion chip UD1 is connected to the power signal VCC, and the enable terminal EN of the power conversion chip UD1 is electrically connected to the output terminal of the switching circuit 20. For example, the power conversion chip UD1 is a synchronous buck DC-DC converter (BUCK) chip, and the power supply circuit is a BUCK power supply.

[0059] See also Figure 6 Optionally, the power conversion chip UD1 also includes its peripheral circuitry. Specifically, the peripheral circuitry includes: a first capacitor CD1, a second capacitor CD2, a third capacitor CD3, a fourth capacitor CD4, a fifth capacitor CD5, a sixth capacitor CD6, a seventh capacitor CD7, a first inductor LD1, a first voltage divider resistor RD1, and a second voltage divider resistor RD2. The first capacitor CD1, the second capacitor CD2, and the third capacitor CD3 are all connected between the power supply terminal and ground, serving as input filter capacitors. The power supply signal VCC is, for example, 12V. The fourth capacitor CD4 is connected between the bootstrap terminal BS and the output terminal SW of the power conversion chip UD1; the first inductor LD1 is connected between the output terminal SW of the power conversion chip UD1 and the switch pin STB of the power board; the output signal of the power conversion chip UD1 is, for example, 5V. The fifth capacitor CD5, the sixth capacitor CD6, and the seventh capacitor CD7 are all connected between the switch pin STB and ground, serving as output filter capacitors; wherein, the seventh capacitor CD7 can be an electrolytic capacitor. The first voltage divider resistor RD1 and the second voltage divider resistor RD2 are connected in series between the switch pin STB and ground. The connection point of the two resistors is electrically connected to the feedback terminal FB of the power conversion chip UD1. The ground terminal CND of the power conversion chip UD1 is directly grounded.

[0060] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A power-off protection circuit, characterized in that, include: A delay circuit includes a first input terminal, a second input terminal, and an output terminal; the first input terminal of the delay circuit is connected to a power signal, and the second input terminal of the delay circuit is grounded; the delay circuit is used to attenuate the power-down bounce pulse in the power signal. A switching circuit includes a control terminal, an input terminal, and an output terminal; the input terminal of the switching circuit is electrically connected to the output terminal of the delay circuit, and the output terminal of the switching circuit outputs an enable signal. The switching circuit is used to intercept power-off bounce pulses when turned off; A threshold circuit includes an input terminal and an output terminal; the input terminal of the threshold circuit is grounded, and the output terminal of the threshold circuit is electrically connected to the control terminal of the switch circuit. The threshold circuit is used to set a threshold voltage, which, together with the output signal of the delay circuit, controls the switching circuit to turn on or off.

2. The power-off protection circuit according to claim 1, characterized in that, The delay circuit includes: a first resistor, a second resistor, and a capacitor; The first end of the first resistor is connected to the power signal; the second end of the first resistor is electrically connected to the first end of the second resistor and serves as the output end of the delay circuit; the first end of the capacitor is electrically connected to the second end of the second resistor, and the second end of the capacitor is grounded.

3. The power-off protection circuit according to claim 2, characterized in that, Also includes: The first discharge circuit includes a control terminal, an input terminal, and an output terminal; the control terminal of the first discharge circuit is electrically connected to the output terminal of the switching circuit, the input terminal of the first discharge circuit is electrically connected to the first terminal of the capacitor, and the output terminal of the first discharge circuit is grounded.

4. The power-off protection circuit according to claim 3, characterized in that, The first discharge circuit includes: a first transistor; the control terminal of the first transistor serves as the control terminal of the first discharge circuit, the first terminal of the first transistor serves as the input terminal of the first discharge circuit, and the second terminal of the first transistor serves as the output terminal of the first discharge circuit.

5. The power-off protection circuit according to claim 2, characterized in that, Also includes: The second discharge circuit includes an input terminal and an output terminal; the input terminal of the second discharge circuit is electrically connected to the first terminal of the capacitor, and the output terminal of the second discharge circuit is electrically connected to the first terminal of the first resistor.

6. The power-off protection circuit according to claim 5, characterized in that, The second discharge circuit includes a diode; the first terminal of the diode serves as the input terminal of the second discharge circuit, and the second terminal of the diode serves as the output terminal of the second discharge circuit.

7. The power-off protection circuit according to claim 1, characterized in that, The threshold circuit includes a third resistor and a Zener diode; the first terminal of the Zener diode serves as the input terminal of the threshold circuit, and the second terminal of the Zener diode is electrically connected to the second terminal of the third resistor; the first terminal of the third resistor serves as the output terminal of the threshold circuit.

8. The power-off protection circuit according to claim 1, characterized in that, The switching circuit includes: a second transistor; the control electrode of the second transistor serves as the control terminal of the switching circuit, the second electrode of the second transistor serves as the input terminal of the switching circuit, and the first electrode of the second transistor serves as the output terminal of the switching circuit.

9. The power-off protection circuit according to claim 8, characterized in that, The second transistor is a PNP transistor or a P-type MOS transistor.

10. A power supply circuit, characterized in that, include: A power conversion chip and a power-down protection circuit as described in any one of claims 1-9; The power conversion chip has its input terminal connected to the power signal, and its enable terminal is electrically connected to the output terminal of the switching circuit.

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