A circuit for improving power supply transient response during secondary power-up

Abstract

A circuit for improving power supply transient response during secondary power-on, characterized in that: the circuit includes an undervoltage lockout unit, a control unit, a pull-down unit, a charge pump, and a power transistor; wherein, the undervoltage lockout unit is connected to the control unit and is used to adjust the input voltage V based on the input voltage V. in With undervoltage lockout threshold V UVLO The control voltage V′ is obtained by comparison. UVLO The control unit, connected to the pull-down unit, is used to control voltage V′. UVLO The circuit controls the on / off state of the pull-down unit. The pull-down unit is connected to the control unit, the charge pump, and the power transistor, respectively, and is used to completely discharge the gate of the power transistor when it is in the on state, and to maintain the gate voltage of the power transistor when it is in the off state. The charge pump is connected to the gate of the power transistor and is used to provide the gate voltage to the power transistor. This invention features a simple circuit structure, low power consumption, and supports a wide range of applications through flexible parameter adjustments.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically, to a circuit for improving the transient response of a power supply during a second power-on process. Background Technology

[0002] In existing technologies, a pull-down unit is typically connected between the charge pump and the gate of the power transistor in the gate drive circuit. This ensures that when the input voltage of the gate drive circuit drops rapidly, the pull-down unit can completely discharge the gate of the power transistor, preventing the power transistor from shooting through due to incomplete gate discharge when the drain is powered on again, which could cause excessive current to flow through the power transistor to the load and damage it. However, due to the presence of the pull-down circuit, when the input voltage drops rapidly but does not fall below the undervoltage lockout threshold... When this happens, the pull-down circuit will form a low-resistance discharge path, which will quickly pull down the gate voltage of the power transistor to ground potential, causing the power transistor to fail to conduct and further affecting the normal operation of the power transistor.

[0003] Therefore, in order to ensure that chips with gate drive circuits, and whose gate drive circuits include pull-down units, can achieve reasonable and normal use in application scenarios, there is an urgent need for a new improved circuit that can prevent the input voltage Vin from rapidly dropping below the undervoltage lockout threshold and ensure the normal operation of the power transistor when the input voltage Vin is above the undervoltage lockout threshold, while also preventing the power transistor gate voltage from being completely discharged. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide a circuit that improves the transient response of the power supply during secondary power-on. By adding an undervoltage lockout control unit, the on and off states of the pull-down unit are further controlled, thereby preventing the gate voltage of the power transistor from becoming too high while ensuring the normal operation of the power transistor.

[0005] The present invention adopts the following technical solution.

[0006] A circuit for improving power supply transient response during secondary power-up, comprising an undervoltage lockout unit, a control unit, a pull-down unit, a charge pump, and a power transistor; the undervoltage lockout unit, connected to the control unit, is used to adjust the input voltage based on the control unit's transient response. With undervoltage lockout threshold The control voltage is obtained by comparison. The control unit, connected to the pull-down unit, is used to control voltage... Controls the on or off state of the pull-down unit; the pull-down unit, connected to the control unit, charge pump and power transistor respectively, is used to completely discharge the gate of the power transistor when it is in the on state and maintain the gate voltage of the power transistor when it is in the off state; the charge pump, connected to the gate of the power transistor, is used to provide the gate voltage to the power transistor.

[0007] Preferably, in the undervoltage lockout unit, when the input voltage... Greater than the undervoltage lockout threshold At that time, the control unit The output is high; when the input voltage is high. Less than the undervoltage lockout threshold At that time, the control unit The output is low.

[0008] Preferably, the control unit includes a bias current generating structure, a first current mirror, a second current mirror, and a switching control transistor; wherein, the bias current generating structure is connected to the first current mirror and is used to generate a bias current and input it into the first current mirror; the first current mirror is connected to both the bias current generating structure and the second current mirror and is used to generate a first mirror current based on the bias current; the second current mirror is connected to both the first current mirror and the switching control transistor and is used to generate a second mirror current based on the first mirror current; the switching control transistor is connected to the output terminal of the undervoltage lockout unit, the second current mirror, and the pull-down unit and is used to control the output current based on the control voltage. The control selection will output the second mirror current to the pull-down unit.

[0009] Preferably, the bias current generating structure includes resistors R3 and R4, and MOSFETs Mn1 and Mn2; and one end of resistor R3 is connected to the input voltage. One end is connected to the drain of MOSFET Mn1 and the gate of MOSFET Mn2, respectively; the source of MOSFET Mn1 is grounded, and the gate is connected to one end of resistor R4 and the source of MOSFET Mn2, respectively; the other end of resistor R4 is grounded; the drain of MOSFET Mn2 is connected to the first current mirror as the output terminal of the bias current generation structure.

[0010] Preferably, the first current mirror includes mirror MOSFETs Mp1 and Mp2; wherein the source of Mp1 is connected to the input voltage. The drain and gate are connected to the gate of Mp2 and the output terminal of the bias current generating structure, respectively; the source of Mp2 is connected to the input voltage. The drain is connected to the second current mirror as the output terminal of the first current mirror.

[0011] Preferably, the second current mirror includes mirror MOS transistors Mn3 and Mn4; wherein the source of Mn3 is grounded, and the drain and gate are connected to the gate of Mn4 and the output terminal of the first current mirror, respectively; the source of Mn4 is grounded, and the drain is connected to the switching control transistor as the output terminal of the second current mirror.

[0012] Preferably, the gate of the switching control transistor Mn5 is connected to the control voltage output from the undervoltage lockout unit. And based on control voltage The switch control transistor Mn5 is turned on or off; its source is connected to the output of the second current mirror, and its drain is connected to the pull-down unit as the output of the control unit.

[0013] Preferably, when the switch control transistor Mn5 is turned on, the output current of the control unit is ;in, This is the gate-source voltage of the NMOS transistor Mn1.

[0014] Preferably, the pull-down circuit includes a first branch and a second branch; wherein the first branch is connected to the output terminal of the control unit and is used to control the generation of a control voltage based on the output current of the control unit. The second branch connects to the first branch and is based on the control voltage. It enables the transistor to be turned on or off, and when it is turned on, it completely discharges the gate of the power transistor, and when it is turned off, it maintains the gate voltage of the power transistor.

[0015] Preferably, the first branch includes an NMOS transistor Mn6, a PMOS transistor Mp3, a step-down resistor R2, a voltage-regulating resistor R1, a voltage-regulating capacitor C1, and a current source Ibias; wherein, the gate of the NMOS transistor Mn6 is connected to one end of the voltage-regulating resistor R1, one end of the voltage-regulating capacitor C1, and the gate of the NMOS transistor Mn7 in the second branch; the other end of the voltage-regulating resistor R1 is connected to the input voltage. The connection is as follows: the other end of the voltage regulator capacitor C1 is grounded; the drain of NMOS transistor Mn6 is connected to the output of the charge pump and the gate of the power transistor, respectively, and the source is connected to one end of the buck resistor R2; the other end of the buck resistor R2 is connected to the output of the control unit and the source of PMOS transistor Mp3; the gate of PMOS transistor Mp3 is connected to the input voltage... The drain is connected to one end of the current source Ibias and the gate of the NMOS transistor Mn8 in the second branch, respectively, and the other end of the current source Ibias is grounded.

[0016] Preferably, when the control unit generates an output current, the voltage drop generated by the step-down resistor R2 in the first branch is: ;in, This is the gate-source voltage of the NMOS transistor Mn1.

[0017] Preferably, when the control unit generates an output current, the first branch is in the off state and the control voltage is 0V; when the control unit does not generate an output current, the first branch is in the on state and the control voltage controls the conduction of the second branch.

[0018] Preferably, the resistance values ​​of resistors R2 and R4 are adjusted so that the equation... Established; among them, Input voltage Pressure drop; This is the gate-source voltage of the NMOS transistor Mn1; and These are the turn-on threshold voltages for MOSFETs Mn6 and Mp3, respectively.

[0019] Preferably, the second branch includes NMOS transistors Mn7 and Mn8; wherein, the gate of NMOS transistor Mn7 is connected to the gate of NMOS transistor Mn6 in the first branch, one end of the voltage regulator resistor R1 and one end of the voltage regulator capacitor C1 respectively; the drain of NMOS transistor Mn7 is connected to the output terminal of the charge pump, the gate of the power transistor MnPWR, and the source is connected to the drain of NMOS transistor Mn8 respectively; the gate of NMOS transistor Mn8 is connected to the gate of PMOS transistor Mp3 in the first branch and one end of the current source Ibias respectively, and the source is grounded.

[0020] Preferably, when the control voltage is 0V, the second branch is in the off state, maintaining the gate voltage of the power transistor; when the control voltage controls the second branch to be turned on, the second branch performs a complete discharge on the gate of the power transistor.

[0021] Preferably, the gate of the power transistor MnPWR is connected to the charge pump and the pull-down unit, the drain is connected to the input voltage, and the source is used as the output voltage terminal of the power transistor.

[0022] Preferably, when the pull-down unit maintains the gate voltage of the power transistor, the power transistor remains on, and the output voltage of the power transistor... With the input voltage of the power transistor Equal; when the pull-down unit performs a complete discharge on the gate of the power transistor, the power transistor switches to the cut-off state after being completely discharged.

[0023] The beneficial effects of this invention are that, compared with the prior art, the circuit for improving the transient response of the power supply during secondary power-on can further control the conduction and cutoff states of the pull-down unit by adding an undervoltage lockout control unit, thus preventing the power transistor gate voltage from becoming too high while ensuring the normal operation of the power transistor. This invention has a simple circuit structure, low power consumption, and supports a wide range of applications through flexible parameter adjustments. Attached Figure Description

[0024] Figure 1This is a schematic diagram of a gate driving circuit in the prior art of the present invention;

[0025] Figure 2 This is a schematic diagram of the voltage curve of the output voltage changing with the input voltage and the gate voltage in a gate driving circuit according to the prior art of this invention;

[0026] Figure 3 This is a schematic diagram of the circuit structure for improving the transient response of the power supply during secondary power-on according to the present invention;

[0027] Figure 4 This is a schematic diagram of the voltage curve showing the output voltage changing with the input voltage and gate voltage in a circuit for improving the transient response of the power supply during secondary power-up according to the present invention. Detailed Implementation

[0028] The present application will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and should not be construed as limiting the scope of protection of the present application.

[0029] Figure 1 This is a schematic diagram of a gate driving circuit in the prior art of this invention. (See diagram below.) Figure 1 As shown, a gate drive circuit in the prior art includes a charge pump, a power transistor MnPWR, and a pull-down circuit for providing a complete discharge function for the power transistor.

[0030] Specifically, the output terminals of the charge pump and pull-down circuit are both connected to the gate of the power transistor MnPWR. The drain of MnPWR is the input voltage terminal, and the source is the output voltage terminal.

[0031] Understandably, the pull-down circuit includes NMOS transistors Mn6, Mn7, and Mn8, a PMOS transistor Mp3, a current source Ibias, resistor R1, and capacitor C1. To achieve the pull-down effect, Mn6, Mp3, and the current source are connected sequentially to form a branch. The drain of Mn1 is connected to the charge pump and power transistor respectively, the gate of Mn6 is connected to R1 and C1 respectively, and the source of Mn1 is connected to the source of Mp3. Understandably, the other end of resistor R1 is connected to the input voltage. The other end of capacitor C1 is grounded, therefore it can be known that when the input voltage... Under relatively stable conditions, the gate voltage of Mn1 stabilizes at the input voltage. However, when the input voltage When drastic changes occur, the gate voltage of Mn1 will remain relatively stable for a short period of time due to the blocking effect of resistor R1 and the charging and discharging effect of capacitor C1, that is, forming a state with input voltage. Delayed stable voltage .

[0032] Additionally, in this branch, the gate of Mp3 is also connected to the input voltage. The circuit is connected such that its drain is grounded via a current source Ibias. Based on this circuit connection, it can be seen that in this branch, when the input voltage is stable at a high level, the MOSFET Mp3... The voltage is cut off due to the action of the control voltage, which is the voltage at point C. The voltage is 0V, thus preventing the NMOS transistor Mn8 on the other branch from conducting. In this state, since both branches in the pull-down branch are off, all voltage output from the charge pump can be effectively received by the gate of the power transistor, thereby achieving effective conduction of the power transistor and enabling the power transistor to conduct based on the input voltage. Generate output voltage Its basic functions.

[0033] On the other hand, because the input voltage of the subsequent circuit is when performing its normal function... It's impossible for it to remain in a constant state forever. When the input voltage of the subsequent circuit... When a sudden change occurs, for example, in one embodiment of the invention, when the input voltage... When the power supply voltage drops from 5V to 2V, although the input voltage The voltage has been reduced, but according to the design purpose of the existing circuit, it is still desirable for the power transistor to be in the on state and to operate according to the lower input voltage. Output a lower output voltage to the subsequent stage circuit. In other words, if the input voltage of the power transistor is reduced at this time... If the gate drive circuit is cut off, then the unexpected problem will occur, and it will be unable to provide normal response and feedback to the subsequent circuits.

[0034] However, with the addition of pull-down circuits in existing technologies, when the input voltage... When the voltage value drops rapidly, the aforementioned problem is likely to occur. For example, in one embodiment of the present invention, when the input voltage... When the power supply voltage drops rapidly from 5V to 2V, the gate voltage of NMOS transistor Mn6 will remain at 5V for a short period, while the gate voltage of PMOS transistor Mp3 will decrease with the input voltage. The voltage decreases and the circuit is turned on. In this case, MOSFETs Mn6 and Mp3 in this branch are both turned on, which makes the entire branch turn on, and the voltage across the current source decreases. It was also boosted. This boost was sufficient to turn on the NMOS transistor Mn8 in the other branch.

[0035] As a result of this situation, NMOS transistors Mn7 and Mn8 in the other branch are also turned on. In this branch, due to the absence of current sources and other components, a low-resistance discharge path is created, pulling the gate voltage of power transistor MnPWR down to ground potential, thus causing the power transistor to turn off and the output voltage to 0V. Therefore, when this situation occurs, the power transistor in this invention unexpectedly turns off during the input voltage reduction process, resulting in a loss of power supply to the downstream circuitry.

[0036] Figure 2 This is a schematic diagram illustrating the voltage curve of the output voltage as a function of the input voltage and the gate voltage in a gate driving circuit according to the prior art of this invention. Figure 2 As shown, in conjunction with the above, when the input voltage of the power transistor... When held at a high level, its gate voltage will also remain high, thus turning on the power transistor and causing its output voltage to... With input voltage They are of equal magnitude. However, when the input voltage of the power transistor... During the rapid voltage drop, although it doesn't reach 0V, the gate voltage of the power transistor drops rapidly to 0V under the action of the pull-down circuit, causing the power transistor to turn off. At this time, the output voltage... Its output voltage will also change as the power transistor is turned off. The voltage is initially 0V. Subsequently, in the pull-down circuit, capacitor C1 discharges completely, and the gate voltage of NMOS transistor Mn6 gradually stabilizes. This causes the pull-down circuit current to decrease until it is cut off again, and the gate voltage gradually rises, driving the output voltage. It starts at 0V and gradually increases, eventually stabilizing at the input voltage. The reduced state.

[0037] It can be seen that during this process, the output voltage It did not completely follow the input voltage It changes with the input voltage, not with the change in voltage. During the rapid voltage drop, it briefly decreases to 0V before returning to the input voltage. The voltage value.

[0038] To address this problem, the present invention provides a circuit for improving the transient response of the power supply during secondary power-on.

[0039] Figure 3 This is a schematic diagram of a circuit for improving the transient response of a power supply during secondary power-on, according to the present invention. Figure 3As shown, a circuit for improving the transient response of a power supply during secondary power-on is disclosed. The circuit includes an undervoltage lockout unit, a control unit, a pull-down unit, a charge pump, and a power transistor. The undervoltage lockout unit, connected to the control unit, is used to adjust the input voltage based on the transient response of the power supply. With undervoltage lockout threshold The control voltage is obtained by comparison. The control unit, connected to the pull-down unit, is used to control voltage... The control unit controls the on or off state of the pull-down unit; the pull-down unit is connected to the control unit, the charge pump and the power transistor respectively, and is used to completely discharge the gate of the power transistor when it is in the on state, and to maintain the gate voltage of the power transistor when it is in the off state; the charge pump is connected to the gate of the power transistor and is used to provide the gate voltage to the power transistor.

[0040] It is understood that in this invention, a control unit is added to the existing pull-down circuit. The high and low levels of the control voltage from the control unit determine whether an input current needs to be generated in the pull-down unit, and the voltage drop generated by this input current controls the opening and closing of the pull-down unit. In this way, when an input voltage is detected... The voltage drops rapidly, but remains above the undervoltage lockout threshold, ensuring the power transistor remains on. This method avoids the pull-down circuit's inability to withstand low input voltage. The problem of performing a complete discharge of the power transistor gate during the rapid descent process.

[0041] In this invention, an undervoltage lockout threshold is designed. The circuit's principle is based on distinguishing input voltages. With undervoltage lockout threshold The relationship between these two conditions is as follows: When the input voltage is higher than the undervoltage lockout voltage, it can be understood that although the circuit generates a voltage drop during operation, it can still support the turn-on of the downstream circuit without needing undervoltage lockout or power transistor cutoff. Therefore, in this case, even if the input voltage drops rapidly, the control circuit can ensure the power transistor remains on. On the other hand, when the input voltage falls below the undervoltage lockout threshold during operation, the circuit should execute the undervoltage lockout logic. At this time, the control circuit can ensure that the charge pump voltage flows out through the pull-down circuit, the power transistor gate voltage drops to 0V, and the power transistor is cut off.

[0042] In this invention, the undervoltage lockout unit is mainly implemented using devices in the prior art such as comparators, and is used to control the input voltage. With undervoltage lockout threshold The two values ​​are compared, and high and low levels are output based on the different comparison results.

[0043] In addition, the control unit can control the on or off state of one branch in the pull-down unit, so that the pull-down unit can be turned on or off under reasonable conditions.

[0044] Preferably, in the undervoltage lockout unit, when the input voltage... Greater than the undervoltage lockout threshold At that time, the control unit The output is high; when the input voltage is high. Less than the undervoltage lockout threshold At that time, the control unit The output is low.

[0045] although Figure 3 The circuit diagram of the undervoltage lockout unit is not specifically shown. However, the undervoltage lockout unit in this invention can be implemented using a comparison circuit commonly used in the prior art. The undervoltage lockout unit can preset an undervoltage lockout threshold and output a high or low level based on the comparison result between the undervoltage lockout threshold and the input voltage.

[0046] It is understood that in this invention, since the power supply voltage is approximately 5V, the undervoltage lockout threshold is set to 1.8V based on the circuit's function. However, depending on the actual application of this circuit, the undervoltage lockout threshold can also be flexibly set according to specific circumstances.

[0047] For the undervoltage lockout unit, when it detects the input voltage Even when the voltage is still above 1.8V, it will still output a high level despite a rapid drop; while the input voltage... When the value is less than 1.8V, a low level will be output.

[0048] Preferably, the control unit includes a bias current generating structure, a first current mirror, a second current mirror, and a switching control transistor; wherein, the bias current generating structure is connected to the first current mirror and is used to generate a push-pull current and input it into the first current mirror; the first current mirror is connected to both the bias current generating structure and the second current mirror and is used to generate a first mirror current based on the push-pull current; the second current mirror is connected to both the first current mirror and the switching control transistor and is used to generate a second mirror current based on the first mirror current; the switching control transistor is connected to the output terminal of the undervoltage lockout unit, the second current mirror, and the pull-down unit and is used to control the output current based on the control voltage. The control selection will output the second mirror current to the pull-down unit.

[0049] In this invention, a bias current generating structure can be used to achieve a relatively stable current, while two current mirror structures are used to achieve a mirrored output of the push-pull current. Furthermore, due to the use of a switching control transistor, the mirrored input of the push-pull current from the control unit can be selectively turned on or off to the pull-down unit.

[0050] Preferably, the bias current generating structure includes push-pull resistors R3 and R4, and push-pull MOSFETs Mn1 and Mn2; furthermore, one end of the push-pull resistor R3 is connected to the input voltage. One end is connected to the drain of push-pull MOSFET Mn1 and the gate of push-pull MOSFET Mn2 respectively; the source of push-pull MOSFET Mn1 is grounded, and the gate is connected to one end of push-pull resistor R4 and the source of push-pull MOSFET Mn2 respectively; the other end of push-pull resistor R4 is grounded; the drain of push-pull MOSFET Mn2 is connected to the first current mirror as the output terminal of the bias current generation structure.

[0051] like Figure 3 As shown, in the push-pull circuit of this invention, the gates of the two NMOS transistors Mn1 and Mn2 are respectively connected to the source of the other, thereby forming a stable bias current generating structure. Additionally, a resistor is connected to the gate of each transistor. In this way, the bias current generating structure produces a stable current. Furthermore, this current can be determined based on the current flowing through the resistor R4 connected between the gate and source of NMOS transistor Mn1. It is understood that the voltage across R4 should be the gate-source voltage of NMOS transistor Mn1. And its resistance value is Therefore, the quotient of this voltage and resistance is the value of the push-pull current in this invention.

[0052] Preferably, the first current mirror includes mirror MOSFETs Mp1 and Mp2; wherein the source of Mp1 is connected to the input voltage. The drain and gate are connected to the gate of Mp2 and the output terminal of the bias current generating structure, respectively; the source of Mp2 is connected to the input voltage. The drain is connected to the second current mirror as the output terminal of the first current mirror.

[0053] To ensure consistency in the circuit structure on both sides of the push-pull current, a current mirror is used in this invention to isolate the push-pull circuit and the switching control transistor. Because of the current mirror, it can be ensured that the current in the branch containing the switching control transistor is the same as the push-pull current.

[0054] Preferably, the second current mirror includes mirror MOS transistors Mn3 and Mn4; wherein the source of Mn3 is grounded, and the drain and gate are connected to the gate of Mn4 and the output terminal of the first current mirror, respectively; the source of Mn4 is grounded, and the drain is connected to the switching control transistor as the output terminal of the second current mirror.

[0055] Since the direction of the current controlled by the switch control tube in this invention is actually from the pull-down unit to the control unit, an additional current mirror can be added to facilitate the connection between the switch control tube and the pull-down unit.

[0056] Preferably, the gate of the switching control transistor Mn5 is connected to the control voltage output from the undervoltage lockout unit. And based on control voltage The switch control transistor Mn5 is turned on or off; its source is connected to the output of the second current mirror, and its drain is connected to the pull-down unit as the output of the control unit.

[0057] In this invention, the switching control transistor is based on the control voltage generated by the undervoltage lockout unit. The state of the switch control transistor Mn5 determines whether the output current is input to the pull-down unit. Understandably, when the control voltage received by Mn5 is high, it will be turned on, thus controlling the output current. Conversely, when the control voltage received by Mn5 is low, it will be turned off, thus preventing the output current from being output. In other words, when the input voltage is greater than 1.8V, there is input current; when it is less than 1.8V, the output current is cut off.

[0058] Preferably, when the switch control transistor Mn5 is turned on, the output current of the control unit is ;in, This is the gate-source voltage of the NMOS transistor Mn1.

[0059] As mentioned above, when the input voltage is greater than 1.8V, the switching control transistor Mn5 is turned on. At this time, the output current of the control unit is equal to the push-pull current. .

[0060] Preferably, the pull-down circuit includes a first branch and a second branch; wherein, the first branch is connected to the output terminal of the control unit and is used to generate a control voltage based on the output current of the control unit; the second branch is connected to the first branch and is turned on or off based on the control voltage, and when turned on, it completely discharges the gate of the power transistor, and when turned off, it maintains the gate voltage of the power transistor.

[0061] Using the method of this invention, the first and second branches of the pull-down circuit can be turned on or off under the control of the control unit. Specifically, the first branch will be turned on or off according to the output current of the control unit, while the second branch will be turned on or off according to the voltage at the voltage divider point in the first branch.

[0062] Preferably, the first branch includes an NMOS transistor Mn6, a PMOS transistor Mp3, a step-down resistor R2, a voltage-regulating resistor R1, a voltage-regulating capacitor C1, and a current source Ibias; wherein, the gate of the NMOS transistor Mn6 is connected to one end of the voltage-regulating resistor R1, one end of the voltage-regulating capacitor C1, and the gate of the NMOS transistor Mn7 in the second branch; the other end of the voltage-regulating resistor R1 is connected to the input voltage. The connection is as follows: the other end of the voltage regulator capacitor C1 is grounded; the drain of NMOS transistor Mn6 is connected to the output of the charge pump and the gate of the power transistor, respectively, and the source is connected to one end of the buck resistor R2; the other end of the buck resistor R2 is connected to the output of the control unit and the source of PMOS transistor Mp3; the gate of PMOS transistor Mp3 is connected to the input voltage via an inverter. The drain is connected to one end of the current source Ibias and the gate of the NMOS transistor Mn8 in the second branch, respectively, and the other end of the current source Ibias is grounded.

[0063] In this invention, two NMOS transistors, a step-down resistor, and a current source are connected in series on the first branch. The gate control voltage of the two NMOS transistors can control their conduction or cutoff. Specifically, for NMOS transistor Mn6, its gate voltage is related to the input voltage. Approximately equivalent. When the input voltage is relatively stable, its gate voltage... Equal to the input voltage, while when the input voltage When the gate voltage decreases rapidly, The voltage will not change abruptly under the influence of capacitor C1. In this way, even when the input voltage... The voltage has dropped rapidly, but Mn6 can still maintain its conduction state for a period of time.

[0064] Furthermore, for Mp3, its gate voltage varies with the input voltage. It changes in real time due to changes in the input voltage. When the change in voltage exceeds the sum of the conduction thresholds of Mn6 and Mp3, then Mp3 will also conduct. Therefore, for this branch, there is also an input voltage... The situation where both NMOS transistors are turned on simultaneously during rapid reduction.

[0065] To prevent this from happening, the resistor added between the two MOSFETs in the first branch will generate a large voltage drop. The resistance value of this resistor is pre-calculated so that the voltage drop generated by the resistor is large enough to prevent the two MOSFETs from conducting simultaneously when the output current of the control unit is connected.

[0066] Preferably, when the control unit generates an output current, the voltage drop generated by the step-down resistor R2 in the first branch is: ;in, This is the gate-source voltage of the NMOS transistor Mn1.

[0067] It is understood that the presence of the voltage drop resistor R2 in this invention ensures that the two MOSFETs do not conduct simultaneously. Therefore, when the output current of the control unit is... When this happens, current will flow into the control unit through Mn6 and R2. At this time, the voltage drop across R2 is... .

[0068] Preferably, when the control unit generates an output current, the first branch is in the off state and the control voltage is 0V; when the control unit does not generate an output current, the first branch is in the on state and the control voltage controls the conduction of the second branch.

[0069] In this invention, when the input voltage is still greater than the undervoltage lockout threshold, after the control unit generates the output current, the circuit will not turn on even if the change in the input voltage is equal to the sum of the Mn6 and Mp3 turn-on thresholds.

[0070] This is because, in this circuit, during the rapid decrease of the input voltage, the gate voltage of Mn6... It remains approximately the same as the voltage value before the input voltage drops, while the gate voltage of Mp3 is at this point. In this case, we can obtain the following equation:

[0071]

[0072] Simplifying this equation, in this invention, the voltage drop generated by the circuit during operation can be designed as follows: Typically, this voltage drop is slightly less than the difference between the power supply voltage and the undervoltage lockout threshold; only in this way can the normal operation of the chip in this invention be guaranteed.

[0073] Therefore, the above equation can be simplified to obtain... In this invention, the proportional relationship between the resistance values ​​of R2 and R4 can be adjusted. After adjustment, the optimal resistance can be determined. weight ratio The size, thus making The value of is less than the sum of the turn-on threshold voltages of the two MOSFETs, that is... .

[0074] Furthermore, based on the above resistor value settings, we can obtain... This is also true. Obviously, in this situation, Mn6 and Mp3 will not conduct simultaneously. Therefore, based on the selected resistor value, during the process of the control unit supplying control current to the pull-down unit, the first branch of the pull-down circuit is always in a cut-off state. Because the first branch is cut off, the voltage across the current source is also 0V.

[0075] On the other hand, when the input voltage is very low, the control unit is turned off, and Mn5 is cut off. Since the gate voltage of Mn6 drops slowly, the first branch can be briefly turned on. In this case, a slightly higher voltage is generated across the current source Ibias, which can turn on the Mn8 transistor in the second branch, a point that will be discussed in detail later.

[0076] Preferably, the second branch includes NMOS transistors Mn7 and Mn8; wherein, the gate of NMOS transistor Mn7 is connected to the gate of NMOS transistor Mn6 in the first branch, one end of the voltage regulator resistor R1 and one end of the voltage regulator capacitor C1 respectively; the drain of NMOS transistor Mn7 is connected to the output terminal of the charge pump, the gate of the power transistor MnPWR, and the source is connected to the drain of NMOS transistor Mn8 respectively; the gate of NMOS transistor Mn8 is connected to the gate of PMOS transistor Mp3 in the first branch and one end of the current source Ibias respectively, and the source is grounded.

[0077] It is understood that the second branch in this invention is composed of MOSFETs Mn7 and Mn8. In this circuit, Mn7 can be adjusted according to voltage. The control of Mn8 is used to open it, while Mn8 needs to be controlled by the voltage difference across the current source in the first branch to confirm whether it is open.

[0078] Preferably, when the control voltage is 0V, the second branch is in the off state, maintaining the gate voltage of the power transistor; when the control voltage controls the second branch to be turned on, the second branch performs a complete discharge on the gate of the power transistor.

[0079] As mentioned above, when the input voltage fluctuates between the power supply voltage and the undervoltage lockout threshold, regardless of how rapidly it rises or falls, there will always be a state where the voltage difference across the current source is 0V. Therefore, Mn8 remains off. However, once the input voltage drops below the undervoltage lockout threshold, the voltage difference across the current source is no longer 0V. At this point, the second branch conducts, enabling a complete discharge of the power transistor's gate.

[0080] Preferably, the gate of the power transistor MnPWR is connected to the charge pump and the pull-down unit, the drain is connected to the input voltage, and the source is used as the output voltage terminal of the power transistor.

[0081] As can be seen from the connection method of the power transistor, the output voltage is not only directly related to the input voltage, but also the on or off state is determined by the gate voltage of the power transistor, thus affecting the output voltage.

[0082] Preferably, when the pull-down unit maintains the gate voltage of the power transistor, the power transistor remains on, and the output voltage of the power transistor... With the input voltage of the power transistor Equal; when the pull-down unit performs a complete discharge on the gate of the power transistor, the power transistor switches to the cut-off state after being completely discharged.

[0083] Figure 4 This is a schematic diagram showing the output voltage variation with input voltage and gate voltage in a circuit for improving power supply transient response during secondary power-up according to the present invention. Figure 4 As shown, when the input voltage consistently varies above the undervoltage lockout threshold, even if the input voltage drops from a higher supply voltage, such as 5V, to a lower operating voltage of 2V, the power transistor remains on under the control unit and pull-down unit, and the output voltage of the power transistor remains constant. It is also always related to the input voltage of the power transistor. Keep them equal.

[0084] However, Figure 4 The code does not show the state when the input voltage drops below the undervoltage lockout threshold. Understandably, in this state, when the input voltage decreases, the gate voltage of the power transistor drops directly to 0V, effectively shielding the power transistor's output under undervoltage conditions. In other words, the power transistor's output voltage also becomes 0V at this time.

[0085] The beneficial effects of this invention are that, compared with the prior art, the circuit for improving the transient response of the power supply during secondary power-on can further control the conduction and cutoff states of the pull-down unit by adding an undervoltage lockout control unit, thus preventing the power transistor gate voltage from becoming too high while ensuring the normal operation of the power transistor. This invention has a simple circuit structure, low power consumption, and supports a wide range of applications through flexible parameter adjustments.

[0086] The applicant of this invention has provided a detailed description of the embodiments of the invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are merely preferred embodiments of the invention. The detailed description is only intended to help readers better understand the spirit of the invention and is not intended to limit the scope of protection of the invention. On the contrary, any improvements or modifications made based on the inventive spirit of the invention should fall within the scope of protection of the invention.

Claims

1. A circuit for improving the transient response of a power supply during a secondary power-on process, characterized in that: The circuit includes an undervoltage lockout unit, a control unit, a pull-down unit, a charge pump, and a power transistor MnPWR; wherein, The undervoltage lockout unit is connected to the control unit and is used to lock the input voltage. With undervoltage lockout threshold The control voltage is obtained by comparison. ; The control unit is connected to the pull-down unit and is used to control the voltage. Control the on or off state of the pull-down unit; The pull-down unit is connected to the control unit, the charge pump and the power transistor MnPWR respectively, and is used to completely discharge the gate of the power transistor MnPWR when it is in the on state, and maintain the gate voltage of the power transistor MnPWR when it is in the off state. The charge pump is connected to the gate of the power transistor MnPWR and is used to provide the gate voltage for the power transistor MnPWR.

2. The circuit for improving power supply transient response during secondary power-on as described in claim 1, characterized in that: In the undervoltage lockout unit, when the input voltage Greater than the undervoltage lockout threshold At that time, the control unit The output is high level; When the input voltage Less than the undervoltage lockout threshold At that time, the control unit The output is low.

3. The circuit for improving the transient response of a power supply during a secondary power-on process as described in claim 1, characterized in that: The control unit includes a bias current generating structure, a first current mirror, a second current mirror, and a switching control transistor Mn5; wherein... The bias current generating structure is connected to the first current mirror and is used to generate a bias current and input it into the first current mirror. The first current mirror is connected to the bias current generating structure and the second current mirror, respectively, and is used to generate a first mirror current based on the bias current; The second current mirror is connected to the first current mirror and the switch control transistor Mn5, respectively, and is used to generate a second mirror current based on the first mirror current; The switching control transistor Mn5 is connected to the output terminal of the undervoltage lockout unit, the second current mirror, and the pull-down unit, respectively, and is used to control the voltage based on the control voltage. The control selects to output the second mirror current to the pull-down unit.

4. The circuit for improving power supply transient response during secondary power-on as described in claim 3, characterized in that: The bias current generating structure includes resistors R3 and R4, and MOSFETs Mn1 and Mn2; and... One end of resistor R3 is connected to the input voltage. One end is connected to the drain of MOSFET Mn1 and the other end is connected to the gate of MOSFET Mn2. The source of the MOS transistor Mn1 is grounded, and its gate is connected to one end of the resistor R4 and the source of the MOS transistor Mn2, respectively. The other end of resistor R4 is grounded; The drain of the MOS transistor Mn2 is connected to the first current mirror as the output terminal of the bias current generating structure.

5. The circuit for improving the transient response of a power supply during a secondary power-on process as described in claim 3, characterized in that: The first current mirror includes mirror MOSFETs Mp1 and Mp2; wherein, The source and input voltage of Mp1 The drain and gate are connected to the gate of Mp2 and the output terminal of the bias current generating structure, respectively. The source and input voltage of Mp2 The drain is connected to the second current mirror as the output terminal of the first current mirror.

6. The circuit for improving power supply transient response during secondary power-on as described in claim 3, characterized in that: The second current mirror includes mirrored MOSFETs Mn3 and Mn4; wherein, The source of Mn3 is grounded, and its drain and gate are connected to the gate of Mn4 and the output terminal of the first current mirror, respectively. The source of Mn4 is grounded, and its drain is connected to the switch control transistor Mn5 as the output terminal of the second current mirror.

7. The circuit for improving the transient response of a power supply during a secondary power-on process as described in claim 3, characterized in that: The gate of the switching control transistor Mn5 is connected to the control voltage output from the undervoltage lockout unit. And based on the control voltage On or off; The source of the switch control transistor Mn5 is connected to the output terminal of the second current mirror, and the drain is connected to the pull-down unit as the output terminal of the control unit.

8. The circuit for improving power supply transient response during secondary power-on as described in claim 4, characterized in that: When the switch control transistor Mn5 is turned on, the output current of the control unit is ; in, This is the gate-source voltage of the NMOS transistor Mn1.

9. The circuit for improving the transient response of a power supply during a secondary power-on process according to claim 4, characterized in that: The drop-down unit includes a first branch and a second branch; wherein... The first branch is connected to the output terminal of the control unit and is used to control the generation of a control voltage in the first branch based on the output current of the control unit. ; The second branch is connected to the first branch and is based on the control voltage. It enables the transistor to be turned on or off, and when it is turned on, the gate of the power transistor MnPWR is completely discharged, while when it is turned off, the gate voltage of the power transistor MnPWR is maintained.

10. The circuit for improving power supply transient response during secondary power-on as described in claim 9, characterized in that: The first branch includes an NMOS transistor Mn6, a PMOS transistor Mp3, a step-down resistor R2, a voltage-regulating resistor R1, a voltage-regulating capacitor C1, and a current source Ibias; wherein, The gate of the NMOS transistor Mn6 is connected to one end of the voltage regulator resistor R1, one end of the voltage regulator capacitor C1, and the gate of the NMOS transistor Mn7 in the second branch, respectively. The other end of the voltage regulator resistor R1 is connected to the input voltage. Connect the other end of the voltage regulator capacitor C1 to ground; The drain of the NMOS transistor Mn6 is connected to the output terminal of the charge pump and the gate of the power transistor, respectively, and the source is connected to one end of the step-down resistor R2. The other end of the step-down resistor R2 is connected to the output terminal of the control unit and the source of the PMOS transistor Mp3, respectively. The gate and input voltage of the PMOS transistor Mp3 The drain is connected to one end of the current source Ibias and the gate of the NMOS transistor Mn8 in the second branch, respectively, and the other end of the current source Ibias is grounded.

11. The circuit for improving power supply transient response during secondary power-on as described in claim 10, characterized in that: When the control unit generates an output current, the voltage drop generated by the step-down resistor R2 in the first branch is: ; in, This is the gate-source voltage of the NMOS transistor Mn1.

12. The circuit for improving power supply transient response during secondary power-on as described in claim 10, characterized in that: When the control unit generates an output current, the first branch is in the off state and the control voltage is 0V. When the control unit does not generate output current, the first branch is in a conducting state, and the control voltage controls the conduction of the second branch.

13. The circuit for improving power supply transient response during secondary power-on as described in claim 11, characterized in that: Adjust the resistance values ​​of resistors R2 and R4 to make the equation... Established; among them, Input voltage Pressure drop; This is the gate-source voltage of the NMOS transistor Mn1; and These are the turn-on threshold voltages for MOSFETs Mn6 and Mp3, respectively.

14. The circuit for improving power supply transient response during secondary power-on as described in claim 10, characterized in that: The second branch includes NMOS transistors Mn7 and Mn8; wherein, The gate of the NMOS transistor Mn7 is connected to the gate of the NMOS transistor Mn6 in the first branch, one end of the voltage regulator resistor R1, and one end of the voltage regulator capacitor C1, respectively. The drain of the NMOS transistor Mn7 is connected to the output terminal of the charge pump and the gate of the power transistor MnPWR, respectively, and the source is connected to the drain of the NMOS transistor Mn8. The gate of the NMOS transistor Mn8 is connected to the gate of the PMOS transistor Mp3 in the first branch and one end of the current source Ibias, respectively, with the source grounded.

15. The circuit for improving power supply transient response during secondary power-on as described in claim 14, characterized in that: When the control voltage is 0V, the second branch is in the off state, maintaining the gate voltage of the power transistor MnPWR; When the control voltage controls the conduction of the second branch, the second branch performs a complete discharge on the gate of the power transistor MnPWR.

16. The circuit for improving the transient response of a power supply during a secondary power-on process according to claim 9, characterized in that: The gate of the power transistor MnPWR is connected to the charge pump and the pull-down unit, the drain is connected to the input voltage, and the source is used as the output voltage terminal of the power transistor MnPWR.

17. The circuit for improving the transient response of a power supply during a secondary power-on process according to claim 1, characterized in that: When the pull-down unit maintains the gate voltage of the power transistor MnPWR, the power transistor MnPWR remains on, and the output voltage of the power transistor MnPWR... The input voltage of the power transistor MnPWR equal; When the pull-down unit performs a complete discharge on the gate of the power transistor MnPWR, the power transistor MnPWR switches to the off state after being completely discharged.

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