Latch circuit and LLC resonant converter with such latch circuit

Abstract

This invention primarily discloses a latching circuit applied in an LLC resonant converter having a bridge switch control chip and a bridge switch unit, and mainly includes a signal processing unit. According to the design of this invention, the signal processing unit receives a stop output signal (LLC_S) and an upper arm switch control signal (HG) transmitted by the bridge switch control chip, and then performs a signal latching process, thereby outputting an enable signal to the bridge switch control chip. In this operation, when the bridge switch control chip performs functions such as soft start, overvoltage protection, and undervoltage lockout, the enable signal can adjust the upper arm switch control signal (HG) and the lower arm switch control signal (LG) output by the bridge switch control chip, thereby preventing excessive time differences between the switching components of the bridge switch unit from causing large currents in the resonant tank under unbalanced conditions.

Description

Technical Field

[0001] This invention relates to the technical field of switching-mode power supply (SMPS), and more particularly to a latching circuit applied in LLC resonant converters. Background Technology

[0002] Switching-mode power supply (SMPS) technology has been widely used in the manufacture of power supplies for various motor devices and electronic products. As electronic products trend towards thinner and smaller designs, it is necessary to increase the power density of SMPS by increasing the switching frequency in order to effectively reduce the size of the SMPS. Therefore, the LLC resonant converter, featuring zero-voltage switching (ZVS) and zero-current switching (ZCS), has been proposed.

[0003] Figure 1 This shows a circuit block diagram of a conventional LLC resonant converter. For example... Figure 1 As shown, the conventional LLC resonant converter 1a mainly comprises: a DC power supply circuit 10a consisting of a bridge rectifier and a PFC unit; a bridge switching unit 11a; a resonant unit 12a; a transformer unit 13a including a magnetizing inductor Lm_a; an output rectifier unit 14a; an output capacitor Co_a; a first control unit 15a; and a second control unit 16a. The resonant unit 12a is composed of a resonant inductor Lr_a, a resonant capacitor Cr_a, and the magnetizing inductor Lm_a. The PFC unit has a first switching component, and the first control unit 15a generates a PWM signal to control the on / off switching of the first switching component.

[0004] Figure 2 Show the topology diagram of a half-bridge switching circuit. For example... Figure 2As shown, the bridge switching unit 11a is designed as a half-bridge switching circuit and includes a first upper arm switching component Q1a and a first lower arm switching component Q2a. The second control unit 16a generates an upper arm switching component control signal HG and a lower arm switching component control signal LG to control the on / off switching of the first upper arm switching component Q1a and the first lower arm switching component Q2a, respectively. It is worth noting that existing circuit chips used as the second control unit 16a typically have a bootstrap circuit. During the conduction of the first lower arm switching component Q2a, the low-voltage terminal of the circuit charges the bootstrap capacitor in the bootstrap circuit, causing the bootstrap capacitor to provide the operating voltage to the drain terminal of the first upper arm switching component Q1a during its conduction. Therefore, conventional technology typically adds an additional capacitor charging time to the on-time of the switching components in the lower arm switching component control signal LG. It is worth noting that since the first upper arm switch assembly Q1a operates in the off state during the capacitor charging time interval, it does not store energy in the resonant unit 12a.

[0005] Electronic engineers familiar with LLC resonator design and fabrication should know that the bridge switching unit 11a can also be a full-bridge switching circuit. Figure 3 Show the topology diagram of a full-bridge switching circuit. For example... Figure 3 As shown, the bridge switching unit 11a is designed as a full-bridge switching circuit and includes a first upper arm switching assembly Q1a, a second upper arm switching assembly Q3a, a first lower arm switching assembly Q2a, and a second lower arm switching assembly Q4a. Furthermore, the second control unit 16a generates a first switching assembly control signal HG to control the on / off switching of the first upper arm switching assembly Q1a and the second upper arm switching assembly Q3a, and generates a lower arm switching assembly control signal LG to control the on / off switching of the first lower arm switching assembly Q2a and the second lower arm switching assembly Q4a. Figure 3 As shown, the first upper arm switch assembly Q1a and the second upper arm switch assembly Q3a form a diagonal switch pair, and the first lower arm switch assembly Q2a and the second lower arm switch assembly Q4a form another diagonal switch pair. In practical operation, once either diagonal switch is turned on, it stores energy in the resonant unit 12a. This results in a very large difference in the switching / conduction time when the second control unit 16a circuit chip performs the soft-start function, causing the resonant unit 12a to generate a very large current in an unbalanced state.

[0006] As can be seen from the foregoing description, the prior art second control unit 16a (i.e., the bridge switch unit 11a control chip) obviously has aspects that need improvement. In view of this, the inventors of this case have made great efforts to research and invent, and have finally developed a latching circuit for use in LLC resonators according to the present invention. Summary of the Invention

[0007] The main objective of this invention is to provide a latching circuit for use in an LLC resonant converter having a bridge switch control chip and a bridge switch unit, and mainly includes a signal processing unit. According to the design of this invention, the signal processing unit receives a stop output signal (LLC_S) and an upper arm switch control signal (HG) transmitted by the bridge switch control chip, and then performs a signal latching process to output an enable signal to the bridge switch control chip. In this operation, when the bridge switch control chip performs functions such as soft start, overvoltage protection, and undervoltage lockout, the enable signal can adjust the upper arm switch control signal (HG) and the lower arm switch control signal (LG) output by the bridge switch control chip, thereby preventing excessive time differences between the switching components of the bridge switch unit from causing large currents in the resonant tank under unbalanced conditions.

[0008] To achieve the above objectives, the present invention provides an embodiment of the latching circuit, which is applied in an LLC resonant converter having a bridge switch control chip and a bridge switch unit, and includes:

[0009] A first input terminal is coupled to a control signal for an upper arm switch assembly transmitted by the bridge switch control chip;

[0010] A second input terminal is coupled to a stop output signal;

[0011] The first output terminal is coupled to a bridge switch control chip; and

[0012] A signal processing unit is coupled to the first input terminal, the second input terminal and the first output terminal;

[0013] After receiving the upper arm switch assembly control signal and the stop output signal through the first input terminal and the second input terminal, the signal processing unit performs a signal latching process, and then outputs a first enable signal to the bridge switch control chip through the first output terminal.

[0014] In a feasible embodiment, the bridge switching unit is either a half-bridge switching unit or a full-bridge switching unit.

[0015] In a feasible embodiment, the latching circuit of the present invention further includes: a second output terminal coupled to the signal processing unit, and a signal selection unit coupled to the first output terminal and the second output terminal via one input side, and coupled to the bridge switch control chip via one output side. After completing the signal latching processing, the signal processing unit transmits a first enable signal (Active high enable) and a second enable signal (Active low enable) to the signal selection unit, which selectively transmits either the first enable signal or the second enable signal to the bridge switch control chip.

[0016] In a first embodiment, the signal processing unit is a logic circuit, and it includes:

[0017] A first NAND gate, having two input terminals respectively coupled to the first input terminal and the second input terminal; and

[0018] An RS flip-flop has a first signal input coupled to one of the outputs of a first NAND gate, a second signal input coupled to the second input, a first signal output, and a second signal output, wherein the first signal output and the second signal output respectively output the first enable signal and the second enable signal.

[0019] In a second embodiment, the signal processing unit is a logic circuit, and it includes:

[0020] A first NAND gate has one output terminal and two input terminals respectively coupled to the first input terminal and the second input terminal;

[0021] A second NAND gate has an output and two inputs, and one of its inputs is coupled to the output of the first NAND gate; and

[0022] A third NAND gate has an output terminal and two input terminals respectively coupled to the output terminal and the second input terminal of the second NAND gate;

[0023] Wherein, one of the input terminals of the second NAND gate 2 is coupled to the output terminal of the third NAND gate, such that the output terminal of the second NAND gate and the output terminal of the third NAND gate respectively output the first enable signal and the second enable signal.

[0024] In a third embodiment, the signal processing unit includes:

[0025] A first Schottky diode is coupled to the first input terminal with its anode end connected to the first input terminal;

[0026] A first NMOS transistor is coupled to the cathode of a first Schottky diode via its drain terminal, to the second input terminal via its gate terminal, and to ground via its source terminal.

[0027] A second Schottky diode is coupled to the first output terminal via its anode end;

[0028] A second NMOS transistor is coupled to the cathode of the second Schottky diode via its gate, to the second output terminal via its drain, and to the ground via its source.

[0029] A third NMOS transistor is coupled to the second output terminal with one of its gate terminals and to the ground terminal with one of its source terminals.

[0030] A first resistor has a first terminal and a second terminal, wherein the first terminal is coupled to an operating voltage and the second terminal is coupled to the drain terminal of the second NMOS transistor;

[0031] A second resistor having a first terminal and a second terminal, wherein the first terminal is coupled to the operating voltage, and the second terminal is simultaneously coupled to the first output terminal and a drain terminal of the third NMOS transistor; and

[0032] A capacitor is coupled between the first output terminal and the ground terminal;

[0033] The drain terminal of the first NMOS transistor, the gate terminal of the second NMOS transistor, the cathode terminal of the first Schottky diode, and the cathode terminal of the second Schottky diode are all coupled to the third input terminal.

[0034] In a fourth embodiment, the signal processing unit includes:

[0035] A first Schottky diode is coupled to the first input terminal with its anode end connected to the first input terminal;

[0036] A first NMOS transistor is coupled to the cathode of a first Schottky diode via its drain terminal, to the second input terminal via its gate terminal, and to ground via its source terminal.

[0037] A second Schottky diode is coupled to the first output terminal via its anode end;

[0038] A second NMOS transistor is coupled to the cathode of the second Schottky diode via its gate, to the second output terminal via its drain, and to the ground via its source.

[0039] A third NMOS transistor is coupled to the second output terminal with one of its gate terminals and to the ground terminal with one of its source terminals.

[0040] A first resistor having a first terminal and a second terminal, wherein the second terminal is coupled to the drain terminal of the second NMOS transistor;

[0041] A second resistor having a first terminal and a second terminal, wherein the second terminal is simultaneously coupled to the first output terminal and a drain terminal of the third NMOS transistor;

[0042] A capacitor is coupled between the first output terminal and the ground terminal;

[0043] A first PMOS transistor, with its source terminal coupled to the operating voltage, its drain terminal coupled to the first terminal of the first resistor, and its gate terminal coupled to the gate terminal of the second NMOS transistor; and

[0044] A second PMOS transistor is coupled to the operating voltage at one of its source terminals, coupled to the first terminal of the second resistor at one of its drain terminals, and coupled to both the second output terminal and the gate terminal of the third NMOS transistor at one of its gate terminals.

[0045] The drain terminal of the first NMOS transistor, the gate terminal of the second NMOS transistor, the cathode terminal of the first Schottky diode, and the cathode terminal of the second Schottky diode are all coupled to the third input terminal.

[0046] Furthermore, the present invention also proposes an LLC resonator, which includes a bridge switch control chip and a bridge switch unit; characterized in that the LLC resonator has a latching circuit as described above, which is coupled between the bridge switch control chip and the bridge switch unit. Attached Figure Description

[0047] Figure 1 This is a circuit block diagram of a known LLC resonant converter;

[0048] Figure 2 This is a topology diagram of a half-bridge switching circuit;

[0049] Figure 3 This is a topology diagram of a full-bridge switching circuit;

[0050] Figure 4 This is a first circuit block diagram of an LLC resonant converter that includes a latching circuit according to the present invention;

[0051] Figure 5 This is a block diagram of the second circuit of an LLC resonant converter including the latching circuit of the present invention;

[0052] Figure 6This is a first circuit topology diagram of the latching circuit of the present invention;

[0053] Figure 7 This is a second circuit topology diagram of the latching circuit of the present invention;

[0054] Figure 8 The timing diagram shows the operation of the stop output signal, the upper arm switch assembly control signal, the lower arm switch assembly control signal, the first enable signal, the second enable signal, and the first and second output signals output by the bridge switch unit.

[0055] Figure 9 The timing diagram shows the operation of the stop output signal, the upper arm switch assembly control signal, the lower arm switch assembly control signal, the first enable signal, the second enable signal, and the first and second output signals output by the bridge switch unit.

[0056] Figure 10 This is a topological diagram of a third circuit of the latching circuit of the present invention;

[0057] Figure 11 This is a fourth circuit topology diagram of the latching circuit of the present invention;

[0058] Figure 12 The timing diagram for the stop output signal, upper arm switch assembly control signal, lower arm switch assembly control signal, first enable signal, second enable signal, and the first and second output signals output by the bridge switch unit; and

[0059] Figure 13 The timing diagram shows the operation of the stop output signal, the upper arm switch assembly control signal, the lower arm switch assembly control signal, the first enable signal, the second enable signal, and the first and second output signals output by the bridge switch unit.

[0060] Explanation of reference numerals in the attached figures:

[0061] 1a: LLC resonant converter

[0062] 10a: DC power supply circuit

[0063] 11a: Bridge switch unit

[0064] 12a: Resonant Unit

[0065] 13a: Transformer Unit

[0066] 14a: Output rectifier unit

[0067] 15a: First control unit

[0068] 16a: Second control unit

[0069] Co_a: Output capacitor

[0070] Lr_a: Resonant inductor

[0071] Cr_a: Resonant capacitor

[0072] Lm_a: Magnetizing inductance

[0073] LLC_S: Stop output signal

[0074] OUT_HS: First output signal

[0075] OUT_LS: Second output signal

[0076] LLC_OC: Open collector signal

[0077] LLC_S: Stop output signal

[0078] Q1a: First upper arm switch assembly

[0079] Q2a: First lower arm switch assembly

[0080] Q3a: Second upper arm switch assembly

[0081] Q4a: Second lower arm switch assembly

[0082] 1: LLC resonant converter

[0083] 10: DC power supply circuit

[0084] 11: Bridge switch unit

[0085] 12: Resonant Unit

[0086] 13: Transformer Unit

[0087] 14: Output rectifier unit

[0088] 16: Bridge switch control chip

[0089] Co: Output capacitor

[0090] Lr: Resonant inductance

[0091] Cr: Resonant capacitor

[0092] Lm: Magnetizing inductance

[0093] 2: Latch circuit

[0094] 20: Signal Processing Unit

[0095] 200:RS flip-flop

[0096] 201: First NAND Gate

[0097] 202: Second NAND Gate

[0098] 203: Third NAND Gate

[0099] 21: First input terminal

[0100] 22: Second input terminal

[0101] 23: First output terminal

[0102] 24: Second output terminal

[0103] 25: Signal Selection Unit

[0104] 26: Third input terminal

[0105] D1: First Schottky diode

[0106] D2: Second Schottky diode

[0107] M1: First NMOS transistor

[0108] M2: Second NMOS transistor

[0109] M3: Third NMOS transistor

[0110] R1: First resistor

[0111] R2: Second resistor

[0112] C1: Capacitor

[0113] M4: First PMOS transistor

[0114] M5: Second PMOS transistor

[0115] HG: Upper arm switch assembly control signal

[0116] LG: Lower arm switch assembly control signal

[0117] Vcc: Operating voltage Detailed Implementation

[0118] To more clearly describe the latching circuit and the LLC resonant converter including the latching circuit proposed in this invention, the preferred embodiments of the invention will be described in detail below with reference to the drawings.

[0119] Please see Figure 4 It shows a first circuit block diagram of an LLC resonant converter including a latching circuit of the present invention. Figure 4As shown, the basic structure of the LLC resonant converter 1 includes: a DC power supply circuit 10 consisting of a bridge rectifier and a PFC unit, a bridge switching unit 11, a resonant unit 12, a transformer unit 13 including a magnetizing inductor Lm, an output rectifier unit 14, an output capacitor Co, and a bridge switching control chip 16. The resonant unit 12 is composed of a resonant inductor Lr, a resonant capacitor Cr, and the magnetizing inductor Lm.

[0120] Electronic engineers who have long been involved in the design and fabrication of LLC resonant converters will know that the bridge switch control chip 16 is used to output an upper arm switch component control signal HG and a lower arm switch component control signal LG to the bridge switch unit 11. The bridge switch unit 11 can be a full-bridge switch circuit or a half-bridge switch circuit.

[0121] In one embodiment, the latching circuit 2 of the present invention includes: a first input terminal 21, a second input terminal 22, a first output terminal 23, and a signal processing unit 20, wherein the signal processing unit 20 is coupled to the first input terminal 21, the second input terminal 22, and the first output terminal 23. Figure 4 As shown, the signal processing unit 20 receives an upper arm switch component control signal HG from the bridge switch control chip 16 through the first input terminal 21, and receives a stop output signal LLC_S through the second input terminal 22. According to the present invention, after receiving the upper arm switch component control signal HG and the stop output signal LLC_S, the signal processing unit 20 performs a signal latching process, and then outputs an enable signal to the bridge switch control chip 16 through the first output terminal 23. In this operation, when the bridge switch control chip 16 performs functions such as soft start, overvoltage protection (OVP), and undervoltage lockout (UVLO), the enable signal can adjust the upper arm switch control signal HG and / or the lower arm switch control signal LG output by the bridge switch control chip 16, thereby preventing excessive time differences between the switching / conduction of the upper / lower arm switch components in the bridge switch unit 11, which could lead to a large current being generated in the resonant tank (i.e., the resonant unit 12) under unbalanced conditions.

[0122] Please see Figure 5 It shows a block diagram of the second circuit of an LLC resonant converter including the latching circuit of the present invention. Figure 5As shown, in a feasible embodiment, the latching circuit 2 of the present invention may further include: a second output terminal 24 coupled to the signal processing unit 20, and a signal selection unit 25 coupled to the first output terminal 23 and the second output terminal 24 via one input side, and coupled to the bridge switch control chip 16 via one output side. With this design, after the signal processing unit 20 completes the signal latching process, the signal selection unit 25 receives a first enable signal (Active high enable) and a second enable signal (Active low enable) transmitted by the signal processing unit 20, and then selectively transmits the first enable signal or the second enable signal to the bridge switch control chip 16.

[0123] Please see Figure 6 The diagram shows a first circuit topology of the latching circuit 2 of the present invention. In a first embodiment, the signal processing unit 20 included in the latching circuit 2 is a logic circuit, comprising: a first NAND gate 201 and an RS flip-flop 200. The first NAND gate 201 has two input terminals respectively coupled to the first input terminal 21 and the second input terminal 22. The RS flip-flop 200 has a first signal input terminal (i.e., S terminal) coupled to one output terminal of the first NAND gate 21, a second signal input terminal (i.e., R terminal) coupled to the second input terminal 22, a first signal output terminal (i.e., Q terminal), and a second signal output terminal (i.e., QN terminal), wherein the first signal output terminal and the second signal output terminal respectively output the first enable signal (Active high enable) and the second enable signal (Active low enable).

[0124] Please see Figure 7This diagram shows a second circuit topology of the signal processing unit 20 of the latching circuit 2 of the present invention. In a second embodiment, the signal processing unit 20 included in the latching circuit 2 is also a logic circuit, and it includes: a first NAND gate 201, a second NAND gate 202, and a third NAND gate 203. The first NAND gate 201 has an output terminal and two input terminals respectively coupled to the first input terminal 21 and the second input terminal 22. Similarly, the second NAND gate 202 also has an output terminal and two input terminals, and one of its input terminals is connected to the output terminal of the first NAND gate 201. Furthermore, the third NAND gate 203 also has an output terminal and two input terminals, and its two input terminals are respectively coupled to the output terminal of the second NAND gate 202 and the second input terminal 22, and one of its input terminals is coupled to the output terminal of the third NAND gate 203. According to this circuit design, the output terminal of the second NAND gate 202 is used to output the first enable signal (Active high enable), and the output terminal of the third NAND gate 203 is used to output the second enable signal (Active low enable).

[0125] Please see Figure 8 and Figure 9 This is a timing diagram showing the stop output signal LLC_S, the upper arm switch assembly control signal HG, the lower arm switch assembly control signal LG, the first enable signal (Active high enable), the second enable signal (Active low enable), and the first output signal OUT_HS and the second output signal OUT_LS output by the bridge switch unit 11. Figure 5 , Figure 8 and Figure 9 As shown, according to the design of the present invention, the signal processing unit 20 receives the upper arm switch assembly control signal HG and the stop output signal LLC_S, then performs a signal latching process according to the circuit function, and then outputs a first enable signal (Active high enable) and a second enable signal (Active low enable or Active high enable).

[0126] like Figure 8 As shown, when the LLC resonant converter 1 is operating normally, the signal level of the stop output signal LLC_S is maintained at a high level. At this time, after receiving the stop output signal LLC_S and the upper arm switch assembly control signal HG, the signal processing unit 20 (e.g., Figure 6 and Figure 7The signal level of the first enable signal (Active high enable) output by the device shown is maintained at a high level, while the signal level of the second enable signal (Active low enable) output by the device is maintained at a low level. It is worth noting that, as shown... Figure 9 As shown, when the bridge switch control chip 11 performs functions such as soft start, overvoltage protection (OVP), and undervoltage lockout (UVLO), the signal level of the stop output signal LLC_S is switched to a low level. At this time, the signal level of the first enable signal (Active high enable) output by the signal processing unit 20 is switched from a high level to a low level, and the signal level of the second enable signal (Active low enable) output by the signal processing unit 20 is switched from a low level to a high level. Thus, after receiving the enable signal transmitted by the signal processing unit 20 (through the signal selection unit 25), the upper arm switch control signal HG and the lower arm switch control signal LG output by the bridge switch control chip 16 are adjusted (turned off). Furthermore, since the upper arm switch control signal HG and the lower arm switch control signal LG are turned off, the first output signal (OUT_HS) and the second output signal (OUT_LS) output by the bridge switch unit 11 to the resonant slot (i.e., the resonant unit 12) are also simultaneously adjusted (turned off).

[0127] Please see Figure 10 This diagram shows a third circuit topology of the latching circuit 2 of the present invention. In a third embodiment of the latching circuit 2, the signal processing unit 20 includes: a first Schottky diode D1, a first NMOS transistor M1, a second Schottky diode D2, a second NMOS transistor M2, a third NMOS transistor M3, a first resistor R1, a second resistor R2, and a capacitor C1. Figure 10 As shown, the anode of the first Schottky diode D1 is coupled to the first input terminal 21, and the drain of the first NMOS transistor M1 is coupled to the cathode of the first Schottky diode D1, while its gate and source are coupled to the second input terminal 22 and ground, respectively. On the other hand, the anode of the second Schottky diode D2 is coupled to the first output terminal 23, and the gate of the second NMOS transistor M2 is coupled to the cathode of the second Schottky diode D2, while its drain and source are coupled to the second output terminal 24 and ground, respectively. Furthermore, the gate and source of the third NMOS transistor M3 are coupled to the second output terminal 24 and ground, respectively.

[0128] Furthermore, Figure 10The diagram also shows that the first terminal of the first resistor R1 is coupled to an operating voltage Vcc, and its second terminal is coupled to the drain terminal of the second NMOS transistor M2. Conversely, the first terminal of the second resistor R2 is coupled to the operating voltage Vcc, and its second terminal is coupled to both the first output terminal 23 and the drain terminal of the third NMOS transistor M2. Furthermore, the capacitor C1 is coupled between the first output terminal 23 and ground. Figure 10 As shown, the drain terminal of the first NMOS transistor M1, the gate terminal of the second NMOS transistor M2, the cathode terminal of the first Schottky diode D1, and the cathode terminal of the second Schottky diode D2 are all coupled to the third input terminal 26. It is worth noting that, in the third embodiment, the latching circuit 2 of the present invention further includes a third input terminal 26 coupled to the signal processing unit 20, for the signal processing unit 20 to receive an open-collector signal LLC_OC through the third input terminal 26.

[0129] Please see Figure 11 This diagram shows a fourth circuit topology of the latching circuit 2 of the present invention. In this fourth embodiment of the latching circuit 2, the signal processing unit 20 also includes: a first Schottky diode D1, a first NMOS transistor M1, a second Schottky diode D2, a second NMOS transistor M2, a third NMOS transistor M3, a first resistor R1, a second resistor R2, and a capacitor C1. Furthermore, as... Figure 11 As shown, the signal processing unit 20 further includes a first PMOS transistor M4 and a second PMOS transistor M5. The source terminal of the first PMOS transistor M4 is coupled to the operating voltage Vcc, and its drain and gate terminals are respectively coupled to the first terminal of the first resistor R1 and the gate terminal of the second NMOS transistor M2. Conversely, the source terminal of the second PMOS transistor M5 is coupled to the operating voltage Vcc, its drain terminal is coupled to the first terminal of the second resistor R2, and its gate terminal is simultaneously coupled to the second output terminal 24 and the gate terminal of the third NMOS transistor M3.

[0130] Please see Figure 12 and Figure 13 This is a timing diagram showing the stop output signal LLC_S, the upper arm switch assembly control signal HG, the lower arm switch assembly control signal LG, the first enable signal (Active high enable), the second enable signal (Active low enable), and the first output signal OUT_HS and the second output signal OUT_LS output by the bridge switch unit 11. Figure 10 , Figure 12 and Figure 13As shown, according to the design of the present invention, the signal processing unit 20 receives the upper arm switch assembly control signal HG and the stop output signal LLC_S, then performs a signal latching process according to the circuit function, and then outputs a first enable signal (Active high enable) and a second enable signal (Active low enable or Active high enable).

[0131] like Figure 12 As shown, when the LLC resonant converter 1 is operating normally, the signal level of the stop output signal LLC_S is maintained at a high level. At this time, after receiving the stop output signal LLC_S and the upper arm switch assembly control signal HG, the signal processing unit 20 (such as...) Figure 10 and Figure 11 The signal level of the first enable signal (Active high enable) output by the device shown is maintained at a high level, while the signal level of the second enable signal (Active low enable) output by the device is maintained at a low level. It is worth noting that, as shown... Figure 13 As shown, when the bridge switch control chip 11 performs functions such as soft start, overvoltage protection (OVP), and undervoltage lockout (UVLO), the signal level of the stop output signal LLC_S is switched to a low level. At this time, the signal level of the first enable signal (Active high enable) output by the signal processing unit 20 is switched from a high level to a low level, and the signal level of the second enable signal (Active low enable) output by the signal processing unit 20 is switched from a low level to a high level. Thus, after receiving the enable signal transmitted by the signal processing unit 20 (through the signal selection unit 25), the upper arm switch control signal HG and the lower arm switch control signal LG output by the bridge switch control chip 16 are adjusted (turned off). Furthermore, since the upper arm switch control signal HG and the lower arm switch control signal LG are turned off, the first output signal (OUT_HS) and the second output signal (OUT_LS) output by the bridge switch unit 11 to the resonant slot (i.e., the resonant unit 12) are also simultaneously adjusted (turned off).

[0132] Thus, the foregoing has fully and clearly described a latching circuit and an LLC resonant converter having the latching circuit of the present invention. It must be emphasized that the above detailed description pertains to specific embodiments of the present invention, but these embodiments are not intended to limit the scope of the patent. All equivalent implementations or modifications that do not depart from the spirit of the present invention should be included within the scope of this patent.

Claims

1. A latching circuit, applied in an LLC resonant converter having a bridge switch control chip and a bridge switch unit, and comprising: A first input terminal is coupled to a control signal for an upper arm switch assembly transmitted by the bridge switch control chip; A second input terminal is coupled to a stop output signal; The first output terminal is coupled to the bridge switch control chip; as well as A signal processing unit is coupled to the first input terminal, the second input terminal and the first output terminal; The feature is that, after receiving the upper arm switch assembly control signal and the stop output signal through the first input terminal and the second input terminal, the signal processing unit performs a signal latching process, and then outputs a first enable signal to the bridge switch control chip through the first output terminal.

2. The latching circuit according to claim 1, characterized in that, The bridge switch unit is either a half-bridge switch unit or a full-bridge switch unit.

3. The latching circuit according to claim 1, characterized in that, It further includes: a second output terminal coupled to the signal processing unit, and a signal selection unit coupled to the first output terminal and the second output terminal via one of its input sides, and coupled to the bridge switch control chip via one of its output sides.

4. The latching circuit according to claim 3, characterized in that, After completing the signal latching process, the signal processing unit transmits the first enable signal and a second enable signal to the signal selection unit, which then selectively transmits either the first enable signal or the second enable signal to the bridge switch control chip.

5. The latching circuit according to claim 4, characterized in that, Including: A third input terminal of the signal processing unit is coupled to enable the signal processing unit to receive an open collector signal through the third input terminal.

6. The latching circuit according to claim 5, characterized in that, The signal processing unit is a logic circuit, and it includes: A first NAND gate, having two input terminals respectively coupled to the first input terminal and the second input terminal; and An RS flip-flop has a first signal input coupled to one of the outputs of a first NAND gate, a second signal input coupled to the second input, a first signal output, and a second signal output, wherein the first signal output and the second signal output respectively output the first enable signal and the second enable signal.

7. The latching circuit according to claim 5, characterized in that, The signal processing unit is a logic circuit, and it includes: A first NAND gate has one output terminal and two input terminals respectively coupled to the first input terminal and the second input terminal; A second NAND gate has one output and two inputs, and one of its inputs is connected to the output of the first NAND gate; and A third NAND gate has an output terminal and two input terminals respectively coupled to the output terminal and the second input terminal of the second NAND gate; Wherein, one of the input terminals of the second NAND gate is coupled to the output terminal of the third NAND gate, such that the output terminal of the second NAND gate and the output terminal of the third NAND gate respectively output the first enable signal and the second enable signal.

8. The latching circuit according to claim 5, characterized in that, The signal processing unit includes: A first Schottky diode is coupled to the first input terminal with its anode end connected to the first input terminal; A first NMOS transistor is coupled to the cathode of a first Schottky diode via its drain terminal, to the second input terminal via its gate terminal, and to ground via its source terminal. A second Schottky diode is coupled to the first output terminal via its anode end; A second NMOS transistor is coupled to the cathode of the second Schottky diode via its gate, to the second output terminal via its drain, and to the ground via its source. A third NMOS transistor is coupled to the second output terminal with one of its gate terminals and to the ground terminal with one of its source terminals. A first resistor has a first terminal and a second terminal, wherein the first terminal is coupled to an operating voltage and the second terminal is coupled to the drain terminal of the second NMOS transistor; A second resistor having a first terminal and a second terminal, wherein the first terminal is coupled to the operating voltage, and the second terminal is simultaneously coupled to the first output terminal and a drain terminal of the third NMOS transistor; and A capacitor is coupled between the first output terminal and the ground terminal; The drain terminal of the first NMOS transistor, the gate terminal of the second NMOS transistor, the cathode terminal of the first Schottky diode, and the cathode terminal of the second Schottky diode are all coupled to the third input terminal.

9. The latching circuit according to claim 5, characterized in that, The signal processing unit includes: A first Schottky diode is coupled to the first input terminal with its anode end connected to the first input terminal; A first NMOS transistor is coupled to the cathode of a first Schottky diode via its drain terminal, to the second input terminal via its gate terminal, and to ground via its source terminal. A second Schottky diode is coupled to the first output terminal via its anode end; A second NMOS transistor is coupled to the cathode of the second Schottky diode via its gate, to the second output terminal via its drain, and to the ground via its source. A third NMOS transistor is coupled to the second output terminal with one of its gate terminals and to the ground terminal with one of its source terminals. A first resistor having a first terminal and a second terminal, wherein the second terminal is coupled to the drain terminal of the second NMOS transistor; A second resistor having a first terminal and a second terminal, wherein the second terminal is simultaneously coupled to the first output terminal and a drain terminal of the third NMOS transistor; A capacitor is coupled between the first output terminal and the ground terminal; A first PMOS transistor, having its source terminal coupled to an operating voltage, its drain terminal coupled to the first terminal of the first resistor, and its gate terminal coupled to the gate terminal of the second NMOS transistor; and A second PMOS transistor is coupled to the operating voltage at one of its source terminals, to the first terminal of the second resistor at one of its drain terminals, and to the gate terminal of both the second output terminal and the gate terminal of the third NMOS transistor at one of its gate terminals. The drain terminal of the first NMOS transistor, the gate terminal of the second NMOS transistor, the cathode terminal of the first Schottky diode, and the cathode terminal of the second Schottky diode are all coupled to the third input terminal.

10. An LLC resonator, comprising a bridge switch control chip and a bridge switch unit; characterized in that, The LLC resonator has a latching circuit as described in any one of claims 1 to 9.

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