Video processing device

Abstract

A video processing apparatus, implemented in-chip, includes an on-chip prediction buffer and processing circuitry. The on-chip prediction buffer is shared by multiple prediction codecs and is used to store reference data. The processing circuitry supports codecs for prediction, reads multiple first reference data from the on-chip prediction buffer as input data for first codecs (included in the codecs and enabled by the processing circuitry), and writes the output data of the first codecs enabled by the processing circuitry into the on-chip prediction buffer as multiple second reference data.

Description

[0001] Related citations

[0002] This invention claims priority to U.S. Provisional Application No. 63 / 233,831, filed on August 17, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a video processing design, and more specifically, to a video processing apparatus using an internal prediction buffer shared by multiple codec tools for prediction. Background Technology

[0004] Traditional video codec standards typically employ block-based coding techniques to leverage spatial and temporal redundancy. For example, the basic approach involves dividing the entire source image into multiple blocks, performing intra / inter-frame prediction on each block, transforming the residuals of each block, and then quantizing and entropy coding. Furthermore, reconstructed images are generated within the coding loop to provide reference pixel data for encoding and decoding subsequent blocks. For a specific video codec standard, loop filters can be used to enhance the image quality of the reconstructed image. The video decoder performs the inverse operations of the video encoding performed by the video encoder. For example, a video decoder may have multiple processing circuits, such as entropy decoding circuits, intra-frame prediction circuits, motion compensation circuits, inverse quantization circuits, inverse transform circuits, reconstruction circuits, and loop filters.

[0005] Intra-frame / inter-frame prediction can utilize various codec tools to improve the accuracy of prediction data. In traditional designs, the reference data required by the codec tools for intra-frame prediction is read from a large off-chip memory such as dynamic random access memory (DRAM). For example, the input data for a first codec tool used for intra-frame prediction is read from a first dedicated memory area allocated in DRAM, and the output data of the first codec tool used for intra-frame prediction is written to the first dedicated memory area allocated in DRAM for later use; similarly, the input data for a second codec tool used for intra-frame prediction is read from a second dedicated memory area allocated in DRAM, and the output data of the second codec tool used for intra-frame prediction is written to the second dedicated memory area allocated in DRAM for later use. Furthermore, because the reference data required for intra-frame prediction is stored in DRAM, intra-frame prediction performance may be degraded due to DRAM latency.

[0006] Therefore, an innovative design is needed that can reduce reference storage size and / or improve processing latency and performance. Summary of the Invention

[0007] One object of the present invention is to provide a video processing apparatus that uses an internal prediction buffer shared by multiple codec tools for prediction.

[0008] According to a first aspect of the present invention, an exemplary video processing apparatus implemented in a chip is disclosed. The exemplary video processing apparatus includes an on-chip prediction buffer and processing circuitry. The on-chip prediction buffer is shared by a plurality of codec tools for prediction and is arranged to store reference data. The processing circuitry is arranged to support the plurality of codec tools for prediction, read a plurality of first reference data from the on-chip prediction buffer as input data for a first codec tool, the first codec tool being included in the plurality of codec tools and enabled by the processing circuitry, and write output data of the first codec tool enabled by the processing circuitry into the on-chip prediction buffer as a plurality of second reference data.

[0009] According to a second aspect of the present invention, an exemplary video processing apparatus is disclosed. The exemplary video processing apparatus includes a prediction buffer and processing circuitry. The prediction buffer is shared by a plurality of codec tools for prediction and is arranged to store reference data, wherein the prediction buffer is not dynamic random access memory (DRAM). The processing circuitry is arranged to support the plurality of codec tools for prediction, read a plurality of first reference data from the prediction buffer as input data for a first codec tool, which is included in the plurality of codec tools and enabled by the processing circuitry, and write output data of the first codec tool enabled by the processing circuitry into the prediction buffer as a plurality of second reference data.

[0010] These and other objects of the invention will undoubtedly become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments shown in the various accompanying drawings. Attached Figure Description

[0011] Various embodiments of this disclosure presented as examples will be described in detail with reference to the following drawings, wherein the same numerals denote the same elements, and wherein:

[0012] Figure 1 A schematic diagram of a first video processing apparatus according to an embodiment of the present invention is shown.

[0013] Figure 2 A diagram illustrating the footprint of an on-chip prediction buffer according to an embodiment of the present invention is provided.

[0014] Figure 3 A schematic diagram of data transmission between the processing circuitry and the on-chip prediction buffer in CCLM mode according to an embodiment of the present invention is shown.

[0015] Figure 4 A schematic diagram of data transmission between the processing circuitry and the on-chip prediction buffer in MRLP mode according to an embodiment of the present invention is shown.

[0016] Figure 5 A schematic diagram illustrating data transmission between the processing circuitry and the on-chip prediction buffer in CIIP mode according to an embodiment of the present invention is shown.

[0017] Figure 6 This diagram illustrates another data transfer between the processing circuitry and the on-chip prediction buffer in CIIP mode according to an embodiment of the present invention.

[0018] Figure 7 A diagram illustrating data transfer between the processing circuitry and the on-chip prediction buffer in IBC mode according to an embodiment of the present invention.

[0019] Figure 8 A schematic diagram of a second video processing apparatus according to an embodiment of the present invention is shown.

[0020] Figure 9 A schematic diagram of a third video processing apparatus according to an embodiment of the present invention is shown.

[0021] Figure 10 A schematic diagram of a fourth video processing apparatus according to an embodiment of the present invention is shown. Detailed Implementation

[0022] Specific terms are used in the following description and claims to refer to specific elements. As will be understood by those skilled in the art, electronic device manufacturers may use different names to refer to an element. This document is not intended to distinguish between elements with different names but different functions. In the following description and claims, the terms "comprising" and "including" are used in an open-ended manner and should therefore be interpreted as meaning "including but not limited to...". Furthermore, the term "coupled" is intended to indicate an indirect or direct electrical connection. Thus, if one device is coupled to another device, the connection can be through a direct electrical connection or through an indirect electrical connection via other devices and connections.

[0023] Figure 1A schematic diagram of a first video processing apparatus according to an embodiment of the present invention is shown. The video processing apparatus 100 is implemented in a chip 10 and coupled to off-chip memory such as dynamic random access memory (DRAM) 20. The video processing apparatus 100 may be part of a Versatile Video Coding (VVC) encoder / decoder. However, this is for illustrative purposes only and is not intended to limit the invention. In fact, any video encoder / decoder using the architecture proposed in this invention falls within the scope of this invention. In this embodiment, the video processing apparatus 100 includes processing circuitry 102, an on-chip prediction buffer 104, and post-processing circuitry (labeled "PP") 106. Processing circuitry 102 includes an inter-frame prediction module (labeled "INTER") 108 and an intra-frame prediction module (labeled "INTRA") 110. Processing circuitry 102 supports multiple codec tools for prediction. For example, the intra-prediction tools supported by the intra-prediction module 100 may include two or more of the following: intra-block copy (IBC), combined inter-intra-prediction (CIIP), cross-component linear model (CCLM), and multiple reference line prediction (MRLP). In this embodiment, the processing circuit 102 can enable an intra-prediction mode selected from IBC, CIIP, CCLM, and MRLP. IBC, CIIP, CCLM, and MRLP are specified in the VVC codec standard. Since the principles of IBC, CIIP, CCLM, and MRLP are well known to those skilled in the art, they will not be described in detail here for the sake of brevity.

[0024] The on-chip prediction buffer 104 is an internal buffer shared by multiple codec tools (such as IBC, CIIP, CCLM, and MRLP) used for prediction, and is arranged to store reference data. It should be noted that the on-chip prediction buffer 104 is not DRAM. For example, the on-chip prediction buffer 104 could be implemented using static random access memory (SRAM). Since the on-chip prediction buffer 104 is shared by multiple codec tools (e.g., IBC, CIIP, CCLM, and MRLP) used for prediction, the processing circuit 102 (in particular, the intra-frame prediction module 110 of the processing circuit 102) is arranged to read multiple first reference data from the on-chip prediction buffer 104 as input data for a selected codec tool (e.g., one of IBC, CIIP, CCLM, and MRLP) enabled by the processing circuit 102 (in particular, the intra-frame prediction module 110 of the processing circuit 102), and to write the output data of the selected codec tool (e.g., one of IBC, CIIP, CCLM, and MRLP) enabled by the processing circuit 102 (in particular, the intra-frame prediction module 110 of the processing circuit 102) into the on-chip prediction buffer 104 as multiple second reference data.

[0025] Figure 2 A diagram illustrating the occupied space of an on-chip prediction buffer 104 according to an embodiment of the present invention is provided. In this embodiment, the reference data stored in the on-chip prediction buffer 104 includes prediction data (represented by block 202) and reconstruction data (represented by block 204). It should be noted that the prediction data can be converted into reconstruction data by adding the prediction data and the corresponding residual data. The on-chip prediction buffer 104 may have unused areas (represented by block 206). For example, the prediction data (represented by block 202) may include intra-frame prediction data (i.e., prediction data generated by intra-frame prediction) and inter-frame prediction data (i.e., prediction data generated by inter-frame prediction). For another example, the reconstruction data (represented by block 204) may include intra-frame reconstruction data (i.e., reconstruction data generated in intra-frame prediction mode) and inter-frame reconstruction data (i.e., reconstruction data generated in inter-frame prediction mode). When the intra-frame prediction mode is set by CCLM, MRLP, or IBC, intra / inter-frame reconstruction data is read from the on-chip prediction buffer 104 as input data for the intra-frame prediction mode, and the output data (reconstructed data) generated from the intra-frame prediction mode is written to the on-chip prediction buffer 104. When the intra-frame prediction mode is set by CIIP, intra / inter-frame prediction data is read from the on-chip prediction buffer 104 as input data for the intra-frame prediction mode, and the output data (reconstructed data) generated from the intra-frame prediction mode is written to the on-chip prediction buffer 104. To better understand the technical features of the present invention, several examples of accessing (reading / writing) reference data using the on-chip prediction buffer 104 are given below.

[0026] Figure 3 This diagram illustrates data transmission between the processing circuit 102 and the on-chip prediction buffer 104 in CCLM mode according to an embodiment of the present invention. Figure 3 As shown in sub-figure (A), the processing circuit 102 (specifically, the intra-frame prediction module 110 of the processing circuit 102) obtains luminance reconstruction data from the on-chip prediction buffer 104. Next, as... Figure 3 As shown in sub-figure (B), the processing circuit 102 (particularly the intra-frame prediction module 110 of the processing circuit 102) downsamples the luminance reconstruction data to generate chrominance reconstruction data and writes the chrominance reconstruction data into the on-chip prediction buffer 104.

[0027] Figure 4 This diagram illustrates data transfer between the processing circuitry 102 and the on-chip prediction buffer 104 in MRLP mode according to an embodiment of the present invention. Since the encoding / decoding tool selected and enabled by the processing circuitry 102 is MRLP, the top and left adjacent blocks of the current block are required. The top and left adjacent blocks of the current block are the reconstructed data of the previous block and are stored in the on-chip prediction buffer 104. Figure 4 As shown in sub-figure (A), the processing circuit 102 (particularly the intra-frame prediction module 110 of the processing circuit 102) obtains the reconstruction data of the previous block from the on-chip prediction buffer 104. Next, as... Figure 4 As shown in sub-figure (B), the processing circuit 102 (specifically, the intra-frame prediction module 110 of the processing circuit 102) determines the reconstruction data of the current block based on the reconstruction data of the previous block, and writes the reconstruction data of the current block into the on-chip prediction buffer 104.

[0028] Figure 5 This diagram illustrates data transmission between the processing circuit 102 and the on-chip prediction buffer 104 in CIIP mode according to an embodiment of the present invention. CIIP performs inter-frame and intra-frame mixing after completing inter-frame prediction and intra-frame prediction. It is assumed that the inter-frame prediction data is prepared first. Figure 5 As shown in sub-Figure (A), processing circuit 102 (particularly the inter-frame prediction module 108 of processing circuit 102) writes inter-frame prediction data into on-chip prediction buffer 104 and waits for intra-frame prediction data. When the intra-frame prediction data is ready, processing circuit 102 (particularly the intra-frame prediction module 110 of processing circuit 102) reads the inter-frame prediction data from on-chip prediction buffer 104 and mixes the inter-frame prediction data and intra-frame prediction data to generate the final prediction data, such as... Figure 5As shown in sub-figure (B). After inter-frame and intra-frame mixing is completed, the processing circuit 102 (specifically the adder of the processing circuit 102) adds the final prediction data to the corresponding residual data to generate reconstructed data as the output data of CIIP. The reconstructed data is written into the on-chip prediction buffer 104 at the same location as the inter-frame prediction data, as shown in the figure. Figure 5 As shown in sub-figure (C), specifically, the inter-frame prediction data stored in and read from the on-chip prediction buffer 104 as input data for CIIP is overwritten by the reconstructed data that serves as the output data for CIIP. Therefore, the reconstructed data output by CIIP does not occupy additional storage space.

[0029] Figure 6 This diagram illustrates another data transmission between the processing circuit 102 and the on-chip prediction buffer 104 in CIIP mode according to an embodiment of the present invention. CIIP performs inter-frame and intra-frame mixing after completing inter-frame prediction and intra-frame prediction. It is assumed that the intra-frame prediction data is prepared first. Figure 6 As shown in sub-Figure (A), processing circuit 102 (particularly the intra-frame prediction module 110 of processing circuit 102) writes intra-frame prediction data into on-chip prediction buffer 104 and waits for inter-frame prediction data. When inter-frame prediction data is ready, processing circuit 102 (particularly the inter-frame prediction module 108 of processing circuit 102) reads intra-frame prediction data from on-chip prediction buffer 104 and mixes inter-frame prediction data and intra-frame prediction data to generate final prediction data, such as... Figure 6 As shown in sub-figure (B). After inter-frame and intra-frame mixing is completed, the processing circuit 102 (especially the adder of the processing circuit 102) adds the final prediction data to the corresponding residual data to generate reconstructed data as the output data of CIIP, and writes the reconstructed data into the on-chip prediction buffer 104 at the same location as the intra-frame prediction data, as shown in the figure. Figure 6 As shown in sub-figure (C), specifically, the intra-frame prediction data stored in and read from the on-chip prediction buffer 104 as input data for CIIP is overwritten by the reconstructed data that serves as output data for CIIP. Therefore, the reconstructed data output by CIIP does not occupy additional storage space.

[0030] Although both the inter-frame prediction module 108 and the intra-frame prediction module 110 can perform inter-frame and intra-frame mixing according to the embodiments shown in Figures 5-6, the invention is not limited thereto. For example, the mixing module (not shown) can only be implemented in the inter-frame prediction module 108, while the intra-frame prediction module 110 can send intra-frame prediction data to the inter-frame prediction module 108 for mixing. Similarly, the mixing module can only be the intra-frame prediction module 110, while the inter-frame prediction module 108 can send inter-frame prediction data to the intra-frame prediction module 110 for mixing.

[0031] Figure 7 This diagram illustrates data transfer between the processing circuitry 102 and the on-chip prediction buffer 104 in IBC mode according to an embodiment of the present invention. IBC reads previously reconstructed blocks, which may originate from intra-frame prediction or inter-frame prediction. Figure 7 As shown in sub-figure (A), the processing circuit 102 (particularly the intra-frame prediction module 110 of the processing circuit 102) reads the reconstruction data of the previous block from the on-chip prediction buffer 104 as the reconstruction data for the current block. Figure 7 As shown in sub-figure (B), the processing circuit 102 (specifically, the intra-frame prediction module 110 of the processing circuit 102) writes the reconstructed data (IBC output data) of the previous block into the on-chip prediction buffer 104. It should be noted that, in order to support VVC IBC, the buffer size of the on-chip prediction buffer 104 must be greater than 4x64x64x1.5 pixels (4:2:0) or 4x64x64x2 pixels (4:2:2).

[0032] In some embodiments of the invention, the reference data stored in the on-chip prediction buffer 104 is used by one codec tool enabled by the processing circuit 102, and reused by another codec tool enabled by the processing circuit 102. For example, if CCLM, MRLP, CIIP, and IBC require the same reference data location, the same reference data stored in the on-chip prediction buffer 104 can be reused. In other words, the on-chip prediction buffer 104 does not need to store duplicate reference data for different codec tools (e.g., CCLM, MRLP, CIIP, and IBC). Thus, the size of the on-chip prediction buffer 104 can be reduced. For example, the size of the on-chip prediction buffer 104 can be less than half the image size.

[0033] In some embodiments, the video processing apparatus 100 may include control circuitry (not shown) communicating with processing circuitry 102 and on-chip prediction buffer 104. The control circuitry ensures that prediction data is not overwritten until it is reused by other codec tools. For example, the control circuitry may send a first signal to the on-chip prediction buffer 104 indicating that the prediction data is read-only, ensuring that the prediction data is available to other codec tools. Once the control circuitry receives a second signal from the processing circuitry indicating that the prediction data is no longer needed, the control circuitry sends a third signal indicating that the prediction data can be overwritten to the on-chip prediction buffer 104, thus preventing the no longer needed prediction data from occupying additional storage space.

[0034] In some embodiments of the invention, any reference data required by multiple codec tools (e.g., CCLM, MRLP, CIIP, and IBC) is read only from the on-chip prediction buffer 104 by the processing circuitry 102. Since the latency of the on-chip prediction buffer 104 (which is an internal buffer of the video processing apparatus 100) is much lower than that of off-chip memory (e.g., DRAM 20 outside the video processing apparatus 100), the processing latency and performance of multiple codec tools (e.g., CCLM, MRLP, CIIP, and IBC) can be improved.

[0035] about Figure 1 In the illustrated embodiment, the on-chip prediction buffer 104 is coupled to off-chip memory (e.g., DRAM 20) outside the video processing apparatus 100. The on-chip prediction buffer 104 is also arranged to output stored reconstructed data to the off-chip memory (e.g., DRAM 20). The post-processing circuitry 106 includes one or more loop filters and is arranged to apply post-processing (e.g., loop filtering) to the reconstructed data read from the off-chip memory (e.g., DRAM 20). In this embodiment, the post-processing circuitry 106 does not apply post-processing to any reconstructed data of a frame until all reconstructed data of the frame is available in the off-chip memory (e.g., DRAM 20). In other words, Figure 1 The architecture shown is a framework-based architecture. However, this is for illustrative purposes only and is not intended to limit the invention.

[0036] Figure 8A schematic diagram of a second video processing apparatus according to an embodiment of the present invention is shown. The video processing apparatus 800 may be part of a VVC encoder / decoder. However, this is for illustrative purposes only and is not intended to limit the invention. In fact, any video encoder / decoder using the architecture proposed in this invention falls within the scope of this invention. The main difference between video processing apparatus 100 and 800 is that the video processing apparatus 800, implemented in chip 30, has an on-chip prediction buffer 804 coupled to a post-processing circuit (labeled “PP”) 806. Specifically, no DRAM is coupled to the on-chip prediction buffer 804. Therefore, the on-chip prediction buffer 804 does not need to output its stored reference data to DRAM. Like the on-chip prediction buffer 104, the on-chip prediction buffer 804 is an internal buffer shared by multiple codec tools for prediction (e.g., two or more intra-frame prediction tools including IBC, CIIP, CCLM, and MRLP) and is arranged to store reference data. The on-chip prediction buffer 804 is not DRAM and may be implemented, for example, by SRAM. In this embodiment, the post-processing circuit 806 includes one or more loop filters and is arranged to apply post-processing (e.g., loop filtering) to the reconstructed data read from the on-chip prediction buffer 804, wherein the post-processing circuit 806 begins applying post-processing to the reconstructed data of the frame before all reconstructed data of the frame is generated from the processing circuit 102. For example, Figure 8 The architecture shown is a block-based architecture.

[0037] Regarding the above Figure 1 and Figure 8 In the hardware implementation of the illustrated embodiment, various codec tools (e.g., CCLM, MRLP, CIIP, and IBC) are implemented in the intra-frame prediction module 110 of the processing circuit 102. Alternatively, IBC (including copy functionality) and / or CIIP (including mixing functionality) can be implemented in the inter-frame prediction module. In short, from a hardware implementation perspective, IBC and / or CIIP can be implemented in either the inter-frame prediction module or the intra-frame prediction module.

[0038] Figure 9A schematic diagram of a third video processing apparatus according to an embodiment of the present invention is shown. The video processing apparatus 900 may be part of a VVC encoder / decoder. However, this is for illustrative purposes only and is not intended to limit the invention. In practice, any video encoder / decoder using the architecture proposed in this invention is within the scope of this invention. The main difference between video processing apparatuses 100 and 900 is that the video processing apparatus 900, implemented in chip 40, has a processing circuit 902 including an inter-frame prediction module (labeled "INTER") 908 and an intra-frame prediction module (labeled "INTRA") 910. The inter-frame prediction module 908 is responsible for processing IBC and CIIP, and the intra-frame prediction module 910 is responsible for processing CCLM and MRLP. Since those skilled in the art can easily understand the details of the video processing apparatus 900 after reading the above paragraphs, further details are omitted here.

[0039] Figure 10 A diagram illustrating a fourth video processing apparatus according to an embodiment of the present invention is shown. The video processing apparatus 1000 may be part of a VVC encoder / decoder. However, this is for illustrative purposes only and is not intended to limit the invention. In fact, any video encoder / decoder using the architecture proposed in this invention falls within the scope of this invention. The main difference between video processing apparatuses 800 and 1000 is that the video processing apparatus 1000 implemented in chip 50 has… Figure 9 The processing circuit 902 is shown. Since those skilled in the art can easily understand the details of the video processing apparatus 1000 after reading the above paragraphs, further details are omitted for brevity.

[0040] Those skilled in the art will readily observe that many modifications and changes can be made to the apparatus and method while retaining the teachings of the present invention. Therefore, the above disclosure should be construed as being limited only by the boundaries and limits of the appended claims.

Claims

1. A video processing apparatus, implemented in a chip, the apparatus comprising: An on-chip prediction buffer is shared by multiple prediction codecs used for prediction and is also arranged to store reference data. as well as A processing circuit, arranged to support the plurality of codec tools for prediction, reads a plurality of first reference data from the on-chip prediction buffer as input data for a first codec tool, the first codec tool being included in the plurality of codec tools and enabled by the processing circuit, and writes the output data of the first codec tool enabled by the processing circuit into the on-chip prediction buffer as a plurality of second reference data. The reference data stored in the on-chip prediction buffer includes reconstructed data, and the video processing apparatus further includes: A post-processing circuit is arranged to apply post-processing to reconstructed data read from the on-chip prediction buffer, wherein the post-processing circuit begins applying post-processing to the reconstructed data of the frame before all reconstructed data of the frame is generated by the processing circuit.

2. The video processing apparatus as described in claim 1, characterized in that, The plurality of codec tools further includes a second codec tool; and the plurality of first reference data stored in the on-chip prediction buffer are used by the first codec tool enabled by the processing circuitry and reused by the second codec tool enabled by the processing circuitry.

3. The video processing apparatus as described in claim 1, characterized in that, Any reference data required by the plurality of codec tools is read only from the on-chip prediction buffer by the processing circuitry.

4. The video processing apparatus as described in claim 1, characterized in that, The multiple encoding and decoding tools include multiple intra-frame prediction tools.

5. The video processing apparatus as described in claim 4, characterized in that, The plurality of intra-frame prediction tools include at least two of intra-frame block copying, combined inter-frame intra-frame prediction, cross-component linear model, and multi-reference line prediction.

6. The video processing apparatus as described in claim 1, characterized in that, The reference data stored in the on-chip prediction buffer includes prediction data and reconstruction data.

7. The video processing apparatus as described in claim 1, characterized in that, The reference data stored in the on-chip prediction buffer includes intra-frame prediction data and inter-frame prediction data.

8. The video processing apparatus as described in claim 1, characterized in that, The reference data stored in the on-chip prediction buffer includes intra-frame reconstruction data and inter-frame reconstruction data.

9. A video processing apparatus, comprising: A prediction buffer, shared by multiple codec tools for prediction, and arranged to store reference data, wherein the prediction buffer is not dynamic random access memory; as well as A processing circuit is arranged to support the plurality of codec tools used for prediction, reads a plurality of first reference data from the prediction buffer as input data for a first codec tool, wherein the first codec tool is included in the plurality of codec tools and is enabled by the processing circuit, and writes the output data of the first codec tool enabled by the processing circuit into the prediction buffer as a plurality of second reference data. The reference data stored in the prediction buffer includes reconstructed data, and the video processing device further includes: A post-processing circuit is arranged to apply post-processing to reconstructed data read from the prediction buffer, wherein the post-processing circuit begins applying post-processing to the reconstructed data of the frame before all reconstructed data of the frame is generated by the processing circuit.

10. The video processing apparatus as described in claim 9, characterized in that, The plurality of codec tools further includes a second codec tool; and the plurality of first reference data stored in the prediction buffer are used by the first codec tool enabled by the processing circuitry, and reused by the second codec tool enabled by the processing circuitry.

11. The video processing apparatus as described in claim 9, characterized in that, Any reference data required by the plurality of encoding and decoding tools is read only from the prediction buffer by the processing circuitry.

12. The video processing apparatus as described in claim 9, characterized in that, The multiple encoding and decoding tools include multiple intra-frame prediction tools.

13. The video processing apparatus as described in claim 12, characterized in that, The plurality of intra-frame prediction tools include at least two of intra-frame block copying, combined inter-frame intra-frame prediction, cross-component linear model, and multi-reference line prediction.

14. The video processing apparatus as described in claim 9, characterized in that, The reference data stored in the prediction buffer includes prediction data and reconstruction data.

15. The video processing apparatus as described in claim 9, characterized in that, The reference data stored in the prediction buffer includes intra-frame prediction data and inter-frame prediction data.

16. The video processing apparatus as described in claim 9, characterized in that, The reference data stored in the prediction buffer includes intra-frame reconstruction data and inter-frame reconstruction data.

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