Semiconductor structure

Abstract

A semiconductor structure comprises: a substrate; a plurality of channel structures on the substrate, the channel structures being mutually separated from each other, and the channel structures being arranged along a first direction of the substrate; the substrate comprising adjacent first and second regions along the arrangement direction of the plurality of channel structures, the first and second regions being used for forming first and second transistors respectively; an isolation layer between the channel structures; gate structures on the substrate and across the mutually separated channel structures, the gate structures being mutually separated from each other, and the gate structures being arranged along a second direction; the extension direction of the gate structures is non-perpendicular to the extension direction of the channel structures, and the first direction is non-perpendicular to the second direction; source-drain doped regions in the channel structures on both sides of the gate structures in the first and second regions. By adjusting the included angle between the extension direction of the gate structures and the extension direction of the channel structures, the device size can be miniaturized, and the performance of the semiconductor structure can be optimized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration, and semiconductor process nodes are continuously shrinking in accordance with Moore's Law. Transistors, as the most basic semiconductor devices, are currently widely used. Therefore, as the component density and integration of semiconductor devices increase, the channel length of transistors must be continuously shortened to adapt to the shrinking process nodes.

[0003] To better adapt to the requirements of proportionally shrinking device dimensions, semiconductor processes are gradually transitioning from planar transistors to more efficient three-dimensional transistors, such as FinFETs and Gate-all-around (GAA) transistors. In FinFETs, the gate structure can control the ultrathin body (fin) from at least two sides, thereby improving the gate structure's control over the channel. In GAA transistors, the gate surrounds the channel area from all sides, thus providing even stronger control over the channel and better suppressing short-channel effects.

[0004] However, the performance of semiconductor structures still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure that facilitates the miniaturization of device size and optimizes the performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; a plurality of channel structures located on the substrate, the channel structures being discrete from each other and arranged along the substrate in a first direction; wherein the substrate includes adjacent first and second regions along the arrangement direction of the plurality of channel structures, the first and second regions being used to form a first transistor and a second transistor, respectively; an isolation layer located between the channels; a gate structure located on the substrate and spanning the discrete channel structures, the gate structures being discrete from each other and arranged along a second direction; the extension direction of the gate structure is not perpendicular to the extension direction of the channel structure, and the first direction is not perpendicular to the second direction; and source / drain doped regions located within the channel structures on both sides of the first region and the gate structure of the first region.

[0007] Optionally, the source / drain doped regions include: a first source / drain doped region located within the channel structure on both sides of the gate structure of the first region; and a second source / drain doped region located within the channel structure on both sides of the gate structure of the second region.

[0008] Optionally, the acute angle between the extension direction of the gate structure and the extension direction of the channel structure is 35° to 85°.

[0009] Optionally, the semiconductor structure further includes a gate dielectric layer located between the gate structure and the channel structure.

[0010] Optionally, the material of the gate dielectric layer includes one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide, and nitrogen-doped silicon oxide.

[0011] Optionally, the channel structure is a fin, and the gate structure covers a portion of the top and a portion of the sidewalls of the fin; or, the channel structure is a channel structure layer, the channel structure layer comprising one or more channel layers suspended at intervals; the gate structure surrounds the channel layer.

[0012] Optionally, the channel structure is a fin; the isolation layer is located on the substrate and surrounds the fin, with the top surface of the isolation layer lower than the top surface of the fin; the gate structure is located on the isolation layer and spans the fin, covering a portion of the top and a portion of the sidewalls of the fin; or, the channel structure is a channel structure layer, the channel structure layer comprising one or more channel layers spaced apart and suspended; the semiconductor structure further includes: a protrusion, protruding from the substrate and located between the channel structure layer and the substrate, with the top of the protrusion spaced apart from the bottom of the channel structure layer; the isolation layer is located on the substrate and surrounds the protrusion; the gate structure is located on the isolation layer and spans the channel structure layer, and the gate structure surrounds the channel layer.

[0013] Optionally, the material of the isolation layer includes silicon oxide, silicon oxynitride, or silicon oxynitride.

[0014] Optionally, the substrate material includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; the channel structure material includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; and the gate structure material includes any one or more of the following: TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0015] Optionally, the substrate includes an SRAM cell, and the first transistor and the second transistor are used to form the SRAM cell, wherein the first transistor is a first pull-up transistor and the second transistor is a second pull-up transistor.

[0016] Optionally, the first transistor and the second transistor are PMOS transistors.

[0017] Optionally, the first source / drain doped region and the second source / drain doped region include a stress layer doped with P-type ions, and the stress layer is made of Si or SiGe.

[0018] Optionally, along the arrangement direction of the plurality of channel structures, the substrate further includes a third region located on the side of the first region away from the second region, and a fourth region located on the side of the second region away from the first region, wherein the third region and the fourth region are respectively used to form a first pull-down transistor and a second pull-down transistor; the source / drain doped regions include: a first source / drain doped region located within the channel structures on both sides of the gate structure of the first region; a second source / drain doped region located within the channel structures on both sides of the gate structure of the second region; the source / drain doped regions further include: a third source / drain doped region located within the channel structures on both sides of the gate structure of the third region; a fourth source / drain doped region located within the channel structures on both sides of the gate structure of the fourth region; the semiconductor structure further includes: a first shared contact structure located above and in contact with the first and third source / drain doped regions; a second shared contact structure located above and in contact with the second and fourth source / drain doped regions, wherein the second shared contact structure is spaced apart from the first shared contact structure.

[0019] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0020] The semiconductor structure provided in this embodiment of the invention has a gate structure whose extension direction is not perpendicular to the channel structure's extension direction. Compared to a scheme where the gate structure's extension direction is perpendicular to the channel structure's extension direction, this embodiment of the invention, without changing the spacing between gate structures or the spacing between channel structures, adjusts the angle between the extension directions of the gate structure and the channel structure. This allows for more space between adjacent channel structures in the first and second regions, which is beneficial for increasing the process window for forming the semiconductor structure, facilitating device miniaturization, increasing the spacing between the source / drain doped regions in the first and second regions, reducing the probability of bridging between the source / drain doped regions in the first and second regions, and optimizing the performance of the semiconductor structure. Attached Figure Description

[0021] Figure 1 This is a partial layout diagram of an SRAM memory array;

[0022] Figure 2 This is a top view of a semiconductor structure;

[0023] Figure 3 This is a schematic diagram of the circuit structure corresponding to an SRAM cell;

[0024] Figures 4 to 5 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0025] As the background technology shows, the performance of current semiconductor structures needs improvement. Taking the FinFET (Fin Field-Effect Transistor) as an example, this paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using a specific semiconductor structure as an example.

[0026] Specifically, the semiconductor structure is applied to a static random access memory (SRAM), which includes a memory array. Figure 1 This is a partial layout diagram of an SRAM memory array.

[0027] The storage array includes multiple storage units arranged in an array. Figure 2 This is a top view schematic diagram of a semiconductor structure, specifically, Figure 2 This is a layout diagram of one of the SRAM cells.

[0028] The semiconductor structure includes: a substrate, comprising a base (not shown) and a plurality of fins 11 disposed on the substrate, the substrate including adjacent first regions 10U1 and second regions 10U2 along the arrangement direction of the plurality of fins 11, the first regions 10U1 and the second regions 10U2 being used to form a first transistor and a second transistor, respectively; and a gate structure 12 located on the substrate and spanning the fins 11, the gate structure 12 covering a portion of the top and a portion of the sidewalls of the fins 11, and the extending direction of the gate structure 12 (i.e., Figure 1 The direction of d1 and the extension direction of the fin 11 (i.e., the direction of d1) are different. Figure 1 The first source / drain doped region 13 is located in the fins 11 on both sides of the gate structure 12 of the first region 10U1; the second source / drain doped region 14 is located in the fins 11 on both sides of the gate structure 12 of the second region 10U2.

[0029] In the semiconductor structure, the extension direction of the gate structure 12 is perpendicular to the extension direction of the fin 11. The miniaturization of the device is limited by the spacing between the first transistor and the second transistor. Specifically, as the device size gradually shrinks, the distance between the first source / drain doped region 13 and the second source / drain doped region 14 gradually decreases, and the probability of bridging between the first source / drain doped region 13 and the second source / drain doped region 14 increases. Correspondingly, the distance between the first contact plug (not shown) corresponding to the first source / drain doped region 13 and the second contact plug (not shown) corresponding to the second source / drain doped region 14 decreases, and the process window for forming the first contact plug and the second contact plug decreases. All of these factors limit the miniaturization of the device.

[0030] Reference Figure 3 The diagram shows the circuit structure of an SRAM cell. In the SRAM cell, the first transistor is a first pull-up transistor PU1, and the second transistor is a second pull-up transistor PU2. The SRAM cell also includes two pull-down transistors PD1 and PD2, and two transmission gate transistors PG1 and PG2.

[0031] The first pull-down transistor PD1 is connected to the first pull-up transistor PU1, and the second pull-down transistor PD2 is connected to the second pull-up transistor PU2. The first transmission gate transistor PG1 is connected to the first pull-down transistor PD1, and the second transmission gate transistor PG2 is connected to the second pull-down transistor PD2.

[0032] In this design, the first source / drain doped region 13 in the first pull-up transistor PU1 and the second source / drain doped region 14 in the second pull-up transistor PU2 are isolated from each other. That is, in the SRAM cell, the first contact plug (not shown) that contacts the first source / drain doped region 13 and the second contact plug that contacts the second source / drain doped region 14 are spaced apart from each other. The reduced distance between the first source / drain doped region 13 and the second source / drain doped region 14 leads to a reduction in the formation window of the first and second contact plugs. The fact that the extension direction of the gate structure 12 is perpendicular to the extension direction of the fin 11 will limit the miniaturization of the SRAM device.

[0033] To address the aforementioned technical problem, embodiments of the present invention provide a semiconductor structure in which the extension direction of the gate structure is not perpendicular to the extension direction of the channel structure. Compared to a scheme where the extension direction of the gate structure is perpendicular to the extension direction of the channel structure, embodiments of the present invention, without changing the spacing between the gate structures or the channel structures, adjust the angle between the extension directions of the gate structure and the channel structure to provide more space between adjacent channel structures in the first and second regions. This is beneficial for increasing the process window for forming the semiconductor structure, facilitating the miniaturization of device dimensions, and increasing the spacing between the source / drain doped regions in the first and second regions, reducing the probability of bridging between the source / drain doped regions in the first and second regions, thus optimizing the performance of the semiconductor structure.

[0034] To make the above-mentioned objects, features, and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (Reference) Figures 4 to 5 , Figure 4 This is a top view. Figure 5 for Figure 4 A cross-sectional view along the 1-1' direction shows a schematic diagram of an embodiment of the semiconductor structure of the present invention.

[0035] Specifically, the semiconductor structure is applied to a static random access memory (SRAM), which includes a memory array comprising a plurality of memory cells arranged in an array.

[0036] Specifically, Figure 4 This is a layout diagram of one of the SRAM cells 200. Figure 5 for Figure 4 A sectional view along the 1-1' direction.

[0037] like Figures 4 to 5As shown, in this embodiment, the semiconductor structure includes: a substrate, including a substrate 100 and a plurality of channel structures 110 located on the substrate 100, the channel structures 110 being discrete from each other, and the channel structures 110 being arranged along the substrate 100 in a first direction (not shown); wherein, the substrate 100 includes adjacent first regions I and second regions II along the arrangement direction of the plurality of channel structures 110, the first regions I and the second regions II being used to form a first transistor and a second transistor, respectively; an isolation layer 120 located between the channel structures 110; a gate structure 190 located on the substrate 100 and spanning the discrete channel structures 110, the gate structures 190 being discrete from each other, and the gate structures 190 being arranged along a second direction (not shown); the extension direction of the gate structure 190 (e.g., Figure 2 (in the d2 direction) and the extension direction of the channel structure 110 (e.g., in ... Figure 2 The first direction (d1 direction) is not perpendicular to the second direction; the source and drain doped regions (not shown) are located in the channel structure 110 on both sides of the gate structure 190 of the first region I and the second region II.

[0038] The substrate is used to provide a process platform for the formation of semiconductor structures.

[0039] In this embodiment, the substrate includes a substrate 100, and the material of the substrate 100 includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. As an example, the substrate 100 is a silicon substrate, that is, the material of the substrate 100 is single-crystal silicon.

[0040] The substrate 100 includes adjacent first region I and second region II along the arrangement direction (i.e., the first direction) of the plurality of fins 110, and the first region I and the second region II are respectively used to form a first transistor and a second transistor.

[0041] In this embodiment, the substrate includes SRAM cells. In this embodiment, the number of SRAM cells is one or more, and the one or more SRAM cells are used to constitute an SRAM device. Multiple SRAM cells are arranged in an array on the substrate 100.

[0042] Accordingly, in this embodiment, the first transistor is a first pull-up (PU) transistor PU1, and the second transistor is a second pull-up transistor PU2.

[0043] In this embodiment, both the first transistor and the second transistor are PMOS transistors.

[0044] It should be noted that, as Figure 4 and Figure 5 As shown, in this embodiment, along the arrangement direction (i.e., the first direction) of the plurality of channel structures 110, the substrate 100 further includes a third region III located on the side of the first region I away from the second region II, and a fourth region IV located on the side of the second region II away from the first region I. The third region III and the fourth region IV are respectively used to form a first pull-down (PD) transistor PD1 and a second pull-down transistor PD2.

[0045] The first pull-down transistor PD1 and the second pull-down transistor PD2 are used together with the first pull-up transistor PU1 and the second pull-up transistor PU2 to form the SRAM cell.

[0046] In this embodiment, both the first pull-down transistor PD1 and the second pull-down transistor PD2 are NMOS transistors.

[0047] In this embodiment, the SRAM cell further includes two transmission gate transistors: a first transmission gate transistor PG1 and a second transmission gate transistor PG2.

[0048] The channel structure 110 is used to provide a conductive channel for the transistor. In this embodiment, the channel structure 110 is arranged along the substrate 100 in a first direction (not shown), which is perpendicular to the extension direction of the channel structure 110.

[0049] In this embodiment, the material of the channel structure 110 includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. As an example, the material of the channel structure 110 is the same as the material of the substrate 100, and the material of the channel structure 110 is single-crystal silicon.

[0050] As one embodiment, the transistor is a FinFET, and the channel structure 110 is a fin 115. The fin 115 is used to provide a conductive channel for the FinFET.

[0051] In other embodiments, the transistor may also be other types of transistors, such as a gate-all-around (GAA) transistor. Accordingly, the channel structure is a channel structure layer, which includes one or more channel layers spaced apart and suspended.

[0052] When the transistor is a fully enclosed gate transistor, the semiconductor structure further includes: a protrusion protruding from the substrate and located between the channel structure layer and the substrate, wherein the top of the protrusion is spaced apart from the bottom of the channel structure layer.

[0053] Specifically, the protrusion and the substrate are an integral structure, and the material of the protrusion is the same as that of the substrate.

[0054] It should be noted that, in this embodiment, the semiconductor structure further includes: an isolation layer 120, located on the substrate 100 and surrounding the fin 115, wherein the top surface of the isolation layer 120 is lower than the top surface of the fin 115.

[0055] The isolation layer 120 is used to isolate adjacent fins 110, and the isolation layer 120 is also used to isolate the substrate 100 from the gate structure 190.

[0056] The insulating layer 120 is made of an insulating material. In this embodiment, the insulating layer 120 is made of one or two of silicon oxide, silicon nitride, and silicon oxynitride.

[0057] In other embodiments, when the transistor is a fully enclosed gate transistor, the channel structure is a channel structure layer, and the semiconductor structure further includes the protrusion, the isolation layer is located on the substrate and surrounds the protrusion.

[0058] In this embodiment, for ease of clear illustration and explanation, the isolation layer 120 is only shown in the cross-sectional schematic diagram.

[0059] The gate structure 190 serves as the device gate structure, used to control the opening and closing of the conductive channel. In this embodiment, the gate structure 190 is arranged along a second direction (not shown), which is perpendicular to the extending direction of the gate structure 190.

[0060] In this embodiment, the channel structure 110 is a fin 115, the gate structure 190 is located on the isolation layer 120 and spans the fin 115, and the gate structure 190 covers part of the top and part of the sidewall of the fin 110.

[0061] In other embodiments, when the channel structure is a channel structure layer comprising one or more spaced-apart channel layers, the gate structure is located on the isolation layer and spans the channel structure layer, and the gate structure surrounds the channel layer.

[0062] The first direction is not perpendicular to the second direction, and the extension direction of the gate structure 190 is not perpendicular to the extension direction of the channel structure 110. Compared with the scheme where the extension direction of the gate structure is perpendicular to the extension direction of the channel structure, this embodiment, without changing the spacing between the gate structures 190 or the spacing between the channel structures 110, adjusts the angle between the extension directions of the gate structure 190 and the channel structure 110, so that there is more space between the adjacent channel structures 110 of the first region I and the second region II. This is beneficial to increasing the process window for forming the semiconductor structure, facilitating the miniaturization of the device size, and increasing the spacing between the source and drain doped regions of the first region I and the second region II, reducing the probability of bridging between the source and drain doped regions of the first region I and the second region II, thus optimizing the performance of the semiconductor structure.

[0063] It should be noted that the acute angle α between the extending direction of the gate structure 190 and the extending direction of the channel structure 110 should not be too small or too large. If the acute angle α is too small, it is not conducive to the layout of the device; if the acute angle α is too large, the difference between the acute angle α and 90° will be too small, and the extending direction of the gate structure 190 will be nearly perpendicular to the extending direction of the channel structure 110, which may result in an insignificant increase in the space between adjacent channel structures 110 in the first region I and the second region II. Therefore, in this embodiment, the acute angle α between the extending direction of the gate structure 190 and the extending direction of the channel structure 110 is 35° to 85°, for example: 40°, 45°, 50°, 60°, 70°, 75°, 80°, etc.

[0064] In this embodiment, the gate structure 190 is a metal gate structure. The material of the gate structure 190 includes any one or more of the following: TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0065] In a specific implementation, the gate structure 190 may include a work function layer (not shown) and a gate electrode layer (not shown) located on the work function layer.

[0066] The work function layer is used to adjust the work function of the gate structure 190, thereby adjusting the threshold voltage of the field-effect transistor. The gate electrode layer is used as an external electrode for electrically connecting the gate structure 190 to an external circuit.

[0067] In this embodiment, a metal gate structure 190 is used as an example for illustration. In other embodiments, based on actual process requirements, the gate structure can also be other types of gate structures, such as polycrystalline silicon gate structures or amorphous silicon gate structures.

[0068] In this embodiment, the semiconductor structure further includes a gate dielectric layer (not shown) located between the gate structure 190 and the channel structure 110.

[0069] The gate dielectric layer is used to achieve electrical isolation between the gate structure 190 and the fin 110.

[0070] The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3.

[0071] In a specific implementation, the gate dielectric layer may be a gate oxide layer, or the gate dielectric layer may be a high-k gate dielectric layer, or the gate dielectric layer may include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer.

[0072] The source and drain doped regions are used as the source or drain of the transistor to provide a source of charge carriers when the transistor is in operation.

[0073] In this embodiment, the source / drain doped regions include: a first source / drain doped region 170, located within the channel structure 110 on both sides of the gate structure 190 of the first region I; and a second source / drain doped region 180, located within the channel structure 110 on both sides of the gate structure 190 of the second region II.

[0074] The first source / drain doped region 170 is used as the source or drain of the first transistor.

[0075] In this embodiment, the first source / drain doped region 170 includes a stress layer doped with ions. The stress layer is used to provide stress to the channel region, thereby improving the carrier mobility.

[0076] In this embodiment, the first transistor is a PMOS transistor, and the first source / drain doped region 170 is doped with P-type ions. Specifically, the first source / drain doped region 170 includes a stress layer doped with P-type ions, and the stress layer is made of Si or SiGe.

[0077] The second source / drain doped region 180 is used as the source or drain of the second transistor.

[0078] In this embodiment, the second source / drain doped region 180 includes a stress layer doped with ions. The stress layer is used to provide stress to the channel region, thereby improving the carrier mobility.

[0079] In this embodiment, the second transistor is a PMOS transistor, and the second source / drain doped region 180 is doped with P-type ions. Specifically, the second source / drain doped region 180 includes a stress layer doped with P-type ions, and the stress layer is made of Si or SiGe.

[0080] The first source / drain doped region 170 and the second source / drain doped region 180 include a stress layer doped with p-type ions, and the stress layer is made of Si or SiGe. That is, the first source / drain doped region 170 and the second source / drain doped region 180 have the same type of doped ions, and the first source / drain doped region 170 and the second source / drain doped region 180 are made of the same material.

[0081] In this embodiment, the doped ion type in the second source / drain doped region 180 is the same as that in the first source / drain doped region 170, and the material of the second source / drain doped region 180 is the same as that of the first source / drain doped region 170, because the second source / drain doped region 180 and the first source / drain doped region 170 are formed in the same step during the formation of the semiconductor structure.

[0082] In this embodiment, by adjusting the angle between the extension directions of the gate structure 190 and the channel structure 110, more space is provided between adjacent channel structures 110 of the first region I and the second region II. This is beneficial for increasing the process window for forming the semiconductor structure, for miniaturizing the device size, and for providing a larger formation space for the first source / drain doped region 170 and the second source / drain doped region 180. Even if the second source / drain doped region 180 and the first source / drain doped region 170 are formed in the same step during the semiconductor structure formation process, it is beneficial for increasing the spacing between the second source / drain doped region 180 and the first source / drain doped region 170 and reducing the probability of bridging between the second source / drain doped region 180 and the first source / drain doped region 170.

[0083] Correspondingly, the distance between the first contact structure that contacts the first source / drain doped region 170 and the second contact structure that contacts the second source / drain doped region 180 is also increased, which helps to increase the process window for forming the first and second contact structures, and thus helps to further reduce the device size.

[0084] In this embodiment, the source / drain doped region further includes: a third source / drain doped region 150, located within the channel structure 110 on both sides of the gate structure 190 of the third region III; and a fourth source / drain doped region 160, located within the channel structure 110 on both sides of the gate structure 190 of the fourth region IV.

[0085] The third source / drain doped region 150 is used as the source or drain of the third transistor.

[0086] The fourth source / drain doped region 160 is used as the source or drain of the fourth transistor.

[0087] In this embodiment, the third source / drain doped region 150 and the fourth source / drain doped region 160 include an ion-doped stress layer, which is used to provide stress to the channel region, thereby improving the carrier mobility.

[0088] In this embodiment, both the third and fourth transistors are NMOS transistors. Therefore, the third source / drain doped region 150 and the fourth source / drain doped region 160 include a stress layer doped with N-type ions. Specifically, the material of the stress layer includes Si.

[0089] In this embodiment, the semiconductor structure further includes: a first shared contact structure 210, located above and in contact with the first source / drain doped region 170 and the third source / drain doped region 150; and a second shared contact structure 220, located above and in contact with the second source / drain doped region 180 and the fourth source / drain doped region 160, wherein the second shared contact structure 220 is spaced apart from the first shared contact structure 210.

[0090] The first shared contact structure 210 is used to realize the electrical connection between the first source / drain doped region 170 and external circuits or other interconnection structures, and is also used to realize the electrical connection between the third source / drain doped region 150 and external circuits or other interconnection structures.

[0091] The first source / drain doped region 170 and the third source / drain doped region 150 share the first shared contact structure 210.

[0092] The second shared contact structure 220 is used to realize the electrical connection between the second source / drain doped region 180 and external circuits or other interconnect structures, and also to realize the electrical connection between the fourth source / drain doped region 160 and external circuits or other interconnect structures.

[0093] The second source / drain doped region 180 and the fourth source / drain doped region 160 share the second shared contact structure 220.

[0094] In this embodiment, by adjusting the angle between the extension directions of the gate structure 190 and the channel structure 110, more space is provided between adjacent channel structures 110 in the first region I and the second region II, thereby increasing the spacing between the first source / drain doped region 170 and the second source / drain doped region 180. This is beneficial for increasing the spacing between the first shared contact structure 210 and the second shared contact structure 220, and increasing the process window for forming the first shared contact structure 210 and the second shared contact structure 220.

[0095] In SRAM cell 200, the first pull-down transistor PD1 is connected to the first pull-up transistor PU1, and the second pull-down transistor PD2 is connected to the second pull-up transistor PU2.

[0096] Specifically, the first source-drain doped region 170 in the first pull-down transistor PD1 is connected to the third source-drain doped region 150 in the first pull-up transistor PU1, and the second source-drain doped region 180 in the second pull-down transistor PD2 is connected to the fourth source-drain doped region 160 in the second pull-up transistor PU2.

[0097] In this embodiment, the first source / drain doped region 170 in the first pull-up transistor PU1 and the second source / drain doped region 180 in the second pull-up transistor PU2 are isolated from each other. That is, in the SRAM cell 200, the first shared contact structure 210 corresponding to the first source / drain doped region 170 and the second shared contact structure 220 corresponding to the second source / drain doped region 180 are spaced apart. When the distance between the first source / drain doped region 170 and the second source / drain doped region 180 is reduced, the layout of the SRAM cell can be adjusted by making the gate structure 160 and the channel structure 110 non-perpendicular in this embodiment. This can increase the spacing between the first source / drain doped region 170 and the second source / drain doped region 180, and correspondingly increase the spacing between the first shared contact structure 210 and the second shared contact structure 220. This increases the process window for forming the first shared contact structure 210 and the second shared contact structure 220, which is beneficial for further miniaturization of the SRAM device.

[0098] In this embodiment, the materials of the first shared contact structure 210 and the second shared contact structure 220 are conductive materials, such as one or more of Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti and TiN.

[0099] It should also be noted that in SRAM cell 200, the first transmission gate transistor PG1 is connected to the first pull-down transistor PD1, and the second transmission gate transistor PG2 is connected to the second pull-down transistor PD2.

[0100] Specifically, the first transmission gate transistor PG1 and the first pull-down transistor PD1 share the third source-drain doped region 150, and the second transmission gate transistor PG2 and the second pull-down transistor PD2 share the fourth source-drain doped region 160.

[0101] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; the substrate includes SRAM cells; The substrate has a plurality of channel structures located on it, the channel structures being independent of each other and arranged along the substrate in a first direction; wherein the substrate includes an adjacent first region and a second region along the arrangement direction of the plurality of channel structures, the first region and the second region being used to form a first transistor and a second transistor, respectively; the first transistor and the second transistor are used to form the SRAM cell, the first transistor being a first pull-up transistor and the second transistor being a second pull-up transistor. An isolation layer is located between the trench structures; A gate structure is located on the substrate and spans the discrete channel structures, the gate structures being discrete from each other and arranged along a second direction; the extending direction of the gate structure is not perpendicular to the extending direction of the channel structure, and the first direction is not perpendicular to the second direction; the angle between the extending direction of the gate structure and the extending direction of the channel structure is an acute angle; the angle between the extending direction of the gate structure and the extending direction of the channel structure is used to increase the spacing between the source / drain doped regions of the first region and the source / drain doped regions of the second region. The source and drain doped regions are located within the channel structures on both sides of the gate structures in the first and second regions.

2. The semiconductor structure as described in claim 1, characterized in that, The source / drain doped region includes: a first source / drain doped region located within the channel structure on both sides of the gate structure of the first region; The second source / drain doped region is located within the channel structure on both sides of the gate structure in the second region.

3. The semiconductor structure as described in claim 1, characterized in that, The acute angle between the extension direction of the gate structure and the extension direction of the channel structure is 35° to 85°.

4. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes a gate dielectric layer located between the gate structure and the channel structure.

5. The semiconductor structure as described in claim 4, characterized in that, The material of the gate dielectric layer includes one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide, and nitrogen-doped silicon oxide.

6. The semiconductor structure as described in claim 1, characterized in that, The channel structure is a fin, and the gate structure covers part of the top and part of the sidewall of the fin; Alternatively, the channel structure is a channel structure layer, which includes one or more channel layers that are spaced apart and suspended. The gate structure surrounds the channel layer.

7. The semiconductor structure as described in claim 6, characterized in that, The channel structure is a fin; the isolation layer is located on the substrate and surrounds the fin, with the top surface of the isolation layer lower than the top surface of the fin; the gate structure is located on the isolation layer and spans the fin, covering part of the top and part of the sidewalls of the fin; or, The channel structure is a channel structure layer, and the channel structure layer includes one or more channel layers that are spaced apart and suspended. The semiconductor structure further includes: a protrusion, which protrudes from the substrate and is located between the channel structure layer and the substrate, and the top of the protrusion is spaced apart from the bottom of the channel structure layer; The isolation layer is located on the substrate and surrounds the protrusion; The gate structure is located on the isolation layer and spans the channel structure layer, and the gate structure surrounds the channel layer.

8. The semiconductor structure as described in claim 1, characterized in that, The material of the isolation layer includes silicon oxide, silicon nitride, or silicon oxynitride.

9. The semiconductor structure as described in claim 1, characterized in that, The substrate material includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; The materials of the channel structure include one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; The material of the gate structure includes any one or more of TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

10. The semiconductor structure as claimed in claim 1, characterized in that, The first transistor and the second transistor are PMOS transistors.

11. The semiconductor structure as claimed in claim 10, characterized in that, The source / drain doped region includes a stress layer doped with P-type ions, and the stress layer is made of Si or SiGe.

12. The semiconductor structure as claimed in claim 1, characterized in that, Along the arrangement direction of the plurality of channel structures, the substrate further includes a third region located on the side of the first region away from the second region, and a fourth region located on the side of the second region away from the first region, wherein the third region and the fourth region are respectively used to form a first pull-down transistor and a second pull-down transistor; The source / drain doped regions include: a first source / drain doped region located within the channel structure on both sides of the gate structure of the first region; and a second source / drain doped region located within the channel structure on both sides of the gate structure of the second region. The source / drain doped region further includes: a third source / drain doped region located within the channel structure on both sides of the gate structure of the third region; and a fourth source / drain doped region located within the channel structure on both sides of the gate structure of the fourth region. The semiconductor structure further includes: a first shared contact structure located above and in contact with the first and third source-drain doped regions; and a second shared contact structure located above and in contact with the second and fourth source-drain doped regions, wherein the second shared contact structure is spaced apart from the first shared contact structure.

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