Light emitting display apparatus and method of manufacturing the same

Abstract

A light emitting display apparatus and a method of manufacturing the same are provided. The light emitting display apparatus includes a display panel including a display area and a non-display area, first reference lines arranged in a first direction in the display area, second reference lines arranged in a second direction crossing the first direction in the display area and electrically connected to the first reference lines, and a power line arranged in the first direction in the display area and disposed between at least two of the first reference lines. The net-type reference lines disposed in the display area and the power line disposed therebetween reduce a pattern density and solve a problem of an increase in line pitch in implementing a narrow bezel and a large screen of the display panel, and minimize a problem of an increase in a second source voltage (EVSS rise), thereby implementing a uniform image without a position-based luminance difference and a color coordinate difference.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0105693, filed on August 10, 2021, with the Korean Intellectual Property Office, which is incorporated herein by reference as fully set forth herein. Technical Field

[0003] This disclosure relates to a light-emitting display device and a method for manufacturing the light-emitting display device. Background Technology

[0004] With the advancement of information technology, the market for display devices, which serve as connection media linking users with information, continues to grow. Consequently, the use of display devices such as light-emitting diode (LED) displays, quantum dot (QDD) displays, and liquid crystal displays (LCDs) is increasing.

[0005] The aforementioned display device includes: a display panel comprising a plurality of sub-pixels; a driver that outputs drive signals for driving the display panel; and a power supply for supplying power to the display panel or the driver.

[0006] In such a display device, when drive signals (e.g., scan signals and data signals) are provided to each sub-pixel disposed in the display panel, the selected sub-pixel can transmit light or emit light itself, and thus can display an image. Summary of the Invention

[0007] To overcome the aforementioned problems in related technologies, this disclosure provides a light-emitting display device and a method for manufacturing the light-emitting display device, wherein the pattern density is reduced and the problem of increased line spacing is solved when achieving a narrow bezel and a large screen for the display panel based on the reference lines of the mesh pattern disposed in the display area and the second power lines disposed therebetween, and the problem of increased second source voltage (EVSS rise) is minimized, thereby achieving a uniform image without position-based brightness differences and color coordinate differences.

[0008] To achieve these objectives and other advantages and for the purposes of this disclosure, as implemented and broadly described herein, a light-emitting display device includes: a display panel comprising a display area and a non-display area; a first reference line arranged in the display area in a first direction; a second reference line arranged in the display area in a second direction intersecting the first direction and electrically connected to the first reference line; and a power line arranged in the display area in the first direction and disposed between at least two of the first reference lines.

[0009] At least one of the first reference line and the second reference line may be set on a different layer than the power line.

[0010] The second reference line may be set on a different layer than the first reference line and the power line.

[0011] The first reference line and the power line may be selected as source and drain metal layers of transistors included in the sub-pixels of the display panel.

[0012] The second reference line may be selected as the semiconductor layer of the transistors included in the sub-pixels constituting the display panel.

[0013] The first reference line and the power line may be disposed between the interlayer insulation layer and the planarization layer, wherein the planarization layer is disposed in a layer higher than the second reference line.

[0014] The second reference line may be disposed between the buffer layer and the gate insulating layer, wherein the gate insulating layer is disposed in a layer lower than the first reference line and the power line.

[0015] The power line may include a low-level power line. The power level of the low-level power line may be lower than a predetermined power level.

[0016] The light-emitting display device may also include an additional power line whose power level is higher than the predetermined power level.

[0017] The first and second baselines can be arranged in a grid pattern.

[0018] The power cord can be configured to have a mesh pattern in the display area.

[0019] In another aspect of this disclosure, a light-emitting display device includes: a buffer layer disposed on a substrate; a lower reference line including a semiconductor layer disposed on the buffer layer and arranged in a horizontal direction in a display area defined on the substrate; at least one insulating layer disposed on the lower reference line; an upper reference line disposed on at least one insulating layer, arranged in a vertical direction in the display area defined on the substrate, and electrically connected to the lower reference line; and a power line disposed on the at least one insulating layer and arranged in the vertical direction in the display area defined on the substrate.

[0020] The upper reference line and the power line may be configured to be separate from each other on the at least one insulating layer and may each include source and drain metal layers.

[0021] In another aspect of this disclosure, a method of manufacturing a light-emitting display device includes: forming a buffer layer on a substrate; forming a lower reference line, the lower reference line including a semiconductor layer disposed on the buffer layer and arranged in a horizontal direction in a display area defined on the substrate; forming at least one insulating layer on the lower reference line; patterning a first source / drain metal layer disposed on the at least one insulating layer and arranged in a vertical direction in the display area defined on the substrate to form an upper reference line electrically connected to the lower reference line; and patterning a second source / drain metal layer disposed on the at least one insulating layer and arranged in the vertical direction in the display area defined on the substrate to form a power line separate from the upper reference line. Attached Figure Description

[0022] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the drawings:

[0023] Figure 1 This is a schematic diagram illustrating a light-emitting display device. Figure 2 It is a schematic map solution Figure 1 The diagram shows the sub-pixel block diagram;

[0024] Figure 3A and Figure 3B This is a diagram illustrating an example of the arrangement of a gate-in-the-panel (GIP) type scan driver. Figure 4 and Figure 5 This is an example diagram illustrating the construction of a device associated with a GIP-type scan driver;

[0025] Figure 6 This is an example diagram illustrating the shape of the display panel. Figure 7 This is an example diagram illustrating the circuit construction of a sub-pixel;

[0026] Figure 8 This is a plan view illustrating the reference lines and second power lines connected to the three sub-pixels according to the first embodiment of this disclosure. Figure 9A and Figure 9B This is a plan view used to describe the comparison between the arrangement structure according to the first embodiment and the experimental example. Figure 10 This is a plan view illustrating various signal lines and second power lines connected to a plurality of sub-pixels according to the first embodiment of the present disclosure;

[0027] Figure 11 This is a plan view illustrating the reference lines and the second power line connected to the three sub-pixels according to the second embodiment of this disclosure. Figure 12This is a plan view illustrating various signal lines and second power lines connected to multiple sub-pixels according to the second embodiment of this disclosure. Figure 13 It is a diagram Figure 12 A cross-sectional view of region A1-A2. Figure 14 It is a diagram Figure 12 A cross-sectional view of region B1-B2. Figure 15 It is a diagram Figure 12 A cross-sectional view of the C1-C2 region; and

[0028] Figure 16A , Figure 16B and Figure 17 This is a diagram used to describe the arrangement of lines according to embodiments of the present disclosure and the advantages based on this arrangement. Figure 18A , Figure 18B and Figure 19 It is a diagram used to describe the arrangement of lines based on experimental examples and the disadvantages of that arrangement. Detailed Implementation

[0029] The present disclosure will be described more fully below with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are illustrated. However, the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make the present disclosure thorough and complete and to fully convey the concept of the present disclosure to those skilled in the art.

[0030] The display devices according to this disclosure can be applied to televisions (TVs), video players, personal computers (PCs), home theaters, electronic devices for vehicles, and smartphones, but are not limited thereto. The display devices according to this disclosure can be implemented as light-emitting display devices, quantum dot display (QDD) devices, or liquid crystal display (LCD) devices. However, for ease of description, the following will describe, for example, self-emissive light-emitting display devices based on inorganic or organic light-emitting diodes.

[0031] Figure 1 This is a schematic diagram illustrating a light-emitting display device. Figure 2 It is a schematic map solution Figure 1 The diagram shows the sub-pixel.

[0032] like Figure 1 and Figure 2 As shown, the light-emitting display device may include a video providing unit 110, a timing controller 120, a scan driver 130, a data driver 140, a display panel 150, and a power supply 180.

[0033] The video providing unit 110 (or device or host system) can output video data signals provided from an external source or video data signals stored in its internal memory, as well as various drive signals. The video providing unit 110 can provide data signals and various drive signals to the timing controller 120.

[0034] The timing controller 120 can output a gate timing control signal GDC for controlling the operating timing of the scan driver 130, a data timing control signal DDC for controlling the operating timing of the data driver 140, and various synchronization signals (e.g., vertical synchronization signal Vsync and horizontal synchronization signal Hsync). The timing controller 120 can provide the data timing control signal DDC and the data signal DATA provided from the video providing unit 110 to the data driver 140. The timing controller 120 can be implemented as an integrated circuit (IC) and can be mounted on a printed circuit board (PCB), but is not limited thereto.

[0035] The scan driver 130 can output a scan signal (or scan voltage) in response to a gate timing control signal GDC provided from the timing controller 120. The scan driver 130 can provide the scan signal to multiple sub-pixels included in the display panel 150 through multiple scan lines GL1 to GLm. The scan driver 130 can be implemented as an IC type or can be directly disposed on the display panel 150 of the gate-in-panel (GIP) type, but is not limited thereto.

[0036] In response to the data timing control signal DDC provided from the timing controller 120, the data driver 140 samples and latches the data signal DATA, converts the digital data signal into an analog data voltage based on a gamma reference voltage, and outputs the analog data voltage. The data driver 140 can provide data voltages to the sub-pixels of the display panel 150 via multiple data lines DL1 to DLn, respectively. The data driver 140 can be implemented as an IC or mounted on the display panel 150 or a PCB, but is not limited thereto.

[0037] Power supply 180 can generate a first drive power with a high level and a second drive power with a low level based on an externally supplied input voltage, and can output the first drive power and the second drive power through a first power line EVDD and a second power line EVSS, respectively. The high level is higher than the low level. The low level is lower than a predetermined power level. The high level is higher than a predetermined power level. In addition to the first drive power and the second drive power, power supply unit 180 can also generate voltages required to drive scan driver 130 (e.g., gate voltage including gate high voltage and gate low voltage) or voltages required to drive data driver 140 (e.g., drain voltage and half-drain voltage).

[0038] The display panel 150 can display images based on a drive signal including a scan signal and a data voltage, a first drive power, and a second drive power. Each sub-pixel of the display panel 150 can be self-emissive. The display panel 150 can be manufactured based on a substrate with rigidity or flexibility, such as glass, silicon, or polyimide. Furthermore, the luminescent sub-pixels can include pixels containing red, green, and blue, or they can include pixels containing red, green, blue, and white.

[0039] For example, a sub-pixel SP can be connected to a first data line DL1, a first gate line GL1, a first power line EVDD, and a second power line EVSS, and may include pixel circuitry, including a switching transistor, a driving transistor, a storage capacitor, and an organic light-emitting diode (OLED). Sub-pixels SP used in light-emitting display devices can be self-emissive, thus their circuitry can be complex. Furthermore, sub-pixels SP may include various circuits, such as compensation circuitry for degradation of OLED emission and for compensating for degradation of the driving transistors that provide drive current to the OLED. Therefore, as can be seen in the figure, the sub-pixel SP is simply represented by a box.

[0040] In the preceding text, each of the timing controller 120, scan driver 130, and data driver 140 has been described as a separate component. However, depending on the implementation type of the light-emitting display device, one or more of the timing controller 120, scan driver 130, and data driver 140 may be integrated into a single IC.

[0041] Figure 3A and Figure 3B This is a diagram illustrating an example of the layout of a GIP-type scan driver. Figure 4 and Figure 5 This is an example diagram illustrating the construction of a device associated with a GIP-type scan driver.

[0042] like Figure 3A and Figure 3B As shown, multiple GIP-type scan drivers 130a and 130b can be arranged in the non-display area NA of the display panel 150. Figure 3A As shown, scan drivers 130a and 130b can be positioned in the non-display areas NA on the left and right sides of the display panel 150. Furthermore, as... Figure 3B As shown, scan drivers 130a and 130b can be disposed in the non-display areas NA on the upper and lower sides of the display panel 150.

[0043] Although examples of scan drivers 130a and 130b being positioned in the non-display areas NA on the left and right sides, or on the top and bottom sides are illustrated and described, scan drivers 130a and 130b may be positioned in only one of the non-display areas NA on the left, right, top, and bottom sides.

[0044] like Figure 4 As shown, the GIP-type scan driver 130 may include a shift register 131 and a level shifter 135. The level shifter 135 can generate a clock signal Clks and a start signal Vst based on signals and voltages output from a timing controller 120 and a power supply 180. The clock signal Clks can be generated in K-phase form (where K is an integer of 2 or greater), in which phases such as two-phase, four-phase, or eight-phase are different.

[0045] The shift register 131 can operate based on signals Clks and Vst output from the level converter 135, and can output scan signals Scan[1] to Scan[m] to turn on / off transistors disposed in the display panel. The shift register 131 can be implemented as a thin-film type on the display panel based on the GIP type. Therefore, the scan drivers 130a and 130b disposed in the non-display area NA of the display panel 150 shown in FIG. 3 can correspond to the shift register 131.

[0046] like Figure 4 and Figure 5 As shown, unlike shift register 131, level shifter 135 can be implemented independently as an IC or may be included in power supply 180. However, this is merely one implementation, and the present disclosure is not limited thereto.

[0047] Figure 6 This is an example diagram illustrating the shape of the display panel. Figure 7 This is an example diagram illustrating the circuit construction of a sub-pixel.

[0048] like Figure 6 As shown, the display panel 150 can be implemented in various shapes, such as rectangular (or quadrilateral) Figure 6 (a) of, circle ( Figure 6 (b) ), oval ( Figure 6 (c) and hexagon ( Figure 6 (d)). Except in Figure 6 In addition to the rectangular display panel 150 widely used in (a), Figure 6 (b) to Figure 6 The display panel 150 of (d) may have a shape that is different from the conventional shape (a shape that is different from the general shape), and may also be referred to as an irregularly shaped display panel.

[0049] like Figure 7As shown, a sub-pixel may include five switching transistors (e.g., first to fifth switching transistors) T1 to T5, a driving transistor DT, a storage capacitor Cst, and a light-emitting diode OLED. Here, Figure 7 The Cgv shown can be a compensation capacitor provided for compensation and can be omitted.

[0050] The first switching transistor T1 can transmit the data voltage applied through the first data line DL1 to the first electrode of the storage capacitor Cst in response to the first scan signal applied through the first scan line SCAN1.

[0051] The second switching transistor T2 can electrically connect the gate electrode of the driving transistor DT to the second electrode of the driving transistor DT in response to the second scan signal applied through the second scan line SCAN2 (so that the driving transistor DT is in a connected state to compensate for the threshold voltage).

[0052] The third switching transistor T3 can transmit the reference voltage (initialization voltage or compensation voltage) applied through the reference line VREF to the first electrode of the storage capacitor Cst in response to the light emission control signal (or third scan signal) applied through the light emission control line (or third scan line) EM.

[0053] The fourth switching transistor T4 can transmit the drive current generated by the driving transistor DT to the anode electrode of the light-emitting diode OLED in response to the light-emitting control signal applied through the light-emitting control line EM.

[0054] The storage capacitor Cst can store data voltage and can drive the driving transistor DT based on the stored data voltage. The light-emitting diode OLED emits light based on the driving current generated from the driving transistor DT.

[0055] Figure 7 The sub-pixels shown can compensate the threshold voltage of the driving transistor DT based on the second switching transistor T2 and the third switching transistor T3, and can control the emission time of the light-emitting diode OLED based on the fourth switching transistor T4, thus having various advantages.

[0056] In addition, Figure 7 An example of implementing all thin-film transistors included in a sub-pixel as P-type has already been described. However, all thin-film transistors included in a sub-pixel can be implemented as N-type, or a hybrid structure of P-type and N-type. Furthermore, Figure 7 The following embodiments are illustrated and described only to aid in understanding the planar and cross-sectional structures of the power lines and various signal lines connected to the sub-pixels, and this disclosure is not limited thereto.

[0057] Figure 8This is a plan view illustrating the reference lines and second power lines connected to the three sub-pixels according to the first embodiment of this disclosure. Figure 9A and Figure 9B This is a plan view used to describe the comparison between the arrangement structure according to the first embodiment and the experimental example. Figure 10 This is a plan view illustrating various signal lines and second power lines connected to a plurality of sub-pixels according to the first embodiment of this disclosure.

[0058] like Figure 8 As shown, according to the first embodiment, a pixel PIX can be provided in the display area AA of the display panel 150, in which the red sub-pixel SPR, the green sub-pixel SPG, and the blue sub-pixel SPB are arranged in sequence. The arrangement order of the sub-pixels in the pixel PIX may be only one embodiment, but the present disclosure is not limited thereto.

[0059] Furthermore, a first reference line VREF1 arranged in a first direction (length direction), a second reference line VREF2 arranged in a second direction (width direction), and a second power line EVSS arranged in the first direction can be provided in the display area AA of the display panel 150. The first reference line VREF1 and the second reference line VREF2 can be arranged in a mesh pattern.

[0060] According to the first embodiment, the first reference line VREF1 and the second reference line VREF2 can be disposed on a different layer than the second power line EVSS. Alternatively, the first reference line VREF1 and the second reference line VREF2 can be disposed on the same layer for electrical connection to each other.

[0061] According to the second embodiment, the second reference line VREF2 may be located on a different layer than the first reference line VREF1 and the second power line EVSS. The second reference line VREF2 may be electrically connected to the first reference line VREF1, and this may be the intersection area between them.

[0062] Will Figure 9A Experimental examples and Figure 9B Compared with the first embodiment, in this disclosure, a second reference line VREF2 intersecting the second direction is also provided, and one of the reference lines VREF arranged in the first direction is replaced with a second power line EVSS. Therefore, the arrangement structure of the lines is modified compared with the experimental example.

[0063] like Figure 10As shown, according to the first embodiment, each of the second power lines EVSS can be disposed between two adjacent first reference lines VREF1. This can be seen from the horizontally symmetrical arrangement of the two first reference lines VREF1 and one second reference line VREF2 with respect to the virtual vertical line that divides the first group of sub-pixels SP_G1 and the second group of sub-pixels SP_G2.

[0064] Based on Figure 7 The sub-pixels shown and described in the text Figure 10 The arrangement of the second power line EVSS connected to multiple sub-pixels and various signal lines VREF1, VREF2, SCAN1, SCAN2, and EM is shown. Based on this, two second scan lines SCAN2, two emission control lines EM, and one first scan line SCAN1 can be arranged between the two second reference lines VREF2. Furthermore, each sub-pixel SP can be electrically connected to the signal lines VREF1, VREF2, SCAN1, SCAN2, and EM, as well as the second power line EVSS arranged adjacent to the signal lines.

[0065] As described above, various effects can be obtained by modifying the arrangement of lines as in the first embodiment compared to the experimental example, which will be described after the second embodiment.

[0066] Figure 11 This is a plan view illustrating the reference lines and the second power line connected to the three sub-pixels according to the second embodiment of this disclosure. Figure 12 This is a plan view illustrating various signal lines and second power lines connected to multiple sub-pixels according to the second embodiment of this disclosure. Figure 13 It is a diagram Figure 12 A cross-sectional view of region A1-A2. Figure 14 It is a diagram Figure 12 A cross-sectional view of region B1-B2. Figure 15 It is a diagram Figure 12 A cross-sectional view of region C1-C2.

[0067] like Figure 11 As shown, according to the second embodiment, a pixel PIX can be provided in the display area AA of the display panel 150, in which the red sub-pixel SPR, the green sub-pixel SPG, and the blue sub-pixel SPB are arranged in sequence. The arrangement order of the sub-pixels in the pixel PIX may be only one embodiment, but the present disclosure is not limited thereto.

[0068] Furthermore, a first reference line VREF1 arranged in a first direction (length direction), a second reference line VREF2 arranged in a second direction (width direction), and a second power line EVSS arranged in the first direction can be provided in the display area AA of the display panel 150. The first reference line VREF1 and the second reference line VREF2 can be arranged in a mesh pattern.

[0069] The second reference line VREF2 can be located on a lower layer (lower layer) than the first reference line VREF1 and the second power line EVSS. The second reference line VREF2 can be electrically connected to the first reference line VREF1 through the contact hole CH.

[0070] The first reference line VREF1 and the second power line EVSS can be disposed on the same layer and can be formed by the source-drain metal layer constituting the source electrode and drain electrode of the transistor included in the sub-pixel SP. Furthermore, the second reference line VREF2 can be formed by the semiconductor layer constituting the active region of the transistor included in the sub-pixel SP. Referring below... Figures 12 to 15 A more detailed description is provided.

[0071] like Figure 12 and Figure 13 As shown, a first buffer layer BUF1 can be formed on a substrate (or film) PI. The first buffer layer BUF1 can be formed from multiple layers. A second buffer layer BUF2 can be formed on the first buffer layer BUF1.

[0072] A semiconductor layer ACT can be disposed on the second buffer layer BUF2. The semiconductor layer ACT may be a portion constituting the second reference line VREF2. The semiconductor layer ACT constituting the second reference line VREF2 can be disposed in a layer lower than the first reference line VREF1, and therefore may be referred to as the lower reference line. A gate insulating layer GI can be disposed on the semiconductor layer ACT. A first interlayer insulating layer ILD1 can be disposed on the gate insulating layer GI. A second interlayer insulating layer ILD2 can be disposed on the first interlayer insulating layer ILD1.

[0073] A first source / drain metal layer SD1 and a second source / drain metal layer SD2 can be disposed on the second interlayer insulating layer ILD2. The first source / drain metal layer SD1 and the second source / drain metal layer SD2 can be disposed separately from each other. The first source / drain metal layer SD1 can be a portion constituting the first reference line VREF1, and the second source / drain metal layer SD2 can be a portion constituting the data line of an adjacent sub-pixel. The first source / drain metal layer SD1 constituting the first reference line VREF1 can be disposed on a layer higher than the second reference line VREF2, and therefore can be referred to as the upper reference line.

[0074] A planarization layer PLN may be provided on the second interlayer insulating layer ILD2. The planarization layer PLN may be selected as a material that covers the first source / drain metal layer SD1 and the second source / drain metal layer SD2 and planarizes the surface.

[0075] An anode electrode layer (ANO) can be set on the planarization layer (PLN). The anode electrode layer (ANO) can be selected as the anode electrode of an organic light-emitting diode (OLED). A dam layer (BNK) can be set on the anode electrode layer (ANO). The dam layer (BNK) can divide sub-pixels. A cathode electrode layer (CAT) can be set on the dam layer (BNK). The cathode electrode layer (CAT) can be selected as the cathode electrode of an organic light-emitting diode (OLED).

[0076] A passivation layer ALD can be formed on the cathode electrode layer (CAT). The passivation layer ALD can be formed in the form of a dense medium using a deposition process that forms layers at atomic units. Additional layers, such as organic / inorganic composite layers, can be further formed on the passivation layer ALD.

[0077] like Figures 12 to 14 As shown, a third source / drain metal layer SD3, a fourth source / drain metal layer SD4, and a fifth source / drain metal layer SD5 can be disposed on the second interlayer insulating layer ILD2.

[0078] The third source-drain metal layer SD3 may be a part of the second power line EVSS, and each of the fourth source-drain metal layer SD4 and the fifth source-drain metal layer SD5 may be a part of the data line of the adjacent sub-pixel.

[0079] like Figures 12 to 15 As shown, a light-shielding layer BSM can be disposed on the first buffer layer BUF1. The light-shielding layer BSM can block external light from shining onto the semiconductor layer ACT of the transistor (especially the semiconductor layer driving the transistor). The light-shielding layer BSM can be selected as a metal layer to reduce light absorption or transmission. The second buffer layer BUF2 can be selected as a material used to planarize the surface of the first buffer layer BUF1 on which the light-shielding layer BSM is formed.

[0080] The semiconductor layer ACT, constituting the active layer of the transistor, can be disposed on the second buffer layer BUF2. A first gate metal layer GAT1, a second gate metal layer GAT2, and a third gate metal layer GAT3 can be disposed on the gate insulating layer GI. The first gate metal layer GAT1 can be a portion constituting the second scan line SCAN2. The second gate metal layer GAT2 can be a portion constituting the lower electrode Cst_L of the storage capacitor Cst. The third gate metal layer GAT3 can be a portion constituting the gate electrode of the transistor.

[0081] A metal layer TM may be disposed on the first interlayer insulating layer ILD1. The metal layer TM may be a portion of the upper electrode Cst_U constituting the storage capacitor Cst. The metal layer TM may be disposed correspondingly to the second gate metal layer GAT2 to form the storage capacitor Cst.

[0082] A sixth source-drain metal layer SD6 and a seventh source-drain metal layer SD7 may be disposed on the second interlayer insulating layer ILD2. The sixth source-drain metal layer SD6 may be a bridging portion electrically connected to the semiconductor layer ACT, which is disposed separately from each other on the second buffer layer BUF2. The seventh source-drain metal layer SD7 may be a portion constituting the data line of an adjacent sub-pixel.

[0083] A first light-emitting layer EL(R) and a second light-emitting layer EL(G), defined by a dam layer BNK, can be formed on the anode electrode layer ANO. Figure 15 The sub-pixels shown are only examples of light-emitting regions that have a diamond shape rather than a quadrilateral (or rectangle), and this disclosure is not limited thereto.

[0084] As can be seen from the above description, the first reference line VREF1 and the second reference line VREF2 are disposed on different layers and can be electrically connected to each other through contact holes CH disposed in the intersection area between them. Furthermore, the first reference line VREF1 and the second power line EVSS can be disposed on the same layer and can be formed by source-drain metal layers constituting the source and drain electrodes of the transistors included in the sub-pixel SP.

[0085] Figure 16A , Figure 16B and Figure 17 This is a diagram used to describe the arrangement of lines according to embodiments of the present disclosure and the advantages based on this arrangement. Figure 18A , Figure 18B and Figure 19 This is a diagram used to describe the arrangement of lines based on an experimental example and the disadvantages of that arrangement. For reference, in Figure 16A When the structure is illustrated as a circuit, the structure is as follows: Figure 16B As shown, and in Figure 18A When the structure is illustrated as a circuit, the structure is as follows: Figure 18B As shown in the image.

[0086] like Figure 16A , Figure 16B and Figure 17 As shown in the embodiments of this disclosure, a second power line EVSS may be disposed in the display area AA and the non-display area NA of the display panel 150. The second power line EVSS may be disposed in the non-display area NA to surround all surfaces of the display area AA, and may be disposed in the display area AA to have a mesh pattern.

[0087] In embodiments of this disclosure, a second power line EVSS with a mesh pattern can be provided in the display area AA, thereby solving the problem of increased second source voltage (EVSS rise) when the display panel 150 is manufactured to a specific size or shape, or driven by a specific method. As a result, a uniform, all-white image can be displayed across the display area AA.

[0088] However, as Figure 18A , Figure 18B and Figure 19 As shown, in the experimental example, in terms of the structural characteristics of the line arrangement, the second power line EVSS may only be provided in the non-display area NA of the display panel 150. In the experimental example, since the second power line EVSS is only provided in the non-display area NA of the display panel 150, it is difficult to solve the problem of increased second source voltage (EVSS rise) when the display panel 150 is manufactured with a specific size or shape, or driven by a specific method. As a result, due to position-based brightness and color coordinate differences caused by the increased second source voltage (EVSS rise), it is difficult to display a uniform, pure white image at the first point A and the second point B in the display area AA. For example, when optical compensation is performed, the second point B will result in a reddish tint.

[0089] In this disclosure, based on the mesh-like baseline, repairs can be performed smoothly and easily when open or short circuits occur in certain lines. Furthermore, in this disclosure, a second power line can be provided in the display area of ​​the display panel, thus minimizing the problem of increased second source voltage (EVSS rise) when achieving narrow bezels and large screens. Additionally, although the second power line is provided in the display area of ​​the display panel, the pattern density can be reduced and the problem of increased line (wiring) spacing can be solved. Furthermore, since the problems of reduced pattern density and increased line (wiring) spacing are solved in this disclosure, the problem of crosstalk and performance degradation of the display panel due to increased parasitic capacitance is minimized. Furthermore, since the performance degradation of the display panel is minimized in this disclosure, a uniform image can be achieved without position-based brightness and color coordinate differences. Furthermore, since the pattern density is reduced and the increase in line spacing is minimized in this disclosure, the problem of reduced productivity caused by short circuits between lines and short circuits caused by particles is solved.

[0090] The effects of this disclosure are not limited to the examples above, and various other effects may be included in this application.

[0091] Although this disclosure has been specifically shown and described with reference to its exemplary embodiments, those skilled in the art will understand that various changes may be made to its form and details without departing from the spirit and scope of this disclosure as defined by the claims.

Claims

1. A light-emitting display device, comprising: The display panel includes both the display area and the non-display area; A first reference line is arranged in a first direction in the display area; A second reference line is arranged in the display area in a second direction intersecting the first direction and is electrically connected to the first reference line. as well as A power cord, which is arranged in the display area in the first direction and positioned between at least two of the first reference lines. The first and second baselines are arranged in a grid pattern. Each of the first and second baselines is connected to a plurality of sub-pixels, and Two first reference lines are arranged between two adjacent power lines.

2. The light-emitting display device according to claim 1, wherein at least one of the first reference line and the second reference line is disposed on a different layer from the power line.

3. The light-emitting display device according to claim 1, wherein the second reference line is disposed on a different layer from the first reference line and the power line.

4. The light-emitting display device according to claim 1, wherein the first reference line and the power line are selected as source / drain metal layers of transistors included in the sub-pixels of the display panel.

5. The light-emitting display device according to claim 4, wherein the second reference line is selected as a semiconductor layer of transistors included in a sub-pixel constituting the display panel.

6. The light-emitting display device according to claim 4, wherein the first reference line and the power line are disposed between the interlayer insulating layer and the planarization layer, and the planarization layer is disposed in a layer higher than the second reference line.

7. The light-emitting display device according to claim 5, wherein the second reference line is disposed between the buffer layer and the gate insulating layer, and the gate insulating layer is disposed in a layer lower than the first reference line and the power line.

8. The light-emitting display device according to claim 1, wherein the power line includes a low-level power line, and The power level of the low-level power line is lower than the predetermined power level.

9. The light-emitting display device according to claim 8 further includes an additional power line having a power level higher than the predetermined power level.

10. The light-emitting display device according to claim 1, wherein the power line is configured to have a mesh pattern in the display area.

11. A light-emitting display device, comprising: A buffer layer disposed on the substrate; The lower reference line includes a semiconductor layer disposed on the buffer layer and arranged in a horizontal direction in a display area defined on the substrate; At least one insulating layer is disposed on the lower reference line; An upper reference line is disposed on at least one insulating layer, arranged in a vertical direction in the display area defined on the substrate, and electrically connected to the lower reference line; as well as A power line, disposed on the at least one insulating layer and arranged in the vertical direction within the display area defined on the substrate. The upper and lower baselines are arranged in a grid pattern. Each of the upper and lower baselines is connected to a plurality of sub-pixels, and Two upper reference lines are arranged between two adjacent power lines.

12. The light-emitting display device of claim 11, wherein the upper reference line and the power line are configured to be separated from each other on the at least one insulating layer and each includes a source / drain metal layer.

13. A method for manufacturing a light-emitting display device, the method comprising: A buffer layer is formed on the substrate; A lower reference line is formed, the lower reference line including a semiconductor layer disposed on the buffer layer and arranged in a horizontal direction in a display area defined on the substrate; At least one insulating layer is formed on the lower reference line; A first source / drain metal layer disposed on the at least one insulating layer and arranged in the vertical direction in the display area defined on the substrate is patterned to form an upper reference line electrically connected to the lower reference line. as well as A second source / drain metal layer disposed on the at least one insulating layer and arranged in the vertical direction within the display area defined on the substrate is patterned to form power lines separate from the upper reference line. The upper and lower baselines are arranged in a grid pattern. Each of the upper and lower baselines is connected to a plurality of sub-pixels, and Two upper reference lines are arranged between two adjacent power lines.

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