Circuit, electronic system and method for measuring voltage drop at a node

Abstract

The present disclosure relates to measuring changes in voltage. A system and method for measuring voltage drop at a node is provided. In an embodiment, a circuit includes an analog-to-digital converter, a current sink, and a controller. An input of the analog-to-digital converter and an input of the current sink are coupled to a node to be measured. A setpoint for the current sink is determined. An output of the analog-to-digital converter is sampled during a voltage drop. And a relative voltage drop value is calculated by subtracting the output of the analog-to-digital converter sampled during the voltage drop from the output of the analog-to-digital converter sampled during a steady state condition. The current sink operates at the setpoint during the steady state condition and during the voltage drop.

Description

Technical Field

[0001] This disclosure generally relates to electronic technology, and in particular embodiments to systems, methods and apparatus for measuring changes in voltage.

[0002] Cross-reference to related applications

[0003] This application relates to co-pending U.S. Patent Application No. 17 / 407,747 entitled “Capacitor Measurement”, which is associated with Agent’s File No. ST-20-CA-1028US01 and filed on the same day as this application, and is incorporated herein by reference in its entirety. Background Technology

[0004] Modern vehicles are typically equipped with airbags, often referred to as Assisted Inflation Restraint Systems (SIR) or Assisted Restraint Systems (SRS). These systems follow the vehicle's seatbelt restraint system and are further used to protect occupants in the event of a collision. A deployment circuit, typically including a microcontroller and accelerometer, actuates the ignition circuitry of the Assisted Restraint System during a collision. The ignition circuitry fires an igniter based on commands from the microcontroller, which then deploys the vehicle's airbags.

[0005] A reliable electrical energy source is essential for the reliable operation of the system. Typically, the vehicle's ignition voltage powers the system via the vehicle's main battery. However, in some instances, during a collision, the vehicle's main battery may disconnect or become inaccessible to the auxiliary restraint systems. One known solution is to provide a reserve capacitor (i.e., an energy storage source) connected to the system—this reserve capacitor provides power when the vehicle's main battery is unavailable. A reliable system for monitoring the operation of this reserve capacitor is desirable. Summary of the Invention

[0006] Technical advantages are generally achieved through embodiments of the systems, methods, and apparatuses described in this disclosure for measuring changes in voltage.

[0007] The first aspect relates to a method for measuring voltage drop at a node. The method includes: arranging a circuit having an analog-to-digital converter (ADC), a current sink, and a controller, the inputs of the ADC and the current sink being coupled to the node; determining a setpoint for the current sink; sampling the output of the ADC during the voltage drop period; and calculating a relative voltage drop value, which includes subtracting the sampled output of the ADC during the voltage drop period from the sampled output of the ADC during steady-state conditions, the current sink operating at the setpoint during both steady-state conditions and the voltage drop period.

[0008] In a first implementation of the method according to the first aspect, determining the set point for the current sink includes: sampling the first output of the analog-to-digital converter during a second steady-state condition, during which the current sink is disabled; and selectively adjusting the amount of current absorbed by the current sink until the output of the analog-to-digital converter is at a target value relative to the first output.

[0009] In a second implementation of the method according to the first aspect itself or any of the foregoing implementations of the first aspect, selectively adjusting the amount of current absorbed by the current absorber includes: monitoring the output of the analog-to-digital converter; adjusting the amount of current absorbed by a control signal generated by a controller based on the monitored output of the analog-to-digital converter; and transmitting the control signal to the digital-to-analog converter (DAC) of the current absorber.

[0010] In a third implementation of the method according to the first aspect itself or any of the foregoing implementations of the first aspect, the target value corresponds to a ratio between 9.9% and 10.1%.

[0011] In a fourth implementation of the method according to the first aspect itself or any of the foregoing implementations of the first aspect, the voltage drop includes enabling a discharge switch coupled to the node, such that the voltage value at the node decreases.

[0012] In a fifth implementation of the method according to the first aspect itself or any of the foregoing implementations of the first aspect, the method further includes: calculating the voltage drop at the node based on a linear relationship between the voltage drop and the relative voltage drop.

[0013] In a sixth implementation of the method according to the first aspect itself or any of the foregoing implementations of the first aspect, the setpoint is selected to prevent analog-to-digital converter saturation.

[0014] In a seventh implementation of the method according to the first aspect itself or any of the foregoing implementations of the first aspect, the node is a node of the reserve capacitor of the auxiliary restraint system (SRS) in the vehicle.

[0015] The second aspect relates to a circuit for measuring voltage drop at a node. The circuit includes: an analog-to-digital converter (ADC) coupled to the node; a current sink coupled to the node and the input of the ADC, the current sink being configured to be adjusted via a control signal to selectively adjust the amount of current absorbed through the current sink; and a controller coupled to the output of the ADC and a control input to the current sink. The controller is configured to determine a setpoint for the current sink; sample the output of the ADC during the voltage drop period; and calculate a relative voltage drop value, including subtracting the sampled output of the ADC during the voltage drop period from the sampled output of the ADC during the steady-state condition, the current sink operating at the setpoint during both the steady-state condition and the voltage drop period.

[0016] In a first implementation of the circuit according to this second aspect, the current sink includes a digital-to-analog converter (ADC) and a load.

[0017] In a second implementation of the circuit according to the second aspect itself or any of the foregoing implementations of the second aspect, determining the set point of the current sink includes: sampling the first output of the analog-to-digital converter during the second steady-state condition, during which the current sink is disabled; and selectively adjusting the amount of current absorbed by the current sink until the output of the analog-to-digital converter is at a target value relative to the first output.

[0018] In a third implementation of the circuit according to the second aspect itself or any of the foregoing implementations of the second aspect, selectively adjusting the amount of current absorbed by the current sink includes: monitoring the output of the analog-to-digital converter; adjusting the amount of current absorbed by a control signal generated by the controller based on the monitored output of the analog-to-digital converter; and transmitting the control signal to the digital-to-analog converter (DAC) of the current sink.

[0019] In a fourth implementation of the circuit according to the second aspect itself or any of the foregoing implementations of the second aspect, the node is coupled to a discharge circuit, and the voltage drop corresponds to enabling a discharge switch of the discharge circuit coupled to the node, so that the voltage value at the node decreases.

[0020] In a fifth implementation of the circuit according to the second aspect itself or any of the foregoing implementations of the second aspect, the controller is further configured to calculate the voltage drop at the node based on the linear relationship between the voltage drop and the relative voltage drop.

[0021] In a sixth implementation of the circuit according to the second aspect itself or any of the foregoing implementations of the second aspect, the set point is selected to prevent the analog-to-digital converter from saturating.

[0022] In a seventh implementation of the circuit according to the second aspect itself or any of the foregoing implementations of the second aspect, the analog-to-digital converter is a sigma-delta (Σ-Δ) converter, and the controller is a proportional-integral-derivative (PID) controller.

[0023] In an eighth implementation of the circuit according to the second aspect itself or any of the foregoing implementations of the second aspect, the node is the node of the spare capacitor in the vehicle's auxiliary restraint system (SRS).

[0024] The third aspect relates to a system. The system includes: a capacitor having a first node; an analog-to-digital converter (ADC) coupled to the first node; a current sink coupled to the first node and the input of the ADC, the current sink being configured to be adjusted via a control signal to selectively adjust the amount of current absorbed through the current sink; and a controller coupled to the output of the ADC and a control input to the current sink. The controller is configured to: determine a setpoint for the current sink; sample the output of the ADC during a voltage drop at the first node; and calculate a relative voltage drop value comprising subtracting the sampled output of the ADC during the voltage drop from the sampled output of the ADC during a steady-state condition, the current sink operating at the setpoint during both the steady-state condition and the voltage drop period.

[0025] In a first implementation of the system according to the third aspect, determining the set point for the current sink includes: sampling the first output of the analog-to-digital converter during a second steady-state condition, during which the current sink is disabled; and selectively adjusting the amount of current absorbed by the current sink until the output of the analog-to-digital converter is at a target value relative to the first output.

[0026] In a second implementation of the system according to the third aspect itself or any of the foregoing implementations of the third aspect, selectively adjusting the amount of current absorbed by the current absorber includes: monitoring the output of the analog-to-digital converter; adjusting the amount of current absorbed by a control signal generated by the controller based on the monitored output of the analog-to-digital converter; and transmitting the control signal to the digital-to-analog converter (DAC) of the current absorber.

[0027] In a third implementation of the system according to the third aspect itself or any of the foregoing implementations of the third aspect, the system further includes a discharge circuit coupled to a capacitor via a first node, the voltage drop corresponding to a discharge switch that enables the discharge circuit coupled to the first node, causing the voltage at the first node to decrease.

[0028] In a fourth implementation of the system based on the third aspect itself or any of the aforementioned implementations of the third aspect, the setpoint is selected to prevent analog-to-digital converter saturation.

[0029] In a fifth implementation of the system according to the third aspect itself or any of the foregoing implementations of the third aspect, the capacitor is a reserve capacitor of the vehicle's auxiliary restraint system (SRS).

[0030] The embodiments can be implemented using hardware, software, or any combination thereof. Attached Figure Description

[0031] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0032] Figure 1a This is a circuit model of the storage capacitor in the embodiment;

[0033] Figure 1b It is a timing diagram of the discharge at the voltage of the capacitor during the discharge routine;

[0034] Figure 2 It is a prior art circuit used to measure voltage drop during capacitor discharge routines;

[0035] Figure 3 It is another prior art circuit used to measure voltage drop during capacitor discharge routines;

[0036] Figure 4 This is an example circuit used to measure voltage changes;

[0037] Figure 5 This is a flowchart of an embodiment method for measuring voltage changes, which can be derived from... Figure 4 The circuit executes;

[0038] Figure 6 It corresponds to Figure 5 Timing diagrams of embodiments of the methods discussed herein;

[0039] Figure 7 This is an example circuit for measuring voltage changes; and

[0040] Figure 8 This is an example circuit used to measure voltage changes.

[0041] Specific implementation

[0042] This disclosure provides numerous applicable inventive concepts that can be embodied in a variety of specific contexts. Specific embodiments are provided only to illustrate particular configurations and do not limit the scope of the claimed embodiments. Unless otherwise stated, features from different embodiments may be combined to form other embodiments.

[0043] The variations or modifications described in one embodiment can also be applied to other embodiments. Furthermore, it should be understood that various changes, substitutions, and alterations may be made herein without departing from the spirit and scope of this disclosure as defined by the appended claims.

[0044] Although the inventive aspects are described primarily in the context of the storage capacitor in an auxiliary restraint system (SRS), they are similarly applicable to any electronic device that can benefit from the measurement of voltage drop above an unknown voltage baseline.

[0045] Typically, a vehicle's auxiliary restraint system includes one or more reserve capacitors that provide alternative power to the system if the primary power source (e.g., the vehicle's main battery) becomes disabled or inaccessible. During normal operation, the charging circuit charges the reserve capacitors via, for example, the vehicle's main battery. The reserve capacitors are typically isolated from the deployment circuitry to minimize the load on the charging circuitry. In the event of a collision and the absence of primary power, the isolation circuitry detects a loss of vehicle ignition voltage and connects the reserve capacitors to the deployment circuitry for continued operation of the auxiliary restraint system.

[0046] The airbag control module of the auxiliary restraint system periodically assesses hardware faults and transmits any errors to the vehicle's diagnostic computer via Diagnostic Trouble Codes (DTCs). In response, the vehicle's dashboard displays the error to the user, for example, by flashing an airbag warning light. Embodiments of this disclosure can be used to determine the health of the reserve capacitors and provide diagnostic fault codes to warn the vehicle owner of problems related to the auxiliary restraint system.

[0047] Embodiments of this disclosure provide application-specific integrated circuits (ASICs) or stand-alone circuits for use in conjunction with circuitry implemented in standard auxiliary constraint systems. In combination, these circuits provide a variety of functions, such as power management, driver deployment capabilities (e.g., support for igniter (squib) and low-energy actuator loads), regulator deployment capabilities, remote sensor interfaces (e.g., support for Peripheral Sensor Interface 5 (PSI5) satellite sensors), diagnostic functions, deployment arming, Hall effect sensor interfaces, switch sensor interfaces, universal low-side drivers, watchdog functionality, Local Internet Network (LIN) interfaces, and more.

[0048] Various aspects of this disclosure include techniques for improving existing circuits that suffer from small dynamic range or low resolution accuracy. In contrast, the systems and methods disclosed herein improve the dynamic range on which a baseline voltage can operate while maintaining high-resolution accuracy. In a particular embodiment, the measurement techniques provide an improved system and method for measuring the normal operation of a storage capacitor used in an auxiliary constraint system.

[0049] In one embodiment, the circuit includes an analog-to-digital converter (ADC), a controller, and a controllable current sink. The circuit is coupled to a capacitor (e.g., a storage capacitor) to be measured. The ADC generates a digital equivalent of an analog voltage at the capacitor's terminals. The controller monitors the ADC's output and uses control signals to control the amount of current absorbed at the controllable current sink.

[0050] In the initial steps and during the steady-state condition of the capacitor, the controller monitors the voltage across the capacitor while adjusting the amount of current absorbed through the controlled current absorber. A desired target (e.g., 10%) of the measured digital equivalent value of the analog voltage at the terminals between (1) the steady-state condition and (2) the activated controlled current absorber is selected to optimize the operating range of the analog-to-digital converter and prevent the analog-to-digital converter from saturating.

[0051] Once the controller has determined the appropriate settings for the controllable current sink to achieve the desired objective, the values ​​of the control signals from the controller to the current sink are frozen. Therefore, once the control signals are frozen, the digital output of the analog-to-digital converter is a known ratio of the voltage values ​​at the capacitor terminals.

[0052] In the second step, a discharge circuit coupled to the terminals of the capacitor is activated, causing the voltage at the capacitor to drop from the first time point to the second time point. The controller continuously monitors the output of the analog-to-digital converter until, for example, the discharge circuit is disabled at the second time point. The absolute difference in the capacitor output from the first time point to the second time point is calculated. Because this difference is related to the voltage drop at the capacitor given a known constant based on the desired objective, the voltage drop at the capacitor is calculated. These and other details are discussed in more detail below.

[0053] Figure 1a The illustration shows a circuit model 100 of the storage capacitor 102 in an embodiment. In addition to the model capacitor 104, the circuit model 100 also includes an equivalent series resistor (ESR) 106. In this embodiment, the storage capacitor 102 serves as an auxiliary power source for powering the vehicle's auxiliary restraint system, acting as an alternative power source to the vehicle's main battery.

[0054] It is desirable to periodically monitor the proper operation of the storage capacitor 102. At set time intervals, the equivalent series resistance and capacitance of the storage capacitor 102 are measured during the discharge routine of the storage capacitor 102 through the discharge circuit 108.

[0055] Charging circuit 120 is coupled to storage capacitor 102. Charging circuit 120 provides a controllable (e.g., serial peripheral interface (SPI) etc.) low-ohm path that, when enabled, allows storage capacitor 102 to charge during its charging routine.

[0056] The discharge circuit 108 provides a controllable (e.g., serial peripheral interface (SPI) etc.) low-ohm path that allows the storage capacitor 102 to discharge during the discharge routine of the storage capacitor 102.

[0057] The discharge circuit 108 includes a discharge switch 110. A discharge resistor 112 is coupled to the discharge circuit 108. When the discharge switch 110 is activated, for example during a discharge routine, current is dissipated through the discharge resistor 112.

[0058] Figure 1a The components shown may (or may not) be arranged as shown. Furthermore, the discharge circuit 108 may include additional or fewer components, as shown, for the purpose of providing a discharge path for the storage capacitor 102 when the discharge switch 110 is in the closed position.

[0059] In this embodiment, the discharge switch 110 is a metal-oxide-semiconductor field-effect transistor (MOSFET). Optionally, the discharge circuit 108 may include a diode connected in series between the discharge switch 110 and the discharge resistor 112. Although the discharge circuit 108 is arranged between the discharge resistor 112 and the reference voltage as shown, in this embodiment, the discharge resistor 112 is coupled in series between the discharge switch 110 and the reference voltage.

[0060] In one embodiment, the discharge resistor 112 is positioned away from the circuitry of the circuit model 100 to minimize power dissipation and reduce circuit temperature during the discharge routine.

[0061] Figure 1b The diagram illustrates the discharge routine of the storage capacitor 102 for V. ER Voltage timing diagram 150. Before time t1, discharge circuit 108 is disabled, and V ER Voltage corresponds to steady-state voltage value V START .

[0062] At time t1, the discharge circuit 108 is activated by the discharge switch 110. In response, the storage capacitor 102 is immediately discharged to the voltage value V. START_t1+ The sharp drop in voltage at time t1 typically corresponds to the non-zero equivalent series resistance of the storage capacitor 102.

[0063] From time t1 to time t2, while the discharge circuit 108 remains enabled and the charging circuit 120 is disabled, the storage capacitor 102 continuously discharges until it reaches the voltage value V. STOP_t2 .

[0064] At time t2, the discharge circuit 108 is disabled, and the charging circuit 120 is enabled. In response, the storage capacitor 102 is immediately charged to its initial voltage value V. STOP Then, the storage capacitor 102 is gradually recharged to the steady-state voltage value V. END .

[0065] Embodiments of this disclosure provide a system and method for measuring the voltage drop at a storage capacitor 102 during a discharge routine from slightly earlier than time t1 (e.g., 64 microseconds before time t1) to slightly later than time t2 (e.g., 64 microseconds after time t2).

[0066] The typical operating value of the storage capacitor 102 in the auxiliary restraint system configuration is a selectable voltage output between 20 and 33 volts. In an embodiment, the voltage of a fully charged storage capacitor 102 is approximately 33 volts (V). In such an embodiment, the voltage drop at time t1 is approximately 600 millivolts (mV).

[0067] Figure 2 The diagram illustrates the measurement of V during the discharge routine of the storage capacitor 102. ER The prior art circuit 200 describes a voltage drop reduction. Circuit 200 includes an analog-to-digital converter 202, a discharge circuit 108, resistors R1 204a and R2 204b. The arrangement of resistors R1 204a and R2 204b at the input of the analog-to-digital converter 202 provides a resistive voltage divider. At times t1 and t2, the analog-to-digital converter 202 reduces the voltage drop by a ratio V (due to the resistive voltage divider). ER The voltage is converted to a digital value. The difference between the voltages at times t1 and t2 is calculated to determine the voltage drop. Disadvantageously, circuit 200 cannot be extended over a wide operating voltage range because, with the baseline voltage V... ER As the input range increases, the resolution accuracy of the measured delta voltage decreases. Therefore, circuit 200 suffers a trade-off between input range and resolution accuracy.

[0068] Figure 3 The diagram illustrates the measurement of V during the discharge routine of the storage capacitor 102. ER The prior art circuit 300 describes a voltage drop. Circuit 300 includes an analog-to-digital converter (ADC) 302, a level shifter 304, and a sample-and-hold circuit 306. By enabling and disabling various switches (e.g., transistors) in the level shifter 304 and the sample-and-hold circuit 306, V... ER Multiple voltage samples were recorded. When V ER When in steady-state condition, the first sample is maintained. Then, multiple samples are maintained during the start-up discharge circuit 108. By comparing the various samples with the steady-state condition, circuit 300 determines V.ER The voltage drop at the point is significant. Disadvantageously, for each sample to be held, circuit 300 requires at least one capacitor and a switch, which significantly increases the footprint of circuit 300. Furthermore, leakage at the various switches can significantly impair the accuracy of voltage drop measurements.

[0069] Figure 4 The diagram illustrates the node V used for measurement. IN The embodiment of voltage variation at the location, circuit 400, has improved dynamic range and resolution compared to circuits 200 and 300. Circuit 400 includes an analog-to-digital converter 402, a controller 404, and a controllable current sink 406, which may (or may not) be arranged as shown.

[0070] The analog-to-digital converter 402 can be a general-purpose analog-to-digital converter, a sigma-delta (Σ-Δ) analog-to-digital converter, etc. The controller 404 can be a digital controller, a proportional-integral-derivative (PID) controller, etc. The current sink 406 is an adjustable current source equipped with a digital-to-analog converter (DAC) and a load (not shown). The analog-to-digital converter 402 and the controller 404 include a clock signal input from a clock generator (not shown) for synchronized operation.

[0071] Controller 404 is further configured to perform computational or other processing-related tasks associated with the methods disclosed herein. For example, controller 404 may be logic circuitry, a microprocessor, a microcontroller, control circuitry, a digital signal processor, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system-on-a-chip (SoC), or a combination thereof.

[0072] Circuit 400 is shown as having a single controller 404; however, in some embodiments, circuit 400 may include other components that combine to perform various functions attributed herein to controller 404. In embodiments, controller 404 may be dedicated circuitry. In other embodiments, controller 404 may refer to an existing processing unit of a system in which circuit 400 is integrated.

[0073] In an embodiment, controller 404 may include memory to store programs or instructions executed by controller 404. The memory may include a non-transitory computer-readable medium. Non-transitory computer-readable media may include all types of computer-readable media, including magnetic storage media, optical storage media, flash memory media, and solid-state storage media. The memory may be embedded in controller 404 or a dedicated memory for storing instructions or data. Controller 404 may alternatively be coupled to existing memory in a device incorporating circuitry 400.

[0074] It should be understood that the software can be installed in circuit 400 and sold together with circuit 400. Alternatively, the software can be obtained and loaded into circuit 400, including obtaining the software through physical media or a distribution system, such as from a server owned by the software creator or a server not owned by the software creator but used by the software creator. For example, the software can be stored on a server for distribution via the Internet.

[0075] The input of the analog-to-digital converter 402 is with V IN A proportional analog signal. The output of the analog-to-digital converter 402 is the corresponding digital signal BS. OUT During the period when the current absorber 406 is at a constant value, BS OUT Changes in (ΔBS) OUT (relative to V) IN Changes in (ΔV) IN The equation ΔBS can be used. OUT =-αΔV IN To calculate, where α is a constant integer. Note that the constant integer value of α depends on the selection of components in circuit 400, such as... Figure 7 Further details are provided below.

[0076] The controller 404 is coupled to a digital-to-analog converter of the current sink 406, allowing the controller 404 to control the current sink 406 via a control signal. The control signal from the controller 404 is adjusted from V... IN The amount of current flowing through the load of the current absorber 406 at the node. Because BS OUT It is V IN Since the known proportional equivalent is available, the operating range of circuit 400 can be increased by absorbing a known amount of current—configurable via controller 404—via current absorber 406. Because circuit 400 is independent of V... IN It operates based on the absolute value, so circuit 400 can measure V with high resolution and accuracy. IN The voltage drop at the point, while maintaining a large V IN Voltage dynamic range.

[0077] Figure 5 It is used to measure node V IN The flowchart of an embodiment of the voltage change at a certain point is shown, which can be executed by circuit 400.

[0078] Figure 6 The diagram shows the corresponding Figure 5 The timing diagram 600 is an embodiment of the method 500 discussed in the text. In step 502, from time t0 to time t1, when V INWhen maintaining steady-state conditions, controller 404 provides a variable control signal to current absorber 406. When controller 404 changes the current absorbed through current absorber 406, controller 404 monitors the changing digital value BS. OUT Until the desired BS is achieved OUT_TARGET Select the desired BS. OUT_TARGET To optimize the range of analog-to-digital converter 402 and avoid saturation of analog-to-digital converter 402.

[0079] In this embodiment, due to the limitation of the analog-to-digital converter 402 in quantizing analog signals into digital signals, the actual BS OUT_TARGET The value may not be exactly equal to the expected value. In such an embodiment, based on the sampling near the expected set point, for example, based on the analog equivalent being closer to achieving the desired ratio, the controller 404 may adjust the ratio to an undesired value that is slightly higher or lower than the initial desired ratio.

[0080] In step 504, once the desired BS is achieved... OUT_TARGET The controller 404 will control the signal value (DAC). code The control signal value (DAC) is stored and maintained (i.e., frozen) in memory. code The current absorbed by the DAC is sent to the current absorber 406 so that the amount of current absorbed by the current absorber 406 remains at the stable value determined at step 502. In an embodiment, once the DAC... code Frozen due to the selected DAC code This may correspond to the selected DAC. code Slightly different unwanted BS OUT_TARGET Therefore, a new measurement is run, and controller 404 stores the BS. OUT (t1).

[0081] For example, when the loop tracking equals 10% of the BS OUT_TARGET When selecting a code, which must be an integer, it can vary between two consecutive codes (e.g., 124 and 125, ideally 124.5). Therefore, once one of the two consecutive codes is selected (e.g., the closest between 124 and 125), BS... OUT Possibly related to BS OUT_TARGET Slightly different. Therefore, a new measurement is run, and the controller 404 stores a BS of 9.9% or 10.1% instead of the ideal 10%. OUT (t1).

[0082] exist Figure 6 In the timing diagram of the embodiment shown in the figure, the control signal value DAC code Start with a high value. Controller 404 gradually decreases the control signal value DAC. codeAt time t1, controller 404 determines the control signal value DAC. code Achieve the expected 10% BS OUT_TARGET Value and freeze control signal value DAC code .

[0083] Note that controller 404 is used to determine the control signal value DAC that results in achieving the desired ratio. code The process followed is not limited to Figure 6 A timing diagram example. For example, the control signal value DAC. code It may be necessary to increase the value of current absorber 406 to initiate operation. As another example, controller 404 could be a proportional-integral-derivative (PID) controller utilizing a closed-loop feedback control system. In this example, the PID controller drives current absorber 406 until the desired BS is reached. OUT_TARGET value.

[0084] By configuring the current absorber 406 to absorb sufficient current to achieve BS OUT_TARGET The value, circuit 400 allows for an improved dynamic operating range to monitor V. IN Voltage. Furthermore, once the control signal value (DAC) code It is set because of the equation ΔBS OUT =αΔV IN If the controller remains active, 404 can be resolved by referring to BS. OUT (t1) for BS OUT (t2) Monitoring is performed to calculate V IN The voltage drops.

[0085] At step 506 and time t1, the control signal value DAC code Configured by controller 404 to achieve the desired BS OUT_TARGET Value. Furthermore, at time t1, discharge switch 110 is activated, and V IN The voltage value begins to decrease. From time t1 to time t2 and at periodic intervals, controller 404 adjusts the voltage at the output of analog-to-digital converter 402. OUT The value is sampled. In one embodiment, the controller 404 samples the BS every 64 microseconds (μs). OUT Sampling is performed. In this embodiment, sampling is configured to achieve acceptable granularity based on the duration for which the discharge circuit 108 remains enabled.

[0086] At step 508 and time t2, discharge switch 110 is disabled, and V IN The value no longer decreases. Because the various components of circuit 400 are synchronized with the clock signal, at time t2 (or slightly earlier), controller 404 sets the clock signal to BS. OUT(t2) Sample and calculate BS OUT (t2) and BS OUT The difference between (t1) (i.e., ΔBS) OUT =BS OUT (t2)-BS OUT (t1)). Because ΔBS OUT =-αΔV IN By updating the equation, controller 404 can calculate, for example, the voltage drop V during the discharge routine of storage capacitor 102. IN (ΔV IN ).

[0087] The measurement ends at step 510. It should be noted that this can be achieved using the equation ΔBS. OUT =αΔV IN Knowing any decrease, the equation corresponds to BS. OUT (t x )-BS OUT (t y )=-α(V IN (t x )-V IN (t y )), where x and y are integers, and x > y.

[0088] Notice, Figure 5 The order of steps shown is not strictly required; therefore, in principle, the steps can be performed in any order. Furthermore, some steps can be skipped, different steps can be added or replaced, or selected steps or groups of steps can be executed in separate applications.

[0089] Embodiments of this disclosure can measure voltage drop across a baseline voltage. In one embodiment, the baseline voltage is 20 to 30 volts. In such an embodiment, the voltage drop can be measured with an accuracy of 10-15 millivolts and a resolution of 1 millivolt.

[0090] Figure 7 The diagram illustrates the node V used for measurement. IN The embodiment circuit 700 illustrates the voltage change at the location. As shown, the analog-to-digital converter 402 is illustrated as a sigma-delta (Σ-Δ) first-order time-continuous analog-to-digital converter. The analog-to-digital converter 402 is shown to include a differential amplifier 706, an integrator 708, a comparator 710, a flip-flop 712, and an R... FB Resistors 714, capacitors 716, switches 718 and 720 may (or may not) be arranged as shown. Furthermore, the analog-to-digital converter 402 is not limited to the circuit arrangement shown, and similar results can be achieved using any type of sigma-delta (Σ-Δ) analog-to-digital converter in circuit 700.

[0091] The current value (I) absorbed by the current absorber 406 DAC (t) is provided by the following formula:

[0092]

[0093] By revising BS OUT The equation for (t) can be written as:

[0094]

[0095] Based on the above, in order to calculate ΔBS OUT =BS OUT (t2)-BS OUT (t1), given the following equation:

[0096]

[0097] When the control signal value (DAC) code When I is set, DAC (t2)=I DAC (t1), for example, during steps 508 and 510 above. Therefore, V can be calculated in the following way. IN Voltage (ΔV) IN Changes in )

[0098]

[0099] Assumption ΔBS OUT With ΔV IN The relationship is:

[0100] ΔBS OUT =-∝ΔV IN .

[0101] Figure 8 The diagram illustrates the measurement of node V. IN Example circuit 800 showing voltage variation at a certain point. (And...) Figure 4 In contrast, circuit 800 includes a proportional-integral-derivative (PID) controller 804. In this embodiment, the PID controller 804 is limited to the integral type. The input setpoint of the PID controller 804 is used to control the output (BS) of the analog-to-digital converter 402. OUT The initial setting of the expected input is used, and voltage variation measurement begins at this initial setting. The operation of circuit 800 is similar to that of the reference circuit. Figures 4-6In addition to the following, the disclosed operation is as follows: the PID controller 804 uses a closed-loop feedback system to determine the control signal to adjust the current absorber 406 to achieve the desired target, thereby optimizing the operating range of the analog-to-digital converter 402 and preventing the analog-to-digital converter 402 from saturating.

[0102] Unless otherwise stated, when referring to two elements electrically connected together, it means that these elements are directly connected without any intermediate elements other than conductors. When referring to two elements electrically coupled together, it means that these two elements can be directly coupled (connected) or coupled via one or more other elements.

[0103] Although a detailed description has been provided, it should be understood that various changes, substitutions, and alterations may be made without departing from the spirit and scope of this disclosure as defined by the appended claims. In the various drawings, the same elements are designated by the same reference numerals. Furthermore, the scope of this disclosure is not intended to be limited to the specific embodiments described herein, as it will be readily understood from this disclosure by those skilled in the art that existing or future processes, machines, manufactures, compositions of matter, components, methods, or steps can perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Therefore, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, components, methods, or steps within their scope.

[0104] It should be understood that the embodiments of this disclosure are not limited to the applications disclosed herein concerning the measurement of voltage drop at a storage capacitor in an auxiliary constraint system. Various embodiments are also applicable to other applications that benefit from measuring voltage drop at the terminals of electronic circuits with unknown baseline voltages.

[0105] Therefore, the specification and drawings are to be regarded only as a description of this disclosure as defined by the appended claims, and are intended to cover any and all modifications, variations, combinations or equivalents falling within the scope of this disclosure.

Claims

1. A method for measuring voltage drop at a node, the method comprising: The circuit includes an analog-to-digital converter, a current sink, and a controller, with the inputs of the analog-to-digital converter and the current sink coupled to the node; The first output of the analog-to-digital converter is sampled during the first steady-state condition, during which the current sink is disabled. The amount of current absorbed through the current absorber is selectively adjusted until the output of the analog-to-digital converter is at a target value relative to the first output; The output of the analog-to-digital converter is sampled during the voltage drop period; as well as The relative voltage drop is calculated by subtracting the output of the analog-to-digital converter sampled during the voltage drop from the output of the analog-to-digital converter sampled during the second steady-state condition, wherein the current sink operates at the target value during the second steady-state condition and during the voltage drop.

2. The method of claim 1, wherein selectively adjusting the amount of current absorbed by the current absorber comprises: Monitor the output of the analog-to-digital converter; Based on monitoring the output of the analog-to-digital converter, the amount of current absorbed is adjusted by a control signal generated by the controller; as well as The control signal is transmitted to the digital-to-analog converter (DAC) of the current sink.

3. The method of claim 1, wherein the target value corresponds to a ratio between 9.9% and 10.1%.

4. The method of claim 1, wherein the voltage drop includes enabling a discharge switch coupled to the node to cause the voltage value at the node to decrease.

5. The method according to claim 1, further comprising: The voltage drop at the node is calculated based on the linear relationship between the voltage drop and the relative voltage drop.

6. The method of claim 1, wherein the target value is selected to prevent the analog-to-digital converter from saturating.

7. The method of claim 1, wherein the node is a node of the reserve capacitor of the auxiliary restraint system SRS in the vehicle.

8. The method of claim 1, wherein the analog-to-digital converter is a sigma-delta Σ-Δ analog-to-digital converter, and the controller is a proportional-integral-derivative PID controller.

9. A circuit for measuring voltage drop at a node, the circuit comprising: An analog-to-digital converter (ADC) coupled to the node; A current sink, coupled to the node and the input of the analog-to-digital converter, is configured to be adjusted via a control signal to selectively adjust the amount of current absorbed through the current sink; as well as A controller, coupled to the output of the analog-to-digital converter and the control input of the current sink, is configured to: The first output of the analog-to-digital converter is sampled during the first steady-state condition, during which the current sink is disabled. The amount of current absorbed through the current absorber is selectively adjusted until the output of the analog-to-digital converter is at a target value relative to the first output; The output of the analog-to-digital converter is sampled during the voltage drop period; as well as The relative voltage drop is calculated by subtracting the output of the analog-to-digital converter sampled during the voltage drop from the output of the analog-to-digital converter sampled during the second steady-state condition, wherein the current sink operates at the target value during the second steady-state condition and during the voltage drop.

10. The circuit of claim 9, wherein the current sink comprises a digital-to-analog converter (ADC) and a load.

11. The circuit of claim 9, wherein selectively adjusting the amount of current absorbed by the current absorber comprises: Monitor the output of the analog-to-digital converter; Based on monitoring the output of the analog-to-digital converter, the amount of current absorbed is adjusted by a control signal generated by the controller; as well as The control signal is transmitted to the digital-to-analog converter (DAC) of the current sink.

12. The circuit of claim 9, wherein the node is coupled to a discharge circuit, and the voltage drop includes activating a discharge switch of the discharge circuit coupled to the node, such that the voltage value at the node decreases.

13. The circuit of claim 9, wherein the controller is further configured to calculate the voltage drop at the node based on a linear relationship between the voltage drop and the relative voltage drop.

14. The circuit of claim 9, wherein the target value is selected to prevent the analog-to-digital converter from saturating.

15. The circuit of claim 9, wherein the analog-to-digital converter is a sigma-delta Σ-Δ analog-to-digital converter, and the controller is a proportional-integral-derivative PID controller.

16. The circuit of claim 9, wherein the node is a node of a storage capacitor in the vehicle's auxiliary restraint system (SRS).

17. The circuit of claim 9, wherein the target value corresponds to a ratio between 9.9% and 10.1%.

18. An electronic system comprising: A capacitor having a first node; An analog-to-digital converter (ADC) is coupled to the first node; A current sink, coupled to the first node and the input of the analog-to-digital converter, is configured to be adjusted via a control signal to selectively adjust the amount of current absorbed through the current sink; as well as A controller, coupled to the output of the analog-to-digital converter and the control input of the current sink, is configured to: The first output of the analog-to-digital converter is sampled during the first steady-state condition, during which the current sink is disabled. The amount of current absorbed through the current absorber is selectively adjusted until the output of the analog-to-digital converter is at a target value relative to the first output; The output of the analog-to-digital converter is sampled during the voltage drop period at the first node; as well as The relative voltage drop is calculated by subtracting the output of the analog-to-digital converter sampled during the voltage drop from the output of the analog-to-digital converter sampled during the second steady-state condition, wherein the current sink operates at the target value during the second steady-state condition and during the voltage drop.

19. The electronic system of claim 18, wherein selectively adjusting the amount of current absorbed by the current absorber comprises: Monitor the output of the analog-to-digital converter; Based on monitoring the output of the analog-to-digital converter, the amount of current absorbed is adjusted by a control signal generated by the controller; as well as The control signal is transmitted to the digital-to-analog converter (DAC) of the current sink.

20. The electronic system of claim 18, further comprising a discharge circuit coupled to the capacitor via the first node, the voltage drop comprising activating a discharge switch of the discharge circuit coupled to the first node, such that the voltage at the first node decreases.

21. The electronic system of claim 18, wherein the target value is selected to prevent the analog-to-digital converter from saturating.

22. The electronic system of claim 18, wherein the capacitor is a reserve capacitor of the vehicle's auxiliary restraint electronic system (SRS).

23. The electronic system of claim 18, wherein the analog-to-digital converter is a sigma-delta Σ-Δ analog-to-digital converter, and the controller is a proportional-integral-derivative PID controller.

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